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authorUlf Hansson <ulf.hansson@linaro.org>2013-01-07 09:30:44 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-01-08 11:32:43 -0500
commit6dbb6ee090e810be337945a7a64d647549b70328 (patch)
tree5ccf991b37fc1ae87b91a941d4ee82c8d0b6a645 /drivers/mmc/host/mmci.c
parentd1c3ed669a2d452cacfb48c2d171a1f364dae2ed (diff)
ARM: 7617/1: mmc: mmci: Support for DDR mode
Add support for DDR mode which may be used for the ux500v2 variant. Corresponding capabilities to enable the DDR support must be set in the platform struct to enable the functionality. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/mmc/host/mmci.c')
-rw-r--r--drivers/mmc/host/mmci.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 150772395cc6..fba51073e94f 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -202,6 +202,9 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
202 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 202 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
203 clk |= MCI_ST_8BIT_BUS; 203 clk |= MCI_ST_8BIT_BUS;
204 204
205 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
206 clk |= MCI_ST_UX500_NEG_EDGE;
207
205 mmci_write_clkreg(host, clk); 208 mmci_write_clkreg(host, clk);
206} 209}
207 210
@@ -680,6 +683,9 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
680 mmci_write_clkreg(host, clk); 683 mmci_write_clkreg(host, clk);
681 } 684 }
682 685
686 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
687 datactrl |= MCI_ST_DPSM_DDRMODE;
688
683 /* 689 /*
684 * Attempt to use DMA operation mode, if this 690 * Attempt to use DMA operation mode, if this
685 * should fail, fall back to PIO mode 691 * should fail, fall back to PIO mode