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authorMattias Nilsson <mattias.i.nilsson@stericsson.com>2011-08-12 04:27:50 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2011-10-24 08:09:18 -0400
commitd65e12d70436cfb2728a78aec3f7bc1cd79eaa34 (patch)
tree1420e6831dc051fb9cc275c1e0499ad6304f1feb /drivers/mfd
parenta592c2e20fe2ba696cc7cd16d02abec8ac16ea41 (diff)
mfd: Initialize DB8500 PRCMU regs
Some clocks may be force enabled when we probe the driver, but they need to be turned off by default so we have a known state. We call this the register initialization function if we need more stuff in there in the future. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/db8500-prcmu.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index dcc690efdc25..e2c4a26a9eb1 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -1840,6 +1840,16 @@ void __init prcmu_early_init(void)
1840 } 1840 }
1841} 1841}
1842 1842
1843static void __init init_prcm_registers(void)
1844{
1845 u32 val;
1846
1847 val = readl(PRCM_A9PL_FORCE_CLKEN);
1848 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
1849 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
1850 writel(val, (PRCM_A9PL_FORCE_CLKEN));
1851}
1852
1843/* 1853/*
1844 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 1854 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
1845 */ 1855 */
@@ -2038,6 +2048,8 @@ static int __init db8500_prcmu_probe(struct platform_device *pdev)
2038 if (ux500_is_svp()) 2048 if (ux500_is_svp())
2039 return -ENODEV; 2049 return -ENODEV;
2040 2050
2051 init_prcm_registers();
2052
2041 /* Clean up the mailbox interrupts after pre-kernel code. */ 2053 /* Clean up the mailbox interrupts after pre-kernel code. */
2042 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 2054 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
2043 2055