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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-01-20 12:37:21 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-20 12:37:21 -0500
commit216f63c41cac9f9f8f181fc19be399293c8c934e (patch)
tree32b793de24f008d79403ac504e27e239767c8932 /drivers/mfd
parentdcd6c92267155e70a94b3927bce681ce74b80d1f (diff)
Revert "ARM: sa1100: Refactor mcp-sa11x0 to use platform resources."
This reverts commit af9081ae64b941d32239b947882cd59ba855c5db. This revert is necessary to revert 5dd7bf59e0e8563265b3e5b33276099ef628fcc7.
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/mcp-sa11x0.c162
1 files changed, 52 insertions, 110 deletions
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index 9adc2eb69492..da4e077a1bee 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -19,7 +19,6 @@
19#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/mfd/mcp.h> 21#include <linux/mfd/mcp.h>
22#include <linux/io.h>
23 22
24#include <mach/dma.h> 23#include <mach/dma.h>
25#include <mach/hardware.h> 24#include <mach/hardware.h>
@@ -27,19 +26,12 @@
27#include <asm/system.h> 26#include <asm/system.h>
28#include <mach/mcp.h> 27#include <mach/mcp.h>
29 28
30/* Register offsets */ 29#include <mach/assabet.h>
31#define MCCR0 0x00 30
32#define MCDR0 0x08
33#define MCDR1 0x0C
34#define MCDR2 0x10
35#define MCSR 0x18
36#define MCCR1 0x00
37 31
38struct mcp_sa11x0 { 32struct mcp_sa11x0 {
39 u32 mccr0; 33 u32 mccr0;
40 u32 mccr1; 34 u32 mccr1;
41 unsigned char *mccr0_base;
42 unsigned char *mccr1_base;
43}; 35};
44 36
45#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp)) 37#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
@@ -47,25 +39,25 @@ struct mcp_sa11x0 {
47static void 39static void
48mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) 40mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
49{ 41{
50 struct mcp_sa11x0 *priv = priv(mcp); 42 unsigned int mccr0;
51 43
52 divisor /= 32; 44 divisor /= 32;
53 45
54 priv->mccr0 &= ~0x00007f00; 46 mccr0 = Ser4MCCR0 & ~0x00007f00;
55 priv->mccr0 |= divisor << 8; 47 mccr0 |= divisor << 8;
56 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); 48 Ser4MCCR0 = mccr0;
57} 49}
58 50
59static void 51static void
60mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) 52mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
61{ 53{
62 struct mcp_sa11x0 *priv = priv(mcp); 54 unsigned int mccr0;
63 55
64 divisor /= 32; 56 divisor /= 32;
65 57
66 priv->mccr0 &= ~0x0000007f; 58 mccr0 = Ser4MCCR0 & ~0x0000007f;
67 priv->mccr0 |= divisor; 59 mccr0 |= divisor;
68 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); 60 Ser4MCCR0 = mccr0;
69} 61}
70 62
71/* 63/*
@@ -79,16 +71,12 @@ mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
79{ 71{
80 int ret = -ETIME; 72 int ret = -ETIME;
81 int i; 73 int i;
82 u32 mcpreg;
83 struct mcp_sa11x0 *priv = priv(mcp);
84 74
85 mcpreg = reg << 17 | MCDR2_Wr | (val & 0xffff); 75 Ser4MCDR2 = reg << 17 | MCDR2_Wr | (val & 0xffff);
86 __raw_writel(mcpreg, priv->mccr0_base + MCDR2);
87 76
88 for (i = 0; i < 2; i++) { 77 for (i = 0; i < 2; i++) {
89 udelay(mcp->rw_timeout); 78 udelay(mcp->rw_timeout);
90 mcpreg = __raw_readl(priv->mccr0_base + MCSR); 79 if (Ser4MCSR & MCSR_CWC) {
91 if (mcpreg & MCSR_CWC) {
92 ret = 0; 80 ret = 0;
93 break; 81 break;
94 } 82 }
@@ -109,18 +97,13 @@ mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
109{ 97{
110 int ret = -ETIME; 98 int ret = -ETIME;
111 int i; 99 int i;
112 u32 mcpreg;
113 struct mcp_sa11x0 *priv = priv(mcp);
114 100
115 mcpreg = reg << 17 | MCDR2_Rd; 101 Ser4MCDR2 = reg << 17 | MCDR2_Rd;
116 __raw_writel(mcpreg, priv->mccr0_base + MCDR2);
117 102
118 for (i = 0; i < 2; i++) { 103 for (i = 0; i < 2; i++) {
119 udelay(mcp->rw_timeout); 104 udelay(mcp->rw_timeout);
120 mcpreg = __raw_readl(priv->mccr0_base + MCSR); 105 if (Ser4MCSR & MCSR_CRC) {
121 if (mcpreg & MCSR_CRC) { 106 ret = Ser4MCDR2 & 0xffff;
122 ret = __raw_readl(priv->mccr0_base + MCDR2)
123 & 0xffff;
124 break; 107 break;
125 } 108 }
126 } 109 }
@@ -133,19 +116,13 @@ mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
133 116
134static void mcp_sa11x0_enable(struct mcp *mcp) 117static void mcp_sa11x0_enable(struct mcp *mcp)
135{ 118{
136 struct mcp_sa11x0 *priv = priv(mcp); 119 Ser4MCSR = -1;
137 120 Ser4MCCR0 |= MCCR0_MCE;
138 __raw_writel(-1, priv->mccr0_base + MCSR);
139 priv->mccr0 |= MCCR0_MCE;
140 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
141} 121}
142 122
143static void mcp_sa11x0_disable(struct mcp *mcp) 123static void mcp_sa11x0_disable(struct mcp *mcp)
144{ 124{
145 struct mcp_sa11x0 *priv = priv(mcp); 125 Ser4MCCR0 &= ~MCCR0_MCE;
146
147 priv->mccr0 &= ~MCCR0_MCE;
148 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
149} 126}
150 127
151/* 128/*
@@ -165,9 +142,6 @@ static int mcp_sa11x0_probe(struct platform_device *pdev)
165 struct mcp_plat_data *data = pdev->dev.platform_data; 142 struct mcp_plat_data *data = pdev->dev.platform_data;
166 struct mcp *mcp; 143 struct mcp *mcp;
167 int ret; 144 int ret;
168 struct mcp_sa11x0 *priv;
169 struct resource *res_mem0, *res_mem1;
170 u32 size0, size1;
171 145
172 if (!data) 146 if (!data)
173 return -ENODEV; 147 return -ENODEV;
@@ -175,59 +149,46 @@ static int mcp_sa11x0_probe(struct platform_device *pdev)
175 if (!data->codec) 149 if (!data->codec)
176 return -ENODEV; 150 return -ENODEV;
177 151
178 res_mem0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 152 if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp"))
179 if (!res_mem0)
180 return -ENODEV;
181 size0 = res_mem0->end - res_mem0->start + 1;
182
183 res_mem1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
184 if (!res_mem1)
185 return -ENODEV;
186 size1 = res_mem1->end - res_mem1->start + 1;
187
188 if (!request_mem_region(res_mem0->start, size0, "sa11x0-mcp"))
189 return -EBUSY; 153 return -EBUSY;
190 154
191 if (!request_mem_region(res_mem1->start, size1, "sa11x0-mcp")) {
192 ret = -EBUSY;
193 goto release;
194 }
195
196 mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0)); 155 mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
197 if (!mcp) { 156 if (!mcp) {
198 ret = -ENOMEM; 157 ret = -ENOMEM;
199 goto release2; 158 goto release;
200 } 159 }
201 160
202 priv = priv(mcp);
203
204 mcp->owner = THIS_MODULE; 161 mcp->owner = THIS_MODULE;
205 mcp->ops = &mcp_sa11x0; 162 mcp->ops = &mcp_sa11x0;
206 mcp->sclk_rate = data->sclk_rate; 163 mcp->sclk_rate = data->sclk_rate;
207 mcp->dma_audio_rd = DDAR_DevAdd(res_mem0->start + MCDR0) 164 mcp->dma_audio_rd = DMA_Ser4MCP0Rd;
208 + DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev; 165 mcp->dma_audio_wr = DMA_Ser4MCP0Wr;
209 mcp->dma_audio_wr = DDAR_DevAdd(res_mem0->start + MCDR0) 166 mcp->dma_telco_rd = DMA_Ser4MCP1Rd;
210 + DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev; 167 mcp->dma_telco_wr = DMA_Ser4MCP1Wr;
211 mcp->dma_telco_rd = DDAR_DevAdd(res_mem0->start + MCDR1)
212 + DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
213 mcp->dma_telco_wr = DDAR_DevAdd(res_mem0->start + MCDR1)
214 + DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
215 mcp->codec = data->codec; 168 mcp->codec = data->codec;
216 169
217 platform_set_drvdata(pdev, mcp); 170 platform_set_drvdata(pdev, mcp);
218 171
172 if (machine_is_assabet()) {
173 ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
174 }
175
176 /*
177 * Setup the PPC unit correctly.
178 */
179 PPDR &= ~PPC_RXD4;
180 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
181 PSDR |= PPC_RXD4;
182 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
183 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
184
219 /* 185 /*
220 * Initialise device. Note that we initially 186 * Initialise device. Note that we initially
221 * set the sampling rate to minimum. 187 * set the sampling rate to minimum.
222 */ 188 */
223 priv->mccr0_base = ioremap(res_mem0->start, size0); 189 Ser4MCSR = -1;
224 priv->mccr1_base = ioremap(res_mem1->start, size1); 190 Ser4MCCR1 = data->mccr1;
225 191 Ser4MCCR0 = data->mccr0 | 0x7f7f;
226 __raw_writel(-1, priv->mccr0_base + MCSR);
227 priv->mccr1 = data->mccr1;
228 priv->mccr0 = data->mccr0 | 0x7f7f;
229 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
230 __raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);
231 192
232 /* 193 /*
233 * Calculate the read/write timeout (us) from the bit clock 194 * Calculate the read/write timeout (us) from the bit clock
@@ -241,49 +202,32 @@ static int mcp_sa11x0_probe(struct platform_device *pdev)
241 if (ret == 0) 202 if (ret == 0)
242 goto out; 203 goto out;
243 204
244 release2:
245 release_mem_region(res_mem1->start, size1);
246 release: 205 release:
247 release_mem_region(res_mem0->start, size0); 206 release_mem_region(0x80060000, 0x60);
248 platform_set_drvdata(pdev, NULL); 207 platform_set_drvdata(pdev, NULL);
249 208
250 out: 209 out:
251 return ret; 210 return ret;
252} 211}
253 212
254static int mcp_sa11x0_remove(struct platform_device *pdev) 213static int mcp_sa11x0_remove(struct platform_device *dev)
255{ 214{
256 struct mcp *mcp = platform_get_drvdata(pdev); 215 struct mcp *mcp = platform_get_drvdata(dev);
257 struct mcp_sa11x0 *priv = priv(mcp);
258 struct resource *res_mem;
259 u32 size;
260 216
261 platform_set_drvdata(pdev, NULL); 217 platform_set_drvdata(dev, NULL);
262 mcp_host_unregister(mcp); 218 mcp_host_unregister(mcp);
219 release_mem_region(0x80060000, 0x60);
263 220
264 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 if (res_mem) {
266 size = res_mem->end - res_mem->start + 1;
267 release_mem_region(res_mem->start, size);
268 }
269 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
270 if (res_mem) {
271 size = res_mem->end - res_mem->start + 1;
272 release_mem_region(res_mem->start, size);
273 }
274 iounmap(priv->mccr0_base);
275 iounmap(priv->mccr1_base);
276 return 0; 221 return 0;
277} 222}
278 223
279static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state) 224static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
280{ 225{
281 struct mcp *mcp = platform_get_drvdata(dev); 226 struct mcp *mcp = platform_get_drvdata(dev);
282 struct mcp_sa11x0 *priv = priv(mcp);
283 u32 mccr0;
284 227
285 mccr0 = priv->mccr0 & ~MCCR0_MCE; 228 priv(mcp)->mccr0 = Ser4MCCR0;
286 __raw_writel(mccr0, priv->mccr0_base + MCCR0); 229 priv(mcp)->mccr1 = Ser4MCCR1;
230 Ser4MCCR0 &= ~MCCR0_MCE;
287 231
288 return 0; 232 return 0;
289} 233}
@@ -291,10 +235,9 @@ static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
291static int mcp_sa11x0_resume(struct platform_device *dev) 235static int mcp_sa11x0_resume(struct platform_device *dev)
292{ 236{
293 struct mcp *mcp = platform_get_drvdata(dev); 237 struct mcp *mcp = platform_get_drvdata(dev);
294 struct mcp_sa11x0 *priv = priv(mcp);
295 238
296 __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); 239 Ser4MCCR1 = priv(mcp)->mccr1;
297 __raw_writel(priv->mccr1, priv->mccr1_base + MCCR1); 240 Ser4MCCR0 = priv(mcp)->mccr0;
298 241
299 return 0; 242 return 0;
300} 243}
@@ -311,7 +254,6 @@ static struct platform_driver mcp_sa11x0_driver = {
311 .resume = mcp_sa11x0_resume, 254 .resume = mcp_sa11x0_resume,
312 .driver = { 255 .driver = {
313 .name = "sa11x0-mcp", 256 .name = "sa11x0-mcp",
314 .owner = THIS_MODULE,
315 }, 257 },
316}; 258};
317 259