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authorPhilipp Zabel <philipp.zabel@gmail.com>2009-06-05 12:31:01 -0400
committerSamuel Ortiz <sameol@linux.intel.com>2009-06-17 13:41:39 -0400
commit6483c1b5e1a6e3489640a1376e951395982e9615 (patch)
tree48dfc13997457dfbd7927762909c9b4dcab5643c /drivers/mfd/asic3.c
parent9e5aca58c2d2202937939dad8f9ce5d789ae4de8 (diff)
mfd: asic3: add asic3_set_register common operation
Used to configure single bits of the SDHWCTRL_SDCONF and EXTCF_RESET/SELECT registers needed for DS1WM, MMC/SDIO and PCMCIA functionality. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/asic3.c')
-rw-r--r--drivers/mfd/asic3.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 9e485459f63b..ad3c59135990 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -52,6 +52,21 @@ static inline u32 asic3_read_register(struct asic3 *asic,
52 (reg >> asic->bus_shift)); 52 (reg >> asic->bus_shift));
53} 53}
54 54
55void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
56{
57 unsigned long flags;
58 u32 val;
59
60 spin_lock_irqsave(&asic->lock, flags);
61 val = asic3_read_register(asic, reg);
62 if (set)
63 val |= bits;
64 else
65 val &= ~bits;
66 asic3_write_register(asic, reg, val);
67 spin_unlock_irqrestore(&asic->lock, flags);
68}
69
55/* IRQs */ 70/* IRQs */
56#define MAX_ASIC_ISR_LOOPS 20 71#define MAX_ASIC_ISR_LOOPS 20
57#define ASIC3_GPIO_BASE_INCR \ 72#define ASIC3_GPIO_BASE_INCR \