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authorAlex Dubov <oakad@yahoo.com>2008-03-19 20:01:08 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-03-19 21:53:37 -0400
commitcf821e8f53e3d147ebae03c8c710d2b8842d88a1 (patch)
treecfe5330049c6f86bc67950fbea1e8b11fac9eaae /drivers/memstick
parent962ee1b10bff5e99e9ecb2a5f4e6399a0214c9cf (diff)
memstick: optimize setup of JMicron host parameters
Set correct clock management values to improve over-all performance. Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/memstick')
-rw-r--r--drivers/memstick/host/jmb38x_ms.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/drivers/memstick/host/jmb38x_ms.c b/drivers/memstick/host/jmb38x_ms.c
index f91037d50422..8770a5fac3b6 100644
--- a/drivers/memstick/host/jmb38x_ms.c
+++ b/drivers/memstick/host/jmb38x_ms.c
@@ -131,6 +131,12 @@ struct jmb38x_ms {
131#define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000 131#define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
132#define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000 132#define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
133 133
134#define CLOCK_CONTROL_40MHZ 0x00000001
135#define CLOCK_CONTROL_50MHZ 0x00000002
136#define CLOCK_CONTROL_60MHZ 0x00000008
137#define CLOCK_CONTROL_62_5MHZ 0x0000000c
138#define CLOCK_CONTROL_OFF 0x00000000
139
134enum { 140enum {
135 CMD_READY = 0x01, 141 CMD_READY = 0x01,
136 FIFO_READY = 0x02, 142 FIFO_READY = 0x02,
@@ -607,19 +613,18 @@ static void jmb38x_ms_reset(struct jmb38x_ms_host *host)
607{ 613{
608 unsigned int host_ctl = readl(host->addr + HOST_CONTROL); 614 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
609 615
610 writel(host_ctl | HOST_CONTROL_RESET_REQ | HOST_CONTROL_RESET, 616 writel(HOST_CONTROL_RESET_REQ, host->addr + HOST_CONTROL);
611 host->addr + HOST_CONTROL);
612 617
613 while (HOST_CONTROL_RESET_REQ 618 while (HOST_CONTROL_RESET_REQ
614 & (host_ctl = readl(host->addr + HOST_CONTROL))) { 619 & (host_ctl = readl(host->addr + HOST_CONTROL))) {
615 ndelay(100); 620 ndelay(20);
616 dev_dbg(&host->chip->pdev->dev, "reset\n"); 621 dev_dbg(&host->chip->pdev->dev, "reset %08x\n", host_ctl);
617 } 622 }
618 623
619 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE); 624 writel(HOST_CONTROL_RESET, host->addr + HOST_CONTROL);
625 mmiowb();
620 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE); 626 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
621 627 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
622 dev_dbg(&host->chip->pdev->dev, "reset\n");
623} 628}
624 629
625static void jmb38x_ms_set_param(struct memstick_host *msh, 630static void jmb38x_ms_set_param(struct memstick_host *msh,
@@ -627,10 +632,8 @@ static void jmb38x_ms_set_param(struct memstick_host *msh,
627 int value) 632 int value)
628{ 633{
629 struct jmb38x_ms_host *host = memstick_priv(msh); 634 struct jmb38x_ms_host *host = memstick_priv(msh);
630 unsigned int host_ctl; 635 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
631 unsigned long flags; 636 unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0;
632
633 spin_lock_irqsave(&host->lock, flags);
634 637
635 switch (param) { 638 switch (param) {
636 case MEMSTICK_POWER: 639 case MEMSTICK_POWER:
@@ -638,60 +641,57 @@ static void jmb38x_ms_set_param(struct memstick_host *msh,
638 jmb38x_ms_reset(host); 641 jmb38x_ms_reset(host);
639 642
640 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1 643 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
641 : PAD_PU_PD_ON_MS_SOCK0, 644 : PAD_PU_PD_ON_MS_SOCK0,
642 host->addr + PAD_PU_PD); 645 host->addr + PAD_PU_PD);
643 646
644 writel(PAD_OUTPUT_ENABLE_MS, 647 writel(PAD_OUTPUT_ENABLE_MS,
645 host->addr + PAD_OUTPUT_ENABLE); 648 host->addr + PAD_OUTPUT_ENABLE);
646 649
647 host_ctl = readl(host->addr + HOST_CONTROL); 650 host_ctl = 7;
648 host_ctl |= 7; 651 host_ctl |= HOST_CONTROL_POWER_EN
649 writel(host_ctl | (HOST_CONTROL_POWER_EN 652 | HOST_CONTROL_CLOCK_EN;
650 | HOST_CONTROL_CLOCK_EN), 653 writel(host_ctl, host->addr + HOST_CONTROL);
651 host->addr + HOST_CONTROL);
652 654
653 dev_dbg(&host->chip->pdev->dev, "power on\n"); 655 dev_dbg(&host->chip->pdev->dev, "power on\n");
654 } else if (value == MEMSTICK_POWER_OFF) { 656 } else if (value == MEMSTICK_POWER_OFF) {
655 writel(readl(host->addr + HOST_CONTROL) 657 host_ctl &= ~(HOST_CONTROL_POWER_EN
656 & ~(HOST_CONTROL_POWER_EN 658 | HOST_CONTROL_CLOCK_EN);
657 | HOST_CONTROL_CLOCK_EN), 659 writel(host_ctl, host->addr + HOST_CONTROL);
658 host->addr + HOST_CONTROL);
659 writel(0, host->addr + PAD_OUTPUT_ENABLE); 660 writel(0, host->addr + PAD_OUTPUT_ENABLE);
660 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD); 661 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
661 dev_dbg(&host->chip->pdev->dev, "power off\n"); 662 dev_dbg(&host->chip->pdev->dev, "power off\n");
662 } 663 }
663 break; 664 break;
664 case MEMSTICK_INTERFACE: 665 case MEMSTICK_INTERFACE:
665 /* jmb38x_ms_reset(host); */
666
667 host_ctl = readl(host->addr + HOST_CONTROL);
668 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT); 666 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
669 /* host_ctl |= 7; */
670 667
671 if (value == MEMSTICK_SERIAL) { 668 if (value == MEMSTICK_SERIAL) {
672 host_ctl &= ~HOST_CONTROL_FAST_CLK; 669 host_ctl &= ~HOST_CONTROL_FAST_CLK;
673 host_ctl |= HOST_CONTROL_IF_SERIAL 670 host_ctl |= HOST_CONTROL_IF_SERIAL
674 << HOST_CONTROL_IF_SHIFT; 671 << HOST_CONTROL_IF_SHIFT;
675 host_ctl |= HOST_CONTROL_REI; 672 host_ctl |= HOST_CONTROL_REI;
676 writel(0, host->addr + CLOCK_DELAY); 673 clock_ctl = CLOCK_CONTROL_40MHZ;
674 clock_delay = 0;
677 } else if (value == MEMSTICK_PAR4) { 675 } else if (value == MEMSTICK_PAR4) {
678 host_ctl |= HOST_CONTROL_FAST_CLK; 676 host_ctl |= HOST_CONTROL_FAST_CLK;
679 host_ctl |= HOST_CONTROL_IF_PAR4 677 host_ctl |= HOST_CONTROL_IF_PAR4
680 << HOST_CONTROL_IF_SHIFT; 678 << HOST_CONTROL_IF_SHIFT;
681 host_ctl &= ~HOST_CONTROL_REI; 679 host_ctl &= ~HOST_CONTROL_REI;
682 writel(4, host->addr + CLOCK_DELAY); 680 clock_ctl = CLOCK_CONTROL_40MHZ;
681 clock_delay = 4;
683 } else if (value == MEMSTICK_PAR8) { 682 } else if (value == MEMSTICK_PAR8) {
684 host_ctl |= HOST_CONTROL_FAST_CLK; 683 host_ctl |= HOST_CONTROL_FAST_CLK;
685 host_ctl |= HOST_CONTROL_IF_PAR8 684 host_ctl |= HOST_CONTROL_IF_PAR8
686 << HOST_CONTROL_IF_SHIFT; 685 << HOST_CONTROL_IF_SHIFT;
687 host_ctl &= ~HOST_CONTROL_REI; 686 host_ctl &= ~HOST_CONTROL_REI;
688 writel(4, host->addr + CLOCK_DELAY); 687 clock_ctl = CLOCK_CONTROL_60MHZ;
688 clock_delay = 0;
689 } 689 }
690 writel(host_ctl, host->addr + HOST_CONTROL); 690 writel(host_ctl, host->addr + HOST_CONTROL);
691 writel(clock_ctl, host->addr + CLOCK_CONTROL);
692 writel(clock_delay, host->addr + CLOCK_DELAY);
691 break; 693 break;
692 }; 694 };
693
694 spin_unlock_irqrestore(&host->lock, flags);
695} 695}
696 696
697#ifdef CONFIG_PM 697#ifdef CONFIG_PM