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authorMauro Carvalho Chehab <mchehab@redhat.com>2013-04-28 10:47:51 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2013-06-08 21:11:39 -0400
commitab5060cdb8829c0503b7be2b239b52e9a25063b4 (patch)
tree54efea67e42938683bf89572e47932b27936ad6d /drivers/media
parent949dd08d92cdbbe7f2560f06ac297eee54b7ea49 (diff)
[media] drxk_hard: Remove most 80-cols checkpatch warnings
X-Patchwork-Delegate: mchehab@redhat.com There are a few cases where breaking the code into separate lines make it worse to read. However, on several places, breaking it to make checkpatch.pl happier is OK and improves code readability. So, break longer lines where that won't cause harm. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/dvb-frontends/drxk_hard.c406
1 files changed, 275 insertions, 131 deletions
diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c
index 7f4b5145a8aa..082014de6875 100644
--- a/drivers/media/dvb-frontends/drxk_hard.c
+++ b/drivers/media/dvb-frontends/drxk_hard.c
@@ -189,8 +189,10 @@ static inline u32 Frac28a(u32 a, u32 c)
189 u32 R0 = 0; 189 u32 R0 = 0;
190 190
191 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ 191 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
192 Q1 = a / c; /* integer part, only the 4 least significant bits 192 Q1 = a / c; /*
193 will be visible in the result */ 193 * integer part, only the 4 least significant
194 * bits will be visible in the result
195 */
194 196
195 /* division using radix 16, 7 nibbles in the result */ 197 /* division using radix 16, 7 nibbles in the result */
196 for (i = 0; i < 7; i++) { 198 for (i = 0; i < 7; i++) {
@@ -783,7 +785,8 @@ static int drxx_open(struct drxk_state *state)
783 785
784 dprintk(1, "\n"); 786 dprintk(1, "\n");
785 /* stop lock indicator process */ 787 /* stop lock indicator process */
786 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 788 status = write16(state, SCU_RAM_GPIO__A,
789 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
787 if (status < 0) 790 if (status < 0)
788 goto error; 791 goto error;
789 /* Check device id */ 792 /* Check device id */
@@ -817,7 +820,8 @@ static int get_device_capabilities(struct drxk_state *state)
817 820
818 /* driver 0.9.0 */ 821 /* driver 0.9.0 */
819 /* stop lock indicator process */ 822 /* stop lock indicator process */
820 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 823 status = write16(state, SCU_RAM_GPIO__A,
824 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
821 if (status < 0) 825 if (status < 0)
822 goto error; 826 goto error;
823 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 827 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
@@ -1055,22 +1059,28 @@ static int hi_cfg_command(struct drxk_state *state)
1055 1059
1056 mutex_lock(&state->mutex); 1060 mutex_lock(&state->mutex);
1057 1061
1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_hi_cfg_timeout); 1062 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1063 state->m_hi_cfg_timeout);
1059 if (status < 0) 1064 if (status < 0)
1060 goto error; 1065 goto error;
1061 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_hi_cfg_ctrl); 1066 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1067 state->m_hi_cfg_ctrl);
1062 if (status < 0) 1068 if (status < 0)
1063 goto error; 1069 goto error;
1064 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_hi_cfg_wake_up_key); 1070 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1071 state->m_hi_cfg_wake_up_key);
1065 if (status < 0) 1072 if (status < 0)
1066 goto error; 1073 goto error;
1067 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_hi_cfg_bridge_delay); 1074 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1075 state->m_hi_cfg_bridge_delay);
1068 if (status < 0) 1076 if (status < 0)
1069 goto error; 1077 goto error;
1070 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_hi_cfg_timing_div); 1078 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1079 state->m_hi_cfg_timing_div);
1071 if (status < 0) 1080 if (status < 0)
1072 goto error; 1081 goto error;
1073 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1082 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1083 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1074 if (status < 0) 1084 if (status < 0)
1075 goto error; 1085 goto error;
1076 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); 1086 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
@@ -1109,7 +1119,8 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1109 state->m_enable_parallel ? "parallel" : "serial"); 1119 state->m_enable_parallel ? "parallel" : "serial");
1110 1120
1111 /* stop lock indicator process */ 1121 /* stop lock indicator process */
1112 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1122 status = write16(state, SCU_RAM_GPIO__A,
1123 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1113 if (status < 0) 1124 if (status < 0)
1114 goto error; 1125 goto error;
1115 1126
@@ -1181,25 +1192,32 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1181 1192
1182 if (state->m_enable_parallel == true) { 1193 if (state->m_enable_parallel == true) {
1183 /* paralel -> enable MD1 to MD7 */ 1194 /* paralel -> enable MD1 to MD7 */
1184 status = write16(state, SIO_PDR_MD1_CFG__A, sio_pdr_mdx_cfg); 1195 status = write16(state, SIO_PDR_MD1_CFG__A,
1196 sio_pdr_mdx_cfg);
1185 if (status < 0) 1197 if (status < 0)
1186 goto error; 1198 goto error;
1187 status = write16(state, SIO_PDR_MD2_CFG__A, sio_pdr_mdx_cfg); 1199 status = write16(state, SIO_PDR_MD2_CFG__A,
1200 sio_pdr_mdx_cfg);
1188 if (status < 0) 1201 if (status < 0)
1189 goto error; 1202 goto error;
1190 status = write16(state, SIO_PDR_MD3_CFG__A, sio_pdr_mdx_cfg); 1203 status = write16(state, SIO_PDR_MD3_CFG__A,
1204 sio_pdr_mdx_cfg);
1191 if (status < 0) 1205 if (status < 0)
1192 goto error; 1206 goto error;
1193 status = write16(state, SIO_PDR_MD4_CFG__A, sio_pdr_mdx_cfg); 1207 status = write16(state, SIO_PDR_MD4_CFG__A,
1208 sio_pdr_mdx_cfg);
1194 if (status < 0) 1209 if (status < 0)
1195 goto error; 1210 goto error;
1196 status = write16(state, SIO_PDR_MD5_CFG__A, sio_pdr_mdx_cfg); 1211 status = write16(state, SIO_PDR_MD5_CFG__A,
1212 sio_pdr_mdx_cfg);
1197 if (status < 0) 1213 if (status < 0)
1198 goto error; 1214 goto error;
1199 status = write16(state, SIO_PDR_MD6_CFG__A, sio_pdr_mdx_cfg); 1215 status = write16(state, SIO_PDR_MD6_CFG__A,
1216 sio_pdr_mdx_cfg);
1200 if (status < 0) 1217 if (status < 0)
1201 goto error; 1218 goto error;
1202 status = write16(state, SIO_PDR_MD7_CFG__A, sio_pdr_mdx_cfg); 1219 status = write16(state, SIO_PDR_MD7_CFG__A,
1220 sio_pdr_mdx_cfg);
1203 if (status < 0) 1221 if (status < 0)
1204 goto error; 1222 goto error;
1205 } else { 1223 } else {
@@ -1390,7 +1408,8 @@ static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1390 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1408 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1391 do { 1409 do {
1392 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1410 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1393 if ((status >= 0 && data == desired_status) || time_is_after_jiffies(end)) 1411 if ((status >= 0 && data == desired_status)
1412 || time_is_after_jiffies(end))
1394 break; 1413 break;
1395 usleep_range(1000, 2000); 1414 usleep_range(1000, 2000);
1396 } while (1); 1415 } while (1);
@@ -1487,7 +1506,8 @@ static int scu_command(struct drxk_state *state,
1487 int ii; 1506 int ii;
1488 1507
1489 for (ii = result_len - 1; ii >= 0; ii -= 1) { 1508 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1490 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); 1509 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1510 &result[ii]);
1491 if (status < 0) 1511 if (status < 0)
1492 goto error; 1512 goto error;
1493 } 1513 }
@@ -1683,11 +1703,17 @@ static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1683 goto error; 1703 goto error;
1684 if (data == SCU_COMM_EXEC_ACTIVE) { 1704 if (data == SCU_COMM_EXEC_ACTIVE) {
1685 /* Send OFDM stop command */ 1705 /* Send OFDM stop command */
1686 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result); 1706 status = scu_command(state,
1707 SCU_RAM_COMMAND_STANDARD_OFDM
1708 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1709 0, NULL, 1, &cmd_result);
1687 if (status < 0) 1710 if (status < 0)
1688 goto error; 1711 goto error;
1689 /* Send OFDM reset command */ 1712 /* Send OFDM reset command */
1690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result); 1713 status = scu_command(state,
1714 SCU_RAM_COMMAND_STANDARD_OFDM
1715 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1716 0, NULL, 1, &cmd_result);
1691 if (status < 0) 1717 if (status < 0)
1692 goto error; 1718 goto error;
1693 } 1719 }
@@ -1733,7 +1759,8 @@ static int setoperation_mode(struct drxk_state *state,
1733 */ 1759 */
1734 1760
1735 /* disable HW lock indicator */ 1761 /* disable HW lock indicator */
1736 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1762 status = write16(state, SCU_RAM_GPIO__A,
1763 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1737 if (status < 0) 1764 if (status < 0)
1738 goto error; 1765 goto error;
1739 1766
@@ -2083,7 +2110,8 @@ static int mpegts_dto_setup(struct drxk_state *state,
2083 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); 2110 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2084 if (status < 0) 2111 if (status < 0)
2085 goto error; 2112 goto error;
2086 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fec_oc_tmd_int_upd_rate); 2113 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2114 fec_oc_tmd_int_upd_rate);
2087 if (status < 0) 2115 if (status < 0)
2088 goto error; 2116 goto error;
2089 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); 2117 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
@@ -2193,17 +2221,21 @@ static int set_agc_rf(struct drxk_state *state,
2193 2221
2194 /* Set TOP, only if IF-AGC is in AUTO mode */ 2222 /* Set TOP, only if IF-AGC is in AUTO mode */
2195 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) 2223 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO)
2196 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->top); 2224 status = write16(state,
2225 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2226 p_agc_cfg->top);
2197 if (status < 0) 2227 if (status < 0)
2198 goto error; 2228 goto error;
2199 2229
2200 /* Cut-Off current */ 2230 /* Cut-Off current */
2201 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, p_agc_cfg->cut_off_current); 2231 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2232 p_agc_cfg->cut_off_current);
2202 if (status < 0) 2233 if (status < 0)
2203 goto error; 2234 goto error;
2204 2235
2205 /* Max. output level */ 2236 /* Max. output level */
2206 status = write16(state, SCU_RAM_AGC_RF_MAX__A, p_agc_cfg->max_output_level); 2237 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2238 p_agc_cfg->max_output_level);
2207 if (status < 0) 2239 if (status < 0)
2208 goto error; 2240 goto error;
2209 2241
@@ -2238,7 +2270,8 @@ static int set_agc_rf(struct drxk_state *state,
2238 goto error; 2270 goto error;
2239 2271
2240 /* Write value to output pin */ 2272 /* Write value to output pin */
2241 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, p_agc_cfg->output_level); 2273 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2274 p_agc_cfg->output_level);
2242 if (status < 0) 2275 if (status < 0)
2243 goto error; 2276 goto error;
2244 break; 2277 break;
@@ -2332,7 +2365,8 @@ static int set_agc_if(struct drxk_state *state,
2332 if (p_rf_agc_settings == NULL) 2365 if (p_rf_agc_settings == NULL)
2333 return -1; 2366 return -1;
2334 /* Restore TOP */ 2367 /* Restore TOP */
2335 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_rf_agc_settings->top); 2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2369 p_rf_agc_settings->top);
2336 if (status < 0) 2370 if (status < 0)
2337 goto error; 2371 goto error;
2338 break; 2372 break;
@@ -2365,7 +2399,8 @@ static int set_agc_if(struct drxk_state *state,
2365 goto error; 2399 goto error;
2366 2400
2367 /* Write value to output pin */ 2401 /* Write value to output pin */
2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->output_level); 2402 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2403 p_agc_cfg->output_level);
2369 if (status < 0) 2404 if (status < 0)
2370 goto error; 2405 goto error;
2371 break; 2406 break;
@@ -2470,16 +2505,20 @@ static int get_dvbt_signal_to_noise(struct drxk_state *state,
2470 2505
2471 dprintk(1, "\n"); 2506 dprintk(1, "\n");
2472 2507
2473 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &eq_reg_td_tps_pwr_ofs); 2508 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2509 &eq_reg_td_tps_pwr_ofs);
2474 if (status < 0) 2510 if (status < 0)
2475 goto error; 2511 goto error;
2476 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &eq_reg_td_req_smb_cnt); 2512 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2513 &eq_reg_td_req_smb_cnt);
2477 if (status < 0) 2514 if (status < 0)
2478 goto error; 2515 goto error;
2479 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &eq_reg_td_sqr_err_exp); 2516 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2517 &eq_reg_td_sqr_err_exp);
2480 if (status < 0) 2518 if (status < 0)
2481 goto error; 2519 goto error;
2482 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &reg_data); 2520 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2521 &reg_data);
2483 if (status < 0) 2522 if (status < 0)
2484 goto error; 2523 goto error;
2485 /* Extend SQR_ERR_I operational range */ 2524 /* Extend SQR_ERR_I operational range */
@@ -2497,7 +2536,8 @@ static int get_dvbt_signal_to_noise(struct drxk_state *state,
2497 (eq_reg_td_sqr_err_q < 0x00000FFFUL)) 2536 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2498 eq_reg_td_sqr_err_q += 0x00010000UL; 2537 eq_reg_td_sqr_err_q += 0x00010000UL;
2499 2538
2500 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmission_params); 2539 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2540 &transmission_params);
2501 if (status < 0) 2541 if (status < 0)
2502 goto error; 2542 goto error;
2503 2543
@@ -2604,12 +2644,14 @@ static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2604 status = get_dvbt_signal_to_noise(state, &signal_to_noise); 2644 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2605 if (status < 0) 2645 if (status < 0)
2606 break; 2646 break;
2607 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &constellation); 2647 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2648 &constellation);
2608 if (status < 0) 2649 if (status < 0)
2609 break; 2650 break;
2610 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2651 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2611 2652
2612 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &code_rate); 2653 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2654 &code_rate);
2613 if (status < 0) 2655 if (status < 0)
2614 break; 2656 break;
2615 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2657 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
@@ -2723,15 +2765,18 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2723 if (state->no_i2c_bridge) 2765 if (state->no_i2c_bridge)
2724 return 0; 2766 return 0;
2725 2767
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2768 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2769 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2727 if (status < 0) 2770 if (status < 0)
2728 goto error; 2771 goto error;
2729 if (b_enable_bridge) { 2772 if (b_enable_bridge) {
2730 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2773 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2774 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2731 if (status < 0) 2775 if (status < 0)
2732 goto error; 2776 goto error;
2733 } else { 2777 } else {
2734 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); 2778 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2779 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2735 if (status < 0) 2780 if (status < 0)
2736 goto error; 2781 goto error;
2737 } 2782 }
@@ -3013,7 +3058,8 @@ static int init_agc(struct drxk_state *state, bool is_dtv)
3013 ingain_tgt_max = 5119; 3058 ingain_tgt_max = 5119;
3014 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; 3059 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3015 3060
3016 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fast_clp_ctrl_delay); 3061 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3062 fast_clp_ctrl_delay);
3017 if (status < 0) 3063 if (status < 0)
3018 goto error; 3064 goto error;
3019 3065
@@ -3029,10 +3075,12 @@ static int init_agc(struct drxk_state *state, bool is_dtv)
3029 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); 3075 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3030 if (status < 0) 3076 if (status < 0)
3031 goto error; 3077 goto error;
3032 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min); 3078 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3079 if_iaccu_hi_tgt_min);
3033 if (status < 0) 3080 if (status < 0)
3034 goto error; 3081 goto error;
3035 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, if_iaccu_hi_tgt_max); 3082 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3083 if_iaccu_hi_tgt_max);
3036 if (status < 0) 3084 if (status < 0)
3037 goto error; 3085 goto error;
3038 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3086 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
@@ -3054,10 +3102,12 @@ static int init_agc(struct drxk_state *state, bool is_dtv)
3054 if (status < 0) 3102 if (status < 0)
3055 goto error; 3103 goto error;
3056 3104
3057 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min); 3105 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3106 ki_innergain_min);
3058 if (status < 0) 3107 if (status < 0)
3059 goto error; 3108 goto error;
3060 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, if_iaccu_hi_tgt); 3109 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3110 if_iaccu_hi_tgt);
3061 if (status < 0) 3111 if (status < 0)
3062 goto error; 3112 goto error;
3063 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); 3113 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
@@ -3158,7 +3208,8 @@ static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3158 if (packet_err == NULL) 3208 if (packet_err == NULL)
3159 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3209 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3160 else 3210 else
3161 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packet_err); 3211 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3212 packet_err);
3162 if (status < 0) 3213 if (status < 0)
3163 pr_err("Error %d on %s\n", status, __func__); 3214 pr_err("Error %d on %s\n", status, __func__);
3164 return status; 3215 return status;
@@ -3332,7 +3383,7 @@ static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3332} 3383}
3333 3384
3334static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, 3385static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3335 struct drxk_cfg_dvbt_echo_thres_t *echo_thres) 3386 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3336{ 3387{
3337 u16 data = 0; 3388 u16 data = 0;
3338 int status; 3389 int status;
@@ -3421,7 +3472,8 @@ static int dvbt_activate_presets(struct drxk_state *state)
3421 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); 3472 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3422 if (status < 0) 3473 if (status < 0)
3423 goto error; 3474 goto error;
3424 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbt_if_agc_cfg.ingain_tgt_max); 3475 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3476 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3425error: 3477error:
3426 if (status < 0) 3478 if (status < 0)
3427 pr_err("Error %d on %s\n", status, __func__); 3479 pr_err("Error %d on %s\n", status, __func__);
@@ -3451,12 +3503,17 @@ static int set_dvbt_standard(struct drxk_state *state,
3451 /* added antenna switch */ 3503 /* added antenna switch */
3452 switch_antenna_to_dvbt(state); 3504 switch_antenna_to_dvbt(state);
3453 /* send OFDM reset command */ 3505 /* send OFDM reset command */
3454 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result); 3506 status = scu_command(state,
3507 SCU_RAM_COMMAND_STANDARD_OFDM
3508 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3509 0, NULL, 1, &cmd_result);
3455 if (status < 0) 3510 if (status < 0)
3456 goto error; 3511 goto error;
3457 3512
3458 /* send OFDM setenv command */ 3513 /* send OFDM setenv command */
3459 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmd_result); 3514 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3515 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3516 0, NULL, 1, &cmd_result);
3460 if (status < 0) 3517 if (status < 0)
3461 goto error; 3518 goto error;
3462 3519
@@ -3510,7 +3567,7 @@ static int set_dvbt_standard(struct drxk_state *state,
3510 status = write16(state, IQM_RC_STRETCH__A, 16); 3567 status = write16(state, IQM_RC_STRETCH__A, 16);
3511 if (status < 0) 3568 if (status < 0)
3512 goto error; 3569 goto error;
3513 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3570 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3514 if (status < 0) 3571 if (status < 0)
3515 goto error; 3572 goto error;
3516 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3573 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
@@ -3531,7 +3588,8 @@ static int set_dvbt_standard(struct drxk_state *state,
3531 if (status < 0) 3588 if (status < 0)
3532 goto error; 3589 goto error;
3533 3590
3534 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3591 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3592 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3535 if (status < 0) 3593 if (status < 0)
3536 goto error; 3594 goto error;
3537 3595
@@ -3585,7 +3643,8 @@ static int set_dvbt_standard(struct drxk_state *state,
3585 3643
3586 if (!state->m_drxk_a3_rom_code) { 3644 if (!state->m_drxk_a3_rom_code) {
3587 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ 3645 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
3588 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); 3646 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3647 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3589 if (status < 0) 3648 if (status < 0)
3590 goto error; 3649 goto error;
3591 } 3650 }
@@ -3650,7 +3709,9 @@ static int dvbt_start(struct drxk_state *state)
3650 /* start correct processes to get in lock */ 3709 /* start correct processes to get in lock */
3651 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3710 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3652 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3711 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3653 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); 3712 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3713 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3714 0, 0, 0);
3654 if (status < 0) 3715 if (status < 0)
3655 goto error; 3716 goto error;
3656 /* start FEC OC */ 3717 /* start FEC OC */
@@ -3686,9 +3747,12 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3686 u16 param1; 3747 u16 param1;
3687 int status; 3748 int status;
3688 3749
3689 dprintk(1, "IF =%d, TFO = %d\n", intermediate_freqk_hz, tuner_freq_offset); 3750 dprintk(1, "IF =%d, TFO = %d\n",
3751 intermediate_freqk_hz, tuner_freq_offset);
3690 3752
3691 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result); 3753 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3754 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3755 0, NULL, 1, &cmd_result);
3692 if (status < 0) 3756 if (status < 0)
3693 goto error; 3757 goto error;
3694 3758
@@ -3711,7 +3775,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3711 if (status < 0) 3775 if (status < 0)
3712 goto error; 3776 goto error;
3713 3777
3714 /*== Write channel settings to device =====================================*/ 3778 /*== Write channel settings to device ================================*/
3715 3779
3716 /* mode */ 3780 /* mode */
3717 switch (state->props.transmission_mode) { 3781 switch (state->props.transmission_mode) {
@@ -3834,71 +3898,92 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3834 break; 3898 break;
3835 } 3899 }
3836 3900
3837 /* SAW filter selection: normaly not necesarry, but if wanted 3901 /*
3838 the application can select a SAW filter via the driver by using UIOs */ 3902 * SAW filter selection: normaly not necesarry, but if wanted
3903 * the application can select a SAW filter via the driver by
3904 * using UIOs
3905 */
3906
3839 /* First determine real bandwidth (Hz) */ 3907 /* First determine real bandwidth (Hz) */
3840 /* Also set delay for impulse noise cruncher */ 3908 /* Also set delay for impulse noise cruncher */
3841 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed 3909 /*
3842 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC 3910 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3843 functions */ 3911 * changed by SC for fix for some 8K,1/8 guard but is restored by
3912 * InitEC and ResetEC functions
3913 */
3844 switch (state->props.bandwidth_hz) { 3914 switch (state->props.bandwidth_hz) {
3845 case 0: 3915 case 0:
3846 state->props.bandwidth_hz = 8000000; 3916 state->props.bandwidth_hz = 8000000;
3847 /* fall though */ 3917 /* fall though */
3848 case 8000000: 3918 case 8000000:
3849 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3919 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3850 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); 3920 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3921 3052);
3851 if (status < 0) 3922 if (status < 0)
3852 goto error; 3923 goto error;
3853 /* cochannel protection for PAL 8 MHz */ 3924 /* cochannel protection for PAL 8 MHz */
3854 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); 3925 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3926 7);
3855 if (status < 0) 3927 if (status < 0)
3856 goto error; 3928 goto error;
3857 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); 3929 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3930 7);
3858 if (status < 0) 3931 if (status < 0)
3859 goto error; 3932 goto error;
3860 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); 3933 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3934 7);
3861 if (status < 0) 3935 if (status < 0)
3862 goto error; 3936 goto error;
3863 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3937 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3938 1);
3864 if (status < 0) 3939 if (status < 0)
3865 goto error; 3940 goto error;
3866 break; 3941 break;
3867 case 7000000: 3942 case 7000000:
3868 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3943 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3869 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); 3944 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3945 3491);
3870 if (status < 0) 3946 if (status < 0)
3871 goto error; 3947 goto error;
3872 /* cochannel protection for PAL 7 MHz */ 3948 /* cochannel protection for PAL 7 MHz */
3873 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); 3949 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3950 8);
3874 if (status < 0) 3951 if (status < 0)
3875 goto error; 3952 goto error;
3876 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); 3953 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3954 8);
3877 if (status < 0) 3955 if (status < 0)
3878 goto error; 3956 goto error;
3879 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); 3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3958 4);
3880 if (status < 0) 3959 if (status < 0)
3881 goto error; 3960 goto error;
3882 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3962 1);
3883 if (status < 0) 3963 if (status < 0)
3884 goto error; 3964 goto error;
3885 break; 3965 break;
3886 case 6000000: 3966 case 6000000:
3887 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3967 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3888 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); 3968 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3969 4073);
3889 if (status < 0) 3970 if (status < 0)
3890 goto error; 3971 goto error;
3891 /* cochannel protection for NTSC 6 MHz */ 3972 /* cochannel protection for NTSC 6 MHz */
3892 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); 3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3974 19);
3893 if (status < 0) 3975 if (status < 0)
3894 goto error; 3976 goto error;
3895 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); 3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3978 19);
3896 if (status < 0) 3979 if (status < 0)
3897 goto error; 3980 goto error;
3898 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); 3981 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3982 14);
3899 if (status < 0) 3983 if (status < 0)
3900 goto error; 3984 goto error;
3901 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3986 1);
3902 if (status < 0) 3987 if (status < 0)
3903 goto error; 3988 goto error;
3904 break; 3989 break;
@@ -3914,13 +3999,16 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3914 ((SysFreq / BandWidth) * (2^21)) - (2^23) 3999 ((SysFreq / BandWidth) * (2^21)) - (2^23)
3915 */ 4000 */
3916 /* (SysFreq / BandWidth) * (2^28) */ 4001 /* (SysFreq / BandWidth) * (2^28) */
3917 /* assert (MAX(sysClk)/MIN(bandwidth) < 16) 4002 /*
3918 => assert(MAX(sysClk) < 16*MIN(bandwidth)) 4003 * assert (MAX(sysClk)/MIN(bandwidth) < 16)
3919 => assert(109714272 > 48000000) = true so Frac 28 can be used */ 4004 * => assert(MAX(sysClk) < 16*MIN(bandwidth))
4005 * => assert(109714272 > 48000000) = true
4006 * so Frac 28 can be used
4007 */
3920 iqm_rc_rate_ofs = Frac28a((u32) 4008 iqm_rc_rate_ofs = Frac28a((u32)
3921 ((state->m_sys_clock_freq * 4009 ((state->m_sys_clock_freq *
3922 1000) / 3), bandwidth); 4010 1000) / 3), bandwidth);
3923 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 4011 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3924 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) 4012 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3925 iqm_rc_rate_ofs += 0x80L; 4013 iqm_rc_rate_ofs += 0x80L;
3926 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; 4014 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
@@ -3942,11 +4030,12 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3942 if (status < 0) 4030 if (status < 0)
3943 goto error; 4031 goto error;
3944#endif 4032#endif
3945 status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true); 4033 status = set_frequency_shifter(state, intermediate_freqk_hz,
4034 tuner_freq_offset, true);
3946 if (status < 0) 4035 if (status < 0)
3947 goto error; 4036 goto error;
3948 4037
3949 /*== start SC, write channel settings to SC ===============================*/ 4038 /*== start SC, write channel settings to SC ==========================*/
3950 4039
3951 /* Activate SCU to enable SCU commands */ 4040 /* Activate SCU to enable SCU commands */
3952 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4041 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
@@ -3962,7 +4051,9 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3962 goto error; 4051 goto error;
3963 4052
3964 4053
3965 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result); 4054 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4055 | SCU_RAM_COMMAND_CMD_DEMOD_START,
4056 0, NULL, 1, &cmd_result);
3966 if (status < 0) 4057 if (status < 0)
3967 goto error; 4058 goto error;
3968 4059
@@ -4071,7 +4162,9 @@ static int power_down_qam(struct drxk_state *state)
4071 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4162 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4072 if (status < 0) 4163 if (status < 0)
4073 goto error; 4164 goto error;
4074 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result); 4165 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4166 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4167 0, NULL, 1, &cmd_result);
4075 if (status < 0) 4168 if (status < 0)
4076 goto error; 4169 goto error;
4077 } 4170 }
@@ -4139,7 +4232,7 @@ static int set_qam_measurement(struct drxk_state *state,
4139 if (status < 0) 4232 if (status < 0)
4140 goto error; 4233 goto error;
4141 4234
4142 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ 4235 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
4143 fec_bits_desired *= 500; /* meas. period [ms] */ 4236 fec_bits_desired *= 500; /* meas. period [ms] */
4144 4237
4145 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4238 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
@@ -4162,7 +4255,8 @@ static int set_qam_measurement(struct drxk_state *state,
4162 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); 4255 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4163 if (status < 0) 4256 if (status < 0)
4164 goto error; 4257 goto error;
4165 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale); 4258 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4259 fec_rs_prescale);
4166 if (status < 0) 4260 if (status < 0)
4167 goto error; 4261 goto error;
4168 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); 4262 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
@@ -4228,7 +4322,8 @@ static int set_qam16(struct drxk_state *state)
4228 goto error; 4322 goto error;
4229 4323
4230 /* QAM Slicer Settings */ 4324 /* QAM Slicer Settings */
4231 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); 4325 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4326 DRXK_QAM_SL_SIG_POWER_QAM16);
4232 if (status < 0) 4327 if (status < 0)
4233 goto error; 4328 goto error;
4234 4329
@@ -4424,7 +4519,8 @@ static int set_qam32(struct drxk_state *state)
4424 4519
4425 /* QAM Slicer Settings */ 4520 /* QAM Slicer Settings */
4426 4521
4427 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); 4522 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4523 DRXK_QAM_SL_SIG_POWER_QAM32);
4428 if (status < 0) 4524 if (status < 0)
4429 goto error; 4525 goto error;
4430 4526
@@ -4617,7 +4713,8 @@ static int set_qam64(struct drxk_state *state)
4617 goto error; 4713 goto error;
4618 4714
4619 /* QAM Slicer Settings */ 4715 /* QAM Slicer Settings */
4620 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); 4716 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4717 DRXK_QAM_SL_SIG_POWER_QAM64);
4621 if (status < 0) 4718 if (status < 0)
4622 goto error; 4719 goto error;
4623 4720
@@ -4813,7 +4910,8 @@ static int set_qam128(struct drxk_state *state)
4813 4910
4814 /* QAM Slicer Settings */ 4911 /* QAM Slicer Settings */
4815 4912
4816 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); 4913 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4914 DRXK_QAM_SL_SIG_POWER_QAM128);
4817 if (status < 0) 4915 if (status < 0)
4818 goto error; 4916 goto error;
4819 4917
@@ -5008,7 +5106,8 @@ static int set_qam256(struct drxk_state *state)
5008 5106
5009 /* QAM Slicer Settings */ 5107 /* QAM Slicer Settings */
5010 5108
5011 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); 5109 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5110 DRXK_QAM_SL_SIG_POWER_QAM256);
5012 if (status < 0) 5111 if (status < 0)
5013 goto error; 5112 goto error;
5014 5113
@@ -5156,7 +5255,9 @@ static int qam_reset_qam(struct drxk_state *state)
5156 if (status < 0) 5255 if (status < 0)
5157 goto error; 5256 goto error;
5158 5257
5159 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result); 5258 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5259 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5260 0, NULL, 1, &cmd_result);
5160error: 5261error:
5161 if (status < 0) 5262 if (status < 0)
5162 pr_err("Error %d on %s\n", status, __func__); 5263 pr_err("Error %d on %s\n", status, __func__);
@@ -5267,8 +5368,10 @@ static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5267 } else { 5368 } else {
5268 /* 0xC000 NEVER LOCKED */ 5369 /* 0xC000 NEVER LOCKED */
5269 /* (system will never be able to lock to the signal) */ 5370 /* (system will never be able to lock to the signal) */
5270 /* TODO: check this, intermediate & standard specific lock states are not 5371 /*
5271 taken into account here */ 5372 * TODO: check this, intermediate & standard specific lock
5373 * states are not taken into account here
5374 */
5272 *p_lock_status = NEVER_LOCK; 5375 *p_lock_status = NEVER_LOCK;
5273 } 5376 }
5274 return status; 5377 return status;
@@ -5300,13 +5403,15 @@ static int qam_demodulator_command(struct drxk_state *state,
5300 set_env_parameters[0] = QAM_TOP_ANNEX_A; 5403 set_env_parameters[0] = QAM_TOP_ANNEX_A;
5301 5404
5302 status = scu_command(state, 5405 status = scu_command(state,
5303 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 5406 SCU_RAM_COMMAND_STANDARD_QAM
5407 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5304 1, set_env_parameters, 1, &cmd_result); 5408 1, set_env_parameters, 1, &cmd_result);
5305 if (status < 0) 5409 if (status < 0)
5306 goto error; 5410 goto error;
5307 5411
5308 status = scu_command(state, 5412 status = scu_command(state,
5309 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5413 SCU_RAM_COMMAND_STANDARD_QAM
5414 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5310 number_of_parameters, set_param_parameters, 5415 number_of_parameters, set_param_parameters,
5311 1, &cmd_result); 5416 1, &cmd_result);
5312 } else if (number_of_parameters == 4) { 5417 } else if (number_of_parameters == 4) {
@@ -5321,7 +5426,8 @@ static int qam_demodulator_command(struct drxk_state *state,
5321 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5426 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5322 5427
5323 status = scu_command(state, 5428 status = scu_command(state,
5324 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5429 SCU_RAM_COMMAND_STANDARD_QAM
5430 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5325 number_of_parameters, set_param_parameters, 5431 number_of_parameters, set_param_parameters,
5326 1, &cmd_result); 5432 1, &cmd_result);
5327 } else { 5433 } else {
@@ -5439,12 +5545,14 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5439 if (status < 0) 5545 if (status < 0)
5440 goto error; 5546 goto error;
5441#endif 5547#endif
5442 status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true); 5548 status = set_frequency_shifter(state, intermediate_freqk_hz,
5549 tuner_freq_offset, true);
5443 if (status < 0) 5550 if (status < 0)
5444 goto error; 5551 goto error;
5445 5552
5446 /* Setup BER measurement */ 5553 /* Setup BER measurement */
5447 status = set_qam_measurement(state, state->m_constellation, state->props.symbol_rate); 5554 status = set_qam_measurement(state, state->m_constellation,
5555 state->props.symbol_rate);
5448 if (status < 0) 5556 if (status < 0)
5449 goto error; 5557 goto error;
5450 5558
@@ -5517,7 +5625,8 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5517 goto error; 5625 goto error;
5518 5626
5519 /* Mirroring, QAM-block starting point not inverted */ 5627 /* Mirroring, QAM-block starting point not inverted */
5520 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5628 status = write16(state, QAM_SY_SP_INV__A,
5629 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5521 if (status < 0) 5630 if (status < 0)
5522 goto error; 5631 goto error;
5523 5632
@@ -5578,7 +5687,9 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5578 goto error; 5687 goto error;
5579 5688
5580 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5689 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5581 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result); 5690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5691 | SCU_RAM_COMMAND_CMD_DEMOD_START,
5692 0, NULL, 1, &cmd_result);
5582 if (status < 0) 5693 if (status < 0)
5583 goto error; 5694 goto error;
5584 5695
@@ -5628,13 +5739,22 @@ static int set_qam_standard(struct drxk_state *state,
5628 boot loader from ROM table */ 5739 boot loader from ROM table */
5629 switch (o_mode) { 5740 switch (o_mode) {
5630 case OM_QAM_ITU_A: 5741 case OM_QAM_ITU_A:
5631 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5742 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5743 DRXK_BLCC_NR_ELEMENTS_TAPS,
5744 DRXK_BLC_TIMEOUT);
5632 break; 5745 break;
5633 case OM_QAM_ITU_C: 5746 case OM_QAM_ITU_C:
5634 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5747 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5748 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5749 DRXK_BLDC_NR_ELEMENTS_TAPS,
5750 DRXK_BLC_TIMEOUT);
5635 if (status < 0) 5751 if (status < 0)
5636 goto error; 5752 goto error;
5637 status = bl_direct_cmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5753 status = bl_direct_cmd(state,
5754 IQM_CF_TAP_IM0__A,
5755 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5756 DRXK_BLDC_NR_ELEMENTS_TAPS,
5757 DRXK_BLC_TIMEOUT);
5638 break; 5758 break;
5639 default: 5759 default:
5640 status = -EINVAL; 5760 status = -EINVAL;
@@ -5642,13 +5762,14 @@ static int set_qam_standard(struct drxk_state *state,
5642 if (status < 0) 5762 if (status < 0)
5643 goto error; 5763 goto error;
5644 5764
5645 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); 5765 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5646 if (status < 0) 5766 if (status < 0)
5647 goto error; 5767 goto error;
5648 status = write16(state, IQM_CF_SYMMETRIC__A, 0); 5768 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5649 if (status < 0) 5769 if (status < 0)
5650 goto error; 5770 goto error;
5651 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5771 status = write16(state, IQM_CF_MIDTAP__A,
5772 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5652 if (status < 0) 5773 if (status < 0)
5653 goto error; 5774 goto error;
5654 5775
@@ -5760,7 +5881,8 @@ static int write_gpio(struct drxk_state *state)
5760 5881
5761 dprintk(1, "\n"); 5882 dprintk(1, "\n");
5762 /* stop lock indicator process */ 5883 /* stop lock indicator process */
5763 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5884 status = write16(state, SCU_RAM_GPIO__A,
5885 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5764 if (status < 0) 5886 if (status < 0)
5765 goto error; 5887 goto error;
5766 5888
@@ -5772,7 +5894,8 @@ static int write_gpio(struct drxk_state *state)
5772 if (state->m_has_sawsw) { 5894 if (state->m_has_sawsw) {
5773 if (state->uio_mask & 0x0001) { /* UIO-1 */ 5895 if (state->uio_mask & 0x0001) { /* UIO-1 */
5774 /* write to io pad configuration register - output mode */ 5896 /* write to io pad configuration register - output mode */
5775 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_gpio_cfg); 5897 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5898 state->m_gpio_cfg);
5776 if (status < 0) 5899 if (status < 0)
5777 goto error; 5900 goto error;
5778 5901
@@ -5791,7 +5914,8 @@ static int write_gpio(struct drxk_state *state)
5791 } 5914 }
5792 if (state->uio_mask & 0x0002) { /* UIO-2 */ 5915 if (state->uio_mask & 0x0002) { /* UIO-2 */
5793 /* write to io pad configuration register - output mode */ 5916 /* write to io pad configuration register - output mode */
5794 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_gpio_cfg); 5917 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5918 state->m_gpio_cfg);
5795 if (status < 0) 5919 if (status < 0)
5796 goto error; 5920 goto error;
5797 5921
@@ -5810,7 +5934,8 @@ static int write_gpio(struct drxk_state *state)
5810 } 5934 }
5811 if (state->uio_mask & 0x0004) { /* UIO-3 */ 5935 if (state->uio_mask & 0x0004) { /* UIO-3 */
5812 /* write to io pad configuration register - output mode */ 5936 /* write to io pad configuration register - output mode */
5813 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_gpio_cfg); 5937 status = write16(state, SIO_PDR_GPIO_CFG__A,
5938 state->m_gpio_cfg);
5814 if (status < 0) 5939 if (status < 0)
5815 goto error; 5940 goto error;
5816 5941
@@ -5909,7 +6034,8 @@ static int power_down_device(struct drxk_state *state)
5909 if (status < 0) 6034 if (status < 0)
5910 goto error; 6035 goto error;
5911 6036
5912 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); 6037 status = write16(state, SIO_CC_PWD_MODE__A,
6038 SIO_CC_PWD_MODE_LEVEL_CLOCK);
5913 if (status < 0) 6039 if (status < 0)
5914 goto error; 6040 goto error;
5915 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6041 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
@@ -5940,13 +6066,19 @@ static int init_drxk(struct drxk_state *state)
5940 if (status < 0) 6066 if (status < 0)
5941 goto error; 6067 goto error;
5942 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 6068 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5943 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); 6069 status = write16(state, SIO_CC_SOFT_RST__A,
6070 SIO_CC_SOFT_RST_OFDM__M
6071 | SIO_CC_SOFT_RST_SYS__M
6072 | SIO_CC_SOFT_RST_OSC__M);
5944 if (status < 0) 6073 if (status < 0)
5945 goto error; 6074 goto error;
5946 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6075 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5947 if (status < 0) 6076 if (status < 0)
5948 goto error; 6077 goto error;
5949 /* TODO is this needed, if yes how much delay in worst case scenario */ 6078 /*
6079 * TODO is this needed? If yes, how much delay in
6080 * worst case scenario
6081 */
5950 usleep_range(1000, 2000); 6082 usleep_range(1000, 2000);
5951 state->m_drxk_a3_patch_code = true; 6083 state->m_drxk_a3_patch_code = true;
5952 status = get_device_capabilities(state); 6084 status = get_device_capabilities(state);
@@ -5979,7 +6111,8 @@ static int init_drxk(struct drxk_state *state)
5979 && !(state->m_DRXK_A2_ROM_CODE)) 6111 && !(state->m_DRXK_A2_ROM_CODE))
5980#endif 6112#endif
5981 { 6113 {
5982 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 6114 status = write16(state, SCU_RAM_GPIO__A,
6115 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5983 if (status < 0) 6116 if (status < 0)
5984 goto error; 6117 goto error;
5985 } 6118 }
@@ -5998,12 +6131,14 @@ static int init_drxk(struct drxk_state *state)
5998 goto error; 6131 goto error;
5999 6132
6000 /* enable token-ring bus through OFDM block for possible ucode upload */ 6133 /* enable token-ring bus through OFDM block for possible ucode upload */
6001 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); 6134 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6135 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6002 if (status < 0) 6136 if (status < 0)
6003 goto error; 6137 goto error;
6004 6138
6005 /* include boot loader section */ 6139 /* include boot loader section */
6006 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); 6140 status = write16(state, SIO_BL_COMM_EXEC__A,
6141 SIO_BL_COMM_EXEC_ACTIVE);
6007 if (status < 0) 6142 if (status < 0)
6008 goto error; 6143 goto error;
6009 status = bl_chain_cmd(state, 0, 6, 100); 6144 status = bl_chain_cmd(state, 0, 6, 100);
@@ -6018,7 +6153,8 @@ static int init_drxk(struct drxk_state *state)
6018 } 6153 }
6019 6154
6020 /* disable token-ring bus through OFDM block for possible ucode upload */ 6155 /* disable token-ring bus through OFDM block for possible ucode upload */
6021 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 6156 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6157 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6022 if (status < 0) 6158 if (status < 0)
6023 goto error; 6159 goto error;
6024 6160
@@ -6048,7 +6184,8 @@ static int init_drxk(struct drxk_state *state)
6048 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6184 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6049 ((DRXK_VERSION_MAJOR % 10) << 4) + 6185 ((DRXK_VERSION_MAJOR % 10) << 4) +
6050 (DRXK_VERSION_MINOR % 10); 6186 (DRXK_VERSION_MINOR % 10);
6051 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driver_version); 6187 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6188 driver_version);
6052 if (status < 0) 6189 if (status < 0)
6053 goto error; 6190 goto error;
6054 driver_version = 6191 driver_version =
@@ -6056,7 +6193,8 @@ static int init_drxk(struct drxk_state *state)
6056 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6193 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6057 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6194 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6058 (DRXK_VERSION_PATCH % 10); 6195 (DRXK_VERSION_PATCH % 10);
6059 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driver_version); 6196 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6197 driver_version);
6060 if (status < 0) 6198 if (status < 0)
6061 goto error; 6199 goto error;
6062 6200
@@ -6064,10 +6202,13 @@ static int init_drxk(struct drxk_state *state)
6064 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 6202 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6065 DRXK_VERSION_PATCH); 6203 DRXK_VERSION_PATCH);
6066 6204
6067 /* Dirty fix of default values for ROM/PATCH microcode 6205 /*
6068 Dirty because this fix makes it impossible to setup suitable values 6206 * Dirty fix of default values for ROM/PATCH microcode
6069 before calling DRX_Open. This solution requires changes to RF AGC speed 6207 * Dirty because this fix makes it impossible to setup
6070 to be done via the CTRL function after calling DRX_Open */ 6208 * suitable values before calling DRX_Open. This solution
6209 * requires changes to RF AGC speed to be done via the CTRL
6210 * function after calling DRX_Open
6211 */
6071 6212
6072 /* m_dvbt_rf_agc_cfg.speed = 3; */ 6213 /* m_dvbt_rf_agc_cfg.speed = 3; */
6073 6214
@@ -6238,7 +6379,8 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
6238 case SYS_DVBC_ANNEX_C: 6379 case SYS_DVBC_ANNEX_C:
6239 if (!state->m_has_dvbc) 6380 if (!state->m_has_dvbc)
6240 return -EINVAL; 6381 return -EINVAL;
6241 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; 6382 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6383 true : false;
6242 if (state->m_itut_annex_c) 6384 if (state->m_itut_annex_c)
6243 setoperation_mode(state, OM_QAM_ITU_C); 6385 setoperation_mode(state, OM_QAM_ITU_C);
6244 else 6386 else
@@ -6352,7 +6494,7 @@ static int get_strength(struct drxk_state *state, u64 *strength)
6352 if (if_agc.output_level > if_agc.max_output_level) 6494 if (if_agc.output_level > if_agc.max_output_level)
6353 if_agc.output_level = if_agc.max_output_level; 6495 if_agc.output_level = if_agc.max_output_level;
6354 6496
6355 agc_range = (u32) (if_agc.max_output_level - if_agc.min_output_level); 6497 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6356 if (agc_range > 0) { 6498 if (agc_range > 0) {
6357 atten += 100UL * 6499 atten += 100UL *
6358 ((u32)(tuner_if_gain)) * 6500 ((u32)(tuner_if_gain)) *
@@ -6433,9 +6575,11 @@ static int drxk_get_stats(struct dvb_frontend *fe)
6433 6575
6434 /* BER measurement is valid if at least FEC lock is achieved */ 6576 /* BER measurement is valid if at least FEC lock is achieved */
6435 6577
6436 /* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be written 6578 /*
6437 to set nr of symbols or bits over which 6579 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6438 to measure EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). */ 6580 * written to set nr of symbols or bits over which to measure
6581 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6582 */
6439 6583
6440 /* Read registers for post/preViterbi BER calculation */ 6584 /* Read registers for post/preViterbi BER calculation */
6441 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16); 6585 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
@@ -6566,8 +6710,8 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6566 return 0; 6710 return 0;
6567} 6711}
6568 6712
6569static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings 6713static int drxk_get_tune_settings(struct dvb_frontend *fe,
6570 *sets) 6714 struct dvb_frontend_tune_settings *sets)
6571{ 6715{
6572 struct drxk_state *state = fe->demodulator_priv; 6716 struct drxk_state *state = fe->demodulator_priv;
6573 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6717 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 05:21:13 -0400