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authorKuninori Morimoto <morimoto.kuninori@renesas.com>2008-10-24 14:43:07 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-29 14:53:25 -0500
commit08a66aea55154b50f9e9e2e89cc85d8b75121568 (patch)
tree0bb2a134305d96cc393afcf5834769f975abf874 /drivers/media/video
parentd1f81da2361804d62f7ade2703eda68dda6cdb48 (diff)
V4L/DVB (9488): Add ov772x driver
This patch adds ov772x driver that use soc_camera framework. It was tested on SH Migo-r board. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/Kconfig6
-rw-r--r--drivers/media/video/Makefile1
-rw-r--r--drivers/media/video/ov772x.c966
3 files changed, 973 insertions, 0 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 057fd7e160c4..af951bdc111d 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -750,6 +750,12 @@ config SOC_CAMERA_PLATFORM
750 help 750 help
751 This is a generic SoC camera platform driver, useful for testing 751 This is a generic SoC camera platform driver, useful for testing
752 752
753config SOC_CAMERA_OV772X
754 tristate "ov772x camera support"
755 depends on SOC_CAMERA && I2C
756 help
757 This is a ov772x camera driver
758
753config VIDEO_PXA27x 759config VIDEO_PXA27x
754 tristate "PXA27x Quick Capture Interface driver" 760 tristate "PXA27x Quick Capture Interface driver"
755 depends on VIDEO_DEV && PXA27x && SOC_CAMERA 761 depends on VIDEO_DEV && PXA27x && SOC_CAMERA
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 52f2e958db77..e5b801379003 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -133,6 +133,7 @@ obj-$(CONFIG_SOC_CAMERA) += soc_camera.o
133obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o 133obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o
134obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o 134obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o
135obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o 135obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o
136obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o
136obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o 137obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o
137 138
138obj-$(CONFIG_VIDEO_AU0828) += au0828/ 139obj-$(CONFIG_VIDEO_AU0828) += au0828/
diff --git a/drivers/media/video/ov772x.c b/drivers/media/video/ov772x.c
new file mode 100644
index 000000000000..6206dff8d02d
--- /dev/null
+++ b/drivers/media/video/ov772x.c
@@ -0,0 +1,966 @@
1/*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/videodev2.h>
24#include <media/v4l2-chip-ident.h>
25#include <media/v4l2-common.h>
26#include <media/soc_camera.h>
27#include <media/ov772x.h>
28
29/*
30 * register offset
31 */
32#define GAIN 0x00 /* AGC - Gain control gain setting */
33#define BLUE 0x01 /* AWB - Blue channel gain setting */
34#define RED 0x02 /* AWB - Red channel gain setting */
35#define GREEN 0x03 /* AWB - Green channel gain setting */
36#define COM1 0x04 /* Common control 1 */
37#define BAVG 0x05 /* U/B Average Level */
38#define GAVG 0x06 /* Y/Gb Average Level */
39#define RAVG 0x07 /* V/R Average Level */
40#define AECH 0x08 /* Exposure Value - AEC MSBs */
41#define COM2 0x09 /* Common control 2 */
42#define PID 0x0A /* Product ID Number MSB */
43#define VER 0x0B /* Product ID Number LSB */
44#define COM3 0x0C /* Common control 3 */
45#define COM4 0x0D /* Common control 4 */
46#define COM5 0x0E /* Common control 5 */
47#define COM6 0x0F /* Common control 6 */
48#define AEC 0x10 /* Exposure Value */
49#define CLKRC 0x11 /* Internal clock */
50#define COM7 0x12 /* Common control 7 */
51#define COM8 0x13 /* Common control 8 */
52#define COM9 0x14 /* Common control 9 */
53#define COM10 0x15 /* Common control 10 */
54#define HSTART 0x17 /* Horizontal sensor size */
55#define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
56#define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
57#define VSIZE 0x1A /* Vertical sensor size */
58#define PSHFT 0x1B /* Data format - pixel delay select */
59#define MIDH 0x1C /* Manufacturer ID byte - high */
60#define MIDL 0x1D /* Manufacturer ID byte - low */
61#define LAEC 0x1F /* Fine AEC value */
62#define COM11 0x20 /* Common control 11 */
63#define BDBASE 0x22 /* Banding filter Minimum AEC value */
64#define DBSTEP 0x23 /* Banding filter Maximum Setp */
65#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
66#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
67#define VPT 0x26 /* AGC/AEC Fast mode operating region */
68#define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
69#define EXHCH 0x2A /* Dummy pixel insert MSB */
70#define EXHCL 0x2B /* Dummy pixel insert LSB */
71#define VOUTSIZE 0x2C /* Vertical data output size MSBs */
72#define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
73#define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
74#define YAVE 0x2F /* Y/G Channel Average value */
75#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
76#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
77#define HREF 0x32 /* Image start and size control */
78#define DM_LNL 0x33 /* Dummy line low 8 bits */
79#define DM_LNH 0x34 /* Dummy line high 8 bits */
80#define ADOFF_B 0x35 /* AD offset compensation value for B channel */
81#define ADOFF_R 0x36 /* AD offset compensation value for R channel */
82#define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
83#define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
84#define OFF_B 0x39 /* Analog process B channel offset value */
85#define OFF_R 0x3A /* Analog process R channel offset value */
86#define OFF_GB 0x3B /* Analog process Gb channel offset value */
87#define OFF_GR 0x3C /* Analog process Gr channel offset value */
88#define COM12 0x3D /* Common control 12 */
89#define COM13 0x3E /* Common control 13 */
90#define COM14 0x3F /* Common control 14 */
91#define COM15 0x40 /* Common control 15*/
92#define COM16 0x41 /* Common control 16 */
93#define TGT_B 0x42 /* BLC blue channel target value */
94#define TGT_R 0x43 /* BLC red channel target value */
95#define TGT_GB 0x44 /* BLC Gb channel target value */
96#define TGT_GR 0x45 /* BLC Gr channel target value */
97#define LCC0 0x46 /* Lens correction control 0 */
98#define LCC1 0x47 /* Lens correction option 1 - X coordinate */
99#define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
100#define LCC3 0x49 /* Lens correction option 3 */
101#define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
102#define LCC5 0x4B /* Lens correction option 5 */
103#define LCC6 0x4C /* Lens correction option 6 */
104#define FIXGAIN 0x4D /* Analog fix gain amplifer */
105#define AREF0 0x4E /* Sensor reference control */
106#define AREF1 0x4F /* Sensor reference current control */
107#define AREF2 0x50 /* Analog reference control */
108#define AREF3 0x51 /* ADC reference control */
109#define AREF4 0x52 /* ADC reference control */
110#define AREF5 0x53 /* ADC reference control */
111#define AREF6 0x54 /* Analog reference control */
112#define AREF7 0x55 /* Analog reference control */
113#define UFIX 0x60 /* U channel fixed value output */
114#define VFIX 0x61 /* V channel fixed value output */
115#define AW_BB_BLK 0x62 /* AWB option for advanced AWB */
116#define AW_B_CTRL0 0x63 /* AWB control byte 0 */
117#define DSP_CTRL1 0x64 /* DSP control byte 1 */
118#define DSP_CTRL2 0x65 /* DSP control byte 2 */
119#define DSP_CTRL3 0x66 /* DSP control byte 3 */
120#define DSP_CTRL4 0x67 /* DSP control byte 4 */
121#define AW_B_BIAS 0x68 /* AWB BLC level clip */
122#define AW_BCTRL1 0x69 /* AWB control 1 */
123#define AW_BCTRL2 0x6A /* AWB control 2 */
124#define AW_BCTRL3 0x6B /* AWB control 3 */
125#define AW_BCTRL4 0x6C /* AWB control 4 */
126#define AW_BCTRL5 0x6D /* AWB control 5 */
127#define AW_BCTRL6 0x6E /* AWB control 6 */
128#define AW_BCTRL7 0x6F /* AWB control 7 */
129#define AW_BCTRL8 0x70 /* AWB control 8 */
130#define AW_BCTRL9 0x71 /* AWB control 9 */
131#define AW_BCTRL10 0x72 /* AWB control 10 */
132#define AW_BCTRL11 0x73 /* AWB control 11 */
133#define AW_BCTRL12 0x74 /* AWB control 12 */
134#define AW_BCTRL13 0x75 /* AWB control 13 */
135#define AW_BCTRL14 0x76 /* AWB control 14 */
136#define AW_BCTRL15 0x77 /* AWB control 15 */
137#define AW_BCTRL16 0x78 /* AWB control 16 */
138#define AW_BCTRL17 0x79 /* AWB control 17 */
139#define AW_BCTRL18 0x7A /* AWB control 18 */
140#define AW_BCTRL19 0x7B /* AWB control 19 */
141#define AW_BCTRL20 0x7C /* AWB control 20 */
142#define AW_BCTRL21 0x7D /* AWB control 21 */
143#define GAM1 0x7E /* Gamma Curve 1st segment input end point */
144#define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
145#define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
146#define GAM4 0x81 /* Gamma Curve 4th segment input end point */
147#define GAM5 0x82 /* Gamma Curve 5th segment input end point */
148#define GAM6 0x83 /* Gamma Curve 6th segment input end point */
149#define GAM7 0x84 /* Gamma Curve 7th segment input end point */
150#define GAM8 0x85 /* Gamma Curve 8th segment input end point */
151#define GAM9 0x86 /* Gamma Curve 9th segment input end point */
152#define GAM10 0x87 /* Gamma Curve 10th segment input end point */
153#define GAM11 0x88 /* Gamma Curve 11th segment input end point */
154#define GAM12 0x89 /* Gamma Curve 12th segment input end point */
155#define GAM13 0x8A /* Gamma Curve 13th segment input end point */
156#define GAM14 0x8B /* Gamma Curve 14th segment input end point */
157#define GAM15 0x8C /* Gamma Curve 15th segment input end point */
158#define SLOP 0x8D /* Gamma curve highest segment slope */
159#define DNSTH 0x8E /* De-noise threshold */
160#define EDGE0 0x8F /* Edge enhancement control 0 */
161#define EDGE1 0x90 /* Edge enhancement control 1 */
162#define DNSOFF 0x91 /* Auto De-noise threshold control */
163#define EDGE2 0x92 /* Edge enhancement strength low point control */
164#define EDGE3 0x93 /* Edge enhancement strength high point control */
165#define MTX1 0x94 /* Matrix coefficient 1 */
166#define MTX2 0x95 /* Matrix coefficient 2 */
167#define MTX3 0x96 /* Matrix coefficient 3 */
168#define MTX4 0x97 /* Matrix coefficient 4 */
169#define MTX5 0x98 /* Matrix coefficient 5 */
170#define MTX6 0x99 /* Matrix coefficient 6 */
171#define MTX_CTRL 0x9A /* Matrix control */
172#define BRIGHT 0x9B /* Brightness control */
173#define CNTRST 0x9C /* Contrast contrast */
174#define CNTRST_CTRL 0x9D /* Contrast contrast center */
175#define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
176#define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
177#define SCAL0 0xA0 /* Scaling control 0 */
178#define SCAL1 0xA1 /* Scaling control 1 */
179#define SCAL2 0xA2 /* Scaling control 2 */
180#define FIFODLYM 0xA3 /* FIFO manual mode delay control */
181#define FIFODLYA 0xA4 /* FIFO auto mode delay control */
182#define SDE 0xA6 /* Special digital effect control */
183#define USAT 0xA7 /* U component saturation control */
184#define VSAT 0xA8 /* V component saturation control */
185#define HUE0 0xA9 /* Hue control 0 */
186#define HUE1 0xAA /* Hue control 1 */
187#define SIGN 0xAB /* Sign bit for Hue and contrast */
188#define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
189
190/*
191 * register detail
192 */
193
194/* COM2 */
195#define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
196 /* Output drive capability */
197#define OCAP_1x 0x00 /* 1x */
198#define OCAP_2x 0x01 /* 2x */
199#define OCAP_3x 0x02 /* 3x */
200#define OCAP_4x 0x03 /* 4x */
201
202/* COM3 */
203#define SWAP_MASK 0x38
204
205#define VFIMG_ON_OFF 0x80 /* Vertical flip image ON/OFF selection */
206#define HMIMG_ON_OFF 0x40 /* Horizontal mirror image ON/OFF selection */
207#define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
208#define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
209#define SWAP_ML 0x08 /* Swap output MSB/LSB */
210 /* Tri-state option for output clock */
211#define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
212 /* 1: No tri-state at this period */
213 /* Tri-state option for output data */
214#define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
215 /* 1: No tri-state at this period */
216#define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
217
218/* COM4 */
219 /* PLL frequency control */
220#define PLL_BYPASS 0x00 /* 00: Bypass PLL */
221#define PLL_4x 0x40 /* 01: PLL 4x */
222#define PLL_6x 0x80 /* 10: PLL 6x */
223#define PLL_8x 0xc0 /* 11: PLL 8x */
224 /* AEC evaluate window */
225#define AEC_FULL 0x00 /* 00: Full window */
226#define AEC_1p2 0x10 /* 01: 1/2 window */
227#define AEC_1p4 0x20 /* 10: 1/4 window */
228#define AEC_2p3 0x30 /* 11: Low 2/3 window */
229
230/* COM5 */
231#define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
232#define AFR_SPPED 0x40 /* Auto frame rate control speed slection */
233 /* Auto frame rate max rate control */
234#define AFR_NO_RATE 0x00 /* No reduction of frame rate */
235#define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
236#define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
237#define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
238 /* Auto frame rate active point control */
239#define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
240#define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
241#define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
242#define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
243 /* AEC max step control */
244#define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
245 /* 1 : No limit to AEC increase step */
246
247/* COM7 */
248 /* SCCB Register Reset */
249#define SCCB_RESET 0x80 /* 0 : No change */
250 /* 1 : Resets all registers to default */
251 /* Resolution selection */
252#define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
253#define SLCT_VGA 0x00 /* 0 : VGA */
254#define SLCT_QVGA 0x40 /* 1 : QVGA */
255#define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
256 /* RGB output format control */
257#define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
258#define FMT_RGB565 0x04 /* 01 : RGB 565 */
259#define FMT_RGB555 0x08 /* 10 : RGB 555 */
260#define FMT_RGB444 0x0c /* 11 : RGB 444 */
261 /* Output format control */
262#define OFMT_YUV 0x00 /* 00 : YUV */
263#define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
264#define OFMT_RGB 0x02 /* 10 : RGB */
265#define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
266
267/* COM8 */
268#define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
269 /* AEC Setp size limit */
270#define UNLMT_STEP 0x40 /* 0 : Step size is limited */
271 /* 1 : Unlimited step size */
272#define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
273#define AEC_BND 0x10 /* Enable AEC below banding value */
274#define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
275#define AGC_ON 0x04 /* AGC Enable */
276#define AWB_ON 0x02 /* AWB Enable */
277#define AEC_ON 0x01 /* AEC Enable */
278
279/* COM9 */
280#define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
281 /* Automatic gain ceiling - maximum AGC value */
282#define GAIN_2x 0x00 /* 000 : 2x */
283#define GAIN_4x 0x10 /* 001 : 4x */
284#define GAIN_8x 0x20 /* 010 : 8x */
285#define GAIN_16x 0x30 /* 011 : 16x */
286#define GAIN_32x 0x40 /* 100 : 32x */
287#define GAIN_64x 0x50 /* 101 : 64x */
288#define GAIN_128x 0x60 /* 110 : 128x */
289#define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
290#define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
291
292/* COM11 */
293#define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
294#define SGLF_TRIG 0x01 /* Single frame transfer trigger */
295
296/* EXHCH */
297#define VSIZE_LSB 0x04 /* Vertical data output size LSB */
298
299/* DSP_CTRL1 */
300#define FIFO_ON 0x80 /* FIFO enable/disable selection */
301#define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
302#define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
303#define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
304#define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
305#define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
306#define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
307#define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
308
309/* DSP_CTRL3 */
310#define UV_MASK 0x80 /* UV output sequence option */
311#define UV_ON 0x80 /* ON */
312#define UV_OFF 0x00 /* OFF */
313#define CBAR_MASK 0x20 /* DSP Color bar mask */
314#define CBAR_ON 0x20 /* ON */
315#define CBAR_OFF 0x00 /* OFF */
316
317/* HSTART */
318#define HST_VGA 0x23
319#define HST_QVGA 0x3F
320
321/* HSIZE */
322#define HSZ_VGA 0xA0
323#define HSZ_QVGA 0x50
324
325/* VSTART */
326#define VST_VGA 0x07
327#define VST_QVGA 0x03
328
329/* VSIZE */
330#define VSZ_VGA 0xF0
331#define VSZ_QVGA 0x78
332
333/* HOUTSIZE */
334#define HOSZ_VGA 0xA0
335#define HOSZ_QVGA 0x50
336
337/* VOUTSIZE */
338#define VOSZ_VGA 0xF0
339#define VOSZ_QVGA 0x78
340
341/*
342 * bit configure (32 bit)
343 * this is used in struct ov772x_color_format :: option
344 */
345#define OP_UV 0x00000001
346#define OP_SWAP_RGB 0x00000002
347
348/*
349 * struct
350 */
351struct regval_list {
352 unsigned char reg_num;
353 unsigned char value;
354};
355
356struct ov772x_color_format {
357 char *name;
358 __u32 fourcc;
359 const struct regval_list *regs;
360 unsigned int option;
361};
362
363struct ov772x_win_size {
364 char *name;
365 __u32 width;
366 __u32 height;
367 unsigned char com7_bit;
368 const struct regval_list *regs;
369};
370
371struct ov772x_priv {
372 struct ov772x_camera_info *info;
373 struct i2c_client *client;
374 struct soc_camera_device icd;
375 const struct ov772x_color_format *fmt;
376 const struct ov772x_win_size *win;
377};
378
379#define ENDMARKER { 0xff, 0xff }
380
381static const struct regval_list ov772x_default_regs[] =
382{
383 { COM3, 0x00 },
384 { COM4, PLL_4x | 0x01 },
385 { 0x16, 0x00 }, /* Mystery */
386 { COM11, 0x10 }, /* Mystery */
387 { 0x28, 0x00 }, /* Mystery */
388 { HREF, 0x00 },
389 { COM13, 0xe2 }, /* Mystery */
390 { AREF0, 0xef },
391 { AREF2, 0x60 },
392 { AREF6, 0x7a },
393 ENDMARKER,
394};
395
396/*
397 * register setting for color format
398 */
399static const struct regval_list ov772x_RGB555_regs[] = {
400 { COM7, FMT_RGB555 | OFMT_RGB },
401 ENDMARKER,
402};
403
404static const struct regval_list ov772x_RGB565_regs[] = {
405 { COM7, FMT_RGB565 | OFMT_RGB },
406 ENDMARKER,
407};
408
409static const struct regval_list ov772x_YYUV_regs[] = {
410 { COM3, SWAP_YUV },
411 { COM7, OFMT_YUV },
412 ENDMARKER,
413};
414
415static const struct regval_list ov772x_UVYY_regs[] = {
416 { COM7, OFMT_YUV },
417 ENDMARKER,
418};
419
420
421/*
422 * register setting for window size
423 */
424static const struct regval_list ov772x_qvga_regs[] = {
425 { HSTART, HST_QVGA },
426 { HSIZE, HSZ_QVGA },
427 { VSTART, VST_QVGA },
428 { VSIZE, VSZ_QVGA },
429 { HOUTSIZE, HOSZ_QVGA },
430 { VOUTSIZE, VOSZ_QVGA },
431 ENDMARKER,
432};
433
434static const struct regval_list ov772x_vga_regs[] = {
435 { HSTART, HST_VGA },
436 { HSIZE, HSZ_VGA },
437 { VSTART, VST_VGA },
438 { VSIZE, VSZ_VGA },
439 { HOUTSIZE, HOSZ_VGA },
440 { VOUTSIZE, VOSZ_VGA },
441 ENDMARKER,
442};
443
444/*
445 * supported format list
446 */
447
448#define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
449static const struct soc_camera_data_format ov772x_fmt_lists[] = {
450 {
451 SETFOURCC(YUYV),
452 .depth = 16,
453 .colorspace = V4L2_COLORSPACE_JPEG,
454 },
455 {
456 SETFOURCC(YVYU),
457 .depth = 16,
458 .colorspace = V4L2_COLORSPACE_JPEG,
459 },
460 {
461 SETFOURCC(UYVY),
462 .depth = 16,
463 .colorspace = V4L2_COLORSPACE_JPEG,
464 },
465 {
466 SETFOURCC(RGB555),
467 .depth = 16,
468 .colorspace = V4L2_COLORSPACE_SRGB,
469 },
470 {
471 SETFOURCC(RGB555X),
472 .depth = 16,
473 .colorspace = V4L2_COLORSPACE_SRGB,
474 },
475 {
476 SETFOURCC(RGB565),
477 .depth = 16,
478 .colorspace = V4L2_COLORSPACE_SRGB,
479 },
480 {
481 SETFOURCC(RGB565X),
482 .depth = 16,
483 .colorspace = V4L2_COLORSPACE_SRGB,
484 },
485};
486
487/*
488 * color format list
489 */
490#define T_YUYV 0
491static const struct ov772x_color_format ov772x_cfmts[] = {
492 [T_YUYV] = {
493 SETFOURCC(YUYV),
494 .regs = ov772x_YYUV_regs,
495 },
496 {
497 SETFOURCC(YVYU),
498 .regs = ov772x_YYUV_regs,
499 .option = OP_UV,
500 },
501 {
502 SETFOURCC(UYVY),
503 .regs = ov772x_UVYY_regs,
504 },
505 {
506 SETFOURCC(RGB555),
507 .regs = ov772x_RGB555_regs,
508 .option = OP_SWAP_RGB,
509 },
510 {
511 SETFOURCC(RGB555X),
512 .regs = ov772x_RGB555_regs,
513 },
514 {
515 SETFOURCC(RGB565),
516 .regs = ov772x_RGB565_regs,
517 .option = OP_SWAP_RGB,
518 },
519 {
520 SETFOURCC(RGB565X),
521 .regs = ov772x_RGB565_regs,
522 },
523};
524
525
526/*
527 * window size list
528 */
529#define VGA_WIDTH 640
530#define VGA_HEIGHT 480
531#define QVGA_WIDTH 320
532#define QVGA_HEIGHT 240
533#define MAX_WIDTH VGA_WIDTH
534#define MAX_HEIGHT VGA_HEIGHT
535
536static const struct ov772x_win_size ov772x_win_vga = {
537 .name = "VGA",
538 .width = VGA_WIDTH,
539 .height = VGA_HEIGHT,
540 .com7_bit = SLCT_VGA,
541 .regs = ov772x_vga_regs,
542};
543
544static const struct ov772x_win_size ov772x_win_qvga = {
545 .name = "QVGA",
546 .width = QVGA_WIDTH,
547 .height = QVGA_HEIGHT,
548 .com7_bit = SLCT_QVGA,
549 .regs = ov772x_qvga_regs,
550};
551
552
553/*
554 * general function
555 */
556
557static int ov772x_write_array(struct i2c_client *client,
558 const struct regval_list *vals)
559{
560 while (vals->reg_num != 0xff) {
561 int ret = i2c_smbus_write_byte_data(client,
562 vals->reg_num,
563 vals->value);
564 if (ret < 0)
565 return ret;
566 vals++;
567 }
568 return 0;
569}
570
571static int ov772x_mask_set(struct i2c_client *client,
572 u8 command,
573 u8 mask,
574 u8 set)
575{
576 s32 val = i2c_smbus_read_byte_data(client, command);
577 val &= ~mask;
578 val |= set;
579
580 return i2c_smbus_write_byte_data(client, command, val);
581}
582
583static int ov772x_reset(struct i2c_client *client)
584{
585 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
586 msleep(1);
587 return ret;
588}
589
590/*
591 * soc_camera_ops function
592 */
593
594static int ov772x_init(struct soc_camera_device *icd)
595{
596 return 0;
597}
598
599static int ov772x_release(struct soc_camera_device *icd)
600{
601 return 0;
602}
603
604static int ov772x_start_capture(struct soc_camera_device *icd)
605{
606 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
607 int ret;
608
609
610 if (!priv->win)
611 priv->win = &ov772x_win_vga;
612 if (!priv->fmt)
613 priv->fmt = &ov772x_cfmts[T_YUYV];
614
615 /*
616 * reset hardware
617 */
618 ov772x_reset(priv->client);
619 ret = ov772x_write_array(priv->client, ov772x_default_regs);
620 if (ret < 0)
621 goto start_end;
622
623 /*
624 * set color format
625 */
626 ret = ov772x_write_array(priv->client, priv->fmt->regs);
627 if (ret < 0)
628 goto start_end;
629
630 /*
631 * set size format
632 */
633 ret = ov772x_write_array(priv->client, priv->win->regs);
634 if (ret < 0)
635 goto start_end;
636
637 /*
638 * set COM7 bit ( QVGA or VGA )
639 */
640 ret = ov772x_mask_set(priv->client,
641 COM7, SLCT_MASK, priv->win->com7_bit);
642 if (ret < 0)
643 goto start_end;
644
645 /*
646 * set UV setting
647 */
648 if (priv->fmt->option & OP_UV) {
649 ret = ov772x_mask_set(priv->client,
650 DSP_CTRL3, UV_MASK, UV_ON);
651 if (ret < 0)
652 goto start_end;
653 }
654
655 /*
656 * set SWAP setting
657 */
658 if (priv->fmt->option & OP_SWAP_RGB) {
659 ret = ov772x_mask_set(priv->client,
660 COM3, SWAP_MASK, SWAP_RGB);
661 if (ret < 0)
662 goto start_end;
663 }
664
665 dev_info(&icd->dev,
666 "format %s, win %s\n", priv->fmt->name, priv->win->name);
667
668start_end:
669 priv->fmt = NULL;
670 priv->win = NULL;
671
672 return ret;
673}
674
675static int ov772x_stop_capture(struct soc_camera_device *icd)
676{
677 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
678 ov772x_reset(priv->client);
679 return 0;
680}
681
682static int ov772x_set_bus_param(struct soc_camera_device *icd,
683 unsigned long flags)
684{
685 return 0;
686}
687
688static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
689{
690 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
691
692 return SOCAM_PCLK_SAMPLE_RISING |
693 SOCAM_HSYNC_ACTIVE_HIGH |
694 SOCAM_VSYNC_ACTIVE_HIGH |
695 SOCAM_MASTER |
696 priv->info->buswidth;
697}
698
699static int ov772x_get_chip_id(struct soc_camera_device *icd,
700 struct v4l2_chip_ident *id)
701{
702 id->ident = V4L2_IDENT_OV772X;
703 id->revision = 0;
704
705 return 0;
706}
707
708#ifdef CONFIG_VIDEO_ADV_DEBUG
709static int ov772x_get_register(struct soc_camera_device *icd,
710 struct v4l2_register *reg)
711{
712 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
713 int ret;
714
715 if (reg->reg > 0xff)
716 return -EINVAL;
717
718 ret = i2c_smbus_read_byte_data(priv->client, reg->reg);
719 if (ret < 0)
720 return ret;
721
722 reg->val = (__u64)ret;
723
724 return 0;
725}
726
727static int ov772x_set_register(struct soc_camera_device *icd,
728 struct v4l2_register *reg)
729{
730 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
731
732 if (reg->reg > 0xff ||
733 reg->val > 0xff)
734 return -EINVAL;
735
736 return i2c_smbus_write_byte_data(priv->client, reg->reg, reg->val);
737}
738#endif
739
740static int ov772x_set_fmt_cap(struct soc_camera_device *icd,
741 __u32 pixfmt,
742 struct v4l2_rect *rect)
743{
744 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
745 int ret = -EINVAL;
746 int i;
747
748 /*
749 * select format
750 */
751 priv->fmt = NULL;
752 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
753 if (pixfmt == ov772x_cfmts[i].fourcc) {
754 priv->fmt = ov772x_cfmts + i;
755 ret = 0;
756 break;
757 }
758 }
759
760 return ret;
761}
762
763static int ov772x_try_fmt_cap(struct soc_camera_device *icd,
764 struct v4l2_format *f)
765{
766 struct v4l2_pix_format *pix = &f->fmt.pix;
767 struct ov772x_priv *priv;
768
769 priv = container_of(icd, struct ov772x_priv, icd);
770
771 /* QVGA */
772 if (pix->width <= ov772x_win_qvga.width ||
773 pix->height <= ov772x_win_qvga.height) {
774 priv->win = &ov772x_win_qvga;
775 pix->width = ov772x_win_qvga.width;
776 pix->height = ov772x_win_qvga.height;
777 }
778
779 /* VGA */
780 else if (pix->width <= ov772x_win_vga.width ||
781 pix->height <= ov772x_win_vga.height) {
782 priv->win = &ov772x_win_vga;
783 pix->width = ov772x_win_vga.width;
784 pix->height = ov772x_win_vga.height;
785 }
786
787 pix->field = V4L2_FIELD_NONE;
788
789 return 0;
790}
791
792static int ov772x_video_probe(struct soc_camera_device *icd)
793{
794 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
795 u8 pid, ver;
796
797 /*
798 * We must have a parent by now. And it cannot be a wrong one.
799 * So this entire test is completely redundant.
800 */
801 if (!icd->dev.parent ||
802 to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
803 return -ENODEV;
804
805 /*
806 * ov772x only use 8 or 10 bit bus width
807 */
808 if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
809 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
810 dev_err(&icd->dev, "bus width error\n");
811 return -ENODEV;
812 }
813
814 icd->formats = ov772x_fmt_lists;
815 icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
816
817 if (priv->info->link.power)
818 priv->info->link.power(&priv->client->dev, 1);
819
820 /*
821 * check and show product ID and manufacturer ID
822 */
823 pid = i2c_smbus_read_byte_data(priv->client, PID);
824 ver = i2c_smbus_read_byte_data(priv->client, VER);
825 if (pid != 0x77 ||
826 ver != 0x21) {
827 if (priv->info->link.power)
828 priv->info->link.power(&priv->client->dev, 0);
829 return -ENODEV;
830 }
831
832 dev_info(&icd->dev,
833 "ov772x Product ID %0x:%0x Manufacturer ID %x:%x\n",
834 pid,
835 ver,
836 i2c_smbus_read_byte_data(priv->client, MIDH),
837 i2c_smbus_read_byte_data(priv->client, MIDL));
838
839
840 return soc_camera_video_start(icd);
841}
842
843static void ov772x_video_remove(struct soc_camera_device *icd)
844{
845 struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
846
847 soc_camera_video_stop(icd);
848
849 if (priv->info->link.power)
850 priv->info->link.power(&priv->client->dev, 0);
851
852}
853
854static struct soc_camera_ops ov772x_ops = {
855 .owner = THIS_MODULE,
856 .probe = ov772x_video_probe,
857 .remove = ov772x_video_remove,
858 .init = ov772x_init,
859 .release = ov772x_release,
860 .start_capture = ov772x_start_capture,
861 .stop_capture = ov772x_stop_capture,
862 .set_fmt_cap = ov772x_set_fmt_cap,
863 .try_fmt_cap = ov772x_try_fmt_cap,
864 .set_bus_param = ov772x_set_bus_param,
865 .query_bus_param = ov772x_query_bus_param,
866 .get_chip_id = ov772x_get_chip_id,
867#ifdef CONFIG_VIDEO_ADV_DEBUG
868 .get_register = ov772x_get_register,
869 .set_register = ov772x_set_register,
870#endif
871};
872
873/*
874 * i2c_driver function
875 */
876
877static int ov772x_probe(struct i2c_client *client,
878 const struct i2c_device_id *did)
879
880{
881 struct ov772x_priv *priv;
882 struct ov772x_camera_info *info;
883 struct soc_camera_device *icd;
884 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
885 int ret;
886
887 info = client->dev.platform_data;
888 if (!info)
889 return -EINVAL;
890
891 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
892 dev_err(&adapter->dev,
893 "I2C-Adapter doesn't support "
894 "I2C_FUNC_SMBUS_BYTE_DATA\n");
895 return -EIO;
896 }
897
898 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
899 if (!priv)
900 return -ENOMEM;
901
902 priv->info = info;
903 priv->client = client;
904 i2c_set_clientdata(client, priv);
905
906 icd = &priv->icd;
907 icd->ops = &ov772x_ops;
908 icd->control = &client->dev;
909 icd->width_max = MAX_WIDTH;
910 icd->height_max = MAX_HEIGHT;
911 icd->iface = priv->info->link.bus_id;
912
913 ret = soc_camera_device_register(icd);
914
915 if (ret)
916 kfree(priv);
917
918 return ret;
919}
920
921static int ov772x_remove(struct i2c_client *client)
922{
923 struct ov772x_priv *priv = i2c_get_clientdata(client);
924
925 soc_camera_device_unregister(&priv->icd);
926 kfree(priv);
927 return 0;
928}
929
930static const struct i2c_device_id ov772x_id[] = {
931 {"ov772x", 0},
932 { }
933};
934MODULE_DEVICE_TABLE(i2c, ov772x_id);
935
936
937static struct i2c_driver ov772x_i2c_driver = {
938 .driver = {
939 .name = "ov772x",
940 },
941 .probe = ov772x_probe,
942 .remove = ov772x_remove,
943 .id_table = ov772x_id,
944};
945
946/*
947 * module function
948 */
949
950static int __init ov772x_module_init(void)
951{
952 printk(KERN_INFO "ov772x driver\n");
953 return i2c_add_driver(&ov772x_i2c_driver);
954}
955
956static void __exit ov772x_module_exit(void)
957{
958 i2c_del_driver(&ov772x_i2c_driver);
959}
960
961module_init(ov772x_module_init);
962module_exit(ov772x_module_exit);
963
964MODULE_DESCRIPTION("SoC Camera driver for ov772x");
965MODULE_AUTHOR("Kuninori Morimoto");
966MODULE_LICENSE("GPL v2");