diff options
author | Sakari Ailus <sakari.ailus@iki.fi> | 2011-02-12 16:05:06 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-03-22 03:53:46 -0400 |
commit | 448de7e7850b804bc8f5efa60305a83333c257bf (patch) | |
tree | b88e08e84457715551b7f4b84ec3342a34e7d563 /drivers/media/video/omap3isp/isp.h | |
parent | c30b46e58b31a0fc420049e21117444862fc7cb7 (diff) |
[media] omap3isp: OMAP3 ISP core
The Image Signal Processor provides the system interface and the
processing capability to connect RAW or YUV image-sensor modules to the
OMAP3.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: David Cohen <dacohen@gmail.com>
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
Signed-off-by: Tuukka Toivonen <tuukkat76@gmail.com>
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Antti Koskipaa <akoskipa@gmail.com>
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: RaniSuneela <r-m@ti.com>
Signed-off-by: Atanas Filipov <afilipov@mm-sol.com>
Signed-off-by: Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Nayden Kanchev <nkanchev@mm-sol.com>
Signed-off-by: Phil Carmody <ext-phil.2.carmody@nokia.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Dominic Curran <dcurran@ti.com>
Signed-off-by: Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
Signed-off-by: Pallavi Kulkarni <p-kulkarni@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/omap3isp/isp.h')
-rw-r--r-- | drivers/media/video/omap3isp/isp.h | 430 |
1 files changed, 430 insertions, 0 deletions
diff --git a/drivers/media/video/omap3isp/isp.h b/drivers/media/video/omap3isp/isp.h new file mode 100644 index 000000000000..a8dfea413d34 --- /dev/null +++ b/drivers/media/video/omap3isp/isp.h | |||
@@ -0,0 +1,430 @@ | |||
1 | /* | ||
2 | * isp.h | ||
3 | * | ||
4 | * TI OMAP3 ISP - Core | ||
5 | * | ||
6 | * Copyright (C) 2009-2010 Nokia Corporation | ||
7 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
8 | * | ||
9 | * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | ||
10 | * Sakari Ailus <sakari.ailus@iki.fi> | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License version 2 as | ||
14 | * published by the Free Software Foundation. | ||
15 | * | ||
16 | * This program is distributed in the hope that it will be useful, but | ||
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
19 | * General Public License for more details. | ||
20 | * | ||
21 | * You should have received a copy of the GNU General Public License | ||
22 | * along with this program; if not, write to the Free Software | ||
23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
24 | * 02110-1301 USA | ||
25 | */ | ||
26 | |||
27 | #ifndef OMAP3_ISP_CORE_H | ||
28 | #define OMAP3_ISP_CORE_H | ||
29 | |||
30 | #include <media/v4l2-device.h> | ||
31 | #include <linux/device.h> | ||
32 | #include <linux/io.h> | ||
33 | #include <linux/platform_device.h> | ||
34 | #include <linux/wait.h> | ||
35 | #include <plat/iommu.h> | ||
36 | #include <plat/iovmm.h> | ||
37 | |||
38 | #include "ispstat.h" | ||
39 | #include "ispccdc.h" | ||
40 | #include "ispreg.h" | ||
41 | #include "ispresizer.h" | ||
42 | #include "isppreview.h" | ||
43 | #include "ispcsiphy.h" | ||
44 | #include "ispcsi2.h" | ||
45 | #include "ispccp2.h" | ||
46 | |||
47 | #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8) | ||
48 | |||
49 | #define ISP_TOK_TERM 0xFFFFFFFF /* | ||
50 | * terminating token for ISP | ||
51 | * modules reg list | ||
52 | */ | ||
53 | #define to_isp_device(ptr_module) \ | ||
54 | container_of(ptr_module, struct isp_device, isp_##ptr_module) | ||
55 | #define to_device(ptr_module) \ | ||
56 | (to_isp_device(ptr_module)->dev) | ||
57 | |||
58 | enum isp_mem_resources { | ||
59 | OMAP3_ISP_IOMEM_MAIN, | ||
60 | OMAP3_ISP_IOMEM_CCP2, | ||
61 | OMAP3_ISP_IOMEM_CCDC, | ||
62 | OMAP3_ISP_IOMEM_HIST, | ||
63 | OMAP3_ISP_IOMEM_H3A, | ||
64 | OMAP3_ISP_IOMEM_PREV, | ||
65 | OMAP3_ISP_IOMEM_RESZ, | ||
66 | OMAP3_ISP_IOMEM_SBL, | ||
67 | OMAP3_ISP_IOMEM_CSI2A_REGS1, | ||
68 | OMAP3_ISP_IOMEM_CSIPHY2, | ||
69 | OMAP3_ISP_IOMEM_CSI2A_REGS2, | ||
70 | OMAP3_ISP_IOMEM_CSI2C_REGS1, | ||
71 | OMAP3_ISP_IOMEM_CSIPHY1, | ||
72 | OMAP3_ISP_IOMEM_CSI2C_REGS2, | ||
73 | OMAP3_ISP_IOMEM_LAST | ||
74 | }; | ||
75 | |||
76 | enum isp_sbl_resource { | ||
77 | OMAP3_ISP_SBL_CSI1_READ = 0x1, | ||
78 | OMAP3_ISP_SBL_CSI1_WRITE = 0x2, | ||
79 | OMAP3_ISP_SBL_CSI2A_WRITE = 0x4, | ||
80 | OMAP3_ISP_SBL_CSI2C_WRITE = 0x8, | ||
81 | OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10, | ||
82 | OMAP3_ISP_SBL_CCDC_WRITE = 0x20, | ||
83 | OMAP3_ISP_SBL_PREVIEW_READ = 0x40, | ||
84 | OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80, | ||
85 | OMAP3_ISP_SBL_RESIZER_READ = 0x100, | ||
86 | OMAP3_ISP_SBL_RESIZER_WRITE = 0x200, | ||
87 | }; | ||
88 | |||
89 | enum isp_subclk_resource { | ||
90 | OMAP3_ISP_SUBCLK_CCDC = (1 << 0), | ||
91 | OMAP3_ISP_SUBCLK_H3A = (1 << 1), | ||
92 | OMAP3_ISP_SUBCLK_HIST = (1 << 2), | ||
93 | OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3), | ||
94 | OMAP3_ISP_SUBCLK_RESIZER = (1 << 4), | ||
95 | }; | ||
96 | |||
97 | enum isp_interface_type { | ||
98 | ISP_INTERFACE_PARALLEL, | ||
99 | ISP_INTERFACE_CSI2A_PHY2, | ||
100 | ISP_INTERFACE_CCP2B_PHY1, | ||
101 | ISP_INTERFACE_CCP2B_PHY2, | ||
102 | ISP_INTERFACE_CSI2C_PHY1, | ||
103 | }; | ||
104 | |||
105 | /* ISP: OMAP 34xx ES 1.0 */ | ||
106 | #define ISP_REVISION_1_0 0x10 | ||
107 | /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */ | ||
108 | #define ISP_REVISION_2_0 0x20 | ||
109 | /* ISP2P: OMAP 36xx */ | ||
110 | #define ISP_REVISION_15_0 0xF0 | ||
111 | |||
112 | /* | ||
113 | * struct isp_res_mapping - Map ISP io resources to ISP revision. | ||
114 | * @isp_rev: ISP_REVISION_x_x | ||
115 | * @map: bitmap for enum isp_mem_resources | ||
116 | */ | ||
117 | struct isp_res_mapping { | ||
118 | u32 isp_rev; | ||
119 | u32 map; | ||
120 | }; | ||
121 | |||
122 | /* | ||
123 | * struct isp_reg - Structure for ISP register values. | ||
124 | * @reg: 32-bit Register address. | ||
125 | * @val: 32-bit Register value. | ||
126 | */ | ||
127 | struct isp_reg { | ||
128 | enum isp_mem_resources mmio_range; | ||
129 | u32 reg; | ||
130 | u32 val; | ||
131 | }; | ||
132 | |||
133 | /** | ||
134 | * struct isp_parallel_platform_data - Parallel interface platform data | ||
135 | * @width: Parallel bus width in bits (8, 10, 11 or 12) | ||
136 | * @data_lane_shift: Data lane shifter | ||
137 | * 0 - CAMEXT[13:0] -> CAM[13:0] | ||
138 | * 1 - CAMEXT[13:2] -> CAM[11:0] | ||
139 | * 2 - CAMEXT[13:4] -> CAM[9:0] | ||
140 | * 3 - CAMEXT[13:6] -> CAM[7:0] | ||
141 | * @clk_pol: Pixel clock polarity | ||
142 | * 0 - Non Inverted, 1 - Inverted | ||
143 | * @bridge: CCDC Bridge input control | ||
144 | * ISPCTRL_PAR_BRIDGE_DISABLE - Disable | ||
145 | * ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian | ||
146 | * ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian | ||
147 | */ | ||
148 | struct isp_parallel_platform_data { | ||
149 | unsigned int width; | ||
150 | unsigned int data_lane_shift:2; | ||
151 | unsigned int clk_pol:1; | ||
152 | unsigned int bridge:4; | ||
153 | }; | ||
154 | |||
155 | /** | ||
156 | * struct isp_ccp2_platform_data - CCP2 interface platform data | ||
157 | * @strobe_clk_pol: Strobe/clock polarity | ||
158 | * 0 - Non Inverted, 1 - Inverted | ||
159 | * @crc: Enable the cyclic redundancy check | ||
160 | * @ccp2_mode: Enable CCP2 compatibility mode | ||
161 | * 0 - MIPI-CSI1 mode, 1 - CCP2 mode | ||
162 | * @phy_layer: Physical layer selection | ||
163 | * ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer | ||
164 | * ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer | ||
165 | * @vpclk_div: Video port output clock control | ||
166 | */ | ||
167 | struct isp_ccp2_platform_data { | ||
168 | unsigned int strobe_clk_pol:1; | ||
169 | unsigned int crc:1; | ||
170 | unsigned int ccp2_mode:1; | ||
171 | unsigned int phy_layer:1; | ||
172 | unsigned int vpclk_div:2; | ||
173 | }; | ||
174 | |||
175 | /** | ||
176 | * struct isp_csi2_platform_data - CSI2 interface platform data | ||
177 | * @crc: Enable the cyclic redundancy check | ||
178 | * @vpclk_div: Video port output clock control | ||
179 | */ | ||
180 | struct isp_csi2_platform_data { | ||
181 | unsigned crc:1; | ||
182 | unsigned vpclk_div:2; | ||
183 | }; | ||
184 | |||
185 | struct isp_subdev_i2c_board_info { | ||
186 | struct i2c_board_info *board_info; | ||
187 | int i2c_adapter_id; | ||
188 | }; | ||
189 | |||
190 | struct isp_v4l2_subdevs_group { | ||
191 | struct isp_subdev_i2c_board_info *subdevs; | ||
192 | enum isp_interface_type interface; | ||
193 | union { | ||
194 | struct isp_parallel_platform_data parallel; | ||
195 | struct isp_ccp2_platform_data ccp2; | ||
196 | struct isp_csi2_platform_data csi2; | ||
197 | } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ | ||
198 | }; | ||
199 | |||
200 | struct isp_platform_data { | ||
201 | struct isp_v4l2_subdevs_group *subdevs; | ||
202 | }; | ||
203 | |||
204 | struct isp_platform_callback { | ||
205 | u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel); | ||
206 | int (*csiphy_config)(struct isp_csiphy *phy, | ||
207 | struct isp_csiphy_dphy_cfg *dphy, | ||
208 | struct isp_csiphy_lanes_cfg *lanes); | ||
209 | void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk); | ||
210 | }; | ||
211 | |||
212 | /* | ||
213 | * struct isp_device - ISP device structure. | ||
214 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
215 | * @revision: Stores current ISP module revision. | ||
216 | * @irq_num: Currently used IRQ number. | ||
217 | * @mmio_base: Array with kernel base addresses for ioremapped ISP register | ||
218 | * regions. | ||
219 | * @mmio_base_phys: Array with physical L4 bus addresses for ISP register | ||
220 | * regions. | ||
221 | * @mmio_size: Array with ISP register regions size in bytes. | ||
222 | * @raw_dmamask: Raw DMA mask | ||
223 | * @stat_lock: Spinlock for handling statistics | ||
224 | * @isp_mutex: Mutex for serializing requests to ISP. | ||
225 | * @has_context: Context has been saved at least once and can be restored. | ||
226 | * @ref_count: Reference count for handling multiple ISP requests. | ||
227 | * @cam_ick: Pointer to camera interface clock structure. | ||
228 | * @cam_mclk: Pointer to camera functional clock structure. | ||
229 | * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure. | ||
230 | * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. | ||
231 | * @l3_ick: Pointer to OMAP3 L3 bus interface clock. | ||
232 | * @irq: Currently attached ISP ISR callbacks information structure. | ||
233 | * @isp_af: Pointer to current settings for ISP AutoFocus SCM. | ||
234 | * @isp_hist: Pointer to current settings for ISP Histogram SCM. | ||
235 | * @isp_h3a: Pointer to current settings for ISP Auto Exposure and | ||
236 | * White Balance SCM. | ||
237 | * @isp_res: Pointer to current settings for ISP Resizer. | ||
238 | * @isp_prev: Pointer to current settings for ISP Preview. | ||
239 | * @isp_ccdc: Pointer to current settings for ISP CCDC. | ||
240 | * @iommu: Pointer to requested IOMMU instance for ISP. | ||
241 | * @platform_cb: ISP driver callback function pointers for platform code | ||
242 | * | ||
243 | * This structure is used to store the OMAP ISP Information. | ||
244 | */ | ||
245 | struct isp_device { | ||
246 | struct v4l2_device v4l2_dev; | ||
247 | struct media_device media_dev; | ||
248 | struct device *dev; | ||
249 | u32 revision; | ||
250 | |||
251 | /* platform HW resources */ | ||
252 | struct isp_platform_data *pdata; | ||
253 | unsigned int irq_num; | ||
254 | |||
255 | void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST]; | ||
256 | unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST]; | ||
257 | resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST]; | ||
258 | |||
259 | u64 raw_dmamask; | ||
260 | |||
261 | /* ISP Obj */ | ||
262 | spinlock_t stat_lock; /* common lock for statistic drivers */ | ||
263 | struct mutex isp_mutex; /* For handling ref_count field */ | ||
264 | int has_context; | ||
265 | int ref_count; | ||
266 | unsigned int autoidle; | ||
267 | u32 xclk_divisor[2]; /* Two clocks, a and b. */ | ||
268 | #define ISP_CLK_CAM_ICK 0 | ||
269 | #define ISP_CLK_CAM_MCLK 1 | ||
270 | #define ISP_CLK_DPLL4_M5_CK 2 | ||
271 | #define ISP_CLK_CSI2_FCK 3 | ||
272 | #define ISP_CLK_L3_ICK 4 | ||
273 | struct clk *clock[5]; | ||
274 | |||
275 | /* ISP modules */ | ||
276 | struct ispstat isp_af; | ||
277 | struct ispstat isp_aewb; | ||
278 | struct ispstat isp_hist; | ||
279 | struct isp_res_device isp_res; | ||
280 | struct isp_prev_device isp_prev; | ||
281 | struct isp_ccdc_device isp_ccdc; | ||
282 | struct isp_csi2_device isp_csi2a; | ||
283 | struct isp_csi2_device isp_csi2c; | ||
284 | struct isp_ccp2_device isp_ccp2; | ||
285 | struct isp_csiphy isp_csiphy1; | ||
286 | struct isp_csiphy isp_csiphy2; | ||
287 | |||
288 | unsigned int sbl_resources; | ||
289 | unsigned int subclk_resources; | ||
290 | |||
291 | struct iommu *iommu; | ||
292 | |||
293 | struct isp_platform_callback platform_cb; | ||
294 | }; | ||
295 | |||
296 | #define v4l2_dev_to_isp_device(dev) \ | ||
297 | container_of(dev, struct isp_device, v4l2_dev) | ||
298 | |||
299 | void omap3isp_hist_dma_done(struct isp_device *isp); | ||
300 | |||
301 | void omap3isp_flush(struct isp_device *isp); | ||
302 | |||
303 | int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, | ||
304 | atomic_t *stopping); | ||
305 | |||
306 | int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, | ||
307 | atomic_t *stopping); | ||
308 | |||
309 | int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, | ||
310 | enum isp_pipeline_stream_state state); | ||
311 | void omap3isp_configure_bridge(struct isp_device *isp, | ||
312 | enum ccdc_input_entity input, | ||
313 | const struct isp_parallel_platform_data *pdata); | ||
314 | |||
315 | #define ISP_XCLK_NONE -1 | ||
316 | #define ISP_XCLK_A 0 | ||
317 | #define ISP_XCLK_B 1 | ||
318 | |||
319 | struct isp_device *omap3isp_get(struct isp_device *isp); | ||
320 | void omap3isp_put(struct isp_device *isp); | ||
321 | |||
322 | void omap3isp_print_status(struct isp_device *isp); | ||
323 | |||
324 | void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res); | ||
325 | void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res); | ||
326 | |||
327 | void omap3isp_subclk_enable(struct isp_device *isp, | ||
328 | enum isp_subclk_resource res); | ||
329 | void omap3isp_subclk_disable(struct isp_device *isp, | ||
330 | enum isp_subclk_resource res); | ||
331 | |||
332 | int omap3isp_pipeline_pm_use(struct media_entity *entity, int use); | ||
333 | |||
334 | int omap3isp_register_entities(struct platform_device *pdev, | ||
335 | struct v4l2_device *v4l2_dev); | ||
336 | void omap3isp_unregister_entities(struct platform_device *pdev); | ||
337 | |||
338 | /* | ||
339 | * isp_reg_readl - Read value of an OMAP3 ISP register | ||
340 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
341 | * @isp_mmio_range: Range to which the register offset refers to. | ||
342 | * @reg_offset: Register offset to read from. | ||
343 | * | ||
344 | * Returns an unsigned 32 bit value with the required register contents. | ||
345 | */ | ||
346 | static inline | ||
347 | u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, | ||
348 | u32 reg_offset) | ||
349 | { | ||
350 | return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); | ||
351 | } | ||
352 | |||
353 | /* | ||
354 | * isp_reg_writel - Write value to an OMAP3 ISP register | ||
355 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
356 | * @reg_value: 32 bit value to write to the register. | ||
357 | * @isp_mmio_range: Range to which the register offset refers to. | ||
358 | * @reg_offset: Register offset to write into. | ||
359 | */ | ||
360 | static inline | ||
361 | void isp_reg_writel(struct isp_device *isp, u32 reg_value, | ||
362 | enum isp_mem_resources isp_mmio_range, u32 reg_offset) | ||
363 | { | ||
364 | __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); | ||
365 | } | ||
366 | |||
367 | /* | ||
368 | * isp_reg_and - Clear individual bits in an OMAP3 ISP register | ||
369 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
370 | * @mmio_range: Range to which the register offset refers to. | ||
371 | * @reg: Register offset to work on. | ||
372 | * @clr_bits: 32 bit value which would be cleared in the register. | ||
373 | */ | ||
374 | static inline | ||
375 | void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, | ||
376 | u32 reg, u32 clr_bits) | ||
377 | { | ||
378 | u32 v = isp_reg_readl(isp, mmio_range, reg); | ||
379 | |||
380 | isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); | ||
381 | } | ||
382 | |||
383 | /* | ||
384 | * isp_reg_set - Set individual bits in an OMAP3 ISP register | ||
385 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
386 | * @mmio_range: Range to which the register offset refers to. | ||
387 | * @reg: Register offset to work on. | ||
388 | * @set_bits: 32 bit value which would be set in the register. | ||
389 | */ | ||
390 | static inline | ||
391 | void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, | ||
392 | u32 reg, u32 set_bits) | ||
393 | { | ||
394 | u32 v = isp_reg_readl(isp, mmio_range, reg); | ||
395 | |||
396 | isp_reg_writel(isp, v | set_bits, mmio_range, reg); | ||
397 | } | ||
398 | |||
399 | /* | ||
400 | * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register | ||
401 | * @dev: Device pointer specific to the OMAP3 ISP. | ||
402 | * @mmio_range: Range to which the register offset refers to. | ||
403 | * @reg: Register offset to work on. | ||
404 | * @clr_bits: 32 bit value which would be cleared in the register. | ||
405 | * @set_bits: 32 bit value which would be set in the register. | ||
406 | * | ||
407 | * The clear operation is done first, and then the set operation. | ||
408 | */ | ||
409 | static inline | ||
410 | void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, | ||
411 | u32 reg, u32 clr_bits, u32 set_bits) | ||
412 | { | ||
413 | u32 v = isp_reg_readl(isp, mmio_range, reg); | ||
414 | |||
415 | isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); | ||
416 | } | ||
417 | |||
418 | static inline enum v4l2_buf_type | ||
419 | isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad) | ||
420 | { | ||
421 | if (pad >= subdev->entity.num_pads) | ||
422 | return 0; | ||
423 | |||
424 | if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK) | ||
425 | return V4L2_BUF_TYPE_VIDEO_OUTPUT; | ||
426 | else | ||
427 | return V4L2_BUF_TYPE_VIDEO_CAPTURE; | ||
428 | } | ||
429 | |||
430 | #endif /* OMAP3_ISP_CORE_H */ | ||