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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-03-03 11:31:36 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-04-06 20:44:02 -0400
commitcde4362f0244a70bab73e37e24f167186bb9a8be (patch)
tree17a52f26a6d14c9742c698b2b7e109fad6ac8695 /drivers/media/video/cx231xx/cx231xx-avcore.c
parent84b5dbf39ed2f51224841bbbf08439158d69d427 (diff)
V4L/DVB (10956): cx231xx: First series of manual CodingStyle fixes
This patch cleans up CodingStyle on the following source files: There are still much more to be fixed on later patches Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx231xx/cx231xx-avcore.c')
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c2107
1 files changed, 886 insertions, 1221 deletions
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index 3c09b9473843..bbfc78ebd94b 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -1,5 +1,6 @@
1/* 1/*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
3 4
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 6
@@ -38,9 +39,9 @@
38 39
39#include "cx231xx.h" 40#include "cx231xx.h"
40 41
41/************************************************************************************* 42/******************************************************************************
42 * C O L I B R I - B L O C K C O N T R O L functions * 43 * C O L I B R I - B L O C K C O N T R O L functions *
43 *************************************************************************************/ 44 ********************************************************************* ********/
44int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) 45int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
45{ 46{
46 int status = 0; 47 int status = 0;
@@ -50,42 +51,35 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
50 51
51 /* super block initialize */ 52 /* super block initialize */
52 temp = (u8) (ref_count & 0xff); 53 temp = (u8) (ref_count & 0xff);
53 status = 54 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
54 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 55 SUP_BLK_TUNE2, 2, temp, 1);
55 2, temp, 1);
56 56
57 status = 57 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
58 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, 58 SUP_BLK_TUNE2, 2,
59 &colibri_power_status, 1); 59 &colibri_power_status, 1);
60 60
61 temp = (u8) ((ref_count & 0x300) >> 8); 61 temp = (u8) ((ref_count & 0x300) >> 8);
62 temp |= 0x40; 62 temp |= 0x40;
63 status = 63 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
64 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 64 SUP_BLK_TUNE1, 2, temp, 1);
65 2, temp, 1); 65 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
66 status = 66 SUP_BLK_PLL2, 2, 0x0f, 1);
67 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2,
68 0x0f, 1);
69 67
70 /* enable pll */ 68 /* enable pll */
71 while (colibri_power_status != 0x18) { 69 while (colibri_power_status != 0x18) {
72 status = 70 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
73 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 71 SUP_BLK_PWRDN, 2, 0x18, 1);
74 SUP_BLK_PWRDN, 2, 0x18, 1); 72 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
75 status = 73 SUP_BLK_PWRDN, 2,
76 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 74 &colibri_power_status, 1);
77 SUP_BLK_PWRDN, 2,
78 &colibri_power_status, 1);
79 colibri_power_status &= 0xff; 75 colibri_power_status &= 0xff;
80 if (status < 0) { 76 if (status < 0) {
81 cx231xx_info 77 cx231xx_info(": Init Super Block failed in sending/receiving cmds\n");
82 (": Init Super Block failed in sending/receiving cmds\n");
83 break; 78 break;
84 } 79 }
85 i++; 80 i++;
86 if (i == 10) { 81 if (i == 10) {
87 cx231xx_info 82 cx231xx_info(": Init Super Block force break in loop !!!!\n");
88 (": Init Super Block force break in loop !!!!\n");
89 status = -1; 83 status = -1;
90 break; 84 break;
91 } 85 }
@@ -95,9 +89,8 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
95 return status; 89 return status;
96 90
97 /* start tuning filter */ 91 /* start tuning filter */
98 status = 92 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
99 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 93 SUP_BLK_TUNE3, 2, 0x40, 1);
100 2, 0x40, 1);
101 msleep(5); 94 msleep(5);
102 95
103 /* exit tuning */ 96 /* exit tuning */
@@ -113,86 +106,64 @@ int cx231xx_colibri_init_channels(struct cx231xx *dev)
113 int status = 0; 106 int status = 0;
114 107
115 /* power up all 3 channels, clear pd_buffer */ 108 /* power up all 3 channels, clear pd_buffer */
116 status = 109 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
117 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
118 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); 110 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
119 status = 111 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
120 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
121 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); 112 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
122 status = 113 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
123 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
124 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); 114 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
125 115
126 /* Enable quantizer calibration */ 116 /* Enable quantizer calibration */
127 status = 117 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
128 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, 118 ADC_COM_QUANT, 2, 0x02, 1);
129 2, 0x02, 1);
130 119
131 /* channel initialize, force modulator (fb) reset */ 120 /* channel initialize, force modulator (fb) reset */
132 status = 121 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
133 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
134 ADC_FB_FRCRST_CH1, 2, 0x17, 1); 122 ADC_FB_FRCRST_CH1, 2, 0x17, 1);
135 status = 123 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
136 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
137 ADC_FB_FRCRST_CH2, 2, 0x17, 1); 124 ADC_FB_FRCRST_CH2, 2, 0x17, 1);
138 status = 125 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
139 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
140 ADC_FB_FRCRST_CH3, 2, 0x17, 1); 126 ADC_FB_FRCRST_CH3, 2, 0x17, 1);
141 127
142 /* start quantilizer calibration */ 128 /* start quantilizer calibration */
143 status = 129 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
144 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
145 ADC_CAL_ATEST_CH1, 2, 0x10, 1); 130 ADC_CAL_ATEST_CH1, 2, 0x10, 1);
146 status = 131 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
147 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
148 ADC_CAL_ATEST_CH2, 2, 0x10, 1); 132 ADC_CAL_ATEST_CH2, 2, 0x10, 1);
149 status = 133 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
150 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
151 ADC_CAL_ATEST_CH3, 2, 0x10, 1); 134 ADC_CAL_ATEST_CH3, 2, 0x10, 1);
152 msleep(5); 135 msleep(5);
153 136
154 /* exit modulator (fb) reset */ 137 /* exit modulator (fb) reset */
155 status = 138 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
156 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
157 ADC_FB_FRCRST_CH1, 2, 0x07, 1); 139 ADC_FB_FRCRST_CH1, 2, 0x07, 1);
158 status = 140 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
159 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
160 ADC_FB_FRCRST_CH2, 2, 0x07, 1); 141 ADC_FB_FRCRST_CH2, 2, 0x07, 1);
161 status = 142 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
162 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
163 ADC_FB_FRCRST_CH3, 2, 0x07, 1); 143 ADC_FB_FRCRST_CH3, 2, 0x07, 1);
164 144
165 /* enable the pre_clamp in each channel for single-ended input */ 145 /* enable the pre_clamp in each channel for single-ended input */
166 status = 146 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
167 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
168 ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); 147 ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1);
169 status = 148 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
170 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
171 ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); 149 ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1);
172 status = 150 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
173 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
174 ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); 151 ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1);
175 152
176 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 153 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
177 status = 154 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
178 cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
179 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 155 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
180 status = 156 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
181 cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
182 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 157 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
183 status = 158 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
184 cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
185 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 159 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
186 160
187 /* dynamic element matching off */ 161 /* dynamic element matching off */
188 status = 162 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
189 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
190 ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); 163 ADC_DCSERVO_DEM_CH1, 2, 0x03, 1);
191 status = 164 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
192 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
193 ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); 165 ADC_DCSERVO_DEM_CH2, 2, 0x03, 1);
194 status = 166 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
195 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
196 ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); 167 ADC_DCSERVO_DEM_CH3, 2, 0x03, 1);
197 168
198 return status; 169 return status;
@@ -235,8 +206,7 @@ int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux)
235 value &= (!INPUT_SEL_MASK); 206 value &= (!INPUT_SEL_MASK);
236 value |= (ch1_setting - 1) << 4; 207 value |= (ch1_setting - 1) << 4;
237 value &= 0xff; 208 value &= 0xff;
238 status = 209 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
239 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
240 ADC_INPUT_CH1, 2, value, 1); 210 ADC_INPUT_CH1, 2, value, 1);
241 } 211 }
242 212
@@ -247,21 +217,19 @@ int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux)
247 value &= (!INPUT_SEL_MASK); 217 value &= (!INPUT_SEL_MASK);
248 value |= (ch2_setting - 1) << 4; 218 value |= (ch2_setting - 1) << 4;
249 value &= 0xff; 219 value &= 0xff;
250 status = 220 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
251 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
252 ADC_INPUT_CH2, 2, value, 1); 221 ADC_INPUT_CH2, 2, value, 1);
253 } 222 }
254 223
255 /* For ch3_setting, the value to put in the register is 7 less than the input number */ 224 /* For ch3_setting, the value to put in the register is
225 7 less than the input number */
256 if (ch3_setting != 0) { 226 if (ch3_setting != 0) {
257 status = 227 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
258 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
259 ADC_INPUT_CH3, 2, &value, 1); 228 ADC_INPUT_CH3, 2, &value, 1);
260 value &= (!INPUT_SEL_MASK); 229 value &= (!INPUT_SEL_MASK);
261 value |= (ch3_setting - 1) << 4; 230 value |= (ch3_setting - 1) << 4;
262 value &= 0xff; 231 value &= 0xff;
263 status = 232 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
264 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
265 ADC_INPUT_CH3, 2, value, 1); 233 ADC_INPUT_CH3, 2, value, 1);
266 } 234 }
267 235
@@ -290,12 +258,9 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
290 break; 258 break;
291 } 259 }
292 260
293 if ((mode != dev->colibri_mode) 261 if ((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION))
294 && (dev->video_input == CX231XX_VMUX_TELEVISION)) { 262 status = cx231xx_colibri_adjust_ref_count(dev,
295 status =
296 cx231xx_colibri_adjust_ref_count(dev,
297 CX231XX_VMUX_TELEVISION); 263 CX231XX_VMUX_TELEVISION);
298 }
299 264
300 dev->colibri_mode = mode; 265 dev->colibri_mode = mode;
301 266
@@ -314,84 +279,80 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
314 279
315 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 280 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
316 while (colibri_power_status != 0x18) { 281 while (colibri_power_status != 0x18) {
317 status = 282 status = cx231xx_write_i2c_data(dev,
318 cx231xx_write_i2c_data(dev, 283 Colibri_DEVICE_ADDRESS,
319 Colibri_DEVICE_ADDRESS, 284 SUP_BLK_PWRDN, 2,
320 SUP_BLK_PWRDN, 2, 285 0x18, 1);
321 0x18, 1); 286 status = cx231xx_read_i2c_data(dev,
322 status = 287 Colibri_DEVICE_ADDRESS,
323 cx231xx_read_i2c_data(dev, 288 SUP_BLK_PWRDN, 2,
324 Colibri_DEVICE_ADDRESS, 289 &colibri_power_status,
325 SUP_BLK_PWRDN, 2, 290 1);
326 &colibri_power_status,
327 1);
328 if (status < 0) 291 if (status < 0)
329 break; 292 break;
330 } 293 }
331 294
332 status = 295 status = cx231xx_write_i2c_data(dev,
333 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 296 Colibri_DEVICE_ADDRESS,
334 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 297 ADC_PWRDN_CLAMP_CH1, 2, 0x00,
335 1); 298 1);
336 status = 299 status = cx231xx_write_i2c_data(dev,
337 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 300 Colibri_DEVICE_ADDRESS,
338 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 301 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
339 1); 302 1);
340 status = 303 status = cx231xx_write_i2c_data(dev,
341 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 304 Colibri_DEVICE_ADDRESS,
342 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 305 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
343 1); 306 1);
344 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 307 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
345 status = 308 status = cx231xx_write_i2c_data(dev,
346 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 309 Colibri_DEVICE_ADDRESS,
347 ADC_PWRDN_CLAMP_CH1, 2, 0x70, 310 ADC_PWRDN_CLAMP_CH1, 2, 0x70,
348 1); 311 1);
349 status = 312 status = cx231xx_write_i2c_data(dev,
350 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 313 Colibri_DEVICE_ADDRESS,
351 ADC_PWRDN_CLAMP_CH2, 2, 0x70, 314 ADC_PWRDN_CLAMP_CH2, 2, 0x70,
352 1); 315 1);
353 status = 316 status = cx231xx_write_i2c_data(dev,
354 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 317 Colibri_DEVICE_ADDRESS,
355 ADC_PWRDN_CLAMP_CH3, 2, 0x70, 318 ADC_PWRDN_CLAMP_CH3, 2, 0x70,
356 1); 319 1);
357 320
358 status = 321 status = cx231xx_read_i2c_data(dev,
359 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 322 Colibri_DEVICE_ADDRESS,
360 SUP_BLK_PWRDN, 2, 323 SUP_BLK_PWRDN, 2,
361 &colibri_power_status, 1); 324 &colibri_power_status, 1);
362 colibri_power_status |= 0x07; 325 colibri_power_status |= 0x07;
363 status = 326 status = cx231xx_write_i2c_data(dev,
364 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 327 Colibri_DEVICE_ADDRESS,
365 SUP_BLK_PWRDN, 2, 328 SUP_BLK_PWRDN, 2,
366 colibri_power_status, 1); 329 colibri_power_status, 1);
367 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 330 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
368 331
369 while (colibri_power_status != 0x18) { 332 while (colibri_power_status != 0x18) {
370 status = 333 status = cx231xx_write_i2c_data(dev,
371 cx231xx_write_i2c_data(dev, 334 Colibri_DEVICE_ADDRESS,
372 Colibri_DEVICE_ADDRESS, 335 SUP_BLK_PWRDN, 2,
373 SUP_BLK_PWRDN, 2, 336 0x18, 1);
374 0x18, 1); 337 status = cx231xx_read_i2c_data(dev,
375 status = 338 Colibri_DEVICE_ADDRESS,
376 cx231xx_read_i2c_data(dev, 339 SUP_BLK_PWRDN, 2,
377 Colibri_DEVICE_ADDRESS, 340 &colibri_power_status,
378 SUP_BLK_PWRDN, 2, 341 1);
379 &colibri_power_status,
380 1);
381 if (status < 0) 342 if (status < 0)
382 break; 343 break;
383 } 344 }
384 345
385 status = 346 status = cx231xx_write_i2c_data(dev,
386 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 347 Colibri_DEVICE_ADDRESS,
387 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 348 ADC_PWRDN_CLAMP_CH1, 2, 0x00,
388 1); 349 1);
389 status = 350 status = cx231xx_write_i2c_data(dev,
390 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 351 Colibri_DEVICE_ADDRESS,
391 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 352 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
392 1); 353 1);
393 status = 354 status = cx231xx_write_i2c_data(dev,
394 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 355 Colibri_DEVICE_ADDRESS,
395 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 356 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
396 1); 357 1);
397 } else { 358 } else {
@@ -402,85 +363,83 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
402 default: 363 default:
403 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 364 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
404 while (colibri_power_status != 0x18) { 365 while (colibri_power_status != 0x18) {
405 status = 366 status = cx231xx_write_i2c_data(dev,
406 cx231xx_write_i2c_data(dev, 367 Colibri_DEVICE_ADDRESS,
407 Colibri_DEVICE_ADDRESS, 368 SUP_BLK_PWRDN, 2,
408 SUP_BLK_PWRDN, 2, 369 0x18, 1);
409 0x18, 1); 370 status = cx231xx_read_i2c_data(dev,
410 status = 371 Colibri_DEVICE_ADDRESS,
411 cx231xx_read_i2c_data(dev, 372 SUP_BLK_PWRDN, 2,
412 Colibri_DEVICE_ADDRESS, 373 &colibri_power_status,
413 SUP_BLK_PWRDN, 2, 374 1);
414 &colibri_power_status,
415 1);
416 if (status < 0) 375 if (status < 0)
417 break; 376 break;
418 } 377 }
419 378
420 status = 379 status = cx231xx_write_i2c_data(dev,
421 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 380 Colibri_DEVICE_ADDRESS,
422 ADC_PWRDN_CLAMP_CH1, 2, 0x40, 381 ADC_PWRDN_CLAMP_CH1, 2,
423 1); 382 0x40, 1);
424 status = 383 status = cx231xx_write_i2c_data(dev,
425 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 384 Colibri_DEVICE_ADDRESS,
426 ADC_PWRDN_CLAMP_CH2, 2, 0x40, 385 ADC_PWRDN_CLAMP_CH2, 2,
427 1); 386 0x40, 1);
428 status = 387 status = cx231xx_write_i2c_data(dev,
429 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 388 Colibri_DEVICE_ADDRESS,
430 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 389 ADC_PWRDN_CLAMP_CH3, 2,
431 1); 390 0x00, 1);
432 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 391 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
433 status = 392 status = cx231xx_write_i2c_data(dev,
434 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 393 Colibri_DEVICE_ADDRESS,
435 ADC_PWRDN_CLAMP_CH1, 2, 0x70, 394 ADC_PWRDN_CLAMP_CH1, 2,
436 1); 395 0x70, 1);
437 status = 396 status = cx231xx_write_i2c_data(dev,
438 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 397 Colibri_DEVICE_ADDRESS,
439 ADC_PWRDN_CLAMP_CH2, 2, 0x70, 398 ADC_PWRDN_CLAMP_CH2, 2,
440 1); 399 0x70, 1);
441 status = 400 status = cx231xx_write_i2c_data(dev,
442 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 401 Colibri_DEVICE_ADDRESS,
443 ADC_PWRDN_CLAMP_CH3, 2, 0x70, 402 ADC_PWRDN_CLAMP_CH3, 2,
444 1); 403 0x70, 1);
445 404
446 status = 405 status = cx231xx_read_i2c_data(dev,
447 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 406 Colibri_DEVICE_ADDRESS,
448 SUP_BLK_PWRDN, 2, 407 SUP_BLK_PWRDN, 2,
449 &colibri_power_status, 1); 408 &colibri_power_status,
409 1);
450 colibri_power_status |= 0x07; 410 colibri_power_status |= 0x07;
451 status = 411 status = cx231xx_write_i2c_data(dev,
452 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 412 Colibri_DEVICE_ADDRESS,
453 SUP_BLK_PWRDN, 2, 413 SUP_BLK_PWRDN, 2,
454 colibri_power_status, 1); 414 colibri_power_status,
415 1);
455 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 416 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
456 while (colibri_power_status != 0x18) { 417 while (colibri_power_status != 0x18) {
457 status = 418 status = cx231xx_write_i2c_data(dev,
458 cx231xx_write_i2c_data(dev, 419 Colibri_DEVICE_ADDRESS,
459 Colibri_DEVICE_ADDRESS, 420 SUP_BLK_PWRDN, 2,
460 SUP_BLK_PWRDN, 2, 421 0x18, 1);
461 0x18, 1); 422 status = cx231xx_read_i2c_data(dev,
462 status = 423 Colibri_DEVICE_ADDRESS,
463 cx231xx_read_i2c_data(dev, 424 SUP_BLK_PWRDN, 2,
464 Colibri_DEVICE_ADDRESS, 425 &colibri_power_status,
465 SUP_BLK_PWRDN, 2, 426 1);
466 &colibri_power_status,
467 1);
468 if (status < 0) 427 if (status < 0)
469 break; 428 break;
470 } 429 }
471 430
472 status = 431 status = cx231xx_write_i2c_data(dev,
473 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 432 Colibri_DEVICE_ADDRESS,
474 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 433 ADC_PWRDN_CLAMP_CH1, 2,
475 1); 434 0x00, 1);
476 status = 435 status = cx231xx_write_i2c_data(dev,
477 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 436 Colibri_DEVICE_ADDRESS,
478 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 437 ADC_PWRDN_CLAMP_CH2, 2,
479 1); 438 0x00, 1);
480 status = 439 status = cx231xx_write_i2c_data(dev,
481 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 440 Colibri_DEVICE_ADDRESS,
482 ADC_PWRDN_CLAMP_CH3, 2, 0x40, 441 ADC_PWRDN_CLAMP_CH3, 2,
483 1); 442 0x40, 1);
484 } else { 443 } else {
485 cx231xx_info("Invalid AV mode input\n"); 444 cx231xx_info("Invalid AV mode input\n");
486 status = -1; 445 status = -1;
@@ -499,19 +458,15 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
499 dev->video_input = video_input; 458 dev->video_input = video_input;
500 459
501 if (video_input == CX231XX_VMUX_TELEVISION) { 460 if (video_input == CX231XX_VMUX_TELEVISION) {
502 status = 461 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
503 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
504 ADC_INPUT_CH3, 2, &input_mode, 1); 462 ADC_INPUT_CH3, 2, &input_mode, 1);
505 status = 463 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
506 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
507 ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, 464 ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode,
508 1); 465 1);
509 } else { 466 } else {
510 status = 467 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
511 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
512 ADC_INPUT_CH1, 2, &input_mode, 1); 468 ADC_INPUT_CH1, 2, &input_mode, 1);
513 status = 469 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
514 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
515 ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, 470 ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode,
516 1); 471 1);
517 } 472 }
@@ -540,9 +495,9 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
540 return status; 495 return status;
541} 496}
542 497
543/************************************************************************************* 498/******************************************************************************
544 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 499 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
545 *************************************************************************************/ 500 ******************************************++**********************************/
546int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 501int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
547{ 502{
548 int status = 0; 503 int status = 0;
@@ -552,38 +507,38 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
552 case CX231XX_VMUX_SVIDEO: 507 case CX231XX_VMUX_SVIDEO:
553 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 508 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
554 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 509 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
555 status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */ 510 /* External AV */
511 status = cx231xx_set_power_mode(dev,
512 POLARIS_AVMODE_ENXTERNAL_AV);
556 if (status < 0) { 513 if (status < 0) {
557 cx231xx_errdev 514 cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
558 ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
559 __func__, status); 515 __func__, status);
560 return status; 516 return status;
561 } 517 }
562 } 518 }
563 status = 519 status = cx231xx_set_decoder_video_input(dev,
564 cx231xx_set_decoder_video_input(dev, INPUT(input)->type, 520 INPUT(input)->type,
565 INPUT(input)->vmux); 521 INPUT(input)->vmux);
566 break; 522 break;
567 case CX231XX_VMUX_TELEVISION: 523 case CX231XX_VMUX_TELEVISION:
568 case CX231XX_VMUX_CABLE: 524 case CX231XX_VMUX_CABLE:
569 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 525 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
570 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 526 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
571 status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */ 527 /* Tuner */
528 status = cx231xx_set_power_mode(dev,
529 POLARIS_AVMODE_ANALOGT_TV);
572 if (status < 0) { 530 if (status < 0) {
573 cx231xx_errdev 531 cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
574 ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
575 __func__, status); 532 __func__, status);
576 return status; 533 return status;
577 } 534 }
578 } 535 }
579 status = 536 status = cx231xx_set_decoder_video_input(dev,
580 cx231xx_set_decoder_video_input(dev, 537 CX231XX_VMUX_COMPOSITE1,
581 CX231XX_VMUX_COMPOSITE1, 538 INPUT(input)->vmux);
582 INPUT(input)->vmux);
583 break; 539 break;
584 default: 540 default:
585 cx231xx_errdev 541 cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n",
586 ("%s: cx231xx_set_power_mode : Unknown Input %d !\n",
587 __func__, INPUT(input)->type); 542 __func__, INPUT(input)->type);
588 break; 543 break;
589 } 544 }
@@ -602,8 +557,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input)
602 if (pin_type != dev->video_input) { 557 if (pin_type != dev->video_input) {
603 status = cx231xx_colibri_adjust_ref_count(dev, pin_type); 558 status = cx231xx_colibri_adjust_ref_count(dev, pin_type);
604 if (status < 0) { 559 if (status < 0) {
605 cx231xx_errdev 560 cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n",
606 ("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n",
607 __func__, status); 561 __func__, status);
608 return status; 562 return status;
609 } 563 }
@@ -612,57 +566,190 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input)
612 /* call colibri block to set video inputs */ 566 /* call colibri block to set video inputs */
613 status = cx231xx_colibri_set_input_mux(dev, input); 567 status = cx231xx_colibri_set_input_mux(dev, input);
614 if (status < 0) { 568 if (status < 0) {
615 cx231xx_errdev 569 cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n",
616 ("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n",
617 __func__, status); 570 __func__, status);
618 return status; 571 return status;
619 } 572 }
620 573
621 switch (pin_type) { 574 switch (pin_type) {
622 case CX231XX_VMUX_COMPOSITE1: 575 case CX231XX_VMUX_COMPOSITE1:
623 { 576 status = cx231xx_read_i2c_data(dev,
624 status = 577 HAMMERHEAD_I2C_ADDRESS,
625 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 578 AFE_CTRL, 2, &value, 4);
626 AFE_CTRL, 2, &value, 4); 579 value |= (0 << 13) | (1 << 4);
580 value &= ~(1 << 5);
581
582 value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */
583 value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
584 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
585 AFE_CTRL, 2, value, 4);
586
587 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
588 OUT_CTRL1, 2, &value, 4);
589 value |= (1 << 7);
590 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
591 OUT_CTRL1, 2, value, 4);
592
593 /* Set vip 1.1 output mode */
594 status = cx231xx_read_modify_write_i2c_dword(dev,
595 HAMMERHEAD_I2C_ADDRESS,
596 OUT_CTRL1,
597 FLD_OUT_MODE,
598 OUT_MODE_VIP11);
599
600 /* Tell DIF object to go to baseband mode */
601 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
602 if (status < 0) {
603 cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
604 __func__, status);
605 return status;
606 }
607
608 /* Read the DFE_CTRL1 register */
609 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
610 DFE_CTRL1, 2, &value, 4);
611
612 /* enable the VBI_GATE_EN */
613 value |= FLD_VBI_GATE_EN;
614
615 /* Enable the auto-VGA enable */
616 value |= FLD_VGA_AUTO_EN;
617
618 /* Write it back */
619 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
620 DFE_CTRL1, 2, value, 4);
621
622 /* Disable auto config of registers */
623 status = cx231xx_read_modify_write_i2c_dword(dev,
624 HAMMERHEAD_I2C_ADDRESS,
625 MODE_CTRL, FLD_ACFG_DIS,
626 cx231xx_set_field(FLD_ACFG_DIS, 1));
627
628 /* Set CVBS input mode */
629 status = cx231xx_read_modify_write_i2c_dword(dev,
630 HAMMERHEAD_I2C_ADDRESS,
631 MODE_CTRL, FLD_INPUT_MODE,
632 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
633 break;
634 case CX231XX_VMUX_SVIDEO:
635 /* Disable the use of DIF */
636
637 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
638 AFE_CTRL, 2, &value, 4);
639
640 value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */
641 value |= 0x1000010; /* set FUNC_MODE[24:23] = 2
642 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
643 status = cx231xx_write_i2c_data(dev,
644 HAMMERHEAD_I2C_ADDRESS,
645 AFE_CTRL, 2, value, 4);
646
647 /* Tell DIF object to go to baseband mode */
648 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
649 if (status < 0) {
650 cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
651 __func__, status);
652 return status;
653 }
654
655 /* Read the DFE_CTRL1 register */
656 status = cx231xx_read_i2c_data(dev,
657 HAMMERHEAD_I2C_ADDRESS,
658 DFE_CTRL1, 2, &value, 4);
659
660 /* enable the VBI_GATE_EN */
661 value |= FLD_VBI_GATE_EN;
662
663 /* Enable the auto-VGA enable */
664 value |= FLD_VGA_AUTO_EN;
665
666 /* Write it back */
667 status = cx231xx_write_i2c_data(dev,
668 HAMMERHEAD_I2C_ADDRESS,
669 DFE_CTRL1, 2, value, 4);
670
671 /* Disable auto config of registers */
672 status = cx231xx_read_modify_write_i2c_dword(dev,
673 HAMMERHEAD_I2C_ADDRESS,
674 MODE_CTRL, FLD_ACFG_DIS,
675 cx231xx_set_field(FLD_ACFG_DIS, 1));
676
677 /* Set YC input mode */
678 status = cx231xx_read_modify_write_i2c_dword(dev,
679 HAMMERHEAD_I2C_ADDRESS,
680 MODE_CTRL,
681 FLD_INPUT_MODE,
682 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
683
684 /* Chroma to ADC2 */
685 status = cx231xx_read_i2c_data(dev,
686 HAMMERHEAD_I2C_ADDRESS,
687 AFE_CTRL, 2, &value, 4);
688 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
689
690 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
691 This sets them to use video
692 rather than audio. Only one of the two will be in use. */
693 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
694
695 status = cx231xx_write_i2c_data(dev,
696 HAMMERHEAD_I2C_ADDRESS,
697 AFE_CTRL, 2, value, 4);
698
699 status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND);
700 break;
701 case CX231XX_VMUX_TELEVISION:
702 case CX231XX_VMUX_CABLE:
703 default:
704 switch (dev->model) {
705 case CX231XX_BOARD_CNXT_RDE_250:
706 case CX231XX_BOARD_CNXT_RDU_250:
707 /* Disable the use of DIF */
708
709 status = cx231xx_read_i2c_data(dev,
710 HAMMERHEAD_I2C_ADDRESS,
711 AFE_CTRL, 2,
712 &value, 4);
627 value |= (0 << 13) | (1 << 4); 713 value |= (0 << 13) | (1 << 4);
628 value &= ~(1 << 5); 714 value &= ~(1 << 5);
629 715
630 value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ 716 value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */
631 value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 717 value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
632 status = 718 status = cx231xx_write_i2c_data(dev,
633 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 719 HAMMERHEAD_I2C_ADDRESS,
634 AFE_CTRL, 2, value, 4); 720 AFE_CTRL, 2,
721 value, 4);
635 722
636 status = 723 status = cx231xx_read_i2c_data(dev,
637 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 724 HAMMERHEAD_I2C_ADDRESS,
638 OUT_CTRL1, 2, &value, 4); 725 OUT_CTRL1, 2,
726 &value, 4);
639 value |= (1 << 7); 727 value |= (1 << 7);
640 status = 728 status = cx231xx_write_i2c_data(dev,
641 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 729 HAMMERHEAD_I2C_ADDRESS,
642 OUT_CTRL1, 2, value, 4); 730 OUT_CTRL1, 2,
731 value, 4);
643 732
644 /* Set vip 1.1 output mode */ 733 /* Set vip 1.1 output mode */
645 status = 734 status = cx231xx_read_modify_write_i2c_dword(dev,
646 cx231xx_read_modify_write_i2c_dword(dev, 735 HAMMERHEAD_I2C_ADDRESS,
647 HAMMERHEAD_I2C_ADDRESS, 736 OUT_CTRL1, FLD_OUT_MODE,
648 OUT_CTRL1, 737 OUT_MODE_VIP11);
649 FLD_OUT_MODE,
650 OUT_MODE_VIP11);
651 738
652 /* Tell DIF object to go to baseband mode */ 739 /* Tell DIF object to go to baseband mode */
653 status = 740 status = cx231xx_dif_set_standard(dev,
654 cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 741 DIF_USE_BASEBAND);
655 if (status < 0) { 742 if (status < 0) {
656 cx231xx_errdev 743 cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
657 ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", 744 __func__, status);
658 __func__, status);
659 return status; 745 return status;
660 } 746 }
661 747
662 /* Read the DFE_CTRL1 register */ 748 /* Read the DFE_CTRL1 register */
663 status = 749 status = cx231xx_read_i2c_data(dev,
664 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 750 HAMMERHEAD_I2C_ADDRESS,
665 DFE_CTRL1, 2, &value, 4); 751 DFE_CTRL1, 2,
752 &value, 4);
666 753
667 /* enable the VBI_GATE_EN */ 754 /* enable the VBI_GATE_EN */
668 value |= FLD_VBI_GATE_EN; 755 value |= FLD_VBI_GATE_EN;
@@ -671,349 +758,144 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input)
671 value |= FLD_VGA_AUTO_EN; 758 value |= FLD_VGA_AUTO_EN;
672 759
673 /* Write it back */ 760 /* Write it back */
674 status = 761 status = cx231xx_write_i2c_data(dev,
675 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 762 HAMMERHEAD_I2C_ADDRESS,
676 DFE_CTRL1, 2, value, 4); 763 DFE_CTRL1, 2,
764 value, 4);
677 765
678 /* Disable auto config of registers */ 766 /* Disable auto config of registers */
679 status = 767 status = cx231xx_read_modify_write_i2c_dword(dev,
680 cx231xx_read_modify_write_i2c_dword(dev, 768 HAMMERHEAD_I2C_ADDRESS,
681 HAMMERHEAD_I2C_ADDRESS, 769 MODE_CTRL, FLD_ACFG_DIS,
682 MODE_CTRL, 770 cx231xx_set_field(FLD_ACFG_DIS, 1));
683 FLD_ACFG_DIS,
684 cx231xx_set_field
685 (FLD_ACFG_DIS,
686 1));
687 771
688 /* Set CVBS input mode */ 772 /* Set CVBS input mode */
689 status = 773 status = cx231xx_read_modify_write_i2c_dword(dev,
690 cx231xx_read_modify_write_i2c_dword(dev, 774 HAMMERHEAD_I2C_ADDRESS,
691 HAMMERHEAD_I2C_ADDRESS, 775 MODE_CTRL, FLD_INPUT_MODE,
692 MODE_CTRL, 776 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
693 FLD_INPUT_MODE, 777 break;
694 cx231xx_set_field 778 default:
695 (FLD_INPUT_MODE, 779 /* Enable the DIF for the tuner */
696 INPUT_MODE_CVBS_0));
697 }
698 break;
699 case CX231XX_VMUX_SVIDEO:
700 {
701 /* Disable the use of DIF */
702
703 status =
704 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
705 AFE_CTRL, 2, &value, 4);
706
707 value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */
708 value |= 0x1000010; /* set FUNC_MODE[24:23] = 2
709 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
710 status =
711 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
712 AFE_CTRL, 2, value, 4);
713 780
714 /* Tell DIF object to go to baseband mode */ 781 /* Reinitialize the DIF */
715 status = 782 status = cx231xx_dif_set_standard(dev, dev->norm);
716 cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
717 if (status < 0) { 783 if (status < 0) {
718 cx231xx_errdev 784 cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
719 ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", 785 __func__, status);
720 __func__, status);
721 return status; 786 return status;
722 } 787 }
723 788
789 /* Make sure bypass is cleared */
790 status = cx231xx_read_i2c_data(dev,
791 HAMMERHEAD_I2C_ADDRESS,
792 DIF_MISC_CTRL,
793 2, &value, 4);
794
795 /* Clear the bypass bit */
796 value &= ~FLD_DIF_DIF_BYPASS;
797
798 /* Enable the use of the DIF block */
799 status = cx231xx_write_i2c_data(dev,
800 HAMMERHEAD_I2C_ADDRESS,
801 DIF_MISC_CTRL,
802 2, value, 4);
803
724 /* Read the DFE_CTRL1 register */ 804 /* Read the DFE_CTRL1 register */
725 status = 805 status = cx231xx_read_i2c_data(dev,
726 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 806 HAMMERHEAD_I2C_ADDRESS,
727 DFE_CTRL1, 2, &value, 4); 807 DFE_CTRL1, 2,
808 &value, 4);
728 809
729 /* enable the VBI_GATE_EN */ 810 /* Disable the VBI_GATE_EN */
730 value |= FLD_VBI_GATE_EN; 811 value &= ~FLD_VBI_GATE_EN;
731 812
732 /* Enable the auto-VGA enable */ 813 /* Enable the auto-VGA enable, AGC, and
733 value |= FLD_VGA_AUTO_EN; 814 set the skip count to 2 */
815 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
734 816
735 /* Write it back */ 817 /* Write it back */
736 status = 818 status = cx231xx_write_i2c_data(dev,
737 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 819 HAMMERHEAD_I2C_ADDRESS,
738 DFE_CTRL1, 2, value, 4); 820 DFE_CTRL1, 2,
821 value, 4);
739 822
740 /* Disable auto config of registers */ 823 /* Wait 15 ms */
741 status = 824 msleep(1);
742 cx231xx_read_modify_write_i2c_dword(dev,
743 HAMMERHEAD_I2C_ADDRESS,
744 MODE_CTRL,
745 FLD_ACFG_DIS,
746 cx231xx_set_field
747 (FLD_ACFG_DIS,
748 1));
749
750 /* Set YC input mode */
751 status =
752 cx231xx_read_modify_write_i2c_dword(dev,
753 HAMMERHEAD_I2C_ADDRESS,
754 MODE_CTRL,
755 FLD_INPUT_MODE,
756 cx231xx_set_field
757 (FLD_INPUT_MODE,
758 INPUT_MODE_YC_1));
759
760 /* Chroma to ADC2 */
761 status =
762 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
763 AFE_CTRL, 2, &value, 4);
764 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
765 825
766 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) This sets them to use video 826 /* Disable the auto-VGA enable AGC */
767 rather than audio. Only one of the two will be in use. */ 827 value &= ~(FLD_VGA_AUTO_EN);
768 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
769 828
770 status = 829 /* Write it back */
771 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 830 status = cx231xx_write_i2c_data(dev,
772 AFE_CTRL, 2, value, 4); 831 HAMMERHEAD_I2C_ADDRESS,
832 DFE_CTRL1, 2,
833 value, 4);
773 834
774 status = 835 /* Enable Polaris B0 AGC output */
775 cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); 836 status = cx231xx_read_i2c_data(dev,
776 } 837 HAMMERHEAD_I2C_ADDRESS,
777 break; 838 PIN_CTRL, 2,
778 case CX231XX_VMUX_TELEVISION: 839 &value, 4);
779 case CX231XX_VMUX_CABLE: 840 value |= (FLD_OEF_AGC_RF) |
780 default: 841 (FLD_OEF_AGC_IFVGA) |
781 { 842 (FLD_OEF_AGC_IF);
782 switch (dev->model) { 843 status = cx231xx_write_i2c_data(dev,
783 case CX231XX_BOARD_CNXT_RDE_250: 844 HAMMERHEAD_I2C_ADDRESS,
784 case CX231XX_BOARD_CNXT_RDU_250: 845 PIN_CTRL, 2,
785 { 846 value, 4);
786 /* Disable the use of DIF */ 847
787 848 /* Set vip 1.1 output mode */
788 status = 849 status = cx231xx_read_modify_write_i2c_dword(dev,
789 cx231xx_read_i2c_data(dev, 850 HAMMERHEAD_I2C_ADDRESS,
790 HAMMERHEAD_I2C_ADDRESS, 851 OUT_CTRL1, FLD_OUT_MODE,
791 AFE_CTRL, 2, 852 OUT_MODE_VIP11);
792 &value, 4); 853
793 value |= (0 << 13) | (1 << 4); 854 /* Disable auto config of registers */
794 value &= ~(1 << 5); 855 status = cx231xx_read_modify_write_i2c_dword(dev,
795 856 HAMMERHEAD_I2C_ADDRESS,
796 value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ 857 MODE_CTRL, FLD_ACFG_DIS,
797 value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 858 cx231xx_set_field(FLD_ACFG_DIS, 1));
798 status = 859
799 cx231xx_write_i2c_data(dev, 860 /* Set CVBS input mode */
800 HAMMERHEAD_I2C_ADDRESS, 861 status = cx231xx_read_modify_write_i2c_dword(dev,
801 AFE_CTRL, 2, 862 HAMMERHEAD_I2C_ADDRESS,
802 value, 4); 863 MODE_CTRL, FLD_INPUT_MODE,
803 864 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
804 status = 865
805 cx231xx_read_i2c_data(dev, 866 /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */
806 HAMMERHEAD_I2C_ADDRESS, 867 /* Clear clamp for channels 2 and 3 (bit 16-17) */
807 OUT_CTRL1, 2, 868 /* Clear droop comp (bit 19-20) */
808 &value, 4); 869 /* Set VGA_SEL (for audio control) (bit 7-8) */
809 value |= (1 << 7); 870 status = cx231xx_read_i2c_data(dev,
810 status = 871 HAMMERHEAD_I2C_ADDRESS,
811 cx231xx_write_i2c_data(dev, 872 AFE_CTRL, 2,
812 HAMMERHEAD_I2C_ADDRESS, 873 &value, 4);
813 OUT_CTRL1, 2, 874
814 value, 4); 875 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
815 876
816 /* Set vip 1.1 output mode */ 877 status = cx231xx_write_i2c_data(dev,
817 status = 878 HAMMERHEAD_I2C_ADDRESS,
818 cx231xx_read_modify_write_i2c_dword 879 AFE_CTRL, 2,
819 (dev, HAMMERHEAD_I2C_ADDRESS, 880 value, 4);
820 OUT_CTRL1, FLD_OUT_MODE, 881 break;
821 OUT_MODE_VIP11);
822
823 /* Tell DIF object to go to baseband mode */
824 status =
825 cx231xx_dif_set_standard(dev,
826 DIF_USE_BASEBAND);
827 if (status < 0) {
828 cx231xx_errdev
829 ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
830 __func__, status);
831 return status;
832 }
833
834 /* Read the DFE_CTRL1 register */
835 status =
836 cx231xx_read_i2c_data(dev,
837 HAMMERHEAD_I2C_ADDRESS,
838 DFE_CTRL1, 2,
839 &value, 4);
840
841 /* enable the VBI_GATE_EN */
842 value |= FLD_VBI_GATE_EN;
843
844 /* Enable the auto-VGA enable */
845 value |= FLD_VGA_AUTO_EN;
846
847 /* Write it back */
848 status =
849 cx231xx_write_i2c_data(dev,
850 HAMMERHEAD_I2C_ADDRESS,
851 DFE_CTRL1, 2,
852 value, 4);
853
854 /* Disable auto config of registers */
855 status =
856 cx231xx_read_modify_write_i2c_dword
857 (dev, HAMMERHEAD_I2C_ADDRESS,
858 MODE_CTRL, FLD_ACFG_DIS,
859 cx231xx_set_field(FLD_ACFG_DIS,
860 1));
861
862 /* Set CVBS input mode */
863 status =
864 cx231xx_read_modify_write_i2c_dword
865 (dev, HAMMERHEAD_I2C_ADDRESS,
866 MODE_CTRL, FLD_INPUT_MODE,
867 cx231xx_set_field(FLD_INPUT_MODE,
868 INPUT_MODE_CVBS_0));
869 }
870 break;
871 default:
872 {
873 /* Enable the DIF for the tuner */
874
875 /* Reinitialize the DIF */
876 status =
877 cx231xx_dif_set_standard(dev,
878 dev->norm);
879 if (status < 0) {
880 cx231xx_errdev
881 ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
882 __func__, status);
883 return status;
884 }
885
886 /* Make sure bypass is cleared */
887 status =
888 cx231xx_read_i2c_data(dev,
889 HAMMERHEAD_I2C_ADDRESS,
890 DIF_MISC_CTRL,
891 2, &value, 4);
892
893 /* Clear the bypass bit */
894 value &= ~FLD_DIF_DIF_BYPASS;
895
896 /* Enable the use of the DIF block */
897 status =
898 cx231xx_write_i2c_data(dev,
899 HAMMERHEAD_I2C_ADDRESS,
900 DIF_MISC_CTRL,
901 2, value, 4);
902
903 /* Read the DFE_CTRL1 register */
904 status =
905 cx231xx_read_i2c_data(dev,
906 HAMMERHEAD_I2C_ADDRESS,
907 DFE_CTRL1, 2,
908 &value, 4);
909
910 /* Disable the VBI_GATE_EN */
911 value &= ~FLD_VBI_GATE_EN;
912
913 /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */
914 value |=
915 FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN |
916 0x00200000;
917
918 /* Write it back */
919 status =
920 cx231xx_write_i2c_data(dev,
921 HAMMERHEAD_I2C_ADDRESS,
922 DFE_CTRL1, 2,
923 value, 4);
924
925 /* Wait 15 ms */
926 msleep(1);
927
928 /* Disable the auto-VGA enable AGC */
929 value &= ~(FLD_VGA_AUTO_EN);
930
931 /* Write it back */
932 status =
933 cx231xx_write_i2c_data(dev,
934 HAMMERHEAD_I2C_ADDRESS,
935 DFE_CTRL1, 2,
936 value, 4);
937
938 /* Enable Polaris B0 AGC output */
939 status =
940 cx231xx_read_i2c_data(dev,
941 HAMMERHEAD_I2C_ADDRESS,
942 PIN_CTRL, 2,
943 &value, 4);
944 value |=
945 (FLD_OEF_AGC_RF) |
946 (FLD_OEF_AGC_IFVGA) |
947 (FLD_OEF_AGC_IF);
948 status =
949 cx231xx_write_i2c_data(dev,
950 HAMMERHEAD_I2C_ADDRESS,
951 PIN_CTRL, 2,
952 value, 4);
953
954 /* Set vip 1.1 output mode */
955 status =
956 cx231xx_read_modify_write_i2c_dword
957 (dev, HAMMERHEAD_I2C_ADDRESS,
958 OUT_CTRL1, FLD_OUT_MODE,
959 OUT_MODE_VIP11);
960
961 /* Disable auto config of registers */
962 status =
963 cx231xx_read_modify_write_i2c_dword
964 (dev, HAMMERHEAD_I2C_ADDRESS,
965 MODE_CTRL, FLD_ACFG_DIS,
966 cx231xx_set_field(FLD_ACFG_DIS,
967 1));
968
969 /* Set CVBS input mode */
970 status =
971 cx231xx_read_modify_write_i2c_dword
972 (dev, HAMMERHEAD_I2C_ADDRESS,
973 MODE_CTRL, FLD_INPUT_MODE,
974 cx231xx_set_field(FLD_INPUT_MODE,
975 INPUT_MODE_CVBS_0));
976
977 /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */
978 /* Clear clamp for channels 2 and 3 (bit 16-17) */
979 /* Clear droop comp (bit 19-20) */
980 /* Set VGA_SEL (for audio control) (bit 7-8) */
981 status =
982 cx231xx_read_i2c_data(dev,
983 HAMMERHEAD_I2C_ADDRESS,
984 AFE_CTRL, 2,
985 &value, 4);
986
987 value |=
988 FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
989
990 status =
991 cx231xx_write_i2c_data(dev,
992 HAMMERHEAD_I2C_ADDRESS,
993 AFE_CTRL, 2,
994 value, 4);
995 }
996 break;
997 882
998 }
999 } 883 }
1000 break; 884 break;
1001 } 885 }
1002 886
1003 /* Set raw VBI mode */ 887 /* Set raw VBI mode */
1004 status = 888 status = cx231xx_read_modify_write_i2c_dword(dev,
1005 cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, 889 HAMMERHEAD_I2C_ADDRESS,
1006 OUT_CTRL1, FLD_VBIHACTRAW_EN, 890 OUT_CTRL1, FLD_VBIHACTRAW_EN,
1007 cx231xx_set_field 891 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
1008 (FLD_VBIHACTRAW_EN, 1));
1009 892
1010 status = 893 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1011 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, 894 OUT_CTRL1, 2,
1012 &value, 4); 895 &value, 4);
1013 if (value & 0x02) { 896 if (value & 0x02) {
1014 value |= (1 << 19); 897 value |= (1 << 19);
1015 status = 898 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1016 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1017 OUT_CTRL1, 2, value, 4); 899 OUT_CTRL1, 2, value, 4);
1018 } 900 }
1019 901
@@ -1032,70 +914,62 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
1032 (unsigned int)dev->norm); 914 (unsigned int)dev->norm);
1033 915
1034 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 916 /* Change the DFE_CTRL3 bp_percent to fix flagging */
1035 status = 917 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1036 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, 918 DFE_CTRL3, 2,
1037 0xCD3F0280, 4); 919 0xCD3F0280, 4);
1038 920
1039 if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) { 921 if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) {
1040 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 922 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
1041 923
1042 /* Move the close caption lines out of active video, adjust the active video start point */ 924 /* Move the close caption lines out of active video,
1043 status = 925 adjust the active video start point */
1044 cx231xx_read_modify_write_i2c_dword(dev, 926 status = cx231xx_read_modify_write_i2c_dword(dev,
1045 HAMMERHEAD_I2C_ADDRESS, 927 HAMMERHEAD_I2C_ADDRESS,
1046 VERT_TIM_CTRL, 928 VERT_TIM_CTRL,
1047 FLD_VBLANK_CNT, 0x18); 929 FLD_VBLANK_CNT, 0x18);
1048 status = 930 status = cx231xx_read_modify_write_i2c_dword(dev,
1049 cx231xx_read_modify_write_i2c_dword(dev,
1050 HAMMERHEAD_I2C_ADDRESS, 931 HAMMERHEAD_I2C_ADDRESS,
1051 VERT_TIM_CTRL, 932 VERT_TIM_CTRL,
1052 FLD_VACTIVE_CNT, 933 FLD_VACTIVE_CNT,
1053 0x1E6000); 934 0x1E6000);
1054 status = 935 status = cx231xx_read_modify_write_i2c_dword(dev,
1055 cx231xx_read_modify_write_i2c_dword(dev,
1056 HAMMERHEAD_I2C_ADDRESS, 936 HAMMERHEAD_I2C_ADDRESS,
1057 VERT_TIM_CTRL, 937 VERT_TIM_CTRL,
1058 FLD_V656BLANK_CNT, 938 FLD_V656BLANK_CNT,
1059 0x1E000000); 939 0x1E000000);
1060 940
1061 status = 941 status = cx231xx_read_modify_write_i2c_dword(dev,
1062 cx231xx_read_modify_write_i2c_dword(dev,
1063 HAMMERHEAD_I2C_ADDRESS, 942 HAMMERHEAD_I2C_ADDRESS,
1064 HORIZ_TIM_CTRL, 943 HORIZ_TIM_CTRL,
1065 FLD_HBLANK_CNT, 944 FLD_HBLANK_CNT,
1066 cx231xx_set_field 945 cx231xx_set_field
1067 (FLD_HBLANK_CNT, 0x79)); 946 (FLD_HBLANK_CNT, 0x79));
1068 } else if (dev-> 947 } else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G |
1069 norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D | 948 V4L2_STD_PAL_D | V4L2_STD_PAL_I |
1070 V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 949 V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1071 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 950 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1072 status = 951 status = cx231xx_read_modify_write_i2c_dword(dev,
1073 cx231xx_read_modify_write_i2c_dword(dev,
1074 HAMMERHEAD_I2C_ADDRESS, 952 HAMMERHEAD_I2C_ADDRESS,
1075 VERT_TIM_CTRL, 953 VERT_TIM_CTRL,
1076 FLD_VBLANK_CNT, 0x24); 954 FLD_VBLANK_CNT, 0x24);
1077 /* Adjust the active video horizontal start point */ 955 /* Adjust the active video horizontal start point */
1078 status = 956 status = cx231xx_read_modify_write_i2c_dword(dev,
1079 cx231xx_read_modify_write_i2c_dword(dev,
1080 HAMMERHEAD_I2C_ADDRESS, 957 HAMMERHEAD_I2C_ADDRESS,
1081 HORIZ_TIM_CTRL, 958 HORIZ_TIM_CTRL,
1082 FLD_HBLANK_CNT, 959 FLD_HBLANK_CNT,
1083 cx231xx_set_field 960 cx231xx_set_field
1084 (FLD_HBLANK_CNT, 0x85)); 961 (FLD_HBLANK_CNT, 0x85));
1085 } else if (dev-> 962 } else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D |
1086 norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | 963 V4L2_STD_SECAM_G | V4L2_STD_SECAM_K |
1087 V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | 964 V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L |
1088 V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | 965 V4L2_STD_SECAM_LC)) {
1089 V4L2_STD_SECAM_LC)) {
1090 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 966 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1091 status = 967 status = cx231xx_read_modify_write_i2c_dword(dev,
1092 cx231xx_read_modify_write_i2c_dword(dev,
1093 HAMMERHEAD_I2C_ADDRESS, 968 HAMMERHEAD_I2C_ADDRESS,
1094 VERT_TIM_CTRL, 969 VERT_TIM_CTRL,
1095 FLD_VBLANK_CNT, 0x24); 970 FLD_VBLANK_CNT, 0x24);
1096 /* Adjust the active video horizontal start point */ 971 /* Adjust the active video horizontal start point */
1097 status = 972 status = cx231xx_read_modify_write_i2c_dword(dev,
1098 cx231xx_read_modify_write_i2c_dword(dev,
1099 HAMMERHEAD_I2C_ADDRESS, 973 HAMMERHEAD_I2C_ADDRESS,
1100 HORIZ_TIM_CTRL, 974 HORIZ_TIM_CTRL,
1101 FLD_HBLANK_CNT, 975 FLD_HBLANK_CNT,
@@ -1137,69 +1011,57 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1137 u32 value = 0; 1011 u32 value = 0;
1138 1012
1139 /* Put it in soft reset */ 1013 /* Put it in soft reset */
1140 status = 1014 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1141 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, 1015 GENERAL_CTL, 2, &gen_ctrl, 1);
1142 &gen_ctrl, 1);
1143 gen_ctrl |= 1; 1016 gen_ctrl |= 1;
1144 status = 1017 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1145 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, 1018 GENERAL_CTL, 2, gen_ctrl, 1);
1146 gen_ctrl, 1);
1147 1019
1148 switch (audio_input) { 1020 switch (audio_input) {
1149 case AUDIO_INPUT_LINE: 1021 case AUDIO_INPUT_LINE:
1150
1151 /* setup AUD_IO control from Merlin paralle output */ 1022 /* setup AUD_IO control from Merlin paralle output */
1152 value = 1023 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1153 cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); 1024 AUD_CHAN_SRC_PARALLEL);
1154 status = 1025 status = cx231xx_write_i2c_data(dev,
1155 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1026 HAMMERHEAD_I2C_ADDRESS,
1156 AUD_IO_CTRL, 2, value, 4); 1027 AUD_IO_CTRL, 2, value, 4);
1157 1028
1158 /* setup input to Merlin, SRC2 connect to AC97 1029 /* setup input to Merlin, SRC2 connect to AC97
1159 bypass upsample-by-2, slave mode, sony mode, left justify 1030 bypass upsample-by-2, slave mode, sony mode, left justify
1160 adr 091c, dat 01000000 */ 1031 adr 091c, dat 01000000 */
1161 status = 1032 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1162 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 1033 AC97_CTL,
1163 2, &dwval, 4); 1034 2, &dwval, 4);
1164 1035
1165 status = 1036 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1166 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1167 AC97_CTL, 2, 1037 AC97_CTL, 2,
1168 (dwval | FLD_AC97_UP2X_BYPASS), 4); 1038 (dwval | FLD_AC97_UP2X_BYPASS), 4);
1169 1039
1170 /* select the parallel1 and SRC3 */ 1040 /* select the parallel1 and SRC3 */
1171 status = 1041 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1172 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1042 BAND_OUT_SEL, 2,
1173 BAND_OUT_SEL, 2, 1043 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1174 cx231xx_set_field(FLD_SRC3_IN_SEL, 1044 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1175 0x0) | 1045 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0),
1176 cx231xx_set_field(FLD_SRC3_CLK_SEL, 1046 4);
1177 0x0) |
1178 cx231xx_set_field
1179 (FLD_PARALLEL1_SRC_SEL, 0x0), 4);
1180 1047
1181 /* unmute all, AC97 in, independence mode 1048 /* unmute all, AC97 in, independence mode
1182 adr 08d0, data 0x00063073 */ 1049 adr 08d0, data 0x00063073 */
1183 status = 1050 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1184 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1185 PATH1_CTL1, 2, 0x00063073, 4); 1051 PATH1_CTL1, 2, 0x00063073, 4);
1186 1052
1187 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1053 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1188 status = 1054 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1189 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1190 PATH1_VOL_CTL, 2, &dwval, 4); 1055 PATH1_VOL_CTL, 2, &dwval, 4);
1191 status = 1056 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1192 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1193 PATH1_VOL_CTL, 2, 1057 PATH1_VOL_CTL, 2,
1194 (dwval | FLD_PATH1_AVC_THRESHOLD), 1058 (dwval | FLD_PATH1_AVC_THRESHOLD),
1195 4); 1059 4);
1196 1060
1197 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1061 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1198 status = 1062 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1199 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1200 PATH1_SC_CTL, 2, &dwval, 4); 1063 PATH1_SC_CTL, 2, &dwval, 4);
1201 status = 1064 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1202 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1203 PATH1_SC_CTL, 2, 1065 PATH1_SC_CTL, 2,
1204 (dwval | FLD_PATH1_SC_THRESHOLD), 4); 1066 (dwval | FLD_PATH1_SC_THRESHOLD), 4);
1205 break; 1067 break;
@@ -1208,73 +1070,46 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1208 default: 1070 default:
1209 1071
1210 /* Setup SRC sources and clocks */ 1072 /* Setup SRC sources and clocks */
1211 status = 1073 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1212 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1074 BAND_OUT_SEL, 2,
1213 BAND_OUT_SEL, 2, 1075 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1214 cx231xx_set_field(FLD_SRC6_IN_SEL, 1076 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1215 0x00) | 1077 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1216 cx231xx_set_field(FLD_SRC6_CLK_SEL, 1078 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1217 0x01) | 1079 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1218 cx231xx_set_field(FLD_SRC5_IN_SEL, 1080 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1219 0x00) | 1081 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1220 cx231xx_set_field(FLD_SRC5_CLK_SEL, 1082 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1221 0x02) | 1083 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1222 cx231xx_set_field(FLD_SRC4_IN_SEL, 1084 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1223 0x02) | 1085 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1224 cx231xx_set_field(FLD_SRC4_CLK_SEL, 1086 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1225 0x03) | 1087 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01), 4);
1226 cx231xx_set_field(FLD_SRC3_IN_SEL,
1227 0x00) |
1228 cx231xx_set_field(FLD_SRC3_CLK_SEL,
1229 0x00) |
1230 cx231xx_set_field
1231 (FLD_BASEBAND_BYPASS_CTL,
1232 0x00) |
1233 cx231xx_set_field(FLD_AC97_SRC_SEL,
1234 0x03) |
1235 cx231xx_set_field(FLD_I2S_SRC_SEL,
1236 0x00) |
1237 cx231xx_set_field
1238 (FLD_PARALLEL2_SRC_SEL,
1239 0x02) |
1240 cx231xx_set_field
1241 (FLD_PARALLEL1_SRC_SEL, 0x01), 4);
1242 1088
1243 /* Setup the AUD_IO control */ 1089 /* Setup the AUD_IO control */
1244 status = 1090 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1245 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1091 AUD_IO_CTRL, 2,
1246 AUD_IO_CTRL, 2, 1092 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1247 cx231xx_set_field(FLD_I2S_PORT_DIR, 1093 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1248 0x00) | 1094 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1249 cx231xx_set_field(FLD_I2S_OUT_SRC, 1095 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1250 0x00) | 1096 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03), 4);
1251 cx231xx_set_field(FLD_AUD_CHAN3_SRC,
1252 0x00) |
1253 cx231xx_set_field(FLD_AUD_CHAN2_SRC,
1254 0x00) |
1255 cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1256 0x03), 4);
1257 1097
1258 status = 1098 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1259 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1260 PATH1_CTL1, 2, 0x1F063870, 4); 1099 PATH1_CTL1, 2, 0x1F063870, 4);
1261 1100
1262 /* setAudioStandard(_audio_standard); */ 1101 /* setAudioStandard(_audio_standard); */
1263 1102
1264 status = 1103 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1265 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1266 PATH1_CTL1, 2, 0x00063870, 4); 1104 PATH1_CTL1, 2, 0x00063870, 4);
1267 switch (dev->model) { 1105 switch (dev->model) {
1268 case CX231XX_BOARD_CNXT_RDE_250: 1106 case CX231XX_BOARD_CNXT_RDE_250:
1269 case CX231XX_BOARD_CNXT_RDU_250: 1107 case CX231XX_BOARD_CNXT_RDU_250:
1270 status = 1108 status = cx231xx_read_modify_write_i2c_dword(dev,
1271 cx231xx_read_modify_write_i2c_dword(dev, 1109 HAMMERHEAD_I2C_ADDRESS,
1272 HAMMERHEAD_I2C_ADDRESS, 1110 CHIP_CTRL,
1273 CHIP_CTRL, 1111 FLD_SIF_EN,
1274 FLD_SIF_EN, 1112 cx231xx_set_field(FLD_SIF_EN, 1));
1275 cx231xx_set_field
1276 (FLD_SIF_EN,
1277 1));
1278 break; 1113 break;
1279 default: 1114 default:
1280 break; 1115 break;
@@ -1289,20 +1124,17 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1289 break; 1124 break;
1290 1125
1291 case AUDIO_INPUT_MUTE: 1126 case AUDIO_INPUT_MUTE:
1292 status = 1127 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1293 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1294 PATH1_CTL1, 2, 0x1F011012, 4); 1128 PATH1_CTL1, 2, 0x1F011012, 4);
1295 break; 1129 break;
1296 } 1130 }
1297 1131
1298 /* Take it out of soft reset */ 1132 /* Take it out of soft reset */
1299 status = 1133 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1300 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, 1134 GENERAL_CTL, 2, &gen_ctrl, 1);
1301 &gen_ctrl, 1);
1302 gen_ctrl &= ~1; 1135 gen_ctrl &= ~1;
1303 status = 1136 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1304 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, 1137 GENERAL_CTL, 2, gen_ctrl, 1);
1305 gen_ctrl, 1);
1306 1138
1307 return status; 1139 return status;
1308} 1140}
@@ -1320,33 +1152,29 @@ int cx231xx_resolution_set(struct cx231xx *dev)
1320 get_scale(dev, width, height, &hscale, &vscale); 1152 get_scale(dev, width, height, &hscale, &vscale);
1321 1153
1322 /* set horzontal scale */ 1154 /* set horzontal scale */
1323 status = 1155 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1324 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, 1156 HSCALE_CTRL, 2, hscale, 4);
1325 hscale, 4);
1326 1157
1327 /* set vertical scale */ 1158 /* set vertical scale */
1328 status = 1159 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1329 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, 1160 VSCALE_CTRL, 2, vscale, 4);
1330 vscale, 4);
1331 1161
1332 return status; 1162 return status;
1333} 1163}
1334 1164
1335/************************************************************************************* 1165/******************************************************************************
1336 * C H I P Specific C O N T R O L functions * 1166 * C H I P Specific C O N T R O L functions *
1337 *************************************************************************************/ 1167 ******************************************************************************/
1338int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1168int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1339{ 1169{
1340 u32 value; 1170 u32 value;
1341 int status = 0; 1171 int status = 0;
1342 1172
1343 status = 1173 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL,
1344 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, 1174 2, &value, 4);
1345 &value, 4);
1346 value |= (~dev->board.ctl_pin_status_mask); 1175 value |= (~dev->board.ctl_pin_status_mask);
1347 status = 1176 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL,
1348 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, 1177 2, value, 4);
1349 value, 4);
1350 1178
1351 return status; 1179 return status;
1352} 1180}
@@ -1357,14 +1185,12 @@ int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1357 int status = 0; 1185 int status = 0;
1358 1186
1359 /* first set the direction to output */ 1187 /* first set the direction to output */
1360 status = 1188 status = cx231xx_set_gpio_direction(dev,
1361 cx231xx_set_gpio_direction(dev, 1189 dev->board.
1362 dev->board. 1190 agc_analog_digital_select_gpio, 1);
1363 agc_analog_digital_select_gpio, 1);
1364 1191
1365 /* 0 - demod ; 1 - Analog mode */ 1192 /* 0 - demod ; 1 - Analog mode */
1366 status = 1193 status = cx231xx_set_gpio_value(dev,
1367 cx231xx_set_gpio_value(dev,
1368 dev->board.agc_analog_digital_select_gpio, 1194 dev->board.agc_analog_digital_select_gpio,
1369 analog_or_digital); 1195 analog_or_digital);
1370 1196
@@ -1378,23 +1204,21 @@ int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1378 1204
1379 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex); 1205 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1380 1206
1381 status = 1207 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1382 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); 1208 PWR_CTL_EN, value, 4);
1383 if (status < 0) 1209 if (status < 0)
1384 return status; 1210 return status;
1385 1211
1386 if (I2CIndex == I2C_1) { 1212 if (I2CIndex == I2C_1) {
1387 if (value[0] & I2C_DEMOD_EN) { 1213 if (value[0] & I2C_DEMOD_EN) {
1388 value[0] &= ~I2C_DEMOD_EN; 1214 value[0] &= ~I2C_DEMOD_EN;
1389 status = 1215 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1390 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1391 PWR_CTL_EN, value, 4); 1216 PWR_CTL_EN, value, 4);
1392 } 1217 }
1393 } else { 1218 } else {
1394 if (!(value[0] & I2C_DEMOD_EN)) { 1219 if (!(value[0] & I2C_DEMOD_EN)) {
1395 value[0] |= I2C_DEMOD_EN; 1220 value[0] |= I2C_DEMOD_EN;
1396 status = 1221 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1397 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1398 PWR_CTL_EN, value, 4); 1222 PWR_CTL_EN, value, 4);
1399 } 1223 }
1400 } 1224 }
@@ -1403,9 +1227,9 @@ int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1403 1227
1404} 1228}
1405 1229
1406/************************************************************************************* 1230/******************************************************************************
1407 * D I F - B L O C K C O N T R O L functions * 1231 * D I F - B L O C K C O N T R O L functions *
1408 *************************************************************************************/ 1232 ******************************************************************************/
1409int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1233int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1410 u32 function_mode, u32 standard) 1234 u32 function_mode, u32 standard)
1411{ 1235{
@@ -1413,10 +1237,14 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1413 1237
1414 if (mode == V4L2_TUNER_RADIO) { 1238 if (mode == V4L2_TUNER_RADIO) {
1415 /* C2HH */ 1239 /* C2HH */
1416 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ 1240 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1417 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ 1241 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */
1418 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ 1242 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1419 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ 1243 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */
1244 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1245 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */
1246 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1247 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */
1420 } else { 1248 } else {
1421 switch (standard) { 1249 switch (standard) {
1422 case V4L2_STD_NTSC_M: /* 75 IRE Setup */ 1250 case V4L2_STD_NTSC_M: /* 75 IRE Setup */
@@ -1424,20 +1252,40 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1424 case V4L2_STD_PAL_M: 1252 case V4L2_STD_PAL_M:
1425 case V4L2_STD_PAL_N: 1253 case V4L2_STD_PAL_N:
1426 case V4L2_STD_PAL_Nc: 1254 case V4L2_STD_PAL_Nc:
1427 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ 1255 status = cx231xx_reg_mask_write(dev,
1428 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ 1256 HAMMERHEAD_I2C_ADDRESS, 32,
1429 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ 1257 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */
1430 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ 1258 status = cx231xx_reg_mask_write(dev,
1431 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1259 HAMMERHEAD_I2C_ADDRESS, 32,
1260 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1261 function_mode); /* FUNC_MODE = DIF */
1262 status = cx231xx_reg_mask_write(dev,
1263 HAMMERHEAD_I2C_ADDRESS, 32,
1264 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */
1265 status = cx231xx_reg_mask_write(dev,
1266 HAMMERHEAD_I2C_ADDRESS, 32,
1267 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */
1268 status = cx231xx_reg_mask_write(dev,
1269 HAMMERHEAD_I2C_ADDRESS, 32,
1270 AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */
1432 break; 1271 break;
1433 1272
1434 case V4L2_STD_PAL_B: 1273 case V4L2_STD_PAL_B:
1435 case V4L2_STD_PAL_G: 1274 case V4L2_STD_PAL_G:
1436 /* C2HH setup */ 1275 /* C2HH setup */
1437 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ 1276 status = cx231xx_reg_mask_write(dev,
1438 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ 1277 HAMMERHEAD_I2C_ADDRESS, 32,
1439 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ 1278 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */
1440 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ 1279 status = cx231xx_reg_mask_write(dev,
1280 HAMMERHEAD_I2C_ADDRESS, 32,
1281 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1282 function_mode); /* FUNC_MODE = DIF */
1283 status = cx231xx_reg_mask_write(dev,
1284 HAMMERHEAD_I2C_ADDRESS, 32,
1285 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */
1286 status = cx231xx_reg_mask_write(dev,
1287 HAMMERHEAD_I2C_ADDRESS, 32,
1288 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */
1441 break; 1289 break;
1442 1290
1443 case V4L2_STD_PAL_D: 1291 case V4L2_STD_PAL_D:
@@ -1450,10 +1298,19 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1450 case V4L2_STD_SECAM_K: 1298 case V4L2_STD_SECAM_K:
1451 case V4L2_STD_SECAM_K1: 1299 case V4L2_STD_SECAM_K1:
1452 /* C2HH setup */ 1300 /* C2HH setup */
1453 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ 1301 status = cx231xx_reg_mask_write(dev,
1454 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ 1302 HAMMERHEAD_I2C_ADDRESS, 32,
1455 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ 1303 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */
1456 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ 1304 status = cx231xx_reg_mask_write(dev,
1305 HAMMERHEAD_I2C_ADDRESS, 32,
1306 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1307 function_mode); /* FUNC_MODE = DIF */
1308 status = cx231xx_reg_mask_write(dev,
1309 HAMMERHEAD_I2C_ADDRESS, 32,
1310 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */
1311 status = cx231xx_reg_mask_write(dev,
1312 HAMMERHEAD_I2C_ADDRESS, 32,
1313 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */
1457 break; 1314 break;
1458 1315
1459 case DIF_USE_BASEBAND: 1316 case DIF_USE_BASEBAND:
@@ -1489,20 +1346,18 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1489 func_mode = 0x01; 1346 func_mode = 0x01;
1490 } 1347 }
1491 1348
1492 status = 1349 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1493 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1494 func_mode, standard); 1350 func_mode, standard);
1495 1351
1496 if (standard == DIF_USE_BASEBAND) { /* base band */ 1352 if (standard == DIF_USE_BASEBAND) { /* base band */
1497 1353 /* There is a different SRC_PHASE_INC value
1498 /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ 1354 for baseband vs. DIF */
1499 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1355 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1500 DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 1356 DIF_SRC_PHASE_INC, 2, 0xDF7DF83,
1501 4); 1357 4);
1502 status = 1358 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1503 cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1359 DIF_MISC_CTRL, 2,
1504 DIF_MISC_CTRL, 2, 1360 &dif_misc_ctrl_value, 4);
1505 &dif_misc_ctrl_value, 4);
1506 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1361 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1507 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1362 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1508 DIF_MISC_CTRL, 2, 1363 DIF_MISC_CTRL, 2,
@@ -1510,127 +1365,92 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1510 1365
1511 } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1366 } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1512 1367
1513 status = 1368 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1514 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1515 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1369 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1516 status = 1370 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1517 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1518 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1371 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1519 status = 1372 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1520 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1521 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1373 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1522 status = 1374 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1523 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1524 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1375 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1525 status = 1376 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1526 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1527 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1377 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1528 status = 1378 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1529 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1530 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1379 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1531 status = 1380 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1532 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1533 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1381 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1534 status = 1382 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1535 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1536 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1383 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1537 status = 1384 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1538 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1539 DIF_AGC_IF_INT_CURRENT, 0, 31, 1385 DIF_AGC_IF_INT_CURRENT, 0, 31,
1540 0x26001700); 1386 0x26001700);
1541 status = 1387 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1542 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1543 DIF_AGC_RF_CURRENT, 0, 31, 1388 DIF_AGC_RF_CURRENT, 0, 31,
1544 0x00002660); 1389 0x00002660);
1545 status = 1390 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1546 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1547 DIF_VIDEO_AGC_CTRL, 0, 31, 1391 DIF_VIDEO_AGC_CTRL, 0, 31,
1548 0x72500800); 1392 0x72500800);
1549 status = 1393 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1550 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1551 DIF_VID_AUD_OVERRIDE, 0, 31, 1394 DIF_VID_AUD_OVERRIDE, 0, 31,
1552 0x27000100); 1395 0x27000100);
1553 status = 1396 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1554 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1555 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 1397 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1556 status = 1398 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1557 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1558 DIF_COMP_FLT_CTRL, 0, 31, 1399 DIF_COMP_FLT_CTRL, 0, 31,
1559 0x00A653A8); 1400 0x00A653A8);
1560 status = 1401 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1561 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1562 DIF_SRC_PHASE_INC, 0, 31, 1402 DIF_SRC_PHASE_INC, 0, 31,
1563 0x1befbf06); 1403 0x1befbf06);
1564 status = 1404 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1565 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1566 DIF_SRC_GAIN_CONTROL, 0, 31, 1405 DIF_SRC_GAIN_CONTROL, 0, 31,
1567 0x000035e8); 1406 0x000035e8);
1568 status = 1407 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1569 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1570 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1408 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1571 /* Save the Spec Inversion value */ 1409 /* Save the Spec Inversion value */
1572 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1410 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1573 dif_misc_ctrl_value |= 0x3a013F11; 1411 dif_misc_ctrl_value |= 0x3a013F11;
1574 1412
1575 } else if (standard & V4L2_STD_PAL_D) { 1413 } else if (standard & V4L2_STD_PAL_D) {
1576 1414 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1577 status =
1578 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1579 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1415 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1580 status = 1416 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1581 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1582 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1417 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1583 status = 1418 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1584 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1585 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1419 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1586 status = 1420 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1587 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1588 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1421 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1589 status = 1422 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1590 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1591 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1423 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1592 status = 1424 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1593 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1594 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1425 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1595 status = 1426 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1596 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1597 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1427 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1598 status = 1428 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1599 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1600 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1429 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1601 status = 1430 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1602 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1603 DIF_AGC_IF_INT_CURRENT, 0, 31, 1431 DIF_AGC_IF_INT_CURRENT, 0, 31,
1604 0x26001700); 1432 0x26001700);
1605 status = 1433 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1606 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1607 DIF_AGC_RF_CURRENT, 0, 31, 1434 DIF_AGC_RF_CURRENT, 0, 31,
1608 0x00002660); 1435 0x00002660);
1609 status = 1436 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1610 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1611 DIF_VIDEO_AGC_CTRL, 0, 31, 1437 DIF_VIDEO_AGC_CTRL, 0, 31,
1612 0x72500800); 1438 0x72500800);
1613 status = 1439 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1614 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1615 DIF_VID_AUD_OVERRIDE, 0, 31, 1440 DIF_VID_AUD_OVERRIDE, 0, 31,
1616 0x27000100); 1441 0x27000100);
1617 status = 1442 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1618 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1619 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1443 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1620 status = 1444 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1621 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1622 DIF_COMP_FLT_CTRL, 0, 31, 1445 DIF_COMP_FLT_CTRL, 0, 31,
1623 0x00000000); 1446 0x00000000);
1624 status = 1447 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1625 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1626 DIF_SRC_PHASE_INC, 0, 31, 1448 DIF_SRC_PHASE_INC, 0, 31,
1627 0x1befbf06); 1449 0x1befbf06);
1628 status = 1450 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1629 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1630 DIF_SRC_GAIN_CONTROL, 0, 31, 1451 DIF_SRC_GAIN_CONTROL, 0, 31,
1631 0x000035e8); 1452 0x000035e8);
1632 status = 1453 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1633 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1634 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1454 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1635 /* Save the Spec Inversion value */ 1455 /* Save the Spec Inversion value */
1636 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1456 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
@@ -1638,116 +1458,86 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1638 1458
1639 } else if (standard & V4L2_STD_PAL_I) { 1459 } else if (standard & V4L2_STD_PAL_I) {
1640 1460
1641 status = 1461 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1642 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1643 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1462 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1644 status = 1463 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1645 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1646 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1464 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1647 status = 1465 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1648 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1649 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1466 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1650 status = 1467 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1651 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1652 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1468 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1653 status = 1469 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1654 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1655 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1470 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1656 status = 1471 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1657 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1658 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1472 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1659 status = 1473 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1660 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1661 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1474 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1662 status = 1475 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1663 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1664 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1476 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1665 status = 1477 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1666 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1667 DIF_AGC_IF_INT_CURRENT, 0, 31, 1478 DIF_AGC_IF_INT_CURRENT, 0, 31,
1668 0x26001700); 1479 0x26001700);
1669 status = 1480 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1670 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1671 DIF_AGC_RF_CURRENT, 0, 31, 1481 DIF_AGC_RF_CURRENT, 0, 31,
1672 0x00002660); 1482 0x00002660);
1673 status = 1483 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1674 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1675 DIF_VIDEO_AGC_CTRL, 0, 31, 1484 DIF_VIDEO_AGC_CTRL, 0, 31,
1676 0x72500800); 1485 0x72500800);
1677 status = 1486 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1678 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1679 DIF_VID_AUD_OVERRIDE, 0, 31, 1487 DIF_VID_AUD_OVERRIDE, 0, 31,
1680 0x27000100); 1488 0x27000100);
1681 status = 1489 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1682 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1683 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1490 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1684 status = 1491 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1685 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1686 DIF_COMP_FLT_CTRL, 0, 31, 1492 DIF_COMP_FLT_CTRL, 0, 31,
1687 0x00000000); 1493 0x00000000);
1688 status = 1494 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1689 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1690 DIF_SRC_PHASE_INC, 0, 31, 1495 DIF_SRC_PHASE_INC, 0, 31,
1691 0x1befbf06); 1496 0x1befbf06);
1692 status = 1497 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1693 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1694 DIF_SRC_GAIN_CONTROL, 0, 31, 1498 DIF_SRC_GAIN_CONTROL, 0, 31,
1695 0x000035e8); 1499 0x000035e8);
1696 status = 1500 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1697 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1698 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1501 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1699 /* Save the Spec Inversion value */ 1502 /* Save the Spec Inversion value */
1700 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1503 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1701 dif_misc_ctrl_value |= 0x3a033F11; 1504 dif_misc_ctrl_value |= 0x3a033F11;
1702 1505
1703 } else if (standard & V4L2_STD_PAL_M) { 1506 } else if (standard & V4L2_STD_PAL_M) {
1704
1705 /* improved Low Frequency Phase Noise */ 1507 /* improved Low Frequency Phase Noise */
1706 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1508 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1707 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); 1509 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1708 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1510 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1709 DIF_PLL_CTRL1, 2, 0xbd038c85, 1511 DIF_PLL_CTRL1, 2, 0xbd038c85,
1710 4); 1512 4);
1711 status = 1513 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1712 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1713 DIF_PLL_CTRL2, 2, 0x1db4640a, 4); 1514 DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1714 status = 1515 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1715 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1716 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1516 DIF_PLL_CTRL3, 2, 0x00008800, 4);
1717 status = 1517 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1718 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1719 DIF_AGC_IF_REF, 2, 0x444C1380, 4); 1518 DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1720 status = 1519 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1721 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1722 DIF_AGC_IF_INT_CURRENT, 2, 1520 DIF_AGC_IF_INT_CURRENT, 2,
1723 0x26001700, 4); 1521 0x26001700, 4);
1724 status = 1522 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1725 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1726 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1523 DIF_AGC_RF_CURRENT, 2, 0x00002660,
1727 4); 1524 4);
1728 status = 1525 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1729 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1730 DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 1526 DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1731 4); 1527 4);
1732 status = 1528 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1733 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1734 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1529 DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1735 4); 1530 4);
1736 status = 1531 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1737 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1738 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); 1532 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1739 status = 1533 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1740 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1741 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); 1534 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1742 status = 1535 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1743 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1744 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); 1536 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1745 status = 1537 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1746 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1747 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 1538 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1748 4); 1539 4);
1749 status = 1540 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1750 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1751 DIF_SOFT_RST_CTRL_REVB, 2, 1541 DIF_SOFT_RST_CTRL_REVB, 2,
1752 0x00000000, 4); 1542 0x00000000, 4);
1753 1543
@@ -1758,52 +1548,38 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1758 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1548 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1759 1549
1760 /* improved Low Frequency Phase Noise */ 1550 /* improved Low Frequency Phase Noise */
1761 status = 1551 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1762 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1763 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); 1552 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1764 status = 1553 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1765 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1766 DIF_PLL_CTRL1, 2, 0xbd038c85, 4); 1554 DIF_PLL_CTRL1, 2, 0xbd038c85, 4);
1767 status = 1555 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1768 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1769 DIF_PLL_CTRL2, 2, 0x1db4640a, 4); 1556 DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1770 status = 1557 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1771 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1772 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1558 DIF_PLL_CTRL3, 2, 0x00008800, 4);
1773 status = 1559 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1774 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1775 DIF_AGC_IF_REF, 2, 0x444C1380, 4); 1560 DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1776 status = 1561 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1777 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1778 DIF_AGC_IF_INT_CURRENT, 2, 1562 DIF_AGC_IF_INT_CURRENT, 2,
1779 0x26001700, 4); 1563 0x26001700, 4);
1780 status = 1564 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1781 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1782 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1565 DIF_AGC_RF_CURRENT, 2, 0x00002660,
1783 4); 1566 4);
1784 status = 1567 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1785 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1786 DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 1568 DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1787 4); 1569 4);
1788 status = 1570 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1789 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1790 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1571 DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1791 4); 1572 4);
1792 status = 1573 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1793 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1794 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); 1574 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1795 status = 1575 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1796 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1797 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); 1576 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1798 status = 1577 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1799 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1800 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); 1578 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1801 status = 1579 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1802 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1803 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 1580 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1804 4); 1581 4);
1805 status = 1582 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1806 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1807 DIF_SOFT_RST_CTRL_REVB, 2, 1583 DIF_SOFT_RST_CTRL_REVB, 2,
1808 0x00000000, 4); 1584 0x00000000, 4);
1809 1585
@@ -1815,62 +1591,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1815 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1591 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1816 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1592 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1817 1593
1818 status = 1594 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1819 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1820 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1595 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1821 status = 1596 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1822 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1823 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1597 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1824 status = 1598 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1825 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1826 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1599 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1827 status = 1600 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1828 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1829 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1601 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1830 status = 1602 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1831 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1832 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1603 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1833 status = 1604 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1834 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1835 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1605 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1836 status = 1606 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1837 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1838 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1607 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1839 status = 1608 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1840 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1841 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1609 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1842 status = 1610 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1843 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1844 DIF_AGC_IF_INT_CURRENT, 0, 31, 1611 DIF_AGC_IF_INT_CURRENT, 0, 31,
1845 0x26001700); 1612 0x26001700);
1846 status = 1613 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1847 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1848 DIF_AGC_RF_CURRENT, 0, 31, 1614 DIF_AGC_RF_CURRENT, 0, 31,
1849 0x00002660); 1615 0x00002660);
1850 status = 1616 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1851 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1852 DIF_VID_AUD_OVERRIDE, 0, 31, 1617 DIF_VID_AUD_OVERRIDE, 0, 31,
1853 0x27000100); 1618 0x27000100);
1854 status = 1619 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1855 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1856 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1620 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1857 status = 1621 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1858 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1859 DIF_COMP_FLT_CTRL, 0, 31, 1622 DIF_COMP_FLT_CTRL, 0, 31,
1860 0x00000000); 1623 0x00000000);
1861 status = 1624 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1862 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1863 DIF_SRC_PHASE_INC, 0, 31, 1625 DIF_SRC_PHASE_INC, 0, 31,
1864 0x1befbf06); 1626 0x1befbf06);
1865 status = 1627 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1866 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1867 DIF_SRC_GAIN_CONTROL, 0, 31, 1628 DIF_SRC_GAIN_CONTROL, 0, 31,
1868 0x000035e8); 1629 0x000035e8);
1869 status = 1630 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1870 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1871 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1631 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1872 status = 1632 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1873 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1874 DIF_VIDEO_AGC_CTRL, 0, 31, 1633 DIF_VIDEO_AGC_CTRL, 0, 31,
1875 0xf4000000); 1634 0xf4000000);
1876 1635
@@ -1881,62 +1640,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1881 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1640 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1882 1641
1883 /* Is it SECAM_L1? */ 1642 /* Is it SECAM_L1? */
1884 status = 1643 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1885 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1886 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1644 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1887 status = 1645 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1888 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1889 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1646 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1890 status = 1647 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1891 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1892 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1648 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1893 status = 1649 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1894 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1895 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1650 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1896 status = 1651 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1897 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1898 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1652 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1899 status = 1653 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1900 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1901 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1654 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1902 status = 1655 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1903 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1904 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1656 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1905 status = 1657 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1906 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1907 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1658 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1908 status = 1659 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1909 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1910 DIF_AGC_IF_INT_CURRENT, 0, 31, 1660 DIF_AGC_IF_INT_CURRENT, 0, 31,
1911 0x26001700); 1661 0x26001700);
1912 status = 1662 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1913 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1914 DIF_AGC_RF_CURRENT, 0, 31, 1663 DIF_AGC_RF_CURRENT, 0, 31,
1915 0x00002660); 1664 0x00002660);
1916 status = 1665 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1917 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1918 DIF_VID_AUD_OVERRIDE, 0, 31, 1666 DIF_VID_AUD_OVERRIDE, 0, 31,
1919 0x27000100); 1667 0x27000100);
1920 status = 1668 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1921 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1922 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1669 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1923 status = 1670 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1924 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1925 DIF_COMP_FLT_CTRL, 0, 31, 1671 DIF_COMP_FLT_CTRL, 0, 31,
1926 0x00000000); 1672 0x00000000);
1927 status = 1673 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1928 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1929 DIF_SRC_PHASE_INC, 0, 31, 1674 DIF_SRC_PHASE_INC, 0, 31,
1930 0x1befbf06); 1675 0x1befbf06);
1931 status = 1676 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1932 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1933 DIF_SRC_GAIN_CONTROL, 0, 31, 1677 DIF_SRC_GAIN_CONTROL, 0, 31,
1934 0x000035e8); 1678 0x000035e8);
1935 status = 1679 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1936 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1937 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1680 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1938 status = 1681 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1939 cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1940 DIF_VIDEO_AGC_CTRL, 0, 31, 1682 DIF_VIDEO_AGC_CTRL, 0, 31,
1941 0xf2560000); 1683 0xf2560000);
1942 1684
@@ -1944,67 +1686,54 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1944 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1686 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1945 dif_misc_ctrl_value |= 0x3a023F11; 1687 dif_misc_ctrl_value |= 0x3a023F11;
1946 1688
1947 } else { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1689 } else {
1690 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1691 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
1948 1692
1949 /* For NTSC the centre frequency of video coming out of sidewinder is 1693 /* For NTSC the centre frequency of video coming out of
1950 around 7.1MHz or 3.6MHz depending on the spectral inversion. 1694 sidewinder is around 7.1MHz or 3.6MHz depending on the
1951 so for a non spectrally inverted channel the pll freq word is 0x03420c49 1695 spectral inversion. so for a non spectrally inverted channel
1696 the pll freq word is 0x03420c49
1952 */ 1697 */
1953 1698
1954 status = 1699 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1955 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1956 DIF_PLL_CTRL, 2, 0x6503BC0C, 4); 1700 DIF_PLL_CTRL, 2, 0x6503BC0C, 4);
1957 status = 1701 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1958 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1959 DIF_PLL_CTRL1, 2, 0xBD038C85, 4); 1702 DIF_PLL_CTRL1, 2, 0xBD038C85, 4);
1960 status = 1703 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1961 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1962 DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); 1704 DIF_PLL_CTRL2, 2, 0x1DB4640A, 4);
1963 status = 1705 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1964 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1965 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1706 DIF_PLL_CTRL3, 2, 0x00008800, 4);
1966 status = 1707 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1967 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1968 DIF_AGC_IF_REF, 2, 0x444C0380, 4); 1708 DIF_AGC_IF_REF, 2, 0x444C0380, 4);
1969 status = 1709 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1970 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1971 DIF_AGC_IF_INT_CURRENT, 2, 1710 DIF_AGC_IF_INT_CURRENT, 2,
1972 0x26001700, 4); 1711 0x26001700, 4);
1973 status = 1712 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1974 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1975 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1713 DIF_AGC_RF_CURRENT, 2, 0x00002660,
1976 4); 1714 4);
1977 status = 1715 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1978 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1979 DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 1716 DIF_VIDEO_AGC_CTRL, 2, 0x04000800,
1980 4); 1717 4);
1981 status = 1718 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1982 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1983 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1719 DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1984 4); 1720 4);
1985 status = 1721 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1986 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1987 DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); 1722 DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4);
1988 1723
1989 status = 1724 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1990 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1991 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); 1725 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1992 status = 1726 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1993 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1994 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); 1727 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1995 status = 1728 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1996 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1997 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 1729 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1998 4); 1730 4);
1999 1731
2000 status = 1732 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2001 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2002 DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); 1733 DIF_AGC_CTRL_IF, 2, 0xC2262600, 4);
2003 status = 1734 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2004 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2005 DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); 1735 DIF_AGC_CTRL_INT, 2, 0xC2262600, 4);
2006 status = 1736 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2007 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2008 DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); 1737 DIF_AGC_CTRL_RF, 2, 0xC2262600, 4);
2009 1738
2010 /* Save the Spec Inversion value */ 1739 /* Save the Spec Inversion value */
@@ -2017,7 +1746,8 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
2017 AUD_SRC_SEL[19] should always be disabled */ 1746 AUD_SRC_SEL[19] should always be disabled */
2018 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 1747 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2019 1748
2020 /* It is still possible to get Set Standard calls even when we are in FM mode 1749 /* It is still possible to get Set Standard calls even when we
1750 are in FM mode.
2021 This is done to override the value for FM. */ 1751 This is done to override the value for FM. */
2022 if (dev->active_mode == V4L2_TUNER_RADIO) 1752 if (dev->active_mode == V4L2_TUNER_RADIO)
2023 dif_misc_ctrl_value = 0x7a080000; 1753 dif_misc_ctrl_value = 0x7a080000;
@@ -2057,12 +1787,11 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2057 DIF_AGC_IF_REF, 2, &dwval, 4); 1787 DIF_AGC_IF_REF, 2, &dwval, 4);
2058 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1788 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2059 1789
2060 if (dev-> 1790 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2061 norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D)) { 1791 V4L2_STD_SECAM_D))
2062 dwval |= 0x88000000; 1792 dwval |= 0x88000000;
2063 } else { 1793 else
2064 dwval |= 0x44000000; 1794 dwval |= 0x44000000;
2065 }
2066 1795
2067 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1796 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
2068 DIF_AGC_IF_REF, 2, dwval, 4); 1797 DIF_AGC_IF_REF, 2, dwval, 4);
@@ -2070,17 +1799,16 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2070 return status; 1799 return status;
2071} 1800}
2072 1801
2073/************************************************************************************* 1802/******************************************************************************
2074 * F L A T I R O N - B L O C K C O N T R O L functions * 1803 * F L A T I R O N - B L O C K C O N T R O L functions *
2075 *************************************************************************************/ 1804 ******************************************************************************/
2076int cx231xx_flatiron_initialize(struct cx231xx *dev) 1805int cx231xx_flatiron_initialize(struct cx231xx *dev)
2077{ 1806{
2078 int status = 0; 1807 int status = 0;
2079 u32 value; 1808 u32 value;
2080 1809
2081 status = 1810 status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2082 cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, 1811 CH_PWR_CTRL1, 1, &value, 1);
2083 &value, 1);
2084 /* enables clock to delta-sigma and decimation filter */ 1812 /* enables clock to delta-sigma and decimation filter */
2085 value |= 0x80; 1813 value |= 0x80;
2086 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1814 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
@@ -2098,8 +1826,7 @@ int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode)
2098 u32 value = 0; 1826 u32 value = 0;
2099 1827
2100 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 1828 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2101 status = 1829 status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2102 cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2103 CH_PWR_CTRL2, 1, &value, 1); 1830 CH_PWR_CTRL2, 1, &value, 1);
2104 value |= 0xfe; 1831 value |= 0xfe;
2105 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1832 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
@@ -2119,7 +1846,6 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
2119 1846
2120 switch (audio_input) { 1847 switch (audio_input) {
2121 case CX231XX_AMUX_LINE_IN: 1848 case CX231XX_AMUX_LINE_IN:
2122
2123 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1849 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
2124 CH_PWR_CTRL2, 1, 0x00, 1); 1850 CH_PWR_CTRL2, 1, 0x00, 1);
2125 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1851 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
@@ -2135,9 +1861,9 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
2135 return status; 1861 return status;
2136} 1862}
2137 1863
2138/************************************************************************************* 1864/******************************************************************************
2139 * P O W E R C O N T R O L functions * 1865 * P O W E R C O N T R O L functions *
2140 *************************************************************************************/ 1866 ******************************************************************************/
2141int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) 1867int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2142{ 1868{
2143 u8 value[4] = { 0, 0, 0, 0 }; 1869 u8 value[4] = { 0, 0, 0, 0 };
@@ -2154,8 +1880,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2154 1880
2155 cx231xx_info(" setPowerMode::mode = %d\n", mode); 1881 cx231xx_info(" setPowerMode::mode = %d\n", mode);
2156 1882
2157 status = 1883 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2158 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); 1884 4);
2159 if (status < 0) 1885 if (status < 0)
2160 return status; 1886 return status;
2161 1887
@@ -2171,9 +1897,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2171 value[1] = (u8) (tmp >> 8); 1897 value[1] = (u8) (tmp >> 8);
2172 value[2] = (u8) (tmp >> 16); 1898 value[2] = (u8) (tmp >> 16);
2173 value[3] = (u8) (tmp >> 24); 1899 value[3] = (u8) (tmp >> 24);
2174 status = 1900 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2175 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 1901 PWR_CTL_EN, value, 4);
2176 value, 4);
2177 msleep(PWR_SLEEP_INTERVAL); 1902 msleep(PWR_SLEEP_INTERVAL);
2178 1903
2179 tmp |= PWR_ISO_EN; 1904 tmp |= PWR_ISO_EN;
@@ -2191,9 +1916,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2191 value[1] = (u8) (tmp >> 8); 1916 value[1] = (u8) (tmp >> 8);
2192 value[2] = (u8) (tmp >> 16); 1917 value[2] = (u8) (tmp >> 16);
2193 value[3] = (u8) (tmp >> 24); 1918 value[3] = (u8) (tmp >> 24);
2194 status = 1919 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2195 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 1920 PWR_CTL_EN, value, 4);
2196 value, 4);
2197 1921
2198 dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ 1922 dev->xc_fw_load_done = 0; /* reset state of xceive tuner */
2199 break; 1923 break;
@@ -2206,9 +1930,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2206 value[1] = (u8) (tmp >> 8); 1930 value[1] = (u8) (tmp >> 8);
2207 value[2] = (u8) (tmp >> 16); 1931 value[2] = (u8) (tmp >> 16);
2208 value[3] = (u8) (tmp >> 24); 1932 value[3] = (u8) (tmp >> 24);
2209 status = 1933 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2210 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 1934 PWR_CTL_EN, value, 4);
2211 value, 4);
2212 msleep(PWR_SLEEP_INTERVAL); 1935 msleep(PWR_SLEEP_INTERVAL);
2213 1936
2214 if (!(tmp & PWR_TUNER_EN)) { 1937 if (!(tmp & PWR_TUNER_EN)) {
@@ -2217,9 +1940,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2217 value[1] = (u8) (tmp >> 8); 1940 value[1] = (u8) (tmp >> 8);
2218 value[2] = (u8) (tmp >> 16); 1941 value[2] = (u8) (tmp >> 16);
2219 value[3] = (u8) (tmp >> 24); 1942 value[3] = (u8) (tmp >> 24);
2220 status = 1943 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2221 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1944 PWR_CTL_EN, value, 4);
2222 PWR_CTL_EN, value, 4);
2223 msleep(PWR_SLEEP_INTERVAL); 1945 msleep(PWR_SLEEP_INTERVAL);
2224 } 1946 }
2225 1947
@@ -2229,9 +1951,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2229 value[1] = (u8) (tmp >> 8); 1951 value[1] = (u8) (tmp >> 8);
2230 value[2] = (u8) (tmp >> 16); 1952 value[2] = (u8) (tmp >> 16);
2231 value[3] = (u8) (tmp >> 24); 1953 value[3] = (u8) (tmp >> 24);
2232 status = 1954 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2233 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1955 PWR_CTL_EN, value, 4);
2234 PWR_CTL_EN, value, 4);
2235 msleep(PWR_SLEEP_INTERVAL); 1956 msleep(PWR_SLEEP_INTERVAL);
2236 } 1957 }
2237 if (!(tmp & PWR_ISO_EN)) { 1958 if (!(tmp & PWR_ISO_EN)) {
@@ -2240,9 +1961,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2240 value[1] = (u8) (tmp >> 8); 1961 value[1] = (u8) (tmp >> 8);
2241 value[2] = (u8) (tmp >> 16); 1962 value[2] = (u8) (tmp >> 16);
2242 value[3] = (u8) (tmp >> 24); 1963 value[3] = (u8) (tmp >> 24);
2243 status = 1964 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2244 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1965 PWR_CTL_EN, value, 4);
2245 PWR_CTL_EN, value, 4);
2246 msleep(PWR_SLEEP_INTERVAL); 1966 msleep(PWR_SLEEP_INTERVAL);
2247 } 1967 }
2248 1968
@@ -2252,15 +1972,13 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2252 value[1] = (u8) (tmp >> 8); 1972 value[1] = (u8) (tmp >> 8);
2253 value[2] = (u8) (tmp >> 16); 1973 value[2] = (u8) (tmp >> 16);
2254 value[3] = (u8) (tmp >> 24); 1974 value[3] = (u8) (tmp >> 24);
2255 status = 1975 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2256 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1976 PWR_CTL_EN, value, 4);
2257 PWR_CTL_EN, value, 4);
2258 msleep(PWR_SLEEP_INTERVAL); 1977 msleep(PWR_SLEEP_INTERVAL);
2259 } 1978 }
2260 1979
2261 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 1980 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2262 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 1981 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2263
2264 /* tuner path to channel 1 from port 3 */ 1982 /* tuner path to channel 1 from port 3 */
2265 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 1983 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2266 1984
@@ -2270,16 +1988,14 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2270 break; 1988 break;
2271 1989
2272 case POLARIS_AVMODE_DIGITAL: 1990 case POLARIS_AVMODE_DIGITAL:
2273
2274 if (!(tmp & PWR_TUNER_EN)) { 1991 if (!(tmp & PWR_TUNER_EN)) {
2275 tmp |= (PWR_TUNER_EN); 1992 tmp |= (PWR_TUNER_EN);
2276 value[0] = (u8) tmp; 1993 value[0] = (u8) tmp;
2277 value[1] = (u8) (tmp >> 8); 1994 value[1] = (u8) (tmp >> 8);
2278 value[2] = (u8) (tmp >> 16); 1995 value[2] = (u8) (tmp >> 16);
2279 value[3] = (u8) (tmp >> 24); 1996 value[3] = (u8) (tmp >> 24);
2280 status = 1997 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2281 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1998 PWR_CTL_EN, value, 4);
2282 PWR_CTL_EN, value, 4);
2283 msleep(PWR_SLEEP_INTERVAL); 1999 msleep(PWR_SLEEP_INTERVAL);
2284 } 2000 }
2285 if (!(tmp & PWR_AV_EN)) { 2001 if (!(tmp & PWR_AV_EN)) {
@@ -2288,9 +2004,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2288 value[1] = (u8) (tmp >> 8); 2004 value[1] = (u8) (tmp >> 8);
2289 value[2] = (u8) (tmp >> 16); 2005 value[2] = (u8) (tmp >> 16);
2290 value[3] = (u8) (tmp >> 24); 2006 value[3] = (u8) (tmp >> 24);
2291 status = 2007 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2292 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2008 PWR_CTL_EN, value, 4);
2293 PWR_CTL_EN, value, 4);
2294 msleep(PWR_SLEEP_INTERVAL); 2009 msleep(PWR_SLEEP_INTERVAL);
2295 } 2010 }
2296 if (!(tmp & PWR_ISO_EN)) { 2011 if (!(tmp & PWR_ISO_EN)) {
@@ -2299,9 +2014,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2299 value[1] = (u8) (tmp >> 8); 2014 value[1] = (u8) (tmp >> 8);
2300 value[2] = (u8) (tmp >> 16); 2015 value[2] = (u8) (tmp >> 16);
2301 value[3] = (u8) (tmp >> 24); 2016 value[3] = (u8) (tmp >> 24);
2302 status = 2017 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2303 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2018 PWR_CTL_EN, value, 4);
2304 PWR_CTL_EN, value, 4);
2305 msleep(PWR_SLEEP_INTERVAL); 2019 msleep(PWR_SLEEP_INTERVAL);
2306 } 2020 }
2307 2021
@@ -2310,9 +2024,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2310 value[1] = (u8) (tmp >> 8); 2024 value[1] = (u8) (tmp >> 8);
2311 value[2] = (u8) (tmp >> 16); 2025 value[2] = (u8) (tmp >> 16);
2312 value[3] = (u8) (tmp >> 24); 2026 value[3] = (u8) (tmp >> 24);
2313 status = 2027 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2314 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2028 PWR_CTL_EN, value, 4);
2315 value, 4);
2316 msleep(PWR_SLEEP_INTERVAL); 2029 msleep(PWR_SLEEP_INTERVAL);
2317 2030
2318 if (!(tmp & PWR_DEMOD_EN)) { 2031 if (!(tmp & PWR_DEMOD_EN)) {
@@ -2321,15 +2034,13 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2321 value[1] = (u8) (tmp >> 8); 2034 value[1] = (u8) (tmp >> 8);
2322 value[2] = (u8) (tmp >> 16); 2035 value[2] = (u8) (tmp >> 16);
2323 value[3] = (u8) (tmp >> 24); 2036 value[3] = (u8) (tmp >> 24);
2324 status = 2037 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2325 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2038 PWR_CTL_EN, value, 4);
2326 PWR_CTL_EN, value, 4);
2327 msleep(PWR_SLEEP_INTERVAL); 2039 msleep(PWR_SLEEP_INTERVAL);
2328 } 2040 }
2329 2041
2330 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 2042 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2331 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 2043 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2332
2333 /* tuner path to channel 1 from port 3 */ 2044 /* tuner path to channel 1 from port 3 */
2334 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 2045 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2335 2046
@@ -2344,16 +2055,16 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2344 2055
2345 msleep(PWR_SLEEP_INTERVAL); 2056 msleep(PWR_SLEEP_INTERVAL);
2346 2057
2347 /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */ 2058 /* For power saving, only enable Pwr_resetout_n
2059 when digital TV is selected. */
2348 if (mode == POLARIS_AVMODE_DIGITAL) { 2060 if (mode == POLARIS_AVMODE_DIGITAL) {
2349 tmp |= PWR_RESETOUT_EN; 2061 tmp |= PWR_RESETOUT_EN;
2350 value[0] = (u8) tmp; 2062 value[0] = (u8) tmp;
2351 value[1] = (u8) (tmp >> 8); 2063 value[1] = (u8) (tmp >> 8);
2352 value[2] = (u8) (tmp >> 16); 2064 value[2] = (u8) (tmp >> 16);
2353 value[3] = (u8) (tmp >> 24); 2065 value[3] = (u8) (tmp >> 24);
2354 status = 2066 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2355 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2067 PWR_CTL_EN, value, 4);
2356 value, 4);
2357 msleep(PWR_SLEEP_INTERVAL); 2068 msleep(PWR_SLEEP_INTERVAL);
2358 } 2069 }
2359 2070
@@ -2363,11 +2074,10 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
2363 /* update power control for flatiron */ 2074 /* update power control for flatiron */
2364 status = cx231xx_flatiron_update_power_control(dev, mode); 2075 status = cx231xx_flatiron_update_power_control(dev, mode);
2365 2076
2366 status = 2077 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2367 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); 2078 4);
2368 cx231xx_info 2079 cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n",
2369 (" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n", 2080 value[0], value[1], value[2], value[3]);
2370 value[0], value[1], value[2], value[3]);
2371 2081
2372 return status; 2082 return status;
2373} 2083}
@@ -2378,8 +2088,8 @@ int cx231xx_power_suspend(struct cx231xx *dev)
2378 u32 tmp = 0; 2088 u32 tmp = 0;
2379 int status = 0; 2089 int status = 0;
2380 2090
2381 status = 2091 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2382 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); 2092 value, 4);
2383 if (status > 0) 2093 if (status > 0)
2384 return status; 2094 return status;
2385 2095
@@ -2390,15 +2100,15 @@ int cx231xx_power_suspend(struct cx231xx *dev)
2390 value[1] = (u8) (tmp >> 8); 2100 value[1] = (u8) (tmp >> 8);
2391 value[2] = (u8) (tmp >> 16); 2101 value[2] = (u8) (tmp >> 16);
2392 value[3] = (u8) (tmp >> 24); 2102 value[3] = (u8) (tmp >> 24);
2393 status = 2103 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2394 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); 2104 value, 4);
2395 2105
2396 return status; 2106 return status;
2397} 2107}
2398 2108
2399/************************************************************************************* 2109/******************************************************************************
2400 * S T R E A M C O N T R O L functions * 2110 * S T R E A M C O N T R O L functions *
2401 *************************************************************************************/ 2111 ******************************************************************************/
2402int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2112int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2403{ 2113{
2404 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2114 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
@@ -2406,8 +2116,8 @@ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2406 int status = 0; 2116 int status = 0;
2407 2117
2408 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 2118 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2409 status = 2119 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2410 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2120 value, 4);
2411 if (status < 0) 2121 if (status < 0)
2412 return status; 2122 return status;
2413 2123
@@ -2418,9 +2128,8 @@ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2418 value[2] = (u8) (tmp >> 16); 2128 value[2] = (u8) (tmp >> 16);
2419 value[3] = (u8) (tmp >> 24); 2129 value[3] = (u8) (tmp >> 24);
2420 2130
2421 status = 2131 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2422 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, 2132 value, 4);
2423 4);
2424 2133
2425 return status; 2134 return status;
2426} 2135}
@@ -2444,9 +2153,8 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2444 value[2] = (u8) (tmp >> 16); 2153 value[2] = (u8) (tmp >> 16);
2445 value[3] = (u8) (tmp >> 24); 2154 value[3] = (u8) (tmp >> 24);
2446 2155
2447 status = 2156 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2448 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, 2157 value, 4);
2449 4);
2450 2158
2451 return status; 2159 return status;
2452} 2160}
@@ -2558,9 +2266,8 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2558 if (start) { 2266 if (start) {
2559 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2267 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2560 2268
2561 if (rc < 0) { 2269 if (rc < 0)
2562 return rc; 2270 return rc;
2563 }
2564 2271
2565 /* enable video capture */ 2272 /* enable video capture */
2566 if (ep_mask > 0) 2273 if (ep_mask > 0)
@@ -2571,20 +2278,14 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2571 rc = cx231xx_stop_stream(dev, ep_mask); 2278 rc = cx231xx_stop_stream(dev, ep_mask);
2572 } 2279 }
2573 2280
2574 if (dev->mode == CX231XX_ANALOG_MODE) {
2575 /* do any in Analog mode */
2576 } else {
2577 /* do any in digital mode */
2578 }
2579 2281
2580 return rc; 2282 return rc;
2581} 2283}
2582
2583EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2284EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2584 2285
2585/************************************************************************************ 2286/*****************************************************************************
2586* G P I O B I T control functions * 2287* G P I O B I T control functions *
2587*************************************************************************************/ 2288******************************************************************************/
2588int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) 2289int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2589{ 2290{
2590 int status = 0; 2291 int status = 0;
@@ -2621,17 +2322,16 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev,
2621 u32 value = 0; 2322 u32 value = 0;
2622 2323
2623 /* Check for valid pin_number - if 32 , bail out */ 2324 /* Check for valid pin_number - if 32 , bail out */
2624 if (pin_number >= 32) { 2325 if (pin_number >= 32)
2625 return -EINVAL; 2326 return -EINVAL;
2626 }
2627 2327
2628 if (pin_value == 0) { /* input */ 2328 /* input */
2329 if (pin_value == 0)
2629 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2330 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2630 } else { 2331 else
2631 value = dev->gpio_dir | (1 << pin_number); 2332 value = dev->gpio_dir | (1 << pin_number);
2632 }
2633 2333
2634 status = cx231xx_set_gpio_bit(dev, value, (u8 *) & dev->gpio_val); 2334 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2635 2335
2636 /* cache the value for future */ 2336 /* cache the value for future */
2637 dev->gpio_dir = value; 2337 dev->gpio_dir = value;
@@ -2664,31 +2364,28 @@ int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2664 /* It was in input mode */ 2364 /* It was in input mode */
2665 value = dev->gpio_dir | (1 << pin_number); 2365 value = dev->gpio_dir | (1 << pin_number);
2666 dev->gpio_dir = value; 2366 dev->gpio_dir = value;
2667 status = 2367 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2668 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2368 (u8 *) &dev->gpio_val);
2669 (u8 *) & dev->gpio_val);
2670 value = 0; 2369 value = 0;
2671 } 2370 }
2672 2371
2673 if (pin_value == 0) { 2372 if (pin_value == 0)
2674 value = dev->gpio_val & (~(1 << pin_number)); 2373 value = dev->gpio_val & (~(1 << pin_number));
2675 } else { 2374 else
2676 value = dev->gpio_val | (1 << pin_number); 2375 value = dev->gpio_val | (1 << pin_number);
2677 }
2678 2376
2679 /* store the value */ 2377 /* store the value */
2680 dev->gpio_val = value; 2378 dev->gpio_val = value;
2681 2379
2682 /* toggle bit0 of GP_IO */ 2380 /* toggle bit0 of GP_IO */
2683 status = 2381 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2684 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2685 2382
2686 return status; 2383 return status;
2687} 2384}
2688 2385
2689/************************************************************************************ 2386/*****************************************************************************
2690* G P I O I2C related functions * 2387* G P I O I2C related functions *
2691*************************************************************************************/ 2388******************************************************************************/
2692int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2389int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2693{ 2390{
2694 int status = 0; 2391 int status = 0;
@@ -2699,31 +2396,25 @@ int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2699 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2396 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2700 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2397 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2701 2398
2702 status = 2399 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2703 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2400 if (status < 0)
2704 if (status < 0) {
2705 return -EINVAL; 2401 return -EINVAL;
2706 }
2707 2402
2708 /* set SCL to output 1; set SDA to output 0 */ 2403 /* set SCL to output 1; set SDA to output 0 */
2709 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2404 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2710 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2405 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2711 2406
2712 status = 2407 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2713 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2408 if (status < 0)
2714 if (status < 0) {
2715 return -EINVAL; 2409 return -EINVAL;
2716 }
2717 2410
2718 /* set SCL to output 0; set SDA to output 0 */ 2411 /* set SCL to output 0; set SDA to output 0 */
2719 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2412 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2720 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2413 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2721 2414
2722 status = 2415 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2723 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2416 if (status < 0)
2724 if (status < 0) {
2725 return -EINVAL; 2417 return -EINVAL;
2726 }
2727 2418
2728 return status; 2419 return status;
2729} 2420}
@@ -2739,21 +2430,17 @@ int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2739 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2430 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2740 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2431 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2741 2432
2742 status = 2433 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2743 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2434 if (status < 0)
2744 if (status < 0) {
2745 return -EINVAL; 2435 return -EINVAL;
2746 }
2747 2436
2748 /* set SCL to output 1; set SDA to output 0 */ 2437 /* set SCL to output 1; set SDA to output 0 */
2749 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2438 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2750 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2439 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2751 2440
2752 status = 2441 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2753 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2442 if (status < 0)
2754 if (status < 0) {
2755 return -EINVAL; 2443 return -EINVAL;
2756 }
2757 2444
2758 /* set SCL to input ,release SCL cable control 2445 /* set SCL to input ,release SCL cable control
2759 set SDA to input ,release SDA cable control */ 2446 set SDA to input ,release SDA cable control */
@@ -2761,10 +2448,10 @@ int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2761 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2448 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2762 2449
2763 status = 2450 status =
2764 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2451 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2765 if (status < 0) { 2452 if (status < 0)
2766 return -EINVAL; 2453 return -EINVAL;
2767 } 2454
2768 return status; 2455 return status;
2769} 2456}
2770 2457
@@ -2782,40 +2469,34 @@ int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2782 /* set SCL to output 0; set SDA to output 0 */ 2469 /* set SCL to output 0; set SDA to output 0 */
2783 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2470 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2784 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2471 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2785 status = 2472 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2786 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2473 (u8 *)&dev->gpio_val);
2787 (u8 *) & dev->gpio_val);
2788 2474
2789 /* set SCL to output 1; set SDA to output 0 */ 2475 /* set SCL to output 1; set SDA to output 0 */
2790 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2476 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2791 status = 2477 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2792 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2478 (u8 *)&dev->gpio_val);
2793 (u8 *) & dev->gpio_val);
2794 2479
2795 /* set SCL to output 0; set SDA to output 0 */ 2480 /* set SCL to output 0; set SDA to output 0 */
2796 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2481 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2797 status = 2482 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2798 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2483 (u8 *)&dev->gpio_val);
2799 (u8 *) & dev->gpio_val);
2800 } else { 2484 } else {
2801 /* set SCL to output 0; set SDA to output 1 */ 2485 /* set SCL to output 0; set SDA to output 1 */
2802 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2486 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2803 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2487 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2804 status = 2488 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2805 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2489 (u8 *)&dev->gpio_val);
2806 (u8 *) & dev->gpio_val);
2807 2490
2808 /* set SCL to output 1; set SDA to output 1 */ 2491 /* set SCL to output 1; set SDA to output 1 */
2809 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2492 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2810 status = 2493 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2811 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2494 (u8 *)&dev->gpio_val);
2812 (u8 *) & dev->gpio_val);
2813 2495
2814 /* set SCL to output 0; set SDA to output 1 */ 2496 /* set SCL to output 0; set SDA to output 1 */
2815 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2497 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2816 status = 2498 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2817 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2499 (u8 *)&dev->gpio_val);
2818 (u8 *) & dev->gpio_val);
2819 } 2500 }
2820 } 2501 }
2821 return status; 2502 return status;
@@ -2833,33 +2514,29 @@ int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2833 2514
2834 /* set SCL to output 0; set SDA to input */ 2515 /* set SCL to output 0; set SDA to input */
2835 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2516 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2836 status = 2517 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2837 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2518 (u8 *)&dev->gpio_val);
2838 (u8 *) & dev->gpio_val);
2839 2519
2840 /* set SCL to output 1; set SDA to input */ 2520 /* set SCL to output 1; set SDA to input */
2841 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2521 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2842 status = 2522 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2843 cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2523 (u8 *)&dev->gpio_val);
2844 (u8 *) & dev->gpio_val);
2845 2524
2846 /* get SDA data bit */ 2525 /* get SDA data bit */
2847 gpio_logic_value = dev->gpio_val; 2526 gpio_logic_value = dev->gpio_val;
2848 status = 2527 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2849 cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2528 (u8 *)&dev->gpio_val);
2850 (u8 *) & dev->gpio_val); 2529 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2851 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) {
2852 value |= (1 << (8 - i - 1)); 2530 value |= (1 << (8 - i - 1));
2853 }
2854 2531
2855 dev->gpio_val = gpio_logic_value; 2532 dev->gpio_val = gpio_logic_value;
2856 } 2533 }
2857 2534
2858 /* set SCL to output 0,finish the read latest SCL signal. 2535 /* set SCL to output 0,finish the read latest SCL signal.
2859 !!!set SDA to input,never to modify SDA direction at the same times */ 2536 !!!set SDA to input, never to modify SDA direction at
2537 the same times */
2860 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2538 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2861 status = 2539 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2862 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2863 2540
2864 /* store the value */ 2541 /* store the value */
2865 *buf = value & 0xff; 2542 *buf = value & 0xff;
@@ -2874,33 +2551,29 @@ int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2874 int nCnt = 10; 2551 int nCnt = 10;
2875 int nInit = nCnt; 2552 int nInit = nCnt;
2876 2553
2877 /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */ 2554 /* clock stretch; set SCL to input; set SDA to input;
2555 get SCL value till SCL = 1 */
2878 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2556 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2879 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2557 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2880 2558
2881 gpio_logic_value = dev->gpio_val; 2559 gpio_logic_value = dev->gpio_val;
2882 status = 2560 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2883 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2884 2561
2885 do { 2562 do {
2886 msleep(2); 2563 msleep(2);
2887 status = 2564 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2888 cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2565 (u8 *)&dev->gpio_val);
2889 (u8 *) & dev->gpio_val);
2890 nCnt--; 2566 nCnt--;
2891 } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) 2567 } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) && (nCnt > 0));
2892 && (nCnt > 0));
2893 2568
2894 if (nCnt == 0) { 2569 if (nCnt == 0)
2895 cx231xx_info 2570 cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!",
2896 ("No ACK after %d msec for clock stretch. GPIO I2C operation failed!", 2571 nInit * 10);
2897 nInit * 10);
2898 }
2899 2572
2900 /* readAck 2573 /* readAck
2901 throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read. */ 2574 throuth clock stretch ,slave has given a SCL signal,
2902 status = 2575 so the SDA data can be directly read. */
2903 cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); 2576 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2904 2577
2905 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2578 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2906 dev->gpio_val = gpio_logic_value; 2579 dev->gpio_val = gpio_logic_value;
@@ -2911,12 +2584,12 @@ int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2911 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2584 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2912 } 2585 }
2913 2586
2914 /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */ 2587 /* read SDA end, set the SCL to output 0, after this operation,
2588 SDA direction can be changed. */
2915 dev->gpio_val = gpio_logic_value; 2589 dev->gpio_val = gpio_logic_value;
2916 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2590 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2917 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2591 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2918 status = 2592 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2919 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2920 2593
2921 return status; 2594 return status;
2922} 2595}
@@ -2927,29 +2600,24 @@ int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2927 2600
2928 /* set SDA to ouput */ 2601 /* set SDA to ouput */
2929 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2602 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2930 status = 2603 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2931 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2932 2604
2933 /* set SCL = 0 (output); set SDA = 0 (output) */ 2605 /* set SCL = 0 (output); set SDA = 0 (output) */
2934 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2606 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2935 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2607 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2936 status = 2608 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2937 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2938 2609
2939 /* set SCL = 1 (output); set SDA = 0 (output) */ 2610 /* set SCL = 1 (output); set SDA = 0 (output) */
2940 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2611 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2941 status = 2612 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2942 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2943 2613
2944 /* set SCL = 0 (output); set SDA = 0 (output) */ 2614 /* set SCL = 0 (output); set SDA = 0 (output) */
2945 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2615 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2946 status = 2616 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2947 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2948 2617
2949 /* set SDA to input,and then the slave will read data from SDA. */ 2618 /* set SDA to input,and then the slave will read data from SDA. */
2950 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2619 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2951 status = 2620 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2952 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2953 2621
2954 return status; 2622 return status;
2955} 2623}
@@ -2961,25 +2629,22 @@ int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2961 /* set scl to output ; set sda to input */ 2629 /* set scl to output ; set sda to input */
2962 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2630 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2963 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2631 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2964 status = 2632 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2965 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2966 2633
2967 /* set scl to output 0; set sda to input */ 2634 /* set scl to output 0; set sda to input */
2968 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2635 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2969 status = 2636 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2970 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2971 2637
2972 /* set scl to output 1; set sda to input */ 2638 /* set scl to output 1; set sda to input */
2973 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2639 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2974 status = 2640 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2975 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val);
2976 2641
2977 return status; 2642 return status;
2978} 2643}
2979 2644
2980/************************************************************************************ 2645/*****************************************************************************
2981* G P I O I2C related functions * 2646* G P I O I2C related functions *
2982*************************************************************************************/ 2647******************************************************************************/
2983/* cx231xx_gpio_i2c_read 2648/* cx231xx_gpio_i2c_read
2984 * Function to read data from gpio based I2C interface 2649 * Function to read data from gpio based I2C interface
2985 */ 2650 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 01:04:53 -0500