[media] rename most media/video usb drivers to media/usb

Rename all USB drivers with their own directory under
drivers/media/video into drivers/media/usb and update the
building system.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

19 files changed, 21403 insertions, 0 deletions

diff --git a/drivers/media/usb/cx231xx/Kconfig b/drivers/media/usb/cx231xx/Kconfig
new file mode 100644
index 000000000000..446f692aabb7
--- /dev/null
+++ b/drivers/media/usb/cx231xx/Kconfig
@@ -0,0 +1,51 @@
+config VIDEO_CX231XX
+        tristate "Conexant cx231xx USB video capture support"
+        depends on VIDEO_DEV && I2C
+        select VIDEO_TUNER
+        select VIDEO_TVEEPROM
+        depends on RC_CORE
+        select VIDEOBUF_VMALLOC
+        select VIDEO_CX25840
+        select VIDEO_CX2341X
+
+        ---help---
+          This is a video4linux driver for Conexant 231xx USB based TV cards.
+
+          To compile this driver as a module, choose M here: the
+          module will be called cx231xx
+
+config VIDEO_CX231XX_RC
+        bool "Conexant cx231xx Remote Controller additional support"
+        depends on RC_CORE
+        depends on VIDEO_CX231XX
+        default y
+        ---help---
+          cx231xx hardware has a builtin RX/TX support. However, a few
+          designs opted to not use it, but, instead, some other hardware.
+          This module enables the usage of those other hardware, like the
+          ones used with ISDB-T boards.
+
+          On most cases, all you need for IR is mceusb module.
+
+config VIDEO_CX231XX_ALSA
+        tristate "Conexant Cx231xx ALSA audio module"
+        depends on VIDEO_CX231XX && SND
+        select SND_PCM
+
+        ---help---
+          This is an ALSA driver for Cx231xx USB based TV cards.
+
+          To compile this driver as a module, choose M here: the
+          module will be called cx231xx-alsa
+
+config VIDEO_CX231XX_DVB
+        tristate "DVB/ATSC Support for Cx231xx based TV cards"
+        depends on VIDEO_CX231XX && DVB_CORE && DVB_CAPTURE_DRIVERS
+        select VIDEOBUF_DVB
+        select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMISE
+        select MEDIA_TUNER_TDA18271 if !MEDIA_TUNER_CUSTOMISE
+        select DVB_MB86A20S if !DVB_FE_CUSTOMISE
+
+        ---help---
+          This adds support for DVB cards based on the
+          Conexant cx231xx chips.
diff --git a/drivers/media/usb/cx231xx/Makefile b/drivers/media/usb/cx231xx/Makefile
new file mode 100644
index 000000000000..1d40fce77601
--- /dev/null
+++ b/drivers/media/usb/cx231xx/Makefile
@@ -0,0 +1,15 @@
+cx231xx-y += cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o
+cx231xx-y += cx231xx-avcore.o cx231xx-417.o cx231xx-pcb-cfg.o cx231xx-vbi.o
+cx231xx-$(CONFIG_VIDEO_CX231XX_RC) += cx231xx-input.o
+
+cx231xx-alsa-objs := cx231xx-audio.o
+
+obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o
+obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-alsa.o
+obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o
+
+ccflags-y += -Idrivers/media/video
+ccflags-y += -Idrivers/media/tuners
+ccflags-y += -Idrivers/media/dvb-core
+ccflags-y += -Idrivers/media/dvb-frontends
+ccflags-y += -Idrivers/media/usb/dvb-usb
diff --git a/drivers/media/usb/cx231xx/cx231xx-417.c b/drivers/media/usb/cx231xx/cx231xx-417.c
new file mode 100644
index 000000000000..b024e5197a75
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-417.c
@@ -0,0 +1,2197 @@
+/*
+ *
+ *  Support for a cx23417 mpeg encoder via cx231xx host port.
+ *
+ *    (c) 2004 Jelle Foks <jelle@foks.us>
+ *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
+ *    (c) 2008 Steven Toth <stoth@linuxtv.org>
+ *      - CX23885/7/8 support
+ *
+ *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <media/cx2341x.h>
+#include <linux/usb.h>
+
+#include "cx231xx.h"
+/*#include "cx23885-ioctl.h"*/
+
+#define CX231xx_FIRM_IMAGE_SIZE 376836
+#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
+
+/* for polaris ITVC */
+#define ITVC_WRITE_DIR          0x03FDFC00
+#define ITVC_READ_DIR            0x0001FC00
+
+#define  MCI_MEMORY_DATA_BYTE0          0x00
+#define  MCI_MEMORY_DATA_BYTE1          0x08
+#define  MCI_MEMORY_DATA_BYTE2          0x10
+#define  MCI_MEMORY_DATA_BYTE3          0x18
+
+#define  MCI_MEMORY_ADDRESS_BYTE2       0x20
+#define  MCI_MEMORY_ADDRESS_BYTE1       0x28
+#define  MCI_MEMORY_ADDRESS_BYTE0       0x30
+
+#define  MCI_REGISTER_DATA_BYTE0        0x40
+#define  MCI_REGISTER_DATA_BYTE1        0x48
+#define  MCI_REGISTER_DATA_BYTE2        0x50
+#define  MCI_REGISTER_DATA_BYTE3        0x58
+
+#define  MCI_REGISTER_ADDRESS_BYTE0     0x60
+#define  MCI_REGISTER_ADDRESS_BYTE1     0x68
+
+#define  MCI_REGISTER_MODE              0x70
+
+/* Read and write modes for polaris ITVC */
+#define  MCI_MODE_REGISTER_READ         0x000
+#define  MCI_MODE_REGISTER_WRITE        0x100
+#define  MCI_MODE_MEMORY_READ           0x000
+#define  MCI_MODE_MEMORY_WRITE          0x4000
+
+static unsigned int mpegbufs = 8;
+module_param(mpegbufs, int, 0644);
+MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
+static unsigned int mpeglines = 128;
+module_param(mpeglines, int, 0644);
+MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
+static unsigned int mpeglinesize = 512;
+module_param(mpeglinesize, int, 0644);
+MODULE_PARM_DESC(mpeglinesize,
+        "number of bytes in each line of an MPEG buffer, range 512-1024");
+
+static unsigned int v4l_debug = 1;
+module_param(v4l_debug, int, 0644);
+MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
+struct cx231xx_dmaqueue *dma_qq;
+#define dprintk(level, fmt, arg...)\
+        do { if (v4l_debug >= level) \
+                printk(KERN_INFO "%s: " fmt, \
+                (dev) ? dev->name : "cx231xx[?]", ## arg); \
+        } while (0)
+
+static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
+        {
+                .name      = "NTSC-M",
+                .id        = V4L2_STD_NTSC_M,
+        }, {
+                .name      = "NTSC-JP",
+                .id        = V4L2_STD_NTSC_M_JP,
+        }, {
+                .name      = "PAL-BG",
+                .id        = V4L2_STD_PAL_BG,
+        }, {
+                .name      = "PAL-DK",
+                .id        = V4L2_STD_PAL_DK,
+        }, {
+                .name      = "PAL-I",
+                .id        = V4L2_STD_PAL_I,
+        }, {
+                .name      = "PAL-M",
+                .id        = V4L2_STD_PAL_M,
+        }, {
+                .name      = "PAL-N",
+                .id        = V4L2_STD_PAL_N,
+        }, {
+                .name      = "PAL-Nc",
+                .id        = V4L2_STD_PAL_Nc,
+        }, {
+                .name      = "PAL-60",
+                .id        = V4L2_STD_PAL_60,
+        }, {
+                .name      = "SECAM-L",
+                .id        = V4L2_STD_SECAM_L,
+        }, {
+                .name      = "SECAM-DK",
+                .id        = V4L2_STD_SECAM_DK,
+        }
+};
+
+/* ------------------------------------------------------------------ */
+enum cx231xx_capture_type {
+        CX231xx_MPEG_CAPTURE,
+        CX231xx_RAW_CAPTURE,
+        CX231xx_RAW_PASSTHRU_CAPTURE
+};
+enum cx231xx_capture_bits {
+        CX231xx_RAW_BITS_NONE             = 0x00,
+        CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
+        CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
+        CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
+        CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
+        CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
+};
+enum cx231xx_capture_end {
+        CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
+        CX231xx_END_NOW, /* stop immediately, no irq */
+};
+enum cx231xx_framerate {
+        CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
+        CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
+};
+enum cx231xx_stream_port {
+        CX231xx_OUTPUT_PORT_MEMORY,
+        CX231xx_OUTPUT_PORT_STREAMING,
+        CX231xx_OUTPUT_PORT_SERIAL
+};
+enum cx231xx_data_xfer_status {
+        CX231xx_MORE_BUFFERS_FOLLOW,
+        CX231xx_LAST_BUFFER,
+};
+enum cx231xx_picture_mask {
+        CX231xx_PICTURE_MASK_NONE,
+        CX231xx_PICTURE_MASK_I_FRAMES,
+        CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
+        CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
+};
+enum cx231xx_vbi_mode_bits {
+        CX231xx_VBI_BITS_SLICED,
+        CX231xx_VBI_BITS_RAW,
+};
+enum cx231xx_vbi_insertion_bits {
+        CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
+        CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
+        CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
+        CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
+        CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
+};
+enum cx231xx_dma_unit {
+        CX231xx_DMA_BYTES,
+        CX231xx_DMA_FRAMES,
+};
+enum cx231xx_dma_transfer_status_bits {
+        CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
+        CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
+        CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
+};
+enum cx231xx_pause {
+        CX231xx_PAUSE_ENCODING,
+        CX231xx_RESUME_ENCODING,
+};
+enum cx231xx_copyright {
+        CX231xx_COPYRIGHT_OFF,
+        CX231xx_COPYRIGHT_ON,
+};
+enum cx231xx_notification_type {
+        CX231xx_NOTIFICATION_REFRESH,
+};
+enum cx231xx_notification_status {
+        CX231xx_NOTIFICATION_OFF,
+        CX231xx_NOTIFICATION_ON,
+};
+enum cx231xx_notification_mailbox {
+        CX231xx_NOTIFICATION_NO_MAILBOX = -1,
+};
+enum cx231xx_field1_lines {
+        CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
+        CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
+        CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
+};
+enum cx231xx_field2_lines {
+        CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
+        CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
+        CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
+};
+enum cx231xx_custom_data_type {
+        CX231xx_CUSTOM_EXTENSION_USR_DATA,
+        CX231xx_CUSTOM_PRIVATE_PACKET,
+};
+enum cx231xx_mute {
+        CX231xx_UNMUTE,
+        CX231xx_MUTE,
+};
+enum cx231xx_mute_video_mask {
+        CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
+        CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
+        CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
+};
+enum cx231xx_mute_video_shift {
+        CX231xx_MUTE_VIDEO_V_SHIFT = 8,
+        CX231xx_MUTE_VIDEO_U_SHIFT = 16,
+        CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
+};
+
+/* defines below are from ivtv-driver.h */
+#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
+
+/* Firmware API commands */
+#define IVTV_API_STD_TIMEOUT 500
+
+/* Registers */
+/* IVTV_REG_OFFSET */
+#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
+#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
+#define IVTV_REG_SPU (0x9050)
+#define IVTV_REG_HW_BLOCKS (0x9054)
+#define IVTV_REG_VPU (0x9058)
+#define IVTV_REG_APU (0xA064)
+
+/*
+ * Bit definitions for MC417_RWD and MC417_OEN registers
+ *
+ * bits 31-16
+ *+-----------+
+ *| Reserved  |
+ *|+-----------+
+ *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
+ *|+-------+-------+-------+-------+-------+-------+-------+-------+
+ *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
+ *|+-------+-------+-------+-------+-------+-------+-------+-------+
+ *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
+ *|+-------+-------+-------+-------+-------+-------+-------+-------+
+ *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
+ *|+-------+-------+-------+-------+-------+-------+-------+-------+
+ */
+#define MC417_MIWR      0x8000
+#define MC417_MIRD      0x4000
+#define MC417_MICS      0x2000
+#define MC417_MIRDY     0x1000
+#define MC417_MIADDR    0x0F00
+#define MC417_MIDATA    0x00FF
+
+
+/* Bit definitions for MC417_CTL register ****
+ *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
+ *+--------+-------------+--------+--------------+------------+
+ *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
+ *+--------+-------------+--------+--------------+------------+
+ */
+#define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
+#define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
+#define MC417_UART_GPIO_EN      0x00000001
+
+/* Values for speed control */
+#define MC417_SPD_CTL_SLOW      0x1
+#define MC417_SPD_CTL_MEDIUM    0x0
+#define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
+
+/* Values for GPIO select */
+#define MC417_GPIO_SEL_GPIO3    0x3
+#define MC417_GPIO_SEL_GPIO2    0x2
+#define MC417_GPIO_SEL_GPIO1    0x1
+#define MC417_GPIO_SEL_GPIO0    0x0
+
+
+#define CX23417_GPIO_MASK 0xFC0003FF
+static int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
+{
+        int status = 0;
+        u32 _gpio_direction = 0;
+
+        _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
+        _gpio_direction = _gpio_direction|gpio_direction;
+        status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
+                         (u8 *)&value, 4, 0, 0);
+        return status;
+}
+static int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
+{
+        int status = 0;
+        u32 _gpio_direction = 0;
+
+        _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
+        _gpio_direction = _gpio_direction|gpio_direction;
+
+        status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
+                 (u8 *)pValue, 4, 0, 1);
+        return status;
+}
+
+static int waitForMciComplete(struct cx231xx *dev)
+{
+        u32 gpio;
+        u32 gpio_driection = 0;
+        u8 count = 0;
+        getITVCReg(dev, gpio_driection, &gpio);
+
+        while (!(gpio&0x020000)) {
+                msleep(10);
+
+                getITVCReg(dev, gpio_driection, &gpio);
+
+                if (count++ > 100) {
+                        dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
+                        return -1;
+                }
+        }
+        return 0;
+}
+
+static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
+{
+        u32 temp;
+        int status = 0;
+
+        temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
+        temp = temp<<10;
+        status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        if (status < 0)
+                return status;
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 1;*/
+        temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 2;*/
+        temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 3;*/
+        temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write address byte 0;*/
+        temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write address byte 1;*/
+        temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*Write that the mode is write.*/
+        temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        return waitForMciComplete(dev);
+}
+
+static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
+{
+        /*write address byte 0;*/
+        u32 temp;
+        u32 return_value = 0;
+        int ret = 0;
+
+        temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
+        temp = temp << 10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp | ((0x05) << 10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write address byte 1;*/
+        temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
+        temp = temp << 10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp | ((0x05) << 10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write that the mode is read;*/
+        temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
+        temp = temp << 10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp | ((0x05) << 10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*wait for the MIRDY line to be asserted ,
+        signalling that the read is done;*/
+        ret = waitForMciComplete(dev);
+
+        /*switch the DATA- GPIO to input mode;*/
+
+        /*Read data byte 0;*/
+        temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp & 0x03FC0000) >> 18);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
+
+        /* Read data byte 1;*/
+        temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+
+        return_value |= ((temp & 0x03FC0000) >> 10);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
+
+        /*Read data byte 2;*/
+        temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp & 0x03FC0000) >> 2);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
+
+        /*Read data byte 3;*/
+        temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp & 0x03FC0000) << 6);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
+
+        *value  = return_value;
+
+
+        return ret;
+}
+
+static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
+{
+        /*write data byte 0;*/
+
+        u32 temp;
+        int ret = 0;
+
+        temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8);
+        temp = temp << 10;
+        ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        if (ret < 0)
+                return ret;
+        temp = temp | ((0x05) << 10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 1;*/
+        temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
+        temp = temp << 10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp | ((0x05) << 10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 2;*/
+        temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write data byte 3;*/
+        temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /* write address byte 2;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
+                ((address & 0x003F0000)>>8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /* write address byte 1;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /* write address byte 0;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*wait for MIRDY line;*/
+        waitForMciComplete(dev);
+
+        return 0;
+}
+
+static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
+{
+        u32 temp = 0;
+        u32 return_value = 0;
+        int ret = 0;
+
+        /*write address byte 2;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
+                ((address & 0x003F0000)>>8);
+        temp = temp<<10;
+        ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        if (ret < 0)
+                return ret;
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write address byte 1*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*write address byte 0*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
+        temp = temp<<10;
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+        temp = temp|((0x05)<<10);
+        setITVCReg(dev, ITVC_WRITE_DIR, temp);
+
+        /*Wait for MIRDY line*/
+        ret = waitForMciComplete(dev);
+
+
+        /*Read data byte 3;*/
+        temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp&0x03FC0000)<<6);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
+
+        /*Read data byte 2;*/
+        temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp&0x03FC0000)>>2);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
+
+        /* Read data byte 1;*/
+        temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp&0x03FC0000)>>10);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
+
+        /*Read data byte 0;*/
+        temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
+        setITVCReg(dev, ITVC_READ_DIR, temp);
+        getITVCReg(dev, ITVC_READ_DIR, &temp);
+        return_value |= ((temp&0x03FC0000)>>18);
+        setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
+
+        *value  = return_value;
+        return ret;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* MPEG encoder API */
+static char *cmd_to_str(int cmd)
+{
+        switch (cmd) {
+        case CX2341X_ENC_PING_FW:
+                return  "PING_FW";
+        case CX2341X_ENC_START_CAPTURE:
+                return  "START_CAPTURE";
+        case CX2341X_ENC_STOP_CAPTURE:
+                return  "STOP_CAPTURE";
+        case CX2341X_ENC_SET_AUDIO_ID:
+                return  "SET_AUDIO_ID";
+        case CX2341X_ENC_SET_VIDEO_ID:
+                return  "SET_VIDEO_ID";
+        case CX2341X_ENC_SET_PCR_ID:
+                return  "SET_PCR_PID";
+        case CX2341X_ENC_SET_FRAME_RATE:
+                return  "SET_FRAME_RATE";
+        case CX2341X_ENC_SET_FRAME_SIZE:
+                return  "SET_FRAME_SIZE";
+        case CX2341X_ENC_SET_BIT_RATE:
+                return  "SET_BIT_RATE";
+        case CX2341X_ENC_SET_GOP_PROPERTIES:
+                return  "SET_GOP_PROPERTIES";
+        case CX2341X_ENC_SET_ASPECT_RATIO:
+                return  "SET_ASPECT_RATIO";
+        case CX2341X_ENC_SET_DNR_FILTER_MODE:
+                return  "SET_DNR_FILTER_PROPS";
+        case CX2341X_ENC_SET_DNR_FILTER_PROPS:
+                return  "SET_DNR_FILTER_PROPS";
+        case CX2341X_ENC_SET_CORING_LEVELS:
+                return  "SET_CORING_LEVELS";
+        case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
+                return  "SET_SPATIAL_FILTER_TYPE";
+        case CX2341X_ENC_SET_VBI_LINE:
+                return  "SET_VBI_LINE";
+        case CX2341X_ENC_SET_STREAM_TYPE:
+                return  "SET_STREAM_TYPE";
+        case CX2341X_ENC_SET_OUTPUT_PORT:
+                return  "SET_OUTPUT_PORT";
+        case CX2341X_ENC_SET_AUDIO_PROPERTIES:
+                return  "SET_AUDIO_PROPERTIES";
+        case CX2341X_ENC_HALT_FW:
+                return  "HALT_FW";
+        case CX2341X_ENC_GET_VERSION:
+                return  "GET_VERSION";
+        case CX2341X_ENC_SET_GOP_CLOSURE:
+                return  "SET_GOP_CLOSURE";
+        case CX2341X_ENC_GET_SEQ_END:
+                return  "GET_SEQ_END";
+        case CX2341X_ENC_SET_PGM_INDEX_INFO:
+                return  "SET_PGM_INDEX_INFO";
+        case CX2341X_ENC_SET_VBI_CONFIG:
+                return  "SET_VBI_CONFIG";
+        case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
+                return  "SET_DMA_BLOCK_SIZE";
+        case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
+                return  "GET_PREV_DMA_INFO_MB_10";
+        case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
+                return  "GET_PREV_DMA_INFO_MB_9";
+        case CX2341X_ENC_SCHED_DMA_TO_HOST:
+                return  "SCHED_DMA_TO_HOST";
+        case CX2341X_ENC_INITIALIZE_INPUT:
+                return  "INITIALIZE_INPUT";
+        case CX2341X_ENC_SET_FRAME_DROP_RATE:
+                return  "SET_FRAME_DROP_RATE";
+        case CX2341X_ENC_PAUSE_ENCODER:
+                return  "PAUSE_ENCODER";
+        case CX2341X_ENC_REFRESH_INPUT:
+                return  "REFRESH_INPUT";
+        case CX2341X_ENC_SET_COPYRIGHT:
+                return  "SET_COPYRIGHT";
+        case CX2341X_ENC_SET_EVENT_NOTIFICATION:
+                return  "SET_EVENT_NOTIFICATION";
+        case CX2341X_ENC_SET_NUM_VSYNC_LINES:
+                return  "SET_NUM_VSYNC_LINES";
+        case CX2341X_ENC_SET_PLACEHOLDER:
+                return  "SET_PLACEHOLDER";
+        case CX2341X_ENC_MUTE_VIDEO:
+                return  "MUTE_VIDEO";
+        case CX2341X_ENC_MUTE_AUDIO:
+                return  "MUTE_AUDIO";
+        case CX2341X_ENC_MISC:
+                return  "MISC";
+        default:
+                return "UNKNOWN";
+        }
+}
+
+static int cx231xx_mbox_func(void *priv,
+                             u32 command,
+                             int in,
+                             int out,
+                             u32 data[CX2341X_MBOX_MAX_DATA])
+{
+        struct cx231xx *dev = priv;
+        unsigned long timeout;
+        u32 value, flag, retval = 0;
+        int i;
+
+        dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
+                cmd_to_str(command));
+
+        /* this may not be 100% safe if we can't read any memory location
+           without side effects */
+        mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
+        if (value != 0x12345678) {
+                dprintk(3,
+                        "Firmware and/or mailbox pointer not initialized "
+                        "or corrupted, signature = 0x%x, cmd = %s\n", value,
+                        cmd_to_str(command));
+                return -1;
+        }
+
+        /* This read looks at 32 bits, but flag is only 8 bits.
+         * Seems we also bail if CMD or TIMEOUT bytes are set???
+         */
+        mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
+        if (flag) {
+                dprintk(3, "ERROR: Mailbox appears to be in use "
+                        "(%x), cmd = %s\n", flag, cmd_to_str(command));
+                return -1;
+        }
+
+        flag |= 1; /* tell 'em we're working on it */
+        mc417_memory_write(dev, dev->cx23417_mailbox, flag);
+
+        /* write command + args + fill remaining with zeros */
+        /* command code */
+        mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
+        mc417_memory_write(dev, dev->cx23417_mailbox + 3,
+                IVTV_API_STD_TIMEOUT); /* timeout */
+        for (i = 0; i < in; i++) {
+                mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
+                dprintk(3, "API Input %d = %d\n", i, data[i]);
+        }
+        for (; i < CX2341X_MBOX_MAX_DATA; i++)
+                mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
+
+        flag |= 3; /* tell 'em we're done writing */
+        mc417_memory_write(dev, dev->cx23417_mailbox, flag);
+
+        /* wait for firmware to handle the API command */
+        timeout = jiffies + msecs_to_jiffies(10);
+        for (;;) {
+                mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
+                if (0 != (flag & 4))
+                        break;
+                if (time_after(jiffies, timeout)) {
+                        dprintk(3, "ERROR: API Mailbox timeout\n");
+                        return -1;
+                }
+                udelay(10);
+        }
+
+        /* read output values */
+        for (i = 0; i < out; i++) {
+                mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
+                dprintk(3, "API Output %d = %d\n", i, data[i]);
+        }
+
+        mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
+        dprintk(3, "API result = %d\n", retval);
+
+        flag = 0;
+        mc417_memory_write(dev, dev->cx23417_mailbox, flag);
+
+        return retval;
+}
+
+/* We don't need to call the API often, so using just one
+ * mailbox will probably suffice
+ */
+static int cx231xx_api_cmd(struct cx231xx *dev,
+                           u32 command,
+                           u32 inputcnt,
+                           u32 outputcnt,
+                           ...)
+{
+        u32 data[CX2341X_MBOX_MAX_DATA];
+        va_list vargs;
+        int i, err;
+
+        dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
+
+        va_start(vargs, outputcnt);
+        for (i = 0; i < inputcnt; i++)
+                data[i] = va_arg(vargs, int);
+
+        err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
+        for (i = 0; i < outputcnt; i++) {
+                int *vptr = va_arg(vargs, int *);
+                *vptr = data[i];
+        }
+        va_end(vargs);
+
+        return err;
+}
+
+static int cx231xx_find_mailbox(struct cx231xx *dev)
+{
+        u32 signature[4] = {
+                0x12345678, 0x34567812, 0x56781234, 0x78123456
+        };
+        int signaturecnt = 0;
+        u32 value;
+        int i;
+        int ret = 0;
+
+        dprintk(2, "%s()\n", __func__);
+
+        for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
+                ret = mc417_memory_read(dev, i, &value);
+                if (ret < 0)
+                        return ret;
+                if (value == signature[signaturecnt])
+                        signaturecnt++;
+                else
+                        signaturecnt = 0;
+                if (4 == signaturecnt) {
+                        dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
+                        return i+1;
+                }
+        }
+        dprintk(3, "Mailbox signature values not found!\n");
+        return -1;
+}
+
+static void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
+                u32 *p_fw_image)
+{
+
+        u32 temp = 0;
+        int i = 0;
+
+        temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /*write data byte 1;*/
+        temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /*write data byte 2;*/
+        temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /*write data byte 3;*/
+        temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /* write address byte 2;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
+                ((address & 0x003F0000)>>8);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /* write address byte 1;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        /* write address byte 0;*/
+        temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
+        temp = temp<<10;
+        *p_fw_image = temp;
+        p_fw_image++;
+        temp = temp|((0x05)<<10);
+        *p_fw_image = temp;
+        p_fw_image++;
+
+        for (i = 0; i < 6; i++) {
+                *p_fw_image = 0xFFFFFFFF;
+                p_fw_image++;
+        }
+}
+
+
+static int cx231xx_load_firmware(struct cx231xx *dev)
+{
+        static const unsigned char magic[8] = {
+                0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
+        };
+        const struct firmware *firmware;
+        int i, retval = 0;
+        u32 value = 0;
+        u32 gpio_output = 0;
+        /*u32 checksum = 0;*/
+        /*u32 *dataptr;*/
+        u32 transfer_size = 0;
+        u32 fw_data = 0;
+        u32 address = 0;
+        /*u32 current_fw[800];*/
+        u32 *p_current_fw, *p_fw;
+        u32 *p_fw_data;
+        int frame = 0;
+        u16 _buffer_size = 4096;
+        u8 *p_buffer;
+
+        p_current_fw = vmalloc(1884180 * 4);
+        p_fw = p_current_fw;
+        if (p_current_fw == NULL) {
+                dprintk(2, "FAIL!!!\n");
+                return -1;
+        }
+
+        p_buffer = vmalloc(4096);
+        if (p_buffer == NULL) {
+                dprintk(2, "FAIL!!!\n");
+                return -1;
+        }
+
+        dprintk(2, "%s()\n", __func__);
+
+        /* Save GPIO settings before reset of APU */
+        retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
+        retval |= mc417_memory_read(dev, 0x900C, &value);
+
+        retval  = mc417_register_write(dev,
+                IVTV_REG_VPU, 0xFFFFFFED);
+        retval |= mc417_register_write(dev,
+                IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
+        retval |= mc417_register_write(dev,
+                IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
+        retval |= mc417_register_write(dev,
+                IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
+        retval |= mc417_register_write(dev,
+                IVTV_REG_APU, 0);
+
+        if (retval != 0) {
+                printk(KERN_ERR "%s: Error with mc417_register_write\n",
+                        __func__);
+                return -1;
+        }
+
+        retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
+                                  &dev->udev->dev);
+
+        if (retval != 0) {
+                printk(KERN_ERR
+                        "ERROR: Hotplug firmware request failed (%s).\n",
+                        CX231xx_FIRM_IMAGE_NAME);
+                printk(KERN_ERR "Please fix your hotplug setup, the board will "
+                        "not work without firmware loaded!\n");
+                return -1;
+        }
+
+        if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
+                printk(KERN_ERR "ERROR: Firmware size mismatch "
+                        "(have %zd, expected %d)\n",
+                        firmware->size, CX231xx_FIRM_IMAGE_SIZE);
+                release_firmware(firmware);
+                return -1;
+        }
+
+        if (0 != memcmp(firmware->data, magic, 8)) {
+                printk(KERN_ERR
+                        "ERROR: Firmware magic mismatch, wrong file?\n");
+                release_firmware(firmware);
+                return -1;
+        }
+
+        initGPIO(dev);
+
+        /* transfer to the chip */
+        dprintk(2, "Loading firmware to GPIO...\n");
+        p_fw_data = (u32 *)firmware->data;
+        dprintk(2, "firmware->size=%zd\n", firmware->size);
+        for (transfer_size = 0; transfer_size < firmware->size;
+                 transfer_size += 4) {
+                fw_data = *p_fw_data;
+
+                 mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
+                address = address + 1;
+                p_current_fw += 20;
+                p_fw_data += 1;
+        }
+
+        /*download the firmware by ep5-out*/
+
+        for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
+             frame++) {
+                for (i = 0; i < _buffer_size; i++) {
+                        *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
+                        i++;
+                        *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
+                        i++;
+                        *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
+                        i++;
+                        *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
+                }
+                cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
+        }
+
+        p_current_fw = p_fw;
+        vfree(p_current_fw);
+        p_current_fw = NULL;
+        uninitGPIO(dev);
+        release_firmware(firmware);
+        dprintk(1, "Firmware upload successful.\n");
+
+        retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
+                IVTV_CMD_HW_BLOCKS_RST);
+        if (retval < 0) {
+                printk(KERN_ERR "%s: Error with mc417_register_write\n",
+                        __func__);
+                return retval;
+        }
+        /* F/W power up disturbs the GPIOs, restore state */
+        retval |= mc417_register_write(dev, 0x9020, gpio_output);
+        retval |= mc417_register_write(dev, 0x900C, value);
+
+        retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
+        retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
+
+        if (retval < 0) {
+                printk(KERN_ERR "%s: Error with mc417_register_write\n",
+                        __func__);
+                return retval;
+        }
+        return 0;
+}
+
+static void cx231xx_417_check_encoder(struct cx231xx *dev)
+{
+        u32 status, seq;
+
+        status = 0;
+        seq = 0;
+        cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
+        dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
+}
+
+static void cx231xx_codec_settings(struct cx231xx *dev)
+{
+        dprintk(1, "%s()\n", __func__);
+
+        /* assign frame size */
+        cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
+                                dev->ts1.height, dev->ts1.width);
+
+        dev->mpeg_params.width = dev->ts1.width;
+        dev->mpeg_params.height = dev->ts1.height;
+
+        cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
+
+        cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
+        cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
+}
+
+static int cx231xx_initialize_codec(struct cx231xx *dev)
+{
+        int version;
+        int retval;
+        u32 i;
+        u32 val = 0;
+
+        dprintk(1, "%s()\n", __func__);
+        cx231xx_disable656(dev);
+        retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
+        if (retval < 0) {
+                dprintk(2, "%s() PING OK\n", __func__);
+                retval = cx231xx_load_firmware(dev);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s() f/w load failed\n", __func__);
+                        return retval;
+                }
+                retval = cx231xx_find_mailbox(dev);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s() mailbox < 0, error\n",
+                                __func__);
+                        return -1;
+                }
+                dev->cx23417_mailbox = retval;
+                retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
+                if (retval < 0) {
+                        printk(KERN_ERR
+                                "ERROR: cx23417 firmware ping failed!\n");
+                        return -1;
+                }
+                retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
+                        &version);
+                if (retval < 0) {
+                        printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
+                                "version failed!\n");
+                        return -1;
+                }
+                dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
+                msleep(200);
+        }
+
+        for (i = 0; i < 1; i++) {
+                retval = mc417_register_read(dev, 0x20f8, &val);
+                dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
+                                 val);
+                if (retval < 0)
+                        return retval;
+        }
+
+        cx231xx_enable656(dev);
+                        /* stop mpeg capture */
+                        cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
+                                 3, 0, 1, 3, 4);
+
+        cx231xx_codec_settings(dev);
+        msleep(60);
+
+/*      cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
+                CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
+        cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
+                CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0);
+*/
+
+#if 0
+        /* TODO */
+        u32 data[7];
+
+        /* Setup to capture VBI */
+        data[0] = 0x0001BD00;
+        data[1] = 1;          /* frames per interrupt */
+        data[2] = 4;          /* total bufs */
+        data[3] = 0x91559155; /* start codes */
+        data[4] = 0x206080C0; /* stop codes */
+        data[5] = 6;          /* lines */
+        data[6] = 64;         /* BPL */
+
+        cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
+                data[2], data[3], data[4], data[5], data[6]);
+
+        for (i = 2; i <= 24; i++) {
+                int valid;
+
+                valid = ((i >= 19) && (i <= 21));
+                cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
+                                valid, 0 , 0, 0);
+                cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
+                                i | 0x80000000, valid, 0, 0, 0);
+        }
+#endif
+/*      cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
+        msleep(60);
+*/
+        /* initialize the video input */
+        retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
+        if (retval < 0)
+                return retval;
+        msleep(60);
+
+        /* Enable VIP style pixel invalidation so we work with scaled mode */
+        mc417_memory_write(dev, 2120, 0x00000080);
+
+        /* start capturing to the host interface */
+        retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
+                CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
+        if (retval < 0)
+                return retval;
+        msleep(10);
+
+        for (i = 0; i < 1; i++) {
+                mc417_register_read(dev, 0x20f8, &val);
+        dprintk(3, "***VIM Capture Lines =%d ***\n", val);
+        }
+
+        return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+static int bb_buf_setup(struct videobuf_queue *q,
+        unsigned int *count, unsigned int *size)
+{
+        struct cx231xx_fh *fh = q->priv_data;
+
+        fh->dev->ts1.ts_packet_size  = mpeglinesize;
+        fh->dev->ts1.ts_packet_count = mpeglines;
+
+        *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
+        *count = mpegbufs;
+
+        return 0;
+}
+static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        unsigned long flags = 0;
+
+        if (in_interrupt())
+                BUG();
+
+        spin_lock_irqsave(&dev->video_mode.slock, flags);
+        if (dev->USE_ISO) {
+                if (dev->video_mode.isoc_ctl.buf == buf)
+                        dev->video_mode.isoc_ctl.buf = NULL;
+        } else {
+                if (dev->video_mode.bulk_ctl.buf == buf)
+                        dev->video_mode.bulk_ctl.buf = NULL;
+        }
+        spin_unlock_irqrestore(&dev->video_mode.slock, flags);
+        videobuf_waiton(vq, &buf->vb, 0, 0);
+        videobuf_vmalloc_free(&buf->vb);
+        buf->vb.state = VIDEOBUF_NEEDS_INIT;
+}
+
+static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
+                struct cx231xx_dmaqueue *dma_q)
+{
+                void *vbuf;
+                struct cx231xx_buffer *buf;
+                u32 tail_data = 0;
+                char *p_data;
+
+                if (dma_q->mpeg_buffer_done == 0) {
+                        if (list_empty(&dma_q->active))
+                                return;
+
+                        buf = list_entry(dma_q->active.next,
+                                        struct cx231xx_buffer, vb.queue);
+                        dev->video_mode.isoc_ctl.buf = buf;
+                        dma_q->mpeg_buffer_done = 1;
+                }
+                /* Fill buffer */
+                buf = dev->video_mode.isoc_ctl.buf;
+                vbuf = videobuf_to_vmalloc(&buf->vb);
+
+                if ((dma_q->mpeg_buffer_completed+len) <
+                   mpeglines*mpeglinesize) {
+                        if (dma_q->add_ps_package_head ==
+                           CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
+                                memcpy(vbuf+dma_q->mpeg_buffer_completed,
+                                       dma_q->ps_head, 3);
+                                dma_q->mpeg_buffer_completed =
+                                  dma_q->mpeg_buffer_completed + 3;
+                                dma_q->add_ps_package_head =
+                                  CX231XX_NONEED_PS_PACKAGE_HEAD;
+                        }
+                        memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
+                        dma_q->mpeg_buffer_completed =
+                          dma_q->mpeg_buffer_completed + len;
+                } else {
+                        dma_q->mpeg_buffer_done = 0;
+
+                        tail_data =
+                          mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
+                        memcpy(vbuf+dma_q->mpeg_buffer_completed,
+                               data, tail_data);
+
+                        buf->vb.state = VIDEOBUF_DONE;
+                        buf->vb.field_count++;
+                        do_gettimeofday(&buf->vb.ts);
+                        list_del(&buf->vb.queue);
+                        wake_up(&buf->vb.done);
+                        dma_q->mpeg_buffer_completed = 0;
+
+                        if (len - tail_data > 0) {
+                                p_data = data + tail_data;
+                                dma_q->left_data_count = len - tail_data;
+                                memcpy(dma_q->p_left_data,
+                                       p_data, len - tail_data);
+                        }
+
+                }
+
+            return;
+}
+
+static void buffer_filled(char *data, int len, struct urb *urb,
+                struct cx231xx_dmaqueue *dma_q)
+{
+                void *vbuf;
+                struct cx231xx_buffer *buf;
+
+                if (list_empty(&dma_q->active))
+                        return;
+
+
+                buf = list_entry(dma_q->active.next,
+                                 struct cx231xx_buffer, vb.queue);
+
+
+                /* Fill buffer */
+                vbuf = videobuf_to_vmalloc(&buf->vb);
+                memcpy(vbuf, data, len);
+                buf->vb.state = VIDEOBUF_DONE;
+                buf->vb.field_count++;
+                do_gettimeofday(&buf->vb.ts);
+                list_del(&buf->vb.queue);
+                wake_up(&buf->vb.done);
+
+            return;
+}
+static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        unsigned char *p_buffer;
+        u32 buffer_size = 0;
+        u32 i = 0;
+
+        for (i = 0; i < urb->number_of_packets; i++) {
+                if (dma_q->left_data_count > 0) {
+                        buffer_copy(dev, dma_q->p_left_data,
+                                    dma_q->left_data_count, urb, dma_q);
+                        dma_q->mpeg_buffer_completed = dma_q->left_data_count;
+                        dma_q->left_data_count = 0;
+                }
+
+                p_buffer = urb->transfer_buffer +
+                                urb->iso_frame_desc[i].offset;
+                buffer_size = urb->iso_frame_desc[i].actual_length;
+
+                if (buffer_size > 0)
+                        buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
+        }
+
+        return 0;
+}
+static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
+{
+
+        /*char *outp;*/
+        /*struct cx231xx_buffer *buf;*/
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        unsigned char *p_buffer, *buffer;
+        u32 buffer_size = 0;
+
+        p_buffer = urb->transfer_buffer;
+        buffer_size = urb->actual_length;
+
+        buffer = kmalloc(buffer_size, GFP_ATOMIC);
+
+        memcpy(buffer, dma_q->ps_head, 3);
+        memcpy(buffer+3, p_buffer, buffer_size-3);
+        memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
+
+        p_buffer = buffer;
+        buffer_filled(p_buffer, buffer_size, urb, dma_q);
+
+        kfree(buffer);
+        return 0;
+}
+
+static int bb_buf_prepare(struct videobuf_queue *q,
+        struct videobuf_buffer *vb, enum v4l2_field field)
+{
+        struct cx231xx_fh *fh = q->priv_data;
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx *dev = fh->dev;
+        int rc = 0, urb_init = 0;
+        int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
+
+        dma_qq = &dev->video_mode.vidq;
+
+        if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
+                return -EINVAL;
+        buf->vb.width = fh->dev->ts1.ts_packet_size;
+        buf->vb.height = fh->dev->ts1.ts_packet_count;
+        buf->vb.size = size;
+        buf->vb.field = field;
+
+        if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
+                rc = videobuf_iolock(q, &buf->vb, NULL);
+                if (rc < 0)
+                        goto fail;
+        }
+
+        if (dev->USE_ISO) {
+                if (!dev->video_mode.isoc_ctl.num_bufs)
+                        urb_init = 1;
+        } else {
+                if (!dev->video_mode.bulk_ctl.num_bufs)
+                        urb_init = 1;
+        }
+        /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
+                urb_init, dev->video_mode.max_pkt_size);*/
+        dev->mode_tv = 1;
+
+        if (urb_init) {
+                rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+                rc = cx231xx_unmute_audio(dev);
+                if (dev->USE_ISO) {
+                        cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
+                        rc = cx231xx_init_isoc(dev, mpeglines,
+                                       mpegbufs,
+                                       dev->ts1_mode.max_pkt_size,
+                                       cx231xx_isoc_copy);
+                } else {
+                        cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
+                        rc = cx231xx_init_bulk(dev, mpeglines,
+                                       mpegbufs,
+                                       dev->ts1_mode.max_pkt_size,
+                                       cx231xx_bulk_copy);
+                }
+                if (rc < 0)
+                        goto fail;
+        }
+
+        buf->vb.state = VIDEOBUF_PREPARED;
+        return 0;
+
+fail:
+        free_buffer(q, buf);
+        return rc;
+}
+
+static void bb_buf_queue(struct videobuf_queue *q,
+        struct videobuf_buffer *vb)
+{
+        struct cx231xx_fh *fh = q->priv_data;
+
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx *dev = fh->dev;
+        struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
+
+        buf->vb.state = VIDEOBUF_QUEUED;
+        list_add_tail(&buf->vb.queue, &vidq->active);
+
+}
+
+static void bb_buf_release(struct videobuf_queue *q,
+        struct videobuf_buffer *vb)
+{
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        /*struct cx231xx_fh *fh = q->priv_data;*/
+        /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
+
+        free_buffer(q, buf);
+}
+
+static struct videobuf_queue_ops cx231xx_qops = {
+        .buf_setup    = bb_buf_setup,
+        .buf_prepare  = bb_buf_prepare,
+        .buf_queue    = bb_buf_queue,
+        .buf_release  = bb_buf_release,
+};
+
+/* ------------------------------------------------------------------ */
+
+static const u32 *ctrl_classes[] = {
+        cx2341x_mpeg_ctrls,
+        NULL
+};
+
+static int cx231xx_queryctrl(struct cx231xx *dev,
+        struct v4l2_queryctrl *qctrl)
+{
+        qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
+        if (qctrl->id == 0)
+                return -EINVAL;
+
+        /* MPEG V4L2 controls */
+        if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
+                qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
+
+        return 0;
+}
+
+static int cx231xx_querymenu(struct cx231xx *dev,
+        struct v4l2_querymenu *qmenu)
+{
+        struct v4l2_queryctrl qctrl;
+
+        qctrl.id = qmenu->id;
+        cx231xx_queryctrl(dev, &qctrl);
+        return v4l2_ctrl_query_menu(qmenu, &qctrl,
+                cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
+}
+
+static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+
+        *norm = dev->encodernorm.id;
+        return 0;
+}
+static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
+                if (*id & cx231xx_tvnorms[i].id)
+                        break;
+        if (i == ARRAY_SIZE(cx231xx_tvnorms))
+                return -EINVAL;
+        dev->encodernorm = cx231xx_tvnorms[i];
+
+        if (dev->encodernorm.id & 0xb000) {
+                dprintk(3, "encodernorm set to NTSC\n");
+                dev->norm = V4L2_STD_NTSC;
+                dev->ts1.height = 480;
+                dev->mpeg_params.is_50hz = 0;
+        } else {
+                dprintk(3, "encodernorm set to PAL\n");
+                dev->norm = V4L2_STD_PAL_B;
+                dev->ts1.height = 576;
+                dev->mpeg_params.is_50hz = 1;
+        }
+        call_all(dev, core, s_std, dev->norm);
+        /* do mode control overrides */
+        cx231xx_do_mode_ctrl_overrides(dev);
+
+        dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
+        return 0;
+}
+static int vidioc_g_audio(struct file *file, void *fh,
+                                        struct v4l2_audio *a)
+{
+                struct v4l2_audio *vin = a;
+
+                int ret = -EINVAL;
+                if (vin->index > 0)
+                        return ret;
+                strncpy(vin->name, "VideoGrabber Audio", 14);
+                vin->capability = V4L2_AUDCAP_STEREO;
+return 0;
+}
+static int vidioc_enumaudio(struct file *file, void *fh,
+                                        struct v4l2_audio *a)
+{
+                struct v4l2_audio *vin = a;
+
+                int ret = -EINVAL;
+
+                if (vin->index > 0)
+                        return ret;
+                strncpy(vin->name, "VideoGrabber Audio", 14);
+                vin->capability = V4L2_AUDCAP_STEREO;
+
+
+return 0;
+}
+static const char *iname[] = {
+        [CX231XX_VMUX_COMPOSITE1] = "Composite1",
+        [CX231XX_VMUX_SVIDEO]     = "S-Video",
+        [CX231XX_VMUX_TELEVISION] = "Television",
+        [CX231XX_VMUX_CABLE]      = "Cable TV",
+        [CX231XX_VMUX_DVB]        = "DVB",
+        [CX231XX_VMUX_DEBUG]      = "for debug only",
+};
+static int vidioc_enum_input(struct file *file, void *priv,
+                                struct v4l2_input *i)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+        struct cx231xx_input *input;
+        int n;
+        dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
+
+        if (i->index >= 4)
+                return -EINVAL;
+
+
+        input = &cx231xx_boards[dev->model].input[i->index];
+
+        if (input->type == 0)
+                return -EINVAL;
+
+        /* FIXME
+         * strcpy(i->name, input->name); */
+
+        n = i->index;
+        strcpy(i->name, iname[INPUT(n)->type]);
+
+        if (input->type == CX231XX_VMUX_TELEVISION ||
+            input->type == CX231XX_VMUX_CABLE)
+                i->type = V4L2_INPUT_TYPE_TUNER;
+        else
+                i->type  = V4L2_INPUT_TYPE_CAMERA;
+
+
+        return 0;
+}
+
+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
+{
+        *i = 0;
+        return  0;
+}
+
+static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+
+        dprintk(3, "enter vidioc_s_input() i=%d\n", i);
+
+        mutex_lock(&dev->lock);
+
+        video_mux(dev, i);
+
+        mutex_unlock(&dev->lock);
+
+        if (i >= 4)
+                return -EINVAL;
+        dev->input = i;
+        dprintk(3, "exit vidioc_s_input()\n");
+        return 0;
+}
+
+static int vidioc_g_tuner(struct file *file, void *priv,
+                                struct v4l2_tuner *t)
+{
+        return 0;
+}
+
+static int vidioc_s_tuner(struct file *file, void *priv,
+                                struct v4l2_tuner *t)
+{
+        return 0;
+}
+
+static int vidioc_g_frequency(struct file *file, void *priv,
+                                struct v4l2_frequency *f)
+{
+        return 0;
+}
+
+static int vidioc_s_frequency(struct file *file, void *priv,
+                                struct v4l2_frequency *f)
+{
+
+
+        return 0;
+}
+
+static int vidioc_s_ctrl(struct file *file, void *priv,
+                                struct v4l2_control *ctl)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_s_ctrl()\n");
+        /* Update the A/V core */
+        call_all(dev, core, s_ctrl, ctl);
+        dprintk(3, "exit vidioc_s_ctrl()\n");
+        return 0;
+}
+static struct v4l2_capability pvr_capability = {
+        .driver         = "cx231xx",
+        .card           = "VideoGrabber",
+        .bus_info       = "usb",
+        .version        = 1,
+        .capabilities   = (V4L2_CAP_VIDEO_CAPTURE |
+                           V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
+                         V4L2_CAP_STREAMING | V4L2_CAP_READWRITE),
+};
+static int vidioc_querycap(struct file *file, void  *priv,
+                                struct v4l2_capability *cap)
+{
+
+
+
+                memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
+        return 0;
+}
+
+static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
+                                        struct v4l2_fmtdesc *f)
+{
+
+        if (f->index != 0)
+                return -EINVAL;
+
+        strlcpy(f->description, "MPEG", sizeof(f->description));
+        f->pixelformat = V4L2_PIX_FMT_MPEG;
+
+        return 0;
+}
+
+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
+        f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
+        f->fmt.pix.bytesperline = 0;
+        f->fmt.pix.sizeimage    =
+                dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
+        f->fmt.pix.colorspace   = 0;
+        f->fmt.pix.width        = dev->ts1.width;
+        f->fmt.pix.height       = dev->ts1.height;
+        f->fmt.pix.field        = fh->vidq.field;
+        dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
+                dev->ts1.width, dev->ts1.height, fh->vidq.field);
+        dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
+        return 0;
+}
+
+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
+        f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
+        f->fmt.pix.bytesperline = 0;
+        f->fmt.pix.sizeimage    =
+                dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
+        f->fmt.pix.colorspace   = 0;
+        dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
+                dev->ts1.width, dev->ts1.height, fh->vidq.field);
+        dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
+        return 0;
+}
+
+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+
+        return 0;
+}
+
+static int vidioc_reqbufs(struct file *file, void *priv,
+                                struct v4l2_requestbuffers *p)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+
+        return videobuf_reqbufs(&fh->vidq, p);
+}
+
+static int vidioc_querybuf(struct file *file, void *priv,
+                                struct v4l2_buffer *p)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+
+        return videobuf_querybuf(&fh->vidq, p);
+}
+
+static int vidioc_qbuf(struct file *file, void *priv,
+                                struct v4l2_buffer *p)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+
+        return videobuf_qbuf(&fh->vidq, p);
+}
+
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+        struct cx231xx_fh  *fh  = priv;
+
+        return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
+}
+
+
+static int vidioc_streamon(struct file *file, void *priv,
+                                enum v4l2_buf_type i)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_streamon()\n");
+                cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
+                cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+                if (dev->USE_ISO)
+                        cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
+                                       CX231XX_NUM_BUFS,
+                                       dev->video_mode.max_pkt_size,
+                                       cx231xx_isoc_copy);
+                else {
+                        cx231xx_init_bulk(dev, 320,
+                                       5,
+                                       dev->ts1_mode.max_pkt_size,
+                                       cx231xx_bulk_copy);
+                }
+        dprintk(3, "exit vidioc_streamon()\n");
+        return videobuf_streamon(&fh->vidq);
+}
+
+static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+
+        return videobuf_streamoff(&fh->vidq);
+}
+
+static int vidioc_g_ext_ctrls(struct file *file, void *priv,
+                                struct v4l2_ext_controls *f)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_g_ext_ctrls()\n");
+        if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+                return -EINVAL;
+        dprintk(3, "exit vidioc_g_ext_ctrls()\n");
+        return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
+}
+
+static int vidioc_s_ext_ctrls(struct file *file, void *priv,
+                                struct v4l2_ext_controls *f)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        struct cx2341x_mpeg_params p;
+        int err;
+        dprintk(3, "enter vidioc_s_ext_ctrls()\n");
+        if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+                return -EINVAL;
+
+        p = dev->mpeg_params;
+        err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
+        if (err == 0) {
+                err = cx2341x_update(dev, cx231xx_mbox_func,
+                        &dev->mpeg_params, &p);
+                dev->mpeg_params = p;
+        }
+
+        return err;
+
+
+return 0;
+}
+
+static int vidioc_try_ext_ctrls(struct file *file, void *priv,
+                                struct v4l2_ext_controls *f)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        struct cx2341x_mpeg_params p;
+        int err;
+        dprintk(3, "enter vidioc_try_ext_ctrls()\n");
+        if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
+                return -EINVAL;
+
+        p = dev->mpeg_params;
+        err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
+        dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
+        return err;
+}
+
+static int vidioc_log_status(struct file *file, void *priv)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        char name[32 + 2];
+
+        snprintf(name, sizeof(name), "%s/2", dev->name);
+        dprintk(3,
+                "%s/2: ============  START LOG STATUS  ============\n",
+               dev->name);
+        call_all(dev, core, log_status);
+        cx2341x_log_status(&dev->mpeg_params, name);
+        dprintk(3,
+                "%s/2: =============  END LOG STATUS  =============\n",
+               dev->name);
+        return 0;
+}
+
+static int vidioc_querymenu(struct file *file, void *priv,
+                                struct v4l2_querymenu *a)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_querymenu()\n");
+        dprintk(3, "exit vidioc_querymenu()\n");
+        return cx231xx_querymenu(dev, a);
+}
+
+static int vidioc_queryctrl(struct file *file, void *priv,
+                                struct v4l2_queryctrl *c)
+{
+        struct cx231xx_fh  *fh  = priv;
+        struct cx231xx *dev = fh->dev;
+        dprintk(3, "enter vidioc_queryctrl()\n");
+        dprintk(3, "exit vidioc_queryctrl()\n");
+        return cx231xx_queryctrl(dev, c);
+}
+
+static int mpeg_open(struct file *file)
+{
+        int minor = video_devdata(file)->minor;
+        struct cx231xx *h, *dev = NULL;
+        /*struct list_head *list;*/
+        struct cx231xx_fh *fh;
+        /*u32 value = 0;*/
+
+        dprintk(2, "%s()\n", __func__);
+
+        list_for_each_entry(h, &cx231xx_devlist, devlist) {
+                if (h->v4l_device->minor == minor)
+                        dev = h;
+        }
+
+        if (dev == NULL)
+                return -ENODEV;
+
+        mutex_lock(&dev->lock);
+
+        /* allocate + initialize per filehandle data */
+        fh = kzalloc(sizeof(*fh), GFP_KERNEL);
+        if (NULL == fh) {
+                mutex_unlock(&dev->lock);
+                return -ENOMEM;
+        }
+
+        file->private_data = fh;
+        fh->dev      = dev;
+
+
+        videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
+                            NULL, &dev->video_mode.slock,
+                            V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
+                            sizeof(struct cx231xx_buffer), fh, NULL);
+/*
+        videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
+                            &dev->udev->dev, &dev->ts1.slock,
+                            V4L2_BUF_TYPE_VIDEO_CAPTURE,
+                            V4L2_FIELD_INTERLACED,
+                            sizeof(struct cx231xx_buffer),
+                            fh, NULL);
+*/
+
+
+        cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
+        cx231xx_set_gpio_value(dev, 2, 0);
+
+        cx231xx_initialize_codec(dev);
+
+        mutex_unlock(&dev->lock);
+        cx231xx_start_TS1(dev);
+
+        return 0;
+}
+
+static int mpeg_release(struct file *file)
+{
+        struct cx231xx_fh  *fh  = file->private_data;
+        struct cx231xx *dev = fh->dev;
+
+        dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
+
+        if (!dev) {
+                dprintk(3, "abort!!!\n");
+                return 0;
+        }
+
+        mutex_lock(&dev->lock);
+
+        cx231xx_stop_TS1(dev);
+
+                /* do this before setting alternate! */
+                if (dev->USE_ISO)
+                        cx231xx_uninit_isoc(dev);
+                else
+                        cx231xx_uninit_bulk(dev);
+                cx231xx_set_mode(dev, CX231XX_SUSPEND);
+
+                cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
+                                CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
+                                CX231xx_RAW_BITS_NONE);
+
+        /* FIXME: Review this crap */
+        /* Shut device down on last close */
+        if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
+                if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
+                        /* stop mpeg capture */
+
+                        msleep(500);
+                        cx231xx_417_check_encoder(dev);
+
+                }
+        }
+
+        if (fh->vidq.streaming)
+                videobuf_streamoff(&fh->vidq);
+        if (fh->vidq.reading)
+                videobuf_read_stop(&fh->vidq);
+
+        videobuf_mmap_free(&fh->vidq);
+        file->private_data = NULL;
+        kfree(fh);
+        mutex_unlock(&dev->lock);
+        return 0;
+}
+
+static ssize_t mpeg_read(struct file *file, char __user *data,
+        size_t count, loff_t *ppos)
+{
+        struct cx231xx_fh *fh = file->private_data;
+        struct cx231xx *dev = fh->dev;
+
+
+        /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
+        /* Start mpeg encoder on first read. */
+        if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
+                if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
+                        if (cx231xx_initialize_codec(dev) < 0)
+                                return -EINVAL;
+                }
+        }
+
+        return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
+                                    file->f_flags & O_NONBLOCK);
+}
+
+static unsigned int mpeg_poll(struct file *file,
+        struct poll_table_struct *wait)
+{
+        struct cx231xx_fh *fh = file->private_data;
+        /*struct cx231xx *dev = fh->dev;*/
+
+        /*dprintk(2, "%s\n", __func__);*/
+
+        return videobuf_poll_stream(file, &fh->vidq, wait);
+}
+
+static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
+{
+        struct cx231xx_fh *fh = file->private_data;
+        struct cx231xx *dev = fh->dev;
+
+        dprintk(2, "%s()\n", __func__);
+
+        return videobuf_mmap_mapper(&fh->vidq, vma);
+}
+
+static struct v4l2_file_operations mpeg_fops = {
+        .owner         = THIS_MODULE,
+        .open          = mpeg_open,
+        .release       = mpeg_release,
+        .read          = mpeg_read,
+        .poll          = mpeg_poll,
+        .mmap          = mpeg_mmap,
+        .ioctl         = video_ioctl2,
+};
+
+static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
+        .vidioc_s_std            = vidioc_s_std,
+        .vidioc_g_std            = vidioc_g_std,
+        .vidioc_enum_input       = vidioc_enum_input,
+        .vidioc_enumaudio        = vidioc_enumaudio,
+        .vidioc_g_audio          = vidioc_g_audio,
+        .vidioc_g_input          = vidioc_g_input,
+        .vidioc_s_input          = vidioc_s_input,
+        .vidioc_g_tuner          = vidioc_g_tuner,
+        .vidioc_s_tuner          = vidioc_s_tuner,
+        .vidioc_g_frequency      = vidioc_g_frequency,
+        .vidioc_s_frequency      = vidioc_s_frequency,
+        .vidioc_s_ctrl           = vidioc_s_ctrl,
+        .vidioc_querycap         = vidioc_querycap,
+        .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
+        .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
+        .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
+        .vidioc_s_fmt_vid_cap    = vidioc_s_fmt_vid_cap,
+        .vidioc_reqbufs          = vidioc_reqbufs,
+        .vidioc_querybuf         = vidioc_querybuf,
+        .vidioc_qbuf             = vidioc_qbuf,
+        .vidioc_dqbuf            = vidioc_dqbuf,
+        .vidioc_streamon         = vidioc_streamon,
+        .vidioc_streamoff        = vidioc_streamoff,
+        .vidioc_g_ext_ctrls      = vidioc_g_ext_ctrls,
+        .vidioc_s_ext_ctrls      = vidioc_s_ext_ctrls,
+        .vidioc_try_ext_ctrls    = vidioc_try_ext_ctrls,
+        .vidioc_log_status       = vidioc_log_status,
+        .vidioc_querymenu        = vidioc_querymenu,
+        .vidioc_queryctrl        = vidioc_queryctrl,
+/*      .vidioc_g_chip_ident     = cx231xx_g_chip_ident,*/
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+/*      .vidioc_g_register       = cx231xx_g_register,*/
+/*      .vidioc_s_register       = cx231xx_s_register,*/
+#endif
+};
+
+static struct video_device cx231xx_mpeg_template = {
+        .name          = "cx231xx",
+        .fops          = &mpeg_fops,
+        .ioctl_ops     = &mpeg_ioctl_ops,
+        .minor         = -1,
+        .tvnorms       = CX231xx_NORMS,
+        .current_norm  = V4L2_STD_NTSC_M,
+};
+
+void cx231xx_417_unregister(struct cx231xx *dev)
+{
+        dprintk(1, "%s()\n", __func__);
+        dprintk(3, "%s()\n", __func__);
+
+        if (dev->v4l_device) {
+                if (-1 != dev->v4l_device->minor)
+                        video_unregister_device(dev->v4l_device);
+                else
+                        video_device_release(dev->v4l_device);
+                dev->v4l_device = NULL;
+        }
+}
+
+static struct video_device *cx231xx_video_dev_alloc(
+        struct cx231xx *dev,
+        struct usb_device *usbdev,
+        struct video_device *template,
+        char *type)
+{
+        struct video_device *vfd;
+
+        dprintk(1, "%s()\n", __func__);
+        vfd = video_device_alloc();
+        if (NULL == vfd)
+                return NULL;
+        *vfd = *template;
+        vfd->minor = -1;
+        snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
+                type, cx231xx_boards[dev->model].name);
+
+        vfd->v4l2_dev = &dev->v4l2_dev;
+        vfd->release = video_device_release;
+
+        return vfd;
+
+}
+
+int cx231xx_417_register(struct cx231xx *dev)
+{
+        /* FIXME: Port1 hardcoded here */
+        int err = -ENODEV;
+        struct cx231xx_tsport *tsport = &dev->ts1;
+
+        dprintk(1, "%s()\n", __func__);
+
+        /* Set default TV standard */
+        dev->encodernorm = cx231xx_tvnorms[0];
+
+        if (dev->encodernorm.id & V4L2_STD_525_60)
+                tsport->height = 480;
+        else
+                tsport->height = 576;
+
+        tsport->width = 720;
+        cx2341x_fill_defaults(&dev->mpeg_params);
+        dev->norm = V4L2_STD_NTSC;
+
+        dev->mpeg_params.port = CX2341X_PORT_SERIAL;
+
+        /* Allocate and initialize V4L video device */
+        dev->v4l_device = cx231xx_video_dev_alloc(dev,
+                dev->udev, &cx231xx_mpeg_template, "mpeg");
+        err = video_register_device(dev->v4l_device,
+                VFL_TYPE_GRABBER, -1);
+        if (err < 0) {
+                dprintk(3, "%s: can't register mpeg device\n", dev->name);
+                return err;
+        }
+
+        dprintk(3, "%s: registered device video%d [mpeg]\n",
+               dev->name, dev->v4l_device->num);
+
+        return 0;
+}
+
+MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME);
diff --git a/drivers/media/usb/cx231xx/cx231xx-audio.c b/drivers/media/usb/cx231xx/cx231xx-audio.c
new file mode 100644
index 000000000000..b4c99c7270cf
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-audio.c
@@ -0,0 +1,780 @@
+/*
+ *  Conexant Cx231xx audio extension
+ *
+ *  Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+ *       Based on em28xx driver
+ *
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/usb.h>
+#include <linux/init.h>
+#include <linux/sound.h>
+#include <linux/spinlock.h>
+#include <linux/soundcard.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/proc_fs.h>
+#include <linux/module.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/info.h>
+#include <sound/initval.h>
+#include <sound/control.h>
+#include <media/v4l2-common.h>
+#include "cx231xx.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "activates debug info");
+
+#define dprintk(fmt, arg...) do {                                       \
+                if (debug)                                              \
+                        printk(KERN_INFO "cx231xx-audio %s: " fmt,      \
+                                __func__, ##arg);                       \
+        } while (0)
+
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
+
+static int cx231xx_isoc_audio_deinit(struct cx231xx *dev)
+{
+        int i;
+
+        dprintk("Stopping isoc\n");
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                if (dev->adev.urb[i]) {
+                        if (!irqs_disabled())
+                                usb_kill_urb(dev->adev.urb[i]);
+                        else
+                                usb_unlink_urb(dev->adev.urb[i]);
+
+                        usb_free_urb(dev->adev.urb[i]);
+                        dev->adev.urb[i] = NULL;
+
+                        kfree(dev->adev.transfer_buffer[i]);
+                        dev->adev.transfer_buffer[i] = NULL;
+                }
+        }
+
+        return 0;
+}
+
+static int cx231xx_bulk_audio_deinit(struct cx231xx *dev)
+{
+        int i;
+
+        dprintk("Stopping bulk\n");
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                if (dev->adev.urb[i]) {
+                        if (!irqs_disabled())
+                                usb_kill_urb(dev->adev.urb[i]);
+                        else
+                                usb_unlink_urb(dev->adev.urb[i]);
+
+                        usb_free_urb(dev->adev.urb[i]);
+                        dev->adev.urb[i] = NULL;
+
+                        kfree(dev->adev.transfer_buffer[i]);
+                        dev->adev.transfer_buffer[i] = NULL;
+                }
+        }
+
+        return 0;
+}
+
+static void cx231xx_audio_isocirq(struct urb *urb)
+{
+        struct cx231xx *dev = urb->context;
+        int i;
+        unsigned int oldptr;
+        int period_elapsed = 0;
+        int status;
+        unsigned char *cp;
+        unsigned int stride;
+        struct snd_pcm_substream *substream;
+        struct snd_pcm_runtime *runtime;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return;
+
+        switch (urb->status) {
+        case 0:         /* success */
+        case -ETIMEDOUT:        /* NAK */
+                break;
+        case -ECONNRESET:       /* kill */
+        case -ENOENT:
+        case -ESHUTDOWN:
+                return;
+        default:                /* error */
+                dprintk("urb completition error %d.\n", urb->status);
+                break;
+        }
+
+        if (atomic_read(&dev->stream_started) == 0)
+                return;
+
+        if (dev->adev.capture_pcm_substream) {
+                substream = dev->adev.capture_pcm_substream;
+                runtime = substream->runtime;
+                stride = runtime->frame_bits >> 3;
+
+                for (i = 0; i < urb->number_of_packets; i++) {
+                        int length = urb->iso_frame_desc[i].actual_length /
+                                     stride;
+                        cp = (unsigned char *)urb->transfer_buffer +
+                                              urb->iso_frame_desc[i].offset;
+
+                        if (!length)
+                                continue;
+
+                        oldptr = dev->adev.hwptr_done_capture;
+                        if (oldptr + length >= runtime->buffer_size) {
+                                unsigned int cnt;
+
+                                cnt = runtime->buffer_size - oldptr;
+                                memcpy(runtime->dma_area + oldptr * stride, cp,
+                                       cnt * stride);
+                                memcpy(runtime->dma_area, cp + cnt * stride,
+                                       length * stride - cnt * stride);
+                        } else {
+                                memcpy(runtime->dma_area + oldptr * stride, cp,
+                                       length * stride);
+                        }
+
+                        snd_pcm_stream_lock(substream);
+
+                        dev->adev.hwptr_done_capture += length;
+                        if (dev->adev.hwptr_done_capture >=
+                                                runtime->buffer_size)
+                                dev->adev.hwptr_done_capture -=
+                                                runtime->buffer_size;
+
+                        dev->adev.capture_transfer_done += length;
+                        if (dev->adev.capture_transfer_done >=
+                                runtime->period_size) {
+                                dev->adev.capture_transfer_done -=
+                                                runtime->period_size;
+                                period_elapsed = 1;
+                        }
+                        snd_pcm_stream_unlock(substream);
+                }
+                if (period_elapsed)
+                        snd_pcm_period_elapsed(substream);
+        }
+        urb->status = 0;
+
+        status = usb_submit_urb(urb, GFP_ATOMIC);
+        if (status < 0) {
+                cx231xx_errdev("resubmit of audio urb failed (error=%i)\n",
+                               status);
+        }
+        return;
+}
+
+static void cx231xx_audio_bulkirq(struct urb *urb)
+{
+        struct cx231xx *dev = urb->context;
+        unsigned int oldptr;
+        int period_elapsed = 0;
+        int status;
+        unsigned char *cp;
+        unsigned int stride;
+        struct snd_pcm_substream *substream;
+        struct snd_pcm_runtime *runtime;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return;
+
+        switch (urb->status) {
+        case 0:         /* success */
+        case -ETIMEDOUT:        /* NAK */
+                break;
+        case -ECONNRESET:       /* kill */
+        case -ENOENT:
+        case -ESHUTDOWN:
+                return;
+        default:                /* error */
+                dprintk("urb completition error %d.\n", urb->status);
+                break;
+        }
+
+        if (atomic_read(&dev->stream_started) == 0)
+                return;
+
+        if (dev->adev.capture_pcm_substream) {
+                substream = dev->adev.capture_pcm_substream;
+                runtime = substream->runtime;
+                stride = runtime->frame_bits >> 3;
+
+                if (1) {
+                        int length = urb->actual_length /
+                                     stride;
+                        cp = (unsigned char *)urb->transfer_buffer;
+
+                        oldptr = dev->adev.hwptr_done_capture;
+                        if (oldptr + length >= runtime->buffer_size) {
+                                unsigned int cnt;
+
+                                cnt = runtime->buffer_size - oldptr;
+                                memcpy(runtime->dma_area + oldptr * stride, cp,
+                                       cnt * stride);
+                                memcpy(runtime->dma_area, cp + cnt * stride,
+                                       length * stride - cnt * stride);
+                        } else {
+                                memcpy(runtime->dma_area + oldptr * stride, cp,
+                                       length * stride);
+                        }
+
+                        snd_pcm_stream_lock(substream);
+
+                        dev->adev.hwptr_done_capture += length;
+                        if (dev->adev.hwptr_done_capture >=
+                                                runtime->buffer_size)
+                                dev->adev.hwptr_done_capture -=
+                                                runtime->buffer_size;
+
+                        dev->adev.capture_transfer_done += length;
+                        if (dev->adev.capture_transfer_done >=
+                                runtime->period_size) {
+                                dev->adev.capture_transfer_done -=
+                                                runtime->period_size;
+                                period_elapsed = 1;
+                        }
+                        snd_pcm_stream_unlock(substream);
+                }
+                if (period_elapsed)
+                        snd_pcm_period_elapsed(substream);
+        }
+        urb->status = 0;
+
+        status = usb_submit_urb(urb, GFP_ATOMIC);
+        if (status < 0) {
+                cx231xx_errdev("resubmit of audio urb failed (error=%i)\n",
+                               status);
+        }
+        return;
+}
+
+static int cx231xx_init_audio_isoc(struct cx231xx *dev)
+{
+        int i, errCode;
+        int sb_size;
+
+        cx231xx_info("%s: Starting ISO AUDIO transfers\n", __func__);
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        sb_size = CX231XX_ISO_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size;
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                struct urb *urb;
+                int j, k;
+
+                dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_ATOMIC);
+                if (!dev->adev.transfer_buffer[i])
+                        return -ENOMEM;
+
+                memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
+                urb = usb_alloc_urb(CX231XX_ISO_NUM_AUDIO_PACKETS, GFP_ATOMIC);
+                if (!urb) {
+                        cx231xx_errdev("usb_alloc_urb failed!\n");
+                        for (j = 0; j < i; j++) {
+                                usb_free_urb(dev->adev.urb[j]);
+                                kfree(dev->adev.transfer_buffer[j]);
+                        }
+                        return -ENOMEM;
+                }
+
+                urb->dev = dev->udev;
+                urb->context = dev;
+                urb->pipe = usb_rcvisocpipe(dev->udev,
+                                                dev->adev.end_point_addr);
+                urb->transfer_flags = URB_ISO_ASAP;
+                urb->transfer_buffer = dev->adev.transfer_buffer[i];
+                urb->interval = 1;
+                urb->complete = cx231xx_audio_isocirq;
+                urb->number_of_packets = CX231XX_ISO_NUM_AUDIO_PACKETS;
+                urb->transfer_buffer_length = sb_size;
+
+                for (j = k = 0; j < CX231XX_ISO_NUM_AUDIO_PACKETS;
+                        j++, k += dev->adev.max_pkt_size) {
+                        urb->iso_frame_desc[j].offset = k;
+                        urb->iso_frame_desc[j].length = dev->adev.max_pkt_size;
+                }
+                dev->adev.urb[i] = urb;
+        }
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                errCode = usb_submit_urb(dev->adev.urb[i], GFP_ATOMIC);
+                if (errCode < 0) {
+                        cx231xx_isoc_audio_deinit(dev);
+                        return errCode;
+                }
+        }
+
+        return errCode;
+}
+
+static int cx231xx_init_audio_bulk(struct cx231xx *dev)
+{
+        int i, errCode;
+        int sb_size;
+
+        cx231xx_info("%s: Starting BULK AUDIO transfers\n", __func__);
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        sb_size = CX231XX_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size;
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                struct urb *urb;
+                int j;
+
+                dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_ATOMIC);
+                if (!dev->adev.transfer_buffer[i])
+                        return -ENOMEM;
+
+                memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
+                urb = usb_alloc_urb(CX231XX_NUM_AUDIO_PACKETS, GFP_ATOMIC);
+                if (!urb) {
+                        cx231xx_errdev("usb_alloc_urb failed!\n");
+                        for (j = 0; j < i; j++) {
+                                usb_free_urb(dev->adev.urb[j]);
+                                kfree(dev->adev.transfer_buffer[j]);
+                        }
+                        return -ENOMEM;
+                }
+
+                urb->dev = dev->udev;
+                urb->context = dev;
+                urb->pipe = usb_rcvbulkpipe(dev->udev,
+                                                dev->adev.end_point_addr);
+                urb->transfer_flags = 0;
+                urb->transfer_buffer = dev->adev.transfer_buffer[i];
+                urb->complete = cx231xx_audio_bulkirq;
+                urb->transfer_buffer_length = sb_size;
+
+                dev->adev.urb[i] = urb;
+
+        }
+
+        for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
+                errCode = usb_submit_urb(dev->adev.urb[i], GFP_ATOMIC);
+                if (errCode < 0) {
+                        cx231xx_bulk_audio_deinit(dev);
+                        return errCode;
+                }
+        }
+
+        return errCode;
+}
+
+static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
+                                        size_t size)
+{
+        struct snd_pcm_runtime *runtime = subs->runtime;
+
+        dprintk("Allocating vbuffer\n");
+        if (runtime->dma_area) {
+                if (runtime->dma_bytes > size)
+                        return 0;
+
+                vfree(runtime->dma_area);
+        }
+        runtime->dma_area = vmalloc(size);
+        if (!runtime->dma_area)
+                return -ENOMEM;
+
+        runtime->dma_bytes = size;
+
+        return 0;
+}
+
+static struct snd_pcm_hardware snd_cx231xx_hw_capture = {
+        .info = SNDRV_PCM_INFO_BLOCK_TRANSFER   |
+            SNDRV_PCM_INFO_MMAP                 |
+            SNDRV_PCM_INFO_INTERLEAVED          |
+            SNDRV_PCM_INFO_MMAP_VALID,
+
+        .formats = SNDRV_PCM_FMTBIT_S16_LE,
+
+        .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_KNOT,
+
+        .rate_min = 48000,
+        .rate_max = 48000,
+        .channels_min = 2,
+        .channels_max = 2,
+        .buffer_bytes_max = 62720 * 8,  /* just about the value in usbaudio.c */
+        .period_bytes_min = 64,         /* 12544/2, */
+        .period_bytes_max = 12544,
+        .periods_min = 2,
+        .periods_max = 98,              /* 12544, */
+};
+
+static int snd_cx231xx_capture_open(struct snd_pcm_substream *substream)
+{
+        struct cx231xx *dev = snd_pcm_substream_chip(substream);
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        int ret = 0;
+
+        dprintk("opening device and trying to acquire exclusive lock\n");
+
+        if (!dev) {
+                cx231xx_errdev("BUG: cx231xx can't find device struct."
+                               " Can't proceed with open\n");
+                return -ENODEV;
+        }
+
+        if (dev->state & DEV_DISCONNECTED) {
+                cx231xx_errdev("Can't open. the device was removed.\n");
+                return -ENODEV;
+        }
+
+        /* Sets volume, mute, etc */
+        dev->mute = 0;
+
+        /* set alternate setting for audio interface */
+        /* 1 - 48000 samples per sec */
+        mutex_lock(&dev->lock);
+        if (dev->USE_ISO)
+                ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 1);
+        else
+                ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0);
+        mutex_unlock(&dev->lock);
+        if (ret < 0) {
+                cx231xx_errdev("failed to set alternate setting !\n");
+
+                return ret;
+        }
+
+        runtime->hw = snd_cx231xx_hw_capture;
+
+        mutex_lock(&dev->lock);
+        /* inform hardware to start streaming */
+        ret = cx231xx_capture_start(dev, 1, Audio);
+
+        dev->adev.users++;
+        mutex_unlock(&dev->lock);
+
+        snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+        dev->adev.capture_pcm_substream = substream;
+        runtime->private_data = dev;
+
+        return 0;
+}
+
+static int snd_cx231xx_pcm_close(struct snd_pcm_substream *substream)
+{
+        int ret;
+        struct cx231xx *dev = snd_pcm_substream_chip(substream);
+
+        dprintk("closing device\n");
+
+        /* inform hardware to stop streaming */
+        mutex_lock(&dev->lock);
+        ret = cx231xx_capture_start(dev, 0, Audio);
+
+        /* set alternate setting for audio interface */
+        /* 1 - 48000 samples per sec */
+        ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0);
+        if (ret < 0) {
+                cx231xx_errdev("failed to set alternate setting !\n");
+
+                mutex_unlock(&dev->lock);
+                return ret;
+        }
+
+        dev->mute = 1;
+        dev->adev.users--;
+        mutex_unlock(&dev->lock);
+
+        if (dev->adev.users == 0 && dev->adev.shutdown == 1) {
+                dprintk("audio users: %d\n", dev->adev.users);
+                dprintk("disabling audio stream!\n");
+                dev->adev.shutdown = 0;
+                dprintk("released lock\n");
+                if (atomic_read(&dev->stream_started) > 0) {
+                        atomic_set(&dev->stream_started, 0);
+                        schedule_work(&dev->wq_trigger);
+                }
+        }
+        return 0;
+}
+
+static int snd_cx231xx_hw_capture_params(struct snd_pcm_substream *substream,
+                                         struct snd_pcm_hw_params *hw_params)
+{
+        int ret;
+
+        dprintk("Setting capture parameters\n");
+
+        ret = snd_pcm_alloc_vmalloc_buffer(substream,
+                                           params_buffer_bytes(hw_params));
+#if 0
+        /* TODO: set up cx231xx audio chip to deliver the correct audio format,
+           current default is 48000hz multiplexed => 96000hz mono
+           which shouldn't matter since analogue TV only supports mono */
+        unsigned int channels, rate, format;
+
+        format = params_format(hw_params);
+        rate = params_rate(hw_params);
+        channels = params_channels(hw_params);
+#endif
+
+        return ret;
+}
+
+static int snd_cx231xx_hw_capture_free(struct snd_pcm_substream *substream)
+{
+        struct cx231xx *dev = snd_pcm_substream_chip(substream);
+
+        dprintk("Stop capture, if needed\n");
+
+        if (atomic_read(&dev->stream_started) > 0) {
+                atomic_set(&dev->stream_started, 0);
+                schedule_work(&dev->wq_trigger);
+        }
+
+        return 0;
+}
+
+static int snd_cx231xx_prepare(struct snd_pcm_substream *substream)
+{
+        struct cx231xx *dev = snd_pcm_substream_chip(substream);
+
+        dev->adev.hwptr_done_capture = 0;
+        dev->adev.capture_transfer_done = 0;
+
+        return 0;
+}
+
+static void audio_trigger(struct work_struct *work)
+{
+        struct cx231xx *dev = container_of(work, struct cx231xx, wq_trigger);
+
+        if (atomic_read(&dev->stream_started)) {
+                dprintk("starting capture");
+                if (is_fw_load(dev) == 0)
+                        cx25840_call(dev, core, load_fw);
+                if (dev->USE_ISO)
+                        cx231xx_init_audio_isoc(dev);
+                else
+                        cx231xx_init_audio_bulk(dev);
+        } else {
+                dprintk("stopping capture");
+                cx231xx_isoc_audio_deinit(dev);
+        }
+}
+
+static int snd_cx231xx_capture_trigger(struct snd_pcm_substream *substream,
+                                       int cmd)
+{
+        struct cx231xx *dev = snd_pcm_substream_chip(substream);
+        int retval = 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        spin_lock(&dev->adev.slock);
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+                atomic_set(&dev->stream_started, 1);
+                break;
+        case SNDRV_PCM_TRIGGER_STOP:
+                atomic_set(&dev->stream_started, 0);
+                break;
+        default:
+                retval = -EINVAL;
+                break;
+        }
+        spin_unlock(&dev->adev.slock);
+
+        schedule_work(&dev->wq_trigger);
+
+        return retval;
+}
+
+static snd_pcm_uframes_t snd_cx231xx_capture_pointer(struct snd_pcm_substream
+                                                     *substream)
+{
+        struct cx231xx *dev;
+        unsigned long flags;
+        snd_pcm_uframes_t hwptr_done;
+
+        dev = snd_pcm_substream_chip(substream);
+
+        spin_lock_irqsave(&dev->adev.slock, flags);
+        hwptr_done = dev->adev.hwptr_done_capture;
+        spin_unlock_irqrestore(&dev->adev.slock, flags);
+
+        return hwptr_done;
+}
+
+static struct page *snd_pcm_get_vmalloc_page(struct snd_pcm_substream *subs,
+                                             unsigned long offset)
+{
+        void *pageptr = subs->runtime->dma_area + offset;
+
+        return vmalloc_to_page(pageptr);
+}
+
+static struct snd_pcm_ops snd_cx231xx_pcm_capture = {
+        .open = snd_cx231xx_capture_open,
+        .close = snd_cx231xx_pcm_close,
+        .ioctl = snd_pcm_lib_ioctl,
+        .hw_params = snd_cx231xx_hw_capture_params,
+        .hw_free = snd_cx231xx_hw_capture_free,
+        .prepare = snd_cx231xx_prepare,
+        .trigger = snd_cx231xx_capture_trigger,
+        .pointer = snd_cx231xx_capture_pointer,
+        .page = snd_pcm_get_vmalloc_page,
+};
+
+static int cx231xx_audio_init(struct cx231xx *dev)
+{
+        struct cx231xx_audio *adev = &dev->adev;
+        struct snd_pcm *pcm;
+        struct snd_card *card;
+        static int devnr;
+        int err;
+        struct usb_interface *uif;
+        int i, isoc_pipe = 0;
+
+        if (dev->has_alsa_audio != 1) {
+                /* This device does not support the extension (in this case
+                   the device is expecting the snd-usb-audio module or
+                   doesn't have analog audio support at all) */
+                return 0;
+        }
+
+        cx231xx_info("cx231xx-audio.c: probing for cx231xx "
+                     "non standard usbaudio\n");
+
+        err = snd_card_create(index[devnr], "Cx231xx Audio", THIS_MODULE,
+                              0, &card);
+        if (err < 0)
+                return err;
+
+        spin_lock_init(&adev->slock);
+        err = snd_pcm_new(card, "Cx231xx Audio", 0, 0, 1, &pcm);
+        if (err < 0) {
+                snd_card_free(card);
+                return err;
+        }
+
+        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
+                        &snd_cx231xx_pcm_capture);
+        pcm->info_flags = 0;
+        pcm->private_data = dev;
+        strcpy(pcm->name, "Conexant cx231xx Capture");
+        snd_card_set_dev(card, &dev->udev->dev);
+        strcpy(card->driver, "Cx231xx-Audio");
+        strcpy(card->shortname, "Cx231xx Audio");
+        strcpy(card->longname, "Conexant cx231xx Audio");
+
+        INIT_WORK(&dev->wq_trigger, audio_trigger);
+
+        err = snd_card_register(card);
+        if (err < 0) {
+                snd_card_free(card);
+                return err;
+        }
+        adev->sndcard = card;
+        adev->udev = dev->udev;
+
+        /* compute alternate max packet sizes for Audio */
+        uif =
+            dev->udev->actconfig->interface[dev->current_pcb_config.
+                                            hs_config_info[0].interface_info.
+                                            audio_index + 1];
+
+        adev->end_point_addr =
+            le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
+                        bEndpointAddress);
+
+        adev->num_alt = uif->num_altsetting;
+        cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
+                     adev->end_point_addr, adev->num_alt);
+        adev->alt_max_pkt_size = kmalloc(32 * adev->num_alt, GFP_KERNEL);
+
+        if (adev->alt_max_pkt_size == NULL) {
+                cx231xx_errdev("out of memory!\n");
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < adev->num_alt; i++) {
+                u16 tmp =
+                    le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].desc.
+                                wMaxPacketSize);
+                adev->alt_max_pkt_size[i] =
+                    (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
+                cx231xx_info("Alternate setting %i, max size= %i\n", i,
+                             adev->alt_max_pkt_size[i]);
+        }
+
+        return 0;
+}
+
+static int cx231xx_audio_fini(struct cx231xx *dev)
+{
+        if (dev == NULL)
+                return 0;
+
+        if (dev->has_alsa_audio != 1) {
+                /* This device does not support the extension (in this case
+                   the device is expecting the snd-usb-audio module or
+                   doesn't have analog audio support at all) */
+                return 0;
+        }
+
+        if (dev->adev.sndcard) {
+                snd_card_free(dev->adev.sndcard);
+                kfree(dev->adev.alt_max_pkt_size);
+                dev->adev.sndcard = NULL;
+        }
+
+        return 0;
+}
+
+static struct cx231xx_ops audio_ops = {
+        .id = CX231XX_AUDIO,
+        .name = "Cx231xx Audio Extension",
+        .init = cx231xx_audio_init,
+        .fini = cx231xx_audio_fini,
+};
+
+static int __init cx231xx_alsa_register(void)
+{
+        return cx231xx_register_extension(&audio_ops);
+}
+
+static void __exit cx231xx_alsa_unregister(void)
+{
+        cx231xx_unregister_extension(&audio_ops);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>");
+MODULE_DESCRIPTION("Cx231xx Audio driver");
+
+module_init(cx231xx_alsa_register);
+module_exit(cx231xx_alsa_unregister);
diff --git a/drivers/media/usb/cx231xx/cx231xx-avcore.c b/drivers/media/usb/cx231xx/cx231xx-avcore.c
new file mode 100644
index 000000000000..447148eff958
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-avcore.c
@@ -0,0 +1,3087 @@
+/*
+   cx231xx_avcore.c - driver for Conexant Cx23100/101/102
+                      USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+
+   This program contains the specific code to control the avdecoder chip and
+   other related usb control functions for cx231xx based chipset.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/bitmap.h>
+#include <linux/usb.h>
+#include <linux/i2c.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <media/tuner.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-chip-ident.h>
+
+#include "cx231xx.h"
+#include "cx231xx-dif.h"
+
+#define TUNER_MODE_FM_RADIO 0
+/******************************************************************************
+                        -: BLOCK ARRANGEMENT :-
+        I2S block ----------------------|
+        [I2S audio]                     |
+                                        |
+        Analog Front End --> Direct IF -|-> Cx25840 --> Audio
+        [video & audio]                 |   [Audio]
+                                        |
+                                        |-> Cx25840 --> Video
+                                            [Video]
+
+*******************************************************************************/
+/******************************************************************************
+ *                    VERVE REGISTER                                          *
+ *                                                                            *
+ ******************************************************************************/
+static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
+{
+        return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
+                                        saddr, 1, data, 1);
+}
+
+static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
+{
+        int status;
+        u32 temp = 0;
+
+        status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
+                                        saddr, 1, &temp, 1);
+        *data = (u8) temp;
+        return status;
+}
+void initGPIO(struct cx231xx *dev)
+{
+        u32 _gpio_direction = 0;
+        u32 value = 0;
+        u8 val = 0;
+
+        _gpio_direction = _gpio_direction & 0xFC0003FF;
+        _gpio_direction = _gpio_direction | 0x03FDFC00;
+        cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
+
+        verve_read_byte(dev, 0x07, &val);
+        cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
+        verve_write_byte(dev, 0x07, 0xF4);
+        verve_read_byte(dev, 0x07, &val);
+        cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
+
+        cx231xx_capture_start(dev, 1, Vbi);
+
+        cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
+        cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
+
+}
+void uninitGPIO(struct cx231xx *dev)
+{
+        u8 value[4] = { 0, 0, 0, 0 };
+
+        cx231xx_capture_start(dev, 0, Vbi);
+        verve_write_byte(dev, 0x07, 0x14);
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                        0x68, value, 4);
+}
+
+/******************************************************************************
+ *                    A F E - B L O C K    C O N T R O L   functions          *
+ *                              [ANALOG FRONT END]                            *
+ ******************************************************************************/
+static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
+{
+        return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
+                                        saddr, 2, data, 1);
+}
+
+static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
+{
+        int status;
+        u32 temp = 0;
+
+        status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
+                                        saddr, 2, &temp, 1);
+        *data = (u8) temp;
+        return status;
+}
+
+int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
+{
+        int status = 0;
+        u8 temp = 0;
+        u8 afe_power_status = 0;
+        int i = 0;
+
+        /* super block initialize */
+        temp = (u8) (ref_count & 0xff);
+        status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
+        if (status < 0)
+                return status;
+
+        status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
+        if (status < 0)
+                return status;
+
+        temp = (u8) ((ref_count & 0x300) >> 8);
+        temp |= 0x40;
+        status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
+        if (status < 0)
+                return status;
+
+        status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
+        if (status < 0)
+                return status;
+
+        /* enable pll     */
+        while (afe_power_status != 0x18) {
+                status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
+                if (status < 0) {
+                        cx231xx_info(
+                        ": Init Super Block failed in send cmd\n");
+                        break;
+                }
+
+                status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
+                afe_power_status &= 0xff;
+                if (status < 0) {
+                        cx231xx_info(
+                        ": Init Super Block failed in receive cmd\n");
+                        break;
+                }
+                i++;
+                if (i == 10) {
+                        cx231xx_info(
+                        ": Init Super Block force break in loop !!!!\n");
+                        status = -1;
+                        break;
+                }
+        }
+
+        if (status < 0)
+                return status;
+
+        /* start tuning filter */
+        status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
+        if (status < 0)
+                return status;
+
+        msleep(5);
+
+        /* exit tuning */
+        status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
+
+        return status;
+}
+
+int cx231xx_afe_init_channels(struct cx231xx *dev)
+{
+        int status = 0;
+
+        /* power up all 3 channels, clear pd_buffer */
+        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
+        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
+        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
+
+        /* Enable quantizer calibration */
+        status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
+
+        /* channel initialize, force modulator (fb) reset */
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
+
+        /* start quantilizer calibration  */
+        status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
+        status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
+        status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
+        msleep(5);
+
+        /* exit modulator (fb) reset */
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
+        status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
+
+        /* enable the pre_clamp in each channel for single-ended input */
+        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
+        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
+        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
+
+        /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
+        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
+                                   ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
+        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
+                                   ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
+        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
+                                   ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
+
+        /* dynamic element matching off */
+        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
+        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
+        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
+
+        return status;
+}
+
+int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
+{
+        u8 c_value = 0;
+        int status = 0;
+
+        status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
+        c_value &= (~(0x50));
+        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
+
+        return status;
+}
+
+/*
+        The Analog Front End in Cx231xx has 3 channels. These
+        channels are used to share between different inputs
+        like tuner, s-video and composite inputs.
+
+        channel 1 ----- pin 1  to pin4(in reg is 1-4)
+        channel 2 ----- pin 5  to pin8(in reg is 5-8)
+        channel 3 ----- pin 9 to pin 12(in reg is 9-11)
+*/
+int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
+{
+        u8 ch1_setting = (u8) input_mux;
+        u8 ch2_setting = (u8) (input_mux >> 8);
+        u8 ch3_setting = (u8) (input_mux >> 16);
+        int status = 0;
+        u8 value = 0;
+
+        if (ch1_setting != 0) {
+                status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
+                value &= ~INPUT_SEL_MASK;
+                value |= (ch1_setting - 1) << 4;
+                value &= 0xff;
+                status = afe_write_byte(dev, ADC_INPUT_CH1, value);
+        }
+
+        if (ch2_setting != 0) {
+                status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
+                value &= ~INPUT_SEL_MASK;
+                value |= (ch2_setting - 1) << 4;
+                value &= 0xff;
+                status = afe_write_byte(dev, ADC_INPUT_CH2, value);
+        }
+
+        /* For ch3_setting, the value to put in the register is
+           7 less than the input number */
+        if (ch3_setting != 0) {
+                status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
+                value &= ~INPUT_SEL_MASK;
+                value |= (ch3_setting - 1) << 4;
+                value &= 0xff;
+                status = afe_write_byte(dev, ADC_INPUT_CH3, value);
+        }
+
+        return status;
+}
+
+int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
+{
+        int status = 0;
+
+        /*
+        * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
+        * Currently, only baseband works.
+        */
+
+        switch (mode) {
+        case AFE_MODE_LOW_IF:
+                cx231xx_Setup_AFE_for_LowIF(dev);
+                break;
+        case AFE_MODE_BASEBAND:
+                status = cx231xx_afe_setup_AFE_for_baseband(dev);
+                break;
+        case AFE_MODE_EU_HI_IF:
+                /* SetupAFEforEuHiIF(); */
+                break;
+        case AFE_MODE_US_HI_IF:
+                /* SetupAFEforUsHiIF(); */
+                break;
+        case AFE_MODE_JAPAN_HI_IF:
+                /* SetupAFEforJapanHiIF(); */
+                break;
+        }
+
+        if ((mode != dev->afe_mode) &&
+                (dev->video_input == CX231XX_VMUX_TELEVISION))
+                status = cx231xx_afe_adjust_ref_count(dev,
+                                                     CX231XX_VMUX_TELEVISION);
+
+        dev->afe_mode = mode;
+
+        return status;
+}
+
+int cx231xx_afe_update_power_control(struct cx231xx *dev,
+                                        enum AV_MODE avmode)
+{
+        u8 afe_power_status = 0;
+        int status = 0;
+
+        switch (dev->model) {
+        case CX231XX_BOARD_CNXT_CARRAERA:
+        case CX231XX_BOARD_CNXT_RDE_250:
+        case CX231XX_BOARD_CNXT_SHELBY:
+        case CX231XX_BOARD_CNXT_RDU_250:
+        case CX231XX_BOARD_CNXT_RDE_253S:
+        case CX231XX_BOARD_CNXT_RDU_253S:
+        case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
+        case CX231XX_BOARD_HAUPPAUGE_EXETER:
+        case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
+        case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
+                if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
+                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
+                                                FLD_PWRDN_ENABLE_PLL)) {
+                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                        FLD_PWRDN_TUNING_BIAS |
+                                                        FLD_PWRDN_ENABLE_PLL);
+                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                        &afe_power_status);
+                                if (status < 0)
+                                        break;
+                        }
+
+                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                        0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                        0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                        0x00);
+                } else if (avmode == POLARIS_AVMODE_DIGITAL) {
+                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                        0x70);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                        0x70);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                        0x70);
+
+                        status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                  &afe_power_status);
+                        afe_power_status |= FLD_PWRDN_PD_BANDGAP |
+                                                FLD_PWRDN_PD_BIAS |
+                                                FLD_PWRDN_PD_TUNECK;
+                        status |= afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                   afe_power_status);
+                } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
+                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
+                                                FLD_PWRDN_ENABLE_PLL)) {
+                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                        FLD_PWRDN_TUNING_BIAS |
+                                                        FLD_PWRDN_ENABLE_PLL);
+                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                        &afe_power_status);
+                                if (status < 0)
+                                        break;
+                        }
+
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                0x00);
+                } else {
+                        cx231xx_info("Invalid AV mode input\n");
+                        status = -1;
+                }
+                break;
+        default:
+                if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
+                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
+                                                FLD_PWRDN_ENABLE_PLL)) {
+                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                        FLD_PWRDN_TUNING_BIAS |
+                                                        FLD_PWRDN_ENABLE_PLL);
+                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                        &afe_power_status);
+                                if (status < 0)
+                                        break;
+                        }
+
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                        0x40);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                        0x40);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                        0x00);
+                } else if (avmode == POLARIS_AVMODE_DIGITAL) {
+                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                        0x70);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                        0x70);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                        0x70);
+
+                        status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                       &afe_power_status);
+                        afe_power_status |= FLD_PWRDN_PD_BANDGAP |
+                                                FLD_PWRDN_PD_BIAS |
+                                                FLD_PWRDN_PD_TUNECK;
+                        status |= afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                        afe_power_status);
+                } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
+                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
+                                                FLD_PWRDN_ENABLE_PLL)) {
+                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
+                                                        FLD_PWRDN_TUNING_BIAS |
+                                                        FLD_PWRDN_ENABLE_PLL);
+                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
+                                                        &afe_power_status);
+                                if (status < 0)
+                                        break;
+                        }
+
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
+                                                        0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
+                                                        0x00);
+                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
+                                                        0x40);
+                } else {
+                        cx231xx_info("Invalid AV mode input\n");
+                        status = -1;
+                }
+        }                       /* switch  */
+
+        return status;
+}
+
+int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
+{
+        u8 input_mode = 0;
+        u8 ntf_mode = 0;
+        int status = 0;
+
+        dev->video_input = video_input;
+
+        if (video_input == CX231XX_VMUX_TELEVISION) {
+                status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
+                status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
+                                        &ntf_mode);
+        } else {
+                status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
+                status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
+                                        &ntf_mode);
+        }
+
+        input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
+
+        switch (input_mode) {
+        case SINGLE_ENDED:
+                dev->afe_ref_count = 0x23C;
+                break;
+        case LOW_IF:
+                dev->afe_ref_count = 0x24C;
+                break;
+        case EU_IF:
+                dev->afe_ref_count = 0x258;
+                break;
+        case US_IF:
+                dev->afe_ref_count = 0x260;
+                break;
+        default:
+                break;
+        }
+
+        status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
+
+        return status;
+}
+
+/******************************************************************************
+ *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
+ ******************************************************************************/
+static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
+{
+        return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                        saddr, 2, data, 1);
+}
+
+static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
+{
+        int status;
+        u32 temp = 0;
+
+        status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                        saddr, 2, &temp, 1);
+        *data = (u8) temp;
+        return status;
+}
+
+static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
+{
+        return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                        saddr, 2, data, 4);
+}
+
+static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
+{
+        return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                        saddr, 2, data, 4);
+}
+int cx231xx_check_fw(struct cx231xx *dev)
+{
+        u8 temp = 0;
+        int status = 0;
+        status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
+        if (status < 0)
+                return status;
+        else
+                return temp;
+
+}
+
+int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
+{
+        int status = 0;
+
+        switch (INPUT(input)->type) {
+        case CX231XX_VMUX_COMPOSITE1:
+        case CX231XX_VMUX_SVIDEO:
+                if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
+                    (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
+                        /* External AV */
+                        status = cx231xx_set_power_mode(dev,
+                                        POLARIS_AVMODE_ENXTERNAL_AV);
+                        if (status < 0) {
+                                cx231xx_errdev("%s: set_power_mode : Failed to"
+                                                " set Power - errCode [%d]!\n",
+                                                __func__, status);
+                                return status;
+                        }
+                }
+                status = cx231xx_set_decoder_video_input(dev,
+                                                         INPUT(input)->type,
+                                                         INPUT(input)->vmux);
+                break;
+        case CX231XX_VMUX_TELEVISION:
+        case CX231XX_VMUX_CABLE:
+                if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
+                    (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
+                        /* Tuner */
+                        status = cx231xx_set_power_mode(dev,
+                                                POLARIS_AVMODE_ANALOGT_TV);
+                        if (status < 0) {
+                                cx231xx_errdev("%s: set_power_mode:Failed"
+                                        " to set Power - errCode [%d]!\n",
+                                        __func__, status);
+                                return status;
+                        }
+                }
+                if (dev->tuner_type == TUNER_NXP_TDA18271)
+                        status = cx231xx_set_decoder_video_input(dev,
+                                                        CX231XX_VMUX_TELEVISION,
+                                                        INPUT(input)->vmux);
+                else
+                        status = cx231xx_set_decoder_video_input(dev,
+                                                        CX231XX_VMUX_COMPOSITE1,
+                                                        INPUT(input)->vmux);
+
+                break;
+        default:
+                cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
+                     __func__, INPUT(input)->type);
+                break;
+        }
+
+        /* save the selection */
+        dev->video_input = input;
+
+        return status;
+}
+
+int cx231xx_set_decoder_video_input(struct cx231xx *dev,
+                                u8 pin_type, u8 input)
+{
+        int status = 0;
+        u32 value = 0;
+
+        if (pin_type != dev->video_input) {
+                status = cx231xx_afe_adjust_ref_count(dev, pin_type);
+                if (status < 0) {
+                        cx231xx_errdev("%s: adjust_ref_count :Failed to set"
+                                "AFE input mux - errCode [%d]!\n",
+                                __func__, status);
+                        return status;
+                }
+        }
+
+        /* call afe block to set video inputs */
+        status = cx231xx_afe_set_input_mux(dev, input);
+        if (status < 0) {
+                cx231xx_errdev("%s: set_input_mux :Failed to set"
+                                " AFE input mux - errCode [%d]!\n",
+                                __func__, status);
+                return status;
+        }
+
+        switch (pin_type) {
+        case CX231XX_VMUX_COMPOSITE1:
+                status = vid_blk_read_word(dev, AFE_CTRL, &value);
+                value |= (0 << 13) | (1 << 4);
+                value &= ~(1 << 5);
+
+                /* set [24:23] [22:15] to 0  */
+                value &= (~(0x1ff8000));
+                /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
+                value |= 0x1000000;
+                status = vid_blk_write_word(dev, AFE_CTRL, value);
+
+                status = vid_blk_read_word(dev, OUT_CTRL1, &value);
+                value |= (1 << 7);
+                status = vid_blk_write_word(dev, OUT_CTRL1, value);
+
+                /* Set output mode */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        OUT_CTRL1,
+                                                        FLD_OUT_MODE,
+                                                        dev->board.output_mode);
+
+                /* Tell DIF object to go to baseband mode  */
+                status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
+                if (status < 0) {
+                        cx231xx_errdev("%s: cx231xx_dif set to By pass"
+                                                   " mode- errCode [%d]!\n",
+                                __func__, status);
+                        return status;
+                }
+
+                /* Read the DFE_CTRL1 register */
+                status = vid_blk_read_word(dev, DFE_CTRL1, &value);
+
+                /* enable the VBI_GATE_EN */
+                value |= FLD_VBI_GATE_EN;
+
+                /* Enable the auto-VGA enable */
+                value |= FLD_VGA_AUTO_EN;
+
+                /* Write it back */
+                status = vid_blk_write_word(dev, DFE_CTRL1, value);
+
+                /* Disable auto config of registers */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        MODE_CTRL, FLD_ACFG_DIS,
+                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
+
+                /* Set CVBS input mode */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                        VID_BLK_I2C_ADDRESS,
+                        MODE_CTRL, FLD_INPUT_MODE,
+                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
+                break;
+        case CX231XX_VMUX_SVIDEO:
+                /* Disable the use of  DIF */
+
+                status = vid_blk_read_word(dev, AFE_CTRL, &value);
+
+                /* set [24:23] [22:15] to 0 */
+                value &= (~(0x1ff8000));
+                /* set FUNC_MODE[24:23] = 2
+                IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
+                value |= 0x1000010;
+                status = vid_blk_write_word(dev, AFE_CTRL, value);
+
+                /* Tell DIF object to go to baseband mode */
+                status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
+                if (status < 0) {
+                        cx231xx_errdev("%s: cx231xx_dif set to By pass"
+                                                   " mode- errCode [%d]!\n",
+                                __func__, status);
+                        return status;
+                }
+
+                /* Read the DFE_CTRL1 register */
+                status = vid_blk_read_word(dev, DFE_CTRL1, &value);
+
+                /* enable the VBI_GATE_EN */
+                value |= FLD_VBI_GATE_EN;
+
+                /* Enable the auto-VGA enable */
+                value |= FLD_VGA_AUTO_EN;
+
+                /* Write it back */
+                status = vid_blk_write_word(dev, DFE_CTRL1, value);
+
+                /* Disable auto config of registers  */
+                status =  cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        MODE_CTRL, FLD_ACFG_DIS,
+                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
+
+                /* Set YC input mode */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                        VID_BLK_I2C_ADDRESS,
+                        MODE_CTRL,
+                        FLD_INPUT_MODE,
+                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
+
+                /* Chroma to ADC2 */
+                status = vid_blk_read_word(dev, AFE_CTRL, &value);
+                value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
+
+                /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
+                   This sets them to use video
+                   rather than audio.  Only one of the two will be in use. */
+                value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
+
+                status = vid_blk_write_word(dev, AFE_CTRL, value);
+
+                status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
+                break;
+        case CX231XX_VMUX_TELEVISION:
+        case CX231XX_VMUX_CABLE:
+        default:
+                /* TODO: Test if this is also needed for xc2028/xc3028 */
+                if (dev->board.tuner_type == TUNER_XC5000) {
+                        /* Disable the use of  DIF   */
+
+                        status = vid_blk_read_word(dev, AFE_CTRL, &value);
+                        value |= (0 << 13) | (1 << 4);
+                        value &= ~(1 << 5);
+
+                        /* set [24:23] [22:15] to 0 */
+                        value &= (~(0x1FF8000));
+                        /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
+                        value |= 0x1000000;
+                        status = vid_blk_write_word(dev, AFE_CTRL, value);
+
+                        status = vid_blk_read_word(dev, OUT_CTRL1, &value);
+                        value |= (1 << 7);
+                        status = vid_blk_write_word(dev, OUT_CTRL1, value);
+
+                        /* Set output mode */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        OUT_CTRL1, FLD_OUT_MODE,
+                                                        dev->board.output_mode);
+
+                        /* Tell DIF object to go to baseband mode */
+                        status = cx231xx_dif_set_standard(dev,
+                                                          DIF_USE_BASEBAND);
+                        if (status < 0) {
+                                cx231xx_errdev("%s: cx231xx_dif set to By pass"
+                                                " mode- errCode [%d]!\n",
+                                                __func__, status);
+                                return status;
+                        }
+
+                        /* Read the DFE_CTRL1 register */
+                        status = vid_blk_read_word(dev, DFE_CTRL1, &value);
+
+                        /* enable the VBI_GATE_EN */
+                        value |= FLD_VBI_GATE_EN;
+
+                        /* Enable the auto-VGA enable */
+                        value |= FLD_VGA_AUTO_EN;
+
+                        /* Write it back */
+                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
+
+                        /* Disable auto config of registers */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        MODE_CTRL, FLD_ACFG_DIS,
+                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
+
+                        /* Set CVBS input mode */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                VID_BLK_I2C_ADDRESS,
+                                MODE_CTRL, FLD_INPUT_MODE,
+                                cx231xx_set_field(FLD_INPUT_MODE,
+                                                INPUT_MODE_CVBS_0));
+                } else {
+                        /* Enable the DIF for the tuner */
+
+                        /* Reinitialize the DIF */
+                        status = cx231xx_dif_set_standard(dev, dev->norm);
+                        if (status < 0) {
+                                cx231xx_errdev("%s: cx231xx_dif set to By pass"
+                                                " mode- errCode [%d]!\n",
+                                                __func__, status);
+                                return status;
+                        }
+
+                        /* Make sure bypass is cleared */
+                        status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
+
+                        /* Clear the bypass bit */
+                        value &= ~FLD_DIF_DIF_BYPASS;
+
+                        /* Enable the use of the DIF block */
+                        status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
+
+                        /* Read the DFE_CTRL1 register */
+                        status = vid_blk_read_word(dev, DFE_CTRL1, &value);
+
+                        /* Disable the VBI_GATE_EN */
+                        value &= ~FLD_VBI_GATE_EN;
+
+                        /* Enable the auto-VGA enable, AGC, and
+                           set the skip count to 2 */
+                        value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
+
+                        /* Write it back */
+                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
+
+                        /* Wait until AGC locks up */
+                        msleep(1);
+
+                        /* Disable the auto-VGA enable AGC */
+                        value &= ~(FLD_VGA_AUTO_EN);
+
+                        /* Write it back */
+                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
+
+                        /* Enable Polaris B0 AGC output */
+                        status = vid_blk_read_word(dev, PIN_CTRL, &value);
+                        value |= (FLD_OEF_AGC_RF) |
+                                 (FLD_OEF_AGC_IFVGA) |
+                                 (FLD_OEF_AGC_IF);
+                        status = vid_blk_write_word(dev, PIN_CTRL, value);
+
+                        /* Set output mode */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                VID_BLK_I2C_ADDRESS,
+                                                OUT_CTRL1, FLD_OUT_MODE,
+                                                dev->board.output_mode);
+
+                        /* Disable auto config of registers */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        MODE_CTRL, FLD_ACFG_DIS,
+                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
+
+                        /* Set CVBS input mode */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                VID_BLK_I2C_ADDRESS,
+                                MODE_CTRL, FLD_INPUT_MODE,
+                                cx231xx_set_field(FLD_INPUT_MODE,
+                                                INPUT_MODE_CVBS_0));
+
+                        /* Set some bits in AFE_CTRL so that channel 2 or 3
+                         * is ready to receive audio */
+                        /* Clear clamp for channels 2 and 3      (bit 16-17) */
+                        /* Clear droop comp                      (bit 19-20) */
+                        /* Set VGA_SEL (for audio control)       (bit 7-8) */
+                        status = vid_blk_read_word(dev, AFE_CTRL, &value);
+
+                        /*Set Func mode:01-DIF 10-baseband 11-YUV*/
+                        value &= (~(FLD_FUNC_MODE));
+                        value |= 0x800000;
+
+                        value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
+
+                        status = vid_blk_write_word(dev, AFE_CTRL, value);
+
+                        if (dev->tuner_type == TUNER_NXP_TDA18271) {
+                                status = vid_blk_read_word(dev, PIN_CTRL,
+                                 &value);
+                                status = vid_blk_write_word(dev, PIN_CTRL,
+                                 (value & 0xFFFFFFEF));
+                        }
+
+                        break;
+
+                }
+                break;
+        }
+
+        /* Set raw VBI mode */
+        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                VID_BLK_I2C_ADDRESS,
+                                OUT_CTRL1, FLD_VBIHACTRAW_EN,
+                                cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
+
+        status = vid_blk_read_word(dev, OUT_CTRL1, &value);
+        if (value & 0x02) {
+                value |= (1 << 19);
+                status = vid_blk_write_word(dev, OUT_CTRL1, value);
+        }
+
+        return status;
+}
+
+void cx231xx_enable656(struct cx231xx *dev)
+{
+        u8 temp = 0;
+        /*enable TS1 data[0:7] as output to export 656*/
+
+        vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
+
+        /*enable TS1 clock as output to export 656*/
+
+        vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
+        temp = temp|0x04;
+
+        vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
+}
+EXPORT_SYMBOL_GPL(cx231xx_enable656);
+
+void cx231xx_disable656(struct cx231xx *dev)
+{
+        u8 temp = 0;
+
+        vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
+
+        vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
+        temp = temp&0xFB;
+
+        vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
+}
+EXPORT_SYMBOL_GPL(cx231xx_disable656);
+
+/*
+ * Handle any video-mode specific overrides that are different
+ * on a per video standards basis after touching the MODE_CTRL
+ * register which resets many values for autodetect
+ */
+int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
+{
+        int status = 0;
+
+        cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
+                     (unsigned int)dev->norm);
+
+        /* Change the DFE_CTRL3 bp_percent to fix flagging */
+        status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
+
+        if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
+                cx231xx_info("do_mode_ctrl_overrides NTSC\n");
+
+                /* Move the close caption lines out of active video,
+                   adjust the active video start point */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VBLANK_CNT, 0x18);
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VACTIVE_CNT,
+                                                        0x1E7000);
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_V656BLANK_CNT,
+                                                        0x1C000000);
+
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        HORIZ_TIM_CTRL,
+                                                        FLD_HBLANK_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_HBLANK_CNT, 0x79));
+
+        } else if (dev->norm & V4L2_STD_SECAM) {
+                cx231xx_info("do_mode_ctrl_overrides SECAM\n");
+                status =  cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VBLANK_CNT, 0x20);
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VACTIVE_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_VACTIVE_CNT,
+                                                         0x244));
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_V656BLANK_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_V656BLANK_CNT,
+                                                        0x24));
+                /* Adjust the active video horizontal start point */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        HORIZ_TIM_CTRL,
+                                                        FLD_HBLANK_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_HBLANK_CNT, 0x85));
+        } else {
+                cx231xx_info("do_mode_ctrl_overrides PAL\n");
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VBLANK_CNT, 0x20);
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_VACTIVE_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_VACTIVE_CNT,
+                                                         0x244));
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        VERT_TIM_CTRL,
+                                                        FLD_V656BLANK_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_V656BLANK_CNT,
+                                                        0x24));
+                /* Adjust the active video horizontal start point */
+                status = cx231xx_read_modify_write_i2c_dword(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        HORIZ_TIM_CTRL,
+                                                        FLD_HBLANK_CNT,
+                                                        cx231xx_set_field
+                                                        (FLD_HBLANK_CNT, 0x85));
+
+        }
+
+        return status;
+}
+
+int cx231xx_unmute_audio(struct cx231xx *dev)
+{
+        return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
+}
+EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
+
+int stopAudioFirmware(struct cx231xx *dev)
+{
+        return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
+}
+
+int restartAudioFirmware(struct cx231xx *dev)
+{
+        return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
+}
+
+int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
+{
+        int status = 0;
+        enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
+
+        switch (INPUT(input)->amux) {
+        case CX231XX_AMUX_VIDEO:
+                ainput = AUDIO_INPUT_TUNER_TV;
+                break;
+        case CX231XX_AMUX_LINE_IN:
+                status = cx231xx_i2s_blk_set_audio_input(dev, input);
+                ainput = AUDIO_INPUT_LINE;
+                break;
+        default:
+                break;
+        }
+
+        status = cx231xx_set_audio_decoder_input(dev, ainput);
+
+        return status;
+}
+
+int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
+                                    enum AUDIO_INPUT audio_input)
+{
+        u32 dwval;
+        int status;
+        u8 gen_ctrl;
+        u32 value = 0;
+
+        /* Put it in soft reset   */
+        status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
+        gen_ctrl |= 1;
+        status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
+
+        switch (audio_input) {
+        case AUDIO_INPUT_LINE:
+                /* setup AUD_IO control from Merlin paralle output */
+                value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
+                                          AUD_CHAN_SRC_PARALLEL);
+                status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
+
+                /* setup input to Merlin, SRC2 connect to AC97
+                   bypass upsample-by-2, slave mode, sony mode, left justify
+                   adr 091c, dat 01000000 */
+                status = vid_blk_read_word(dev, AC97_CTL, &dwval);
+
+                status = vid_blk_write_word(dev, AC97_CTL,
+                                           (dwval | FLD_AC97_UP2X_BYPASS));
+
+                /* select the parallel1 and SRC3 */
+                status = vid_blk_write_word(dev, BAND_OUT_SEL,
+                                cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
+                                cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
+                                cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
+
+                /* unmute all, AC97 in, independence mode
+                   adr 08d0, data 0x00063073 */
+                status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
+                status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
+
+                /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
+                status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
+                status = vid_blk_write_word(dev, PATH1_VOL_CTL,
+                                           (dwval | FLD_PATH1_AVC_THRESHOLD));
+
+                /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
+                status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
+                status = vid_blk_write_word(dev, PATH1_SC_CTL,
+                                           (dwval | FLD_PATH1_SC_THRESHOLD));
+                break;
+
+        case AUDIO_INPUT_TUNER_TV:
+        default:
+                status = stopAudioFirmware(dev);
+                /* Setup SRC sources and clocks */
+                status = vid_blk_write_word(dev, BAND_OUT_SEL,
+                        cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
+                        cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
+                        cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
+                        cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
+                        cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
+                        cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
+                        cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
+                        cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
+                        cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
+                        cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
+                        cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
+                        cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
+                        cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
+
+                /* Setup the AUD_IO control */
+                status = vid_blk_write_word(dev, AUD_IO_CTRL,
+                        cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
+                        cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
+                        cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
+                        cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
+                        cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
+
+                status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
+
+                /* setAudioStandard(_audio_standard); */
+                status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
+
+                status = restartAudioFirmware(dev);
+
+                switch (dev->board.tuner_type) {
+                case TUNER_XC5000:
+                        /* SIF passthrough at 28.6363 MHz sample rate */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        CHIP_CTRL,
+                                        FLD_SIF_EN,
+                                        cx231xx_set_field(FLD_SIF_EN, 1));
+                        break;
+                case TUNER_NXP_TDA18271:
+                        /* Normal mode: SIF passthrough at 14.32 MHz */
+                        status = cx231xx_read_modify_write_i2c_dword(dev,
+                                        VID_BLK_I2C_ADDRESS,
+                                        CHIP_CTRL,
+                                        FLD_SIF_EN,
+                                        cx231xx_set_field(FLD_SIF_EN, 0));
+                        break;
+                default:
+                        /* This is just a casual suggestion to people adding
+                           new boards in case they use a tuner type we don't
+                           currently know about */
+                        printk(KERN_INFO "Unknown tuner type configuring SIF");
+                        break;
+                }
+                break;
+
+        case AUDIO_INPUT_TUNER_FM:
+                /*  use SIF for FM radio
+                   setupFM();
+                   setAudioStandard(_audio_standard);
+                 */
+                break;
+
+        case AUDIO_INPUT_MUTE:
+                status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
+                break;
+        }
+
+        /* Take it out of soft reset */
+        status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
+        gen_ctrl &= ~1;
+        status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
+
+        return status;
+}
+
+/******************************************************************************
+ *                    C H I P Specific  C O N T R O L   functions             *
+ ******************************************************************************/
+int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
+{
+        u32 value;
+        int status = 0;
+
+        status = vid_blk_read_word(dev, PIN_CTRL, &value);
+        value |= (~dev->board.ctl_pin_status_mask);
+        status = vid_blk_write_word(dev, PIN_CTRL, value);
+
+        return status;
+}
+
+int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
+                                              u8 analog_or_digital)
+{
+        int status = 0;
+
+        /* first set the direction to output */
+        status = cx231xx_set_gpio_direction(dev,
+                                            dev->board.
+                                            agc_analog_digital_select_gpio, 1);
+
+        /* 0 - demod ; 1 - Analog mode */
+        status = cx231xx_set_gpio_value(dev,
+                                   dev->board.agc_analog_digital_select_gpio,
+                                   analog_or_digital);
+
+        return status;
+}
+
+int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
+{
+        u8 value[4] = { 0, 0, 0, 0 };
+        int status = 0;
+        bool current_is_port_3;
+
+        if (dev->board.dont_use_port_3)
+                is_port_3 = false;
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
+                                       PWR_CTL_EN, value, 4);
+        if (status < 0)
+                return status;
+
+        current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
+
+        /* Just return, if already using the right port */
+        if (current_is_port_3 == is_port_3)
+                return 0;
+
+        if (is_port_3)
+                value[0] |= I2C_DEMOD_EN;
+        else
+                value[0] &= ~I2C_DEMOD_EN;
+
+        cx231xx_info("Changing the i2c master port to %d\n",
+                     is_port_3 ?  3 : 1);
+
+        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                        PWR_CTL_EN, value, 4);
+
+        return status;
+
+}
+EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
+
+void update_HH_register_after_set_DIF(struct cx231xx *dev)
+{
+/*
+        u8 status = 0;
+        u32 value = 0;
+
+        vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
+        vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
+        vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
+
+        status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
+        vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
+        status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL,  &value);
+*/
+}
+
+void cx231xx_dump_HH_reg(struct cx231xx *dev)
+{
+        u32 value = 0;
+        u16  i = 0;
+
+        value = 0x45005390;
+        vid_blk_write_word(dev, 0x104, value);
+
+        for (i = 0x100; i < 0x140; i++) {
+                vid_blk_read_word(dev, i, &value);
+                cx231xx_info("reg0x%x=0x%x\n", i, value);
+                i = i+3;
+        }
+
+        for (i = 0x300; i < 0x400; i++) {
+                vid_blk_read_word(dev, i, &value);
+                cx231xx_info("reg0x%x=0x%x\n", i, value);
+                i = i+3;
+        }
+
+        for (i = 0x400; i < 0x440; i++) {
+                vid_blk_read_word(dev, i,  &value);
+                cx231xx_info("reg0x%x=0x%x\n", i, value);
+                i = i+3;
+        }
+
+        vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
+        cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
+        vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
+        vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
+        cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
+}
+
+void cx231xx_dump_SC_reg(struct cx231xx *dev)
+{
+        u8 value[4] = { 0, 0, 0, 0 };
+        cx231xx_info("cx231xx_dump_SC_reg!\n");
+
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
+                                 value[1], value[2], value[3]);
+
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
+                                 value[1], value[2], value[3]);
+
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
+                                 value[1], value[2], value[3]);
+
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
+                                 value[1], value[2], value[3]);
+
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
+                                 value[1], value[2], value[3]);
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
+                                 value, 4);
+        cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
+                                 value[1], value[2], value[3]);
+
+
+}
+
+void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
+
+{
+        u8 value = 0;
+
+        afe_read_byte(dev, ADC_STATUS2_CH3, &value);
+        value = (value & 0xFE)|0x01;
+        afe_write_byte(dev, ADC_STATUS2_CH3, value);
+
+        afe_read_byte(dev, ADC_STATUS2_CH3, &value);
+        value = (value & 0xFE)|0x00;
+        afe_write_byte(dev, ADC_STATUS2_CH3, value);
+
+
+/*
+        config colibri to lo-if mode
+
+        FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
+                the diff IF input by half,
+
+                for low-if agc defect
+*/
+
+        afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
+        value = (value & 0xFC)|0x00;
+        afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
+
+        afe_read_byte(dev, ADC_INPUT_CH3, &value);
+        value = (value & 0xF9)|0x02;
+        afe_write_byte(dev, ADC_INPUT_CH3, value);
+
+        afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
+        value = (value & 0xFB)|0x04;
+        afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
+
+        afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
+        value = (value & 0xFC)|0x03;
+        afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
+
+        afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
+        value = (value & 0xFB)|0x04;
+        afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
+
+        afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
+        value = (value & 0xF8)|0x06;
+        afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
+
+        afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
+        value = (value & 0x8F)|0x40;
+        afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
+
+        afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
+        value = (value & 0xDF)|0x20;
+        afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
+}
+
+void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
+                 u8 spectral_invert, u32 mode)
+{
+        u32 colibri_carrier_offset = 0;
+        u32 func_mode = 0x01; /* Device has a DIF if this function is called */
+        u32 standard = 0;
+        u8 value[4] = { 0, 0, 0, 0 };
+
+        cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
+        value[0] = (u8) 0x6F;
+        value[1] = (u8) 0x6F;
+        value[2] = (u8) 0x6F;
+        value[3] = (u8) 0x6F;
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                        PWR_CTL_EN, value, 4);
+
+        /*Set colibri for low IF*/
+        cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
+
+        /* Set C2HH for low IF operation.*/
+        standard = dev->norm;
+        cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
+                                                       func_mode, standard);
+
+        /* Get colibri offsets.*/
+        colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
+                                                                   standard);
+
+        cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
+                     colibri_carrier_offset, standard);
+
+        /* Set the band Pass filter for DIF*/
+        cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
+                                 spectral_invert, mode);
+}
+
+u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
+{
+        u32 colibri_carrier_offset = 0;
+
+        if (mode == TUNER_MODE_FM_RADIO) {
+                colibri_carrier_offset = 1100000;
+        } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
+                colibri_carrier_offset = 4832000;  /*4.83MHz    */
+        } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
+                colibri_carrier_offset = 2700000;  /*2.70MHz       */
+        } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
+                        | V4L2_STD_SECAM)) {
+                colibri_carrier_offset = 2100000;  /*2.10MHz    */
+        }
+
+        return colibri_carrier_offset;
+}
+
+void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
+                 u8 spectral_invert, u32 mode)
+{
+        unsigned long pll_freq_word;
+        u32 dif_misc_ctrl_value = 0;
+        u64 pll_freq_u64 = 0;
+        u32 i = 0;
+
+        cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
+                         if_freq, spectral_invert, mode);
+
+
+        if (mode == TUNER_MODE_FM_RADIO) {
+                pll_freq_word = 0x905A1CAC;
+                vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
+
+        } else /*KSPROPERTY_TUNER_MODE_TV*/{
+                /* Calculate the PLL frequency word based on the adjusted if_freq*/
+                pll_freq_word = if_freq;
+                pll_freq_u64 = (u64)pll_freq_word << 28L;
+                do_div(pll_freq_u64, 50000000);
+                pll_freq_word = (u32)pll_freq_u64;
+                /*pll_freq_word = 0x3463497;*/
+                vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
+
+        if (spectral_invert) {
+                if_freq -= 400000;
+                /* Enable Spectral Invert*/
+                vid_blk_read_word(dev, DIF_MISC_CTRL,
+                                        &dif_misc_ctrl_value);
+                dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
+                vid_blk_write_word(dev, DIF_MISC_CTRL,
+                                        dif_misc_ctrl_value);
+        } else {
+                if_freq += 400000;
+                /* Disable Spectral Invert*/
+                vid_blk_read_word(dev, DIF_MISC_CTRL,
+                                        &dif_misc_ctrl_value);
+                dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
+                vid_blk_write_word(dev, DIF_MISC_CTRL,
+                                        dif_misc_ctrl_value);
+        }
+
+        if_freq = (if_freq/100000)*100000;
+
+        if (if_freq < 3000000)
+                if_freq = 3000000;
+
+        if (if_freq > 16000000)
+                if_freq = 16000000;
+        }
+
+        cx231xx_info("Enter IF=%zd\n",
+                        ARRAY_SIZE(Dif_set_array));
+        for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
+                if (Dif_set_array[i].if_freq == if_freq) {
+                        vid_blk_write_word(dev,
+                        Dif_set_array[i].register_address, Dif_set_array[i].value);
+                }
+        }
+}
+
+/******************************************************************************
+ *                 D I F - B L O C K    C O N T R O L   functions             *
+ ******************************************************************************/
+int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
+                                          u32 function_mode, u32 standard)
+{
+        int status = 0;
+
+
+        if (mode == V4L2_TUNER_RADIO) {
+                /* C2HH */
+                /* lo if big signal */
+                status = cx231xx_reg_mask_write(dev,
+                                VID_BLK_I2C_ADDRESS, 32,
+                                AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
+                /* FUNC_MODE = DIF */
+                status = cx231xx_reg_mask_write(dev,
+                                VID_BLK_I2C_ADDRESS, 32,
+                                AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
+                /* IF_MODE */
+                status = cx231xx_reg_mask_write(dev,
+                                VID_BLK_I2C_ADDRESS, 32,
+                                AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
+                /* no inv */
+                status = cx231xx_reg_mask_write(dev,
+                                VID_BLK_I2C_ADDRESS, 32,
+                                AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
+        } else if (standard != DIF_USE_BASEBAND) {
+                if (standard & V4L2_STD_MN) {
+                        /* lo if big signal */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
+                        /* FUNC_MODE = DIF */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
+                                        function_mode);
+                        /* IF_MODE */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
+                        /* no inv */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
+                        /* 0x124, AUD_CHAN1_SRC = 0x3 */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AUD_IO_CTRL, 0, 31, 0x00000003);
+                } else if ((standard == V4L2_STD_PAL_I) |
+                        (standard & V4L2_STD_PAL_D) |
+                        (standard & V4L2_STD_SECAM)) {
+                        /* C2HH setup */
+                        /* lo if big signal */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
+                        /* FUNC_MODE = DIF */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
+                                        function_mode);
+                        /* IF_MODE */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
+                        /* no inv */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
+                } else {
+                        /* default PAL BG */
+                        /* C2HH setup */
+                        /* lo if big signal */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
+                        /* FUNC_MODE = DIF */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
+                                        function_mode);
+                        /* IF_MODE */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
+                        /* no inv */
+                        status = cx231xx_reg_mask_write(dev,
+                                        VID_BLK_I2C_ADDRESS, 32,
+                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
+                }
+        }
+
+        return status;
+}
+
+int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
+{
+        int status = 0;
+        u32 dif_misc_ctrl_value = 0;
+        u32 func_mode = 0;
+
+        cx231xx_info("%s: setStandard to %x\n", __func__, standard);
+
+        status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
+        if (standard != DIF_USE_BASEBAND)
+                dev->norm = standard;
+
+        switch (dev->model) {
+        case CX231XX_BOARD_CNXT_CARRAERA:
+        case CX231XX_BOARD_CNXT_RDE_250:
+        case CX231XX_BOARD_CNXT_SHELBY:
+        case CX231XX_BOARD_CNXT_RDU_250:
+        case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
+        case CX231XX_BOARD_HAUPPAUGE_EXETER:
+                func_mode = 0x03;
+                break;
+        case CX231XX_BOARD_CNXT_RDE_253S:
+        case CX231XX_BOARD_CNXT_RDU_253S:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
+                func_mode = 0x01;
+                break;
+        default:
+                func_mode = 0x01;
+        }
+
+        status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
+                                                  func_mode, standard);
+
+        if (standard == DIF_USE_BASEBAND) {     /* base band */
+                /* There is a different SRC_PHASE_INC value
+                   for baseband vs. DIF */
+                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
+                status = vid_blk_read_word(dev, DIF_MISC_CTRL,
+                                                &dif_misc_ctrl_value);
+                dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
+                status = vid_blk_write_word(dev, DIF_MISC_CTRL,
+                                                dif_misc_ctrl_value);
+        } else if (standard & V4L2_STD_PAL_D) {
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
+                                           0x26001700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_RF_CURRENT, 0, 31,
+                                           0x00002660);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VIDEO_AGC_CTRL, 0, 31,
+                                           0x72500800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VID_AUD_OVERRIDE, 0, 31,
+                                           0x27000100);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_COMP_FLT_CTRL, 0, 31,
+                                           0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_PHASE_INC, 0, 31,
+                                           0x1befbf06);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_GAIN_CONTROL, 0, 31,
+                                           0x000035e8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a023F11;
+        } else if (standard & V4L2_STD_PAL_I) {
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
+                                           0x26001700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_RF_CURRENT, 0, 31,
+                                           0x00002660);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VIDEO_AGC_CTRL, 0, 31,
+                                           0x72500800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VID_AUD_OVERRIDE, 0, 31,
+                                           0x27000100);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_COMP_FLT_CTRL, 0, 31,
+                                           0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_PHASE_INC, 0, 31,
+                                           0x1befbf06);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_GAIN_CONTROL, 0, 31,
+                                           0x000035e8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a033F11;
+        } else if (standard & V4L2_STD_PAL_M) {
+                /* improved Low Frequency Phase Noise */
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
+                                                0x26001700);
+                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
+                                                0x00002660);
+                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
+                                                0x72500800);
+                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
+                                                0x27000100);
+                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
+                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
+                                                0x009f50c1);
+                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
+                                                0x1befbf06);
+                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
+                                                0x000035e8);
+                status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
+                                                0x00000000);
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3A0A3F10;
+        } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
+                /* improved Low Frequency Phase Noise */
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
+                                                0x26001700);
+                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
+                                                0x00002660);
+                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
+                                                0x72500800);
+                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
+                                                0x27000100);
+                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
+                                                0x012c405d);
+                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
+                                                0x009f50c1);
+                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
+                                                0x1befbf06);
+                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
+                                                0x000035e8);
+                status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
+                                                0x00000000);
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value = 0x3A093F10;
+        } else if (standard &
+                  (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
+                   V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
+
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_REF, 0, 31, 0x888C0380);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
+                                           0x26001700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_RF_CURRENT, 0, 31,
+                                           0x00002660);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VID_AUD_OVERRIDE, 0, 31,
+                                           0x27000100);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_COMP_FLT_CTRL, 0, 31,
+                                           0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_PHASE_INC, 0, 31,
+                                           0x1befbf06);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_GAIN_CONTROL, 0, 31,
+                                           0x000035e8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VIDEO_AGC_CTRL, 0, 31,
+                                           0xf4000000);
+
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a023F11;
+        } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
+                /* Is it SECAM_L1? */
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_REF, 0, 31, 0x888C0380);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
+                                           0x26001700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_RF_CURRENT, 0, 31,
+                                           0x00002660);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VID_AUD_OVERRIDE, 0, 31,
+                                           0x27000100);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_COMP_FLT_CTRL, 0, 31,
+                                           0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_PHASE_INC, 0, 31,
+                                           0x1befbf06);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_GAIN_CONTROL, 0, 31,
+                                           0x000035e8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VIDEO_AGC_CTRL, 0, 31,
+                                           0xf2560000);
+
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a023F11;
+
+        } else if (standard & V4L2_STD_NTSC_M) {
+                /* V4L2_STD_NTSC_M (75 IRE Setup) Or
+                   V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
+
+                /* For NTSC the centre frequency of video coming out of
+                   sidewinder is around 7.1MHz or 3.6MHz depending on the
+                   spectral inversion. so for a non spectrally inverted channel
+                   the pll freq word is 0x03420c49
+                 */
+
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
+                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
+                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
+                                                0x26001700);
+                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
+                                                0x00002660);
+                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
+                                                0x04000800);
+                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
+                                                0x27000100);
+                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
+
+                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
+                                                0x009f50c1);
+                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
+                                                0x1befbf06);
+                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
+                                                0x000035e8);
+
+                status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
+                status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
+                                                0xC2262600);
+                status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
+
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a003F10;
+        } else {
+                /* default PAL BG */
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
+                                           0x26001700);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AGC_RF_CURRENT, 0, 31,
+                                           0x00002660);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VIDEO_AGC_CTRL, 0, 31,
+                                           0x72500800);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_VID_AUD_OVERRIDE, 0, 31,
+                                           0x27000100);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_COMP_FLT_CTRL, 0, 31,
+                                           0x00A653A8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_PHASE_INC, 0, 31,
+                                           0x1befbf06);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_SRC_GAIN_CONTROL, 0, 31,
+                                           0x000035e8);
+                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
+                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
+                /* Save the Spec Inversion value */
+                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
+                dif_misc_ctrl_value |= 0x3a013F11;
+        }
+
+        /* The AGC values should be the same for all standards,
+           AUD_SRC_SEL[19] should always be disabled    */
+        dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
+
+        /* It is still possible to get Set Standard calls even when we
+           are in FM mode.
+           This is done to override the value for FM. */
+        if (dev->active_mode == V4L2_TUNER_RADIO)
+                dif_misc_ctrl_value = 0x7a080000;
+
+        /* Write the calculated value for misc ontrol register      */
+        status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
+
+        return status;
+}
+
+int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
+{
+        int status = 0;
+        u32 dwval;
+
+        /* Set the RF and IF k_agc values to 3 */
+        status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
+        dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
+        dwval |= 0x33000000;
+
+        status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
+
+        return status;
+}
+
+int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
+{
+        int status = 0;
+        u32 dwval;
+        cx231xx_info("cx231xx_tuner_post_channel_change  dev->tuner_type =0%d\n",
+                     dev->tuner_type);
+        /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
+         * SECAM L/B/D standards */
+        status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
+        dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
+
+        if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
+                         V4L2_STD_SECAM_D)) {
+                        if (dev->tuner_type == TUNER_NXP_TDA18271) {
+                                dwval &= ~FLD_DIF_IF_REF;
+                                dwval |= 0x88000300;
+                        } else
+                                dwval |= 0x88000000;
+                } else {
+                        if (dev->tuner_type == TUNER_NXP_TDA18271) {
+                                dwval &= ~FLD_DIF_IF_REF;
+                                dwval |= 0xCC000300;
+                        } else
+                                dwval |= 0x44000000;
+                }
+
+        status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
+
+        return status;
+}
+
+/******************************************************************************
+ *                  I 2 S - B L O C K    C O N T R O L   functions            *
+ ******************************************************************************/
+int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
+{
+        int status = 0;
+        u32 value;
+
+        status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                       CH_PWR_CTRL1, 1, &value, 1);
+        /* enables clock to delta-sigma and decimation filter */
+        value |= 0x80;
+        status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                        CH_PWR_CTRL1, 1, value, 1);
+        /* power up all channel */
+        status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                        CH_PWR_CTRL2, 1, 0x00, 1);
+
+        return status;
+}
+
+int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
+                                        enum AV_MODE avmode)
+{
+        int status = 0;
+        u32 value = 0;
+
+        if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
+                status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                          CH_PWR_CTRL2, 1, &value, 1);
+                value |= 0xfe;
+                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                                CH_PWR_CTRL2, 1, value, 1);
+        } else {
+                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                                CH_PWR_CTRL2, 1, 0x00, 1);
+        }
+
+        return status;
+}
+
+/* set i2s_blk for audio input types */
+int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
+{
+        int status = 0;
+
+        switch (audio_input) {
+        case CX231XX_AMUX_LINE_IN:
+                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                                CH_PWR_CTRL2, 1, 0x00, 1);
+                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                                CH_PWR_CTRL1, 1, 0x80, 1);
+                break;
+        case CX231XX_AMUX_VIDEO:
+        default:
+                break;
+        }
+
+        dev->ctl_ainput = audio_input;
+
+        return status;
+}
+
+/******************************************************************************
+ *                  P O W E R      C O N T R O L   functions                  *
+ ******************************************************************************/
+int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
+{
+        u8 value[4] = { 0, 0, 0, 0 };
+        u32 tmp = 0;
+        int status = 0;
+
+        if (dev->power_mode != mode)
+                dev->power_mode = mode;
+        else {
+                cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
+                             mode);
+                return 0;
+        }
+
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
+                                       4);
+        if (status < 0)
+                return status;
+
+        tmp = *((u32 *) value);
+
+        switch (mode) {
+        case POLARIS_AVMODE_ENXTERNAL_AV:
+
+                tmp &= (~PWR_MODE_MASK);
+
+                tmp |= PWR_AV_EN;
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                msleep(PWR_SLEEP_INTERVAL);
+
+                tmp |= PWR_ISO_EN;
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status =
+                    cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
+                                           value, 4);
+                msleep(PWR_SLEEP_INTERVAL);
+
+                tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+
+                /* reset state of xceive tuner */
+                dev->xc_fw_load_done = 0;
+                break;
+
+        case POLARIS_AVMODE_ANALOGT_TV:
+
+                tmp |= PWR_DEMOD_EN;
+                tmp |= (I2C_DEMOD_EN);
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                msleep(PWR_SLEEP_INTERVAL);
+
+                if (!(tmp & PWR_TUNER_EN)) {
+                        tmp |= (PWR_TUNER_EN);
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+
+                if (!(tmp & PWR_AV_EN)) {
+                        tmp |= PWR_AV_EN;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+                if (!(tmp & PWR_ISO_EN)) {
+                        tmp |= PWR_ISO_EN;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+
+                if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
+                        tmp |= POLARIS_AVMODE_ANALOGT_TV;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+
+                if (dev->board.tuner_type != TUNER_ABSENT) {
+                        /* Enable tuner */
+                        cx231xx_enable_i2c_port_3(dev, true);
+
+                        /* reset the Tuner */
+                        if (dev->board.tuner_gpio)
+                                cx231xx_gpio_set(dev, dev->board.tuner_gpio);
+
+                        if (dev->cx231xx_reset_analog_tuner)
+                                dev->cx231xx_reset_analog_tuner(dev);
+                }
+
+                break;
+
+        case POLARIS_AVMODE_DIGITAL:
+                if (!(tmp & PWR_TUNER_EN)) {
+                        tmp |= (PWR_TUNER_EN);
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+                if (!(tmp & PWR_AV_EN)) {
+                        tmp |= PWR_AV_EN;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+                if (!(tmp & PWR_ISO_EN)) {
+                        tmp |= PWR_ISO_EN;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+
+                tmp &= (~PWR_AV_MODE);
+                tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                msleep(PWR_SLEEP_INTERVAL);
+
+                if (!(tmp & PWR_DEMOD_EN)) {
+                        tmp |= PWR_DEMOD_EN;
+                        value[0] = (u8) tmp;
+                        value[1] = (u8) (tmp >> 8);
+                        value[2] = (u8) (tmp >> 16);
+                        value[3] = (u8) (tmp >> 24);
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                        PWR_CTL_EN, value, 4);
+                        msleep(PWR_SLEEP_INTERVAL);
+                }
+
+                if (dev->board.tuner_type != TUNER_ABSENT) {
+                        /*
+                         * Enable tuner
+                         *      Hauppauge Exeter seems to need to do something different!
+                         */
+                        if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)
+                                cx231xx_enable_i2c_port_3(dev, false);
+                        else
+                                cx231xx_enable_i2c_port_3(dev, true);
+
+                        /* reset the Tuner */
+                        if (dev->board.tuner_gpio)
+                                cx231xx_gpio_set(dev, dev->board.tuner_gpio);
+
+                        if (dev->cx231xx_reset_analog_tuner)
+                                dev->cx231xx_reset_analog_tuner(dev);
+                }
+                break;
+
+        default:
+                break;
+        }
+
+        msleep(PWR_SLEEP_INTERVAL);
+
+        /* For power saving, only enable Pwr_resetout_n
+           when digital TV is selected. */
+        if (mode == POLARIS_AVMODE_DIGITAL) {
+                tmp |= PWR_RESETOUT_EN;
+                value[0] = (u8) tmp;
+                value[1] = (u8) (tmp >> 8);
+                value[2] = (u8) (tmp >> 16);
+                value[3] = (u8) (tmp >> 24);
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                msleep(PWR_SLEEP_INTERVAL);
+        }
+
+        /* update power control for afe */
+        status = cx231xx_afe_update_power_control(dev, mode);
+
+        /* update power control for i2s_blk */
+        status = cx231xx_i2s_blk_update_power_control(dev, mode);
+
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
+                                       4);
+
+        return status;
+}
+
+int cx231xx_power_suspend(struct cx231xx *dev)
+{
+        u8 value[4] = { 0, 0, 0, 0 };
+        u32 tmp = 0;
+        int status = 0;
+
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
+                                       value, 4);
+        if (status > 0)
+                return status;
+
+        tmp = *((u32 *) value);
+        tmp &= (~PWR_MODE_MASK);
+
+        value[0] = (u8) tmp;
+        value[1] = (u8) (tmp >> 8);
+        value[2] = (u8) (tmp >> 16);
+        value[3] = (u8) (tmp >> 24);
+        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
+                                        value, 4);
+
+        return status;
+}
+
+/******************************************************************************
+ *                  S T R E A M    C O N T R O L   functions                  *
+ ******************************************************************************/
+int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
+{
+        u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
+        u32 tmp = 0;
+        int status = 0;
+
+        cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
+                                       value, 4);
+        if (status < 0)
+                return status;
+
+        tmp = *((u32 *) value);
+        tmp |= ep_mask;
+        value[0] = (u8) tmp;
+        value[1] = (u8) (tmp >> 8);
+        value[2] = (u8) (tmp >> 16);
+        value[3] = (u8) (tmp >> 24);
+
+        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
+                                        value, 4);
+
+        return status;
+}
+
+int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
+{
+        u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
+        u32 tmp = 0;
+        int status = 0;
+
+        cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
+        status =
+            cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
+        if (status < 0)
+                return status;
+
+        tmp = *((u32 *) value);
+        tmp &= (~ep_mask);
+        value[0] = (u8) tmp;
+        value[1] = (u8) (tmp >> 8);
+        value[2] = (u8) (tmp >> 16);
+        value[3] = (u8) (tmp >> 24);
+
+        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
+                                        value, 4);
+
+        return status;
+}
+
+int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
+{
+        int status = 0;
+        u32 value = 0;
+        u8 val[4] = { 0, 0, 0, 0 };
+
+        if (dev->udev->speed == USB_SPEED_HIGH) {
+                switch (media_type) {
+                case Audio:
+                        cx231xx_info("%s: Audio enter HANC\n", __func__);
+                        status =
+                            cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
+                        break;
+
+                case Vbi:
+                        cx231xx_info("%s: set vanc registers\n", __func__);
+                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
+                        break;
+
+                case Sliced_cc:
+                        cx231xx_info("%s: set hanc registers\n", __func__);
+                        status =
+                            cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
+                        break;
+
+                case Raw_Video:
+                        cx231xx_info("%s: set video registers\n", __func__);
+                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
+                        break;
+
+                case TS1_serial_mode:
+                        cx231xx_info("%s: set ts1 registers", __func__);
+
+                if (dev->board.has_417) {
+                        cx231xx_info(" MPEG\n");
+                        value &= 0xFFFFFFFC;
+                        value |= 0x3;
+
+                        status = cx231xx_mode_register(dev, TS_MODE_REG, value);
+
+                        val[0] = 0x04;
+                        val[1] = 0xA3;
+                        val[2] = 0x3B;
+                        val[3] = 0x00;
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                 TS1_CFG_REG, val, 4);
+
+                        val[0] = 0x00;
+                        val[1] = 0x08;
+                        val[2] = 0x00;
+                        val[3] = 0x08;
+                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                 TS1_LENGTH_REG, val, 4);
+
+                } else {
+                        cx231xx_info(" BDA\n");
+                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
+                        status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
+                }
+                        break;
+
+                case TS1_parallel_mode:
+                        cx231xx_info("%s: set ts1 parallel mode registers\n",
+                                     __func__);
+                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
+                        status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
+                        break;
+                }
+        } else {
+                status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
+        }
+
+        return status;
+}
+
+int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
+{
+        int rc = -1;
+        u32 ep_mask = -1;
+        struct pcb_config *pcb_config;
+
+        /* get EP for media type */
+        pcb_config = (struct pcb_config *)&dev->current_pcb_config;
+
+        if (pcb_config->config_num) {
+                switch (media_type) {
+                case Raw_Video:
+                        ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
+                        break;
+                case Audio:
+                        ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
+                        break;
+                case Vbi:
+                        ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
+                        break;
+                case Sliced_cc:
+                        ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
+                        break;
+                case TS1_serial_mode:
+                case TS1_parallel_mode:
+                        ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
+                        break;
+                case TS2:
+                        ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
+                        break;
+                }
+        }
+
+        if (start) {
+                rc = cx231xx_initialize_stream_xfer(dev, media_type);
+
+                if (rc < 0)
+                        return rc;
+
+                /* enable video capture */
+                if (ep_mask > 0)
+                        rc = cx231xx_start_stream(dev, ep_mask);
+        } else {
+                /* disable video capture */
+                if (ep_mask > 0)
+                        rc = cx231xx_stop_stream(dev, ep_mask);
+        }
+
+        if (dev->mode == CX231XX_ANALOG_MODE)
+                ;/* do any in Analog mode */
+        else
+                ;/* do any in digital mode */
+
+        return rc;
+}
+EXPORT_SYMBOL_GPL(cx231xx_capture_start);
+
+/*****************************************************************************
+*                   G P I O   B I T control functions                        *
+******************************************************************************/
+int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
+{
+        int status = 0;
+
+        status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
+
+        return status;
+}
+
+int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
+{
+        int status = 0;
+
+        status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
+
+        return status;
+}
+
+/*
+* cx231xx_set_gpio_direction
+*      Sets the direction of the GPIO pin to input or output
+*
+* Parameters :
+*      pin_number : The GPIO Pin number to program the direction for
+*                   from 0 to 31
+*      pin_value : The Direction of the GPIO Pin under reference.
+*                      0 = Input direction
+*                      1 = Output direction
+*/
+int cx231xx_set_gpio_direction(struct cx231xx *dev,
+                               int pin_number, int pin_value)
+{
+        int status = 0;
+        u32 value = 0;
+
+        /* Check for valid pin_number - if 32 , bail out */
+        if (pin_number >= 32)
+                return -EINVAL;
+
+        /* input */
+        if (pin_value == 0)
+                value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
+        else
+                value = dev->gpio_dir | (1 << pin_number);
+
+        status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
+
+        /* cache the value for future */
+        dev->gpio_dir = value;
+
+        return status;
+}
+
+/*
+* cx231xx_set_gpio_value
+*      Sets the value of the GPIO pin to Logic high or low. The Pin under
+*      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
+*
+* Parameters :
+*      pin_number : The GPIO Pin number to program the direction for
+*      pin_value : The value of the GPIO Pin under reference.
+*                      0 = set it to 0
+*                      1 = set it to 1
+*/
+int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
+{
+        int status = 0;
+        u32 value = 0;
+
+        /* Check for valid pin_number - if 0xFF , bail out */
+        if (pin_number >= 32)
+                return -EINVAL;
+
+        /* first do a sanity check - if the Pin is not output, make it output */
+        if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
+                /* It was in input mode */
+                value = dev->gpio_dir | (1 << pin_number);
+                dev->gpio_dir = value;
+                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                              (u8 *) &dev->gpio_val);
+                value = 0;
+        }
+
+        if (pin_value == 0)
+                value = dev->gpio_val & (~(1 << pin_number));
+        else
+                value = dev->gpio_val | (1 << pin_number);
+
+        /* store the value */
+        dev->gpio_val = value;
+
+        /* toggle bit0 of GP_IO */
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        return status;
+}
+
+/*****************************************************************************
+*                      G P I O I2C related functions                         *
+******************************************************************************/
+int cx231xx_gpio_i2c_start(struct cx231xx *dev)
+{
+        int status = 0;
+
+        /* set SCL to output 1 ; set SDA to output 1 */
+        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
+        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
+
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        /* set SCL to output 1; set SDA to output 0 */
+        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        /* set SCL to output 0; set SDA to output 0      */
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        return status;
+}
+
+int cx231xx_gpio_i2c_end(struct cx231xx *dev)
+{
+        int status = 0;
+
+        /* set SCL to output 0; set SDA to output 0      */
+        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
+
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        /* set SCL to output 1; set SDA to output 0      */
+        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        /* set SCL to input ,release SCL cable control
+           set SDA to input ,release SDA cable control */
+        dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
+        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
+
+        status =
+            cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+        if (status < 0)
+                return -EINVAL;
+
+        return status;
+}
+
+int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
+{
+        int status = 0;
+        u8 i;
+
+        /* set SCL to output ; set SDA to output */
+        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
+
+        for (i = 0; i < 8; i++) {
+                if (((data << i) & 0x80) == 0) {
+                        /* set SCL to output 0; set SDA to output 0     */
+                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+                        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+
+                        /* set SCL to output 1; set SDA to output 0     */
+                        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+
+                        /* set SCL to output 0; set SDA to output 0     */
+                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+                } else {
+                        /* set SCL to output 0; set SDA to output 1     */
+                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+                        dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+
+                        /* set SCL to output 1; set SDA to output 1     */
+                        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+
+                        /* set SCL to output 0; set SDA to output 1     */
+                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                                      (u8 *)&dev->gpio_val);
+                }
+        }
+        return status;
+}
+
+int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
+{
+        u8 value = 0;
+        int status = 0;
+        u32 gpio_logic_value = 0;
+        u8 i;
+
+        /* read byte */
+        for (i = 0; i < 8; i++) {       /* send write I2c addr */
+
+                /* set SCL to output 0; set SDA to input */
+                dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                              (u8 *)&dev->gpio_val);
+
+                /* set SCL to output 1; set SDA to input */
+                dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
+                                              (u8 *)&dev->gpio_val);
+
+                /* get SDA data bit */
+                gpio_logic_value = dev->gpio_val;
+                status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
+                                              (u8 *)&dev->gpio_val);
+                if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
+                        value |= (1 << (8 - i - 1));
+
+                dev->gpio_val = gpio_logic_value;
+        }
+
+        /* set SCL to output 0,finish the read latest SCL signal.
+           !!!set SDA to input, never to modify SDA direction at
+           the same times */
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* store the value */
+        *buf = value & 0xff;
+
+        return status;
+}
+
+int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
+{
+        int status = 0;
+        u32 gpio_logic_value = 0;
+        int nCnt = 10;
+        int nInit = nCnt;
+
+        /* clock stretch; set SCL to input; set SDA to input;
+           get SCL value till SCL = 1 */
+        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
+        dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
+
+        gpio_logic_value = dev->gpio_val;
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        do {
+                msleep(2);
+                status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
+                                              (u8 *)&dev->gpio_val);
+                nCnt--;
+        } while (((dev->gpio_val &
+                          (1 << dev->board.tuner_scl_gpio)) == 0) &&
+                         (nCnt > 0));
+
+        if (nCnt == 0)
+                cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
+                             nInit * 10);
+
+        /*
+         * readAck
+         * through clock stretch, slave has given a SCL signal,
+         * so the SDA data can be directly read.
+         */
+        status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
+                dev->gpio_val = gpio_logic_value;
+                dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+                status = 0;
+        } else {
+                dev->gpio_val = gpio_logic_value;
+                dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
+        }
+
+        /* read SDA end, set the SCL to output 0, after this operation,
+           SDA direction can be changed. */
+        dev->gpio_val = gpio_logic_value;
+        dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        return status;
+}
+
+int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
+{
+        int status = 0;
+
+        /* set SDA to ouput */
+        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set SCL = 0 (output); set SDA = 0 (output) */
+        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set SCL = 1 (output); set SDA = 0 (output) */
+        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set SCL = 0 (output); set SDA = 0 (output) */
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set SDA to input,and then the slave will read data from SDA. */
+        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        return status;
+}
+
+int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
+{
+        int status = 0;
+
+        /* set scl to output ; set sda to input */
+        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
+        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set scl to output 0; set sda to input */
+        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        /* set scl to output 1; set sda to input */
+        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
+        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
+
+        return status;
+}
+
+/*****************************************************************************
+*                      G P I O I2C related functions                         *
+******************************************************************************/
+/* cx231xx_gpio_i2c_read
+ * Function to read data from gpio based I2C interface
+ */
+int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
+{
+        int status = 0;
+        int i = 0;
+
+        /* get the lock */
+        mutex_lock(&dev->gpio_i2c_lock);
+
+        /* start */
+        status = cx231xx_gpio_i2c_start(dev);
+
+        /* write dev_addr */
+        status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
+
+        /* readAck */
+        status = cx231xx_gpio_i2c_read_ack(dev);
+
+        /* read data */
+        for (i = 0; i < len; i++) {
+                /* read data */
+                buf[i] = 0;
+                status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
+
+                if ((i + 1) != len) {
+                        /* only do write ack if we more length */
+                        status = cx231xx_gpio_i2c_write_ack(dev);
+                }
+        }
+
+        /* write NAK - inform reads are complete */
+        status = cx231xx_gpio_i2c_write_nak(dev);
+
+        /* write end */
+        status = cx231xx_gpio_i2c_end(dev);
+
+        /* release the lock */
+        mutex_unlock(&dev->gpio_i2c_lock);
+
+        return status;
+}
+
+/* cx231xx_gpio_i2c_write
+ * Function to write data to gpio based I2C interface
+ */
+int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
+{
+        int i = 0;
+
+        /* get the lock */
+        mutex_lock(&dev->gpio_i2c_lock);
+
+        /* start */
+        cx231xx_gpio_i2c_start(dev);
+
+        /* write dev_addr */
+        cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
+
+        /* read Ack */
+        cx231xx_gpio_i2c_read_ack(dev);
+
+        for (i = 0; i < len; i++) {
+                /* Write data */
+                cx231xx_gpio_i2c_write_byte(dev, buf[i]);
+
+                /* read Ack */
+                cx231xx_gpio_i2c_read_ack(dev);
+        }
+
+        /* write End */
+        cx231xx_gpio_i2c_end(dev);
+
+        /* release the lock */
+        mutex_unlock(&dev->gpio_i2c_lock);
+
+        return 0;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-cards.c b/drivers/media/usb/cx231xx/cx231xx-cards.c
new file mode 100644
index 000000000000..02d4d36735d3
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-cards.c
@@ -0,0 +1,1370 @@
+/*
+   cx231xx-cards.c - driver for Conexant Cx23100/101/102
+                                USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+                                Based on em28xx driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/usb.h>
+#include <media/tuner.h>
+#include <media/tveeprom.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-chip-ident.h>
+
+#include <media/cx25840.h>
+#include "dvb-usb-ids.h"
+#include "xc5000.h"
+#include "tda18271.h"
+
+#include "cx231xx.h"
+
+static int tuner = -1;
+module_param(tuner, int, 0444);
+MODULE_PARM_DESC(tuner, "tuner type");
+
+static int transfer_mode = 1;
+module_param(transfer_mode, int, 0444);
+MODULE_PARM_DESC(transfer_mode, "transfer mode (1-ISO or 0-BULK)");
+
+static unsigned int disable_ir;
+module_param(disable_ir, int, 0444);
+MODULE_PARM_DESC(disable_ir, "disable infrared remote support");
+
+/* Bitmask marking allocated devices from 0 to CX231XX_MAXBOARDS */
+static unsigned long cx231xx_devused;
+
+/*
+ *  Reset sequences for analog/digital modes
+ */
+
+static struct cx231xx_reg_seq RDE250_XCV_TUNER[] = {
+        {0x03, 0x01, 10},
+        {0x03, 0x00, 30},
+        {0x03, 0x01, 10},
+        {-1, -1, -1},
+};
+
+/*
+ *  Board definitions
+ */
+struct cx231xx_board cx231xx_boards[] = {
+        [CX231XX_BOARD_UNKNOWN] = {
+                .name = "Unknown CX231xx video grabber",
+                .tuner_type = TUNER_ABSENT,
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_3_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_CARRAERA] = {
+                .name = "Conexant Hybrid TV - CARRAERA",
+                .tuner_type = TUNER_XC5000,
+                .tuner_addr = 0x61,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x02,
+                .norm = V4L2_STD_PAL,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_3_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_SHELBY] = {
+                .name = "Conexant Hybrid TV - SHELBY",
+                .tuner_type = TUNER_XC5000,
+                .tuner_addr = 0x61,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x32,
+                .norm = V4L2_STD_NTSC,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_3_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_RDE_253S] = {
+                .name = "Conexant Hybrid TV - RDE253S",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x1c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x02,
+                .norm = V4L2_STD_PAL,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_3_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+
+        [CX231XX_BOARD_CNXT_RDU_253S] = {
+                .name = "Conexant Hybrid TV - RDU253S",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x1c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x02,
+                .norm = V4L2_STD_PAL,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_3_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_VIDEO_GRABBER] = {
+                .name = "Conexant VIDEO GRABBER",
+                .tuner_type = TUNER_ABSENT,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x1c,
+                .gpio_pin_status_mask = 0x4001000,
+                .norm = V4L2_STD_PAL,
+                .no_alt_vanc = 1,
+                .external_av = 1,
+                .has_417 = 1,
+
+                .input = {{
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_RDE_250] = {
+                .name = "Conexant Hybrid TV - rde 250",
+                .tuner_type = TUNER_XC5000,
+                .tuner_addr = 0x61,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x02,
+                .norm = V4L2_STD_PAL,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_CNXT_RDU_250] = {
+                .name = "Conexant Hybrid TV - RDU 250",
+                .tuner_type = TUNER_XC5000,
+                .tuner_addr = 0x61,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x32,
+                .norm = V4L2_STD_NTSC,
+
+                .input = {{
+                                .type = CX231XX_VMUX_TELEVISION,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_VIDEO,
+                                .gpio = NULL,
+                        }
+                },
+        },
+        [CX231XX_BOARD_HAUPPAUGE_EXETER] = {
+                .name = "Hauppauge EXETER",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .demod_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x0e,
+                .norm = V4L2_STD_NTSC,
+
+                .input = {{
+                        .type = CX231XX_VMUX_TELEVISION,
+                        .vmux = CX231XX_VIN_3_1,
+                        .amux = CX231XX_AMUX_VIDEO,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_HAUPPAUGE_USBLIVE2] = {
+                .name = "Hauppauge USB Live 2",
+                .tuner_type = TUNER_ABSENT,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .norm = V4L2_STD_NTSC,
+                .no_alt_vanc = 1,
+                .external_av = 1,
+                .dont_use_port_3 = 1,
+                .input = {{
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_KWORLD_UB430_USB_HYBRID] = {
+                .name = "Kworld UB430 USB Hybrid",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x11, /* According with PV cxPolaris.inf file */
+                .tuner_sif_gpio = -1,
+                .tuner_scl_gpio = -1,
+                .tuner_sda_gpio = -1,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 2,
+                .demod_i2c_master = 1,
+                .ir_i2c_master = 2,
+                .has_dvb = 1,
+                .demod_addr = 0x10,
+                .norm = V4L2_STD_PAL_M,
+                .input = {{
+                        .type = CX231XX_VMUX_TELEVISION,
+                        .vmux = CX231XX_VIN_3_1,
+                        .amux = CX231XX_AMUX_VIDEO,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_PV_PLAYTV_USB_HYBRID] = {
+                .name = "Pixelview PlayTV USB Hybrid",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x00, /* According with PV cxPolaris.inf file */
+                .tuner_sif_gpio = -1,
+                .tuner_scl_gpio = -1,
+                .tuner_sda_gpio = -1,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 2,
+                .demod_i2c_master = 1,
+                .ir_i2c_master = 2,
+                .rc_map_name = RC_MAP_PIXELVIEW_002T,
+                .has_dvb = 1,
+                .demod_addr = 0x10,
+                .norm = V4L2_STD_PAL_M,
+                .input = {{
+                        .type = CX231XX_VMUX_TELEVISION,
+                        .vmux = CX231XX_VIN_3_1,
+                        .amux = CX231XX_AMUX_VIDEO,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_PV_XCAPTURE_USB] = {
+                .name = "Pixelview Xcapture USB",
+                .tuner_type = TUNER_ABSENT,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .norm = V4L2_STD_NTSC,
+                .no_alt_vanc = 1,
+                .external_av = 1,
+                .dont_use_port_3 = 1,
+
+                .input = {{
+                                .type = CX231XX_VMUX_COMPOSITE1,
+                                .vmux = CX231XX_VIN_2_1,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }, {
+                                .type = CX231XX_VMUX_SVIDEO,
+                                .vmux = CX231XX_VIN_1_1 |
+                                        (CX231XX_VIN_1_2 << 8) |
+                                        CX25840_SVIDEO_ON,
+                                .amux = CX231XX_AMUX_LINE_IN,
+                                .gpio = NULL,
+                        }
+                },
+        },
+
+        [CX231XX_BOARD_ICONBIT_U100] = {
+                .name = "Iconbit Analog Stick U100 FM",
+                .tuner_type = TUNER_ABSENT,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .demod_xfer_mode = 0,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x1C,
+                .gpio_pin_status_mask = 0x4001000,
+
+                .input = {{
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL] = {
+                .name = "Hauppauge WinTV USB2 FM (PAL)",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .norm = V4L2_STD_PAL,
+
+                .input = {{
+                        .type = CX231XX_VMUX_TELEVISION,
+                        .vmux = CX231XX_VIN_3_1,
+                        .amux = CX231XX_AMUX_VIDEO,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+        [CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC] = {
+                .name = "Hauppauge WinTV USB2 FM (NTSC)",
+                .tuner_type = TUNER_NXP_TDA18271,
+                .tuner_addr = 0x60,
+                .tuner_gpio = RDE250_XCV_TUNER,
+                .tuner_sif_gpio = 0x05,
+                .tuner_scl_gpio = 0x1a,
+                .tuner_sda_gpio = 0x1b,
+                .decoder = CX231XX_AVDECODER,
+                .output_mode = OUT_MODE_VIP11,
+                .ctl_pin_status_mask = 0xFFFFFFC4,
+                .agc_analog_digital_select_gpio = 0x0c,
+                .gpio_pin_status_mask = 0x4001000,
+                .tuner_i2c_master = 1,
+                .norm = V4L2_STD_NTSC,
+
+                .input = {{
+                        .type = CX231XX_VMUX_TELEVISION,
+                        .vmux = CX231XX_VIN_3_1,
+                        .amux = CX231XX_AMUX_VIDEO,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_COMPOSITE1,
+                        .vmux = CX231XX_VIN_2_1,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                }, {
+                        .type = CX231XX_VMUX_SVIDEO,
+                        .vmux = CX231XX_VIN_1_1 |
+                                (CX231XX_VIN_1_2 << 8) |
+                                CX25840_SVIDEO_ON,
+                        .amux = CX231XX_AMUX_LINE_IN,
+                        .gpio = NULL,
+                } },
+        },
+};
+const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
+
+/* table of devices that work with this driver */
+struct usb_device_id cx231xx_id_table[] = {
+        {USB_DEVICE(0x0572, 0x5A3C),
+         .driver_info = CX231XX_BOARD_UNKNOWN},
+        {USB_DEVICE(0x0572, 0x58A2),
+         .driver_info = CX231XX_BOARD_CNXT_CARRAERA},
+        {USB_DEVICE(0x0572, 0x58A1),
+         .driver_info = CX231XX_BOARD_CNXT_SHELBY},
+        {USB_DEVICE(0x0572, 0x58A4),
+         .driver_info = CX231XX_BOARD_CNXT_RDE_253S},
+        {USB_DEVICE(0x0572, 0x58A5),
+         .driver_info = CX231XX_BOARD_CNXT_RDU_253S},
+        {USB_DEVICE(0x0572, 0x58A6),
+         .driver_info = CX231XX_BOARD_CNXT_VIDEO_GRABBER},
+        {USB_DEVICE(0x0572, 0x589E),
+         .driver_info = CX231XX_BOARD_CNXT_RDE_250},
+        {USB_DEVICE(0x0572, 0x58A0),
+         .driver_info = CX231XX_BOARD_CNXT_RDU_250},
+        {USB_DEVICE(0x2040, 0xb110),
+         .driver_info = CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL},
+        {USB_DEVICE(0x2040, 0xb111),
+         .driver_info = CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC},
+        {USB_DEVICE(0x2040, 0xb120),
+         .driver_info = CX231XX_BOARD_HAUPPAUGE_EXETER},
+        {USB_DEVICE(0x2040, 0xb140),
+         .driver_info = CX231XX_BOARD_HAUPPAUGE_EXETER},
+        {USB_DEVICE(0x2040, 0xc200),
+         .driver_info = CX231XX_BOARD_HAUPPAUGE_USBLIVE2},
+        {USB_DEVICE_VER(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD, 0x4000, 0x4001),
+         .driver_info = CX231XX_BOARD_PV_PLAYTV_USB_HYBRID},
+        {USB_DEVICE(USB_VID_PIXELVIEW, 0x5014),
+         .driver_info = CX231XX_BOARD_PV_XCAPTURE_USB},
+        {USB_DEVICE(0x1b80, 0xe424),
+         .driver_info = CX231XX_BOARD_KWORLD_UB430_USB_HYBRID},
+        {USB_DEVICE(0x1f4d, 0x0237),
+         .driver_info = CX231XX_BOARD_ICONBIT_U100},
+        {},
+};
+
+MODULE_DEVICE_TABLE(usb, cx231xx_id_table);
+
+/* cx231xx_tuner_callback
+ * will be used to reset XC5000 tuner using GPIO pin
+ */
+
+int cx231xx_tuner_callback(void *ptr, int component, int command, int arg)
+{
+        int rc = 0;
+        struct cx231xx *dev = ptr;
+
+        if (dev->tuner_type == TUNER_XC5000) {
+                if (command == XC5000_TUNER_RESET) {
+                        cx231xx_info
+                                ("Tuner CB: RESET: cmd %d : tuner type %d \n",
+                                 command, dev->tuner_type);
+                        cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
+                                               1);
+                        msleep(10);
+                        cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
+                                               0);
+                        msleep(330);
+                        cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
+                                               1);
+                        msleep(10);
+                }
+        } else if (dev->tuner_type == TUNER_NXP_TDA18271) {
+                switch (command) {
+                case TDA18271_CALLBACK_CMD_AGC_ENABLE:
+                        if (dev->model == CX231XX_BOARD_PV_PLAYTV_USB_HYBRID)
+                                rc = cx231xx_set_agc_analog_digital_mux_select(dev, arg);
+                        break;
+                default:
+                        rc = -EINVAL;
+                        break;
+                }
+        }
+        return rc;
+}
+EXPORT_SYMBOL_GPL(cx231xx_tuner_callback);
+
+void cx231xx_reset_out(struct cx231xx *dev)
+{
+        cx231xx_set_gpio_value(dev, CX23417_RESET, 1);
+        msleep(200);
+        cx231xx_set_gpio_value(dev, CX23417_RESET, 0);
+        msleep(200);
+        cx231xx_set_gpio_value(dev, CX23417_RESET, 1);
+}
+void cx231xx_enable_OSC(struct cx231xx *dev)
+{
+        cx231xx_set_gpio_value(dev, CX23417_OSC_EN, 1);
+}
+void cx231xx_sleep_s5h1432(struct cx231xx *dev)
+{
+        cx231xx_set_gpio_value(dev, SLEEP_S5H1432, 0);
+}
+
+static inline void cx231xx_set_model(struct cx231xx *dev)
+{
+        memcpy(&dev->board, &cx231xx_boards[dev->model], sizeof(dev->board));
+}
+
+/* Since cx231xx_pre_card_setup() requires a proper dev->model,
+ * this won't work for boards with generic PCI IDs
+ */
+void cx231xx_pre_card_setup(struct cx231xx *dev)
+{
+
+        cx231xx_set_model(dev);
+
+        cx231xx_info("Identified as %s (card=%d)\n",
+                     dev->board.name, dev->model);
+
+        /* set the direction for GPIO pins */
+        if (dev->board.tuner_gpio) {
+                cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
+                cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
+        }
+        if (dev->board.tuner_sif_gpio >= 0)
+                cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
+
+        /* request some modules if any required */
+
+        /* set the mode to Analog mode initially */
+        cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
+
+        /* Unlock device */
+        /* cx231xx_set_mode(dev, CX231XX_SUSPEND); */
+
+}
+
+static void cx231xx_config_tuner(struct cx231xx *dev)
+{
+        struct tuner_setup tun_setup;
+        struct v4l2_frequency f;
+
+        if (dev->tuner_type == TUNER_ABSENT)
+                return;
+
+        tun_setup.mode_mask = T_ANALOG_TV | T_RADIO;
+        tun_setup.type = dev->tuner_type;
+        tun_setup.addr = dev->tuner_addr;
+        tun_setup.tuner_callback = cx231xx_tuner_callback;
+
+        tuner_call(dev, tuner, s_type_addr, &tun_setup);
+
+#if 0
+        if (tun_setup.type == TUNER_XC5000) {
+                static struct xc2028_ctrl ctrl = {
+                        .fname = XC5000_DEFAULT_FIRMWARE,
+                        .max_len = 64,
+                        .demod = 0;
+                };
+                struct v4l2_priv_tun_config cfg = {
+                        .tuner = dev->tuner_type,
+                        .priv = &ctrl,
+                };
+                tuner_call(dev, tuner, s_config, &cfg);
+        }
+#endif
+        /* configure tuner */
+        f.tuner = 0;
+        f.type = V4L2_TUNER_ANALOG_TV;
+        f.frequency = 9076;     /* just a magic number */
+        dev->ctl_freq = f.frequency;
+        call_all(dev, tuner, s_frequency, &f);
+
+}
+
+void cx231xx_card_setup(struct cx231xx *dev)
+{
+
+        cx231xx_set_model(dev);
+
+        dev->tuner_type = cx231xx_boards[dev->model].tuner_type;
+        if (cx231xx_boards[dev->model].tuner_addr)
+                dev->tuner_addr = cx231xx_boards[dev->model].tuner_addr;
+
+        /* request some modules */
+        if (dev->board.decoder == CX231XX_AVDECODER) {
+                dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
+                                        &dev->i2c_bus[0].i2c_adap,
+                                        "cx25840", 0x88 >> 1, NULL);
+                if (dev->sd_cx25840 == NULL)
+                        cx231xx_info("cx25840 subdev registration failure\n");
+                cx25840_call(dev, core, load_fw);
+
+        }
+
+        /* Initialize the tuner */
+        if (dev->board.tuner_type != TUNER_ABSENT) {
+                dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev,
+                                                    &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                                                    "tuner",
+                                                    dev->tuner_addr, NULL);
+                if (dev->sd_tuner == NULL)
+                        cx231xx_info("tuner subdev registration failure\n");
+                else
+                        cx231xx_config_tuner(dev);
+        }
+}
+
+/*
+ * cx231xx_config()
+ * inits registers with sane defaults
+ */
+int cx231xx_config(struct cx231xx *dev)
+{
+        /* TBD need to add cx231xx specific code */
+        dev->mute = 1;          /* maybe not the right place... */
+        dev->volume = 0x1f;
+
+        return 0;
+}
+
+/*
+ * cx231xx_config_i2c()
+ * configure i2c attached devices
+ */
+void cx231xx_config_i2c(struct cx231xx *dev)
+{
+        /* u32 input = INPUT(dev->video_input)->vmux; */
+
+        call_all(dev, video, s_stream, 1);
+}
+
+/*
+ * cx231xx_realease_resources()
+ * unregisters the v4l2,i2c and usb devices
+ * called when the device gets disconected or at module unload
+*/
+void cx231xx_release_resources(struct cx231xx *dev)
+{
+        cx231xx_release_analog_resources(dev);
+
+        cx231xx_remove_from_devlist(dev);
+
+        cx231xx_ir_exit(dev);
+
+        /* Release I2C buses */
+        cx231xx_dev_uninit(dev);
+
+        /* delete v4l2 device */
+        v4l2_device_unregister(&dev->v4l2_dev);
+
+        usb_put_dev(dev->udev);
+
+        /* Mark device as unused */
+        clear_bit(dev->devno, &cx231xx_devused);
+
+        kfree(dev->video_mode.alt_max_pkt_size);
+        kfree(dev->vbi_mode.alt_max_pkt_size);
+        kfree(dev->sliced_cc_mode.alt_max_pkt_size);
+        kfree(dev->ts1_mode.alt_max_pkt_size);
+        kfree(dev);
+}
+
+/*
+ * cx231xx_init_dev()
+ * allocates and inits the device structs, registers i2c bus and v4l device
+ */
+static int cx231xx_init_dev(struct cx231xx *dev, struct usb_device *udev,
+                            int minor)
+{
+        int retval = -ENOMEM;
+        int errCode;
+        unsigned int maxh, maxw;
+
+        dev->udev = udev;
+        mutex_init(&dev->lock);
+        mutex_init(&dev->ctrl_urb_lock);
+        mutex_init(&dev->gpio_i2c_lock);
+        mutex_init(&dev->i2c_lock);
+
+        spin_lock_init(&dev->video_mode.slock);
+        spin_lock_init(&dev->vbi_mode.slock);
+        spin_lock_init(&dev->sliced_cc_mode.slock);
+
+        init_waitqueue_head(&dev->open);
+        init_waitqueue_head(&dev->wait_frame);
+        init_waitqueue_head(&dev->wait_stream);
+
+        dev->cx231xx_read_ctrl_reg = cx231xx_read_ctrl_reg;
+        dev->cx231xx_write_ctrl_reg = cx231xx_write_ctrl_reg;
+        dev->cx231xx_send_usb_command = cx231xx_send_usb_command;
+        dev->cx231xx_gpio_i2c_read = cx231xx_gpio_i2c_read;
+        dev->cx231xx_gpio_i2c_write = cx231xx_gpio_i2c_write;
+
+        /* Query cx231xx to find what pcb config it is related to */
+        initialize_cx231xx(dev);
+
+        /*To workaround error number=-71 on EP0 for VideoGrabber,
+                 need set alt here.*/
+        if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER ||
+            dev->model == CX231XX_BOARD_HAUPPAUGE_USBLIVE2) {
+                cx231xx_set_alt_setting(dev, INDEX_VIDEO, 3);
+                cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
+        }
+        /* Cx231xx pre card setup */
+        cx231xx_pre_card_setup(dev);
+
+        errCode = cx231xx_config(dev);
+        if (errCode) {
+                cx231xx_errdev("error configuring device\n");
+                return -ENOMEM;
+        }
+
+        /* set default norm */
+        dev->norm = dev->board.norm;
+
+        /* register i2c bus */
+        errCode = cx231xx_dev_init(dev);
+        if (errCode < 0) {
+                cx231xx_dev_uninit(dev);
+                cx231xx_errdev("%s: cx231xx_i2c_register - errCode [%d]!\n",
+                               __func__, errCode);
+                return errCode;
+        }
+
+        /* Do board specific init */
+        cx231xx_card_setup(dev);
+
+        /* configure the device */
+        cx231xx_config_i2c(dev);
+
+        maxw = norm_maxw(dev);
+        maxh = norm_maxh(dev);
+
+        /* set default image size */
+        dev->width = maxw;
+        dev->height = maxh;
+        dev->interlaced = 0;
+        dev->video_input = 0;
+
+        errCode = cx231xx_config(dev);
+        if (errCode < 0) {
+                cx231xx_errdev("%s: cx231xx_config - errCode [%d]!\n",
+                               __func__, errCode);
+                return errCode;
+        }
+
+        /* init video dma queues */
+        INIT_LIST_HEAD(&dev->video_mode.vidq.active);
+        INIT_LIST_HEAD(&dev->video_mode.vidq.queued);
+
+        /* init vbi dma queues */
+        INIT_LIST_HEAD(&dev->vbi_mode.vidq.active);
+        INIT_LIST_HEAD(&dev->vbi_mode.vidq.queued);
+
+        /* Reset other chips required if they are tied up with GPIO pins */
+        cx231xx_add_into_devlist(dev);
+
+        if (dev->board.has_417) {
+                printk(KERN_INFO "attach 417 %d\n", dev->model);
+                if (cx231xx_417_register(dev) < 0) {
+                        printk(KERN_ERR
+                                "%s() Failed to register 417 on VID_B\n",
+                               __func__);
+                }
+        }
+
+        retval = cx231xx_register_analog_devices(dev);
+        if (retval < 0) {
+                cx231xx_release_resources(dev);
+                return retval;
+        }
+
+        cx231xx_ir_init(dev);
+
+        cx231xx_init_extension(dev);
+
+        return 0;
+}
+
+#if defined(CONFIG_MODULES) && defined(MODULE)
+static void request_module_async(struct work_struct *work)
+{
+        struct cx231xx *dev = container_of(work,
+                                           struct cx231xx, request_module_wk);
+
+        if (dev->has_alsa_audio)
+                request_module("cx231xx-alsa");
+
+        if (dev->board.has_dvb)
+                request_module("cx231xx-dvb");
+
+}
+
+static void request_modules(struct cx231xx *dev)
+{
+        INIT_WORK(&dev->request_module_wk, request_module_async);
+        schedule_work(&dev->request_module_wk);
+}
+
+static void flush_request_modules(struct cx231xx *dev)
+{
+        flush_work_sync(&dev->request_module_wk);
+}
+#else
+#define request_modules(dev)
+#define flush_request_modules(dev)
+#endif /* CONFIG_MODULES */
+
+/*
+ * cx231xx_usb_probe()
+ * checks for supported devices
+ */
+static int cx231xx_usb_probe(struct usb_interface *interface,
+                             const struct usb_device_id *id)
+{
+        struct usb_device *udev;
+        struct usb_interface *uif;
+        struct cx231xx *dev = NULL;
+        int retval = -ENODEV;
+        int nr = 0, ifnum;
+        int i, isoc_pipe = 0;
+        char *speed;
+        struct usb_interface_assoc_descriptor *assoc_desc;
+
+        udev = usb_get_dev(interface_to_usbdev(interface));
+        ifnum = interface->altsetting[0].desc.bInterfaceNumber;
+
+        /*
+         * Interface number 0 - IR interface (handled by mceusb driver)
+         * Interface number 1 - AV interface (handled by this driver)
+         */
+        if (ifnum != 1)
+                return -ENODEV;
+
+        /* Check to see next free device and mark as used */
+        do {
+                nr = find_first_zero_bit(&cx231xx_devused, CX231XX_MAXBOARDS);
+                if (nr >= CX231XX_MAXBOARDS) {
+                        /* No free device slots */
+                        cx231xx_err(DRIVER_NAME ": Supports only %i devices.\n",
+                                        CX231XX_MAXBOARDS);
+                        return -ENOMEM;
+                }
+        } while (test_and_set_bit(nr, &cx231xx_devused));
+
+        /* allocate memory for our device state and initialize it */
+        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        if (dev == NULL) {
+                cx231xx_err(DRIVER_NAME ": out of memory!\n");
+                clear_bit(nr, &cx231xx_devused);
+                return -ENOMEM;
+        }
+
+        snprintf(dev->name, 29, "cx231xx #%d", nr);
+        dev->devno = nr;
+        dev->model = id->driver_info;
+        dev->video_mode.alt = -1;
+
+        dev->interface_count++;
+        /* reset gpio dir and value */
+        dev->gpio_dir = 0;
+        dev->gpio_val = 0;
+        dev->xc_fw_load_done = 0;
+        dev->has_alsa_audio = 1;
+        dev->power_mode = -1;
+        atomic_set(&dev->devlist_count, 0);
+
+        /* 0 - vbi ; 1 -sliced cc mode */
+        dev->vbi_or_sliced_cc_mode = 0;
+
+        /* get maximum no.of IAD interfaces */
+        assoc_desc = udev->actconfig->intf_assoc[0];
+        dev->max_iad_interface_count = assoc_desc->bInterfaceCount;
+
+        /* init CIR module TBD */
+
+        /*mode_tv: digital=1 or analog=0*/
+        dev->mode_tv = 0;
+
+        dev->USE_ISO = transfer_mode;
+
+        switch (udev->speed) {
+        case USB_SPEED_LOW:
+                speed = "1.5";
+                break;
+        case USB_SPEED_UNKNOWN:
+        case USB_SPEED_FULL:
+                speed = "12";
+                break;
+        case USB_SPEED_HIGH:
+                speed = "480";
+                break;
+        default:
+                speed = "unknown";
+        }
+
+        cx231xx_info("New device %s %s @ %s Mbps "
+             "(%04x:%04x) with %d interfaces\n",
+             udev->manufacturer ? udev->manufacturer : "",
+             udev->product ? udev->product : "",
+             speed,
+             le16_to_cpu(udev->descriptor.idVendor),
+             le16_to_cpu(udev->descriptor.idProduct),
+             dev->max_iad_interface_count);
+
+        /* increment interface count */
+        dev->interface_count++;
+
+        /* get device number */
+        nr = dev->devno;
+
+        assoc_desc = udev->actconfig->intf_assoc[0];
+        if (assoc_desc->bFirstInterface != ifnum) {
+                cx231xx_err(DRIVER_NAME ": Not found "
+                            "matching IAD interface\n");
+                clear_bit(dev->devno, &cx231xx_devused);
+                kfree(dev);
+                dev = NULL;
+                return -ENODEV;
+        }
+
+        cx231xx_info("registering interface %d\n", ifnum);
+
+        /* save our data pointer in this interface device */
+        usb_set_intfdata(interface, dev);
+
+        /*
+         * AV device initialization - only done at the last interface
+         */
+
+        /* Create v4l2 device */
+        retval = v4l2_device_register(&interface->dev, &dev->v4l2_dev);
+        if (retval) {
+                cx231xx_errdev("v4l2_device_register failed\n");
+                clear_bit(dev->devno, &cx231xx_devused);
+                kfree(dev);
+                dev = NULL;
+                return -EIO;
+        }
+        /* allocate device struct */
+        retval = cx231xx_init_dev(dev, udev, nr);
+        if (retval) {
+                clear_bit(dev->devno, &cx231xx_devused);
+                v4l2_device_unregister(&dev->v4l2_dev);
+                kfree(dev);
+                dev = NULL;
+                usb_set_intfdata(interface, NULL);
+
+                return retval;
+        }
+
+        /* compute alternate max packet sizes for video */
+        uif = udev->actconfig->interface[dev->current_pcb_config.
+                       hs_config_info[0].interface_info.video_index + 1];
+
+        dev->video_mode.end_point_addr = le16_to_cpu(uif->altsetting[0].
+                        endpoint[isoc_pipe].desc.bEndpointAddress);
+
+        dev->video_mode.num_alt = uif->num_altsetting;
+        cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
+                     dev->video_mode.end_point_addr,
+                     dev->video_mode.num_alt);
+        dev->video_mode.alt_max_pkt_size =
+                kmalloc(32 * dev->video_mode.num_alt, GFP_KERNEL);
+
+        if (dev->video_mode.alt_max_pkt_size == NULL) {
+                cx231xx_errdev("out of memory!\n");
+                clear_bit(dev->devno, &cx231xx_devused);
+                v4l2_device_unregister(&dev->v4l2_dev);
+                kfree(dev);
+                dev = NULL;
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < dev->video_mode.num_alt; i++) {
+                u16 tmp = le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
+                                desc.wMaxPacketSize);
+                dev->video_mode.alt_max_pkt_size[i] =
+                    (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
+                cx231xx_info("Alternate setting %i, max size= %i\n", i,
+                             dev->video_mode.alt_max_pkt_size[i]);
+        }
+
+        /* compute alternate max packet sizes for vbi */
+        uif = udev->actconfig->interface[dev->current_pcb_config.
+                                       hs_config_info[0].interface_info.
+                                       vanc_index + 1];
+
+        dev->vbi_mode.end_point_addr =
+            le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
+                        bEndpointAddress);
+
+        dev->vbi_mode.num_alt = uif->num_altsetting;
+        cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
+                     dev->vbi_mode.end_point_addr,
+                     dev->vbi_mode.num_alt);
+        dev->vbi_mode.alt_max_pkt_size =
+            kmalloc(32 * dev->vbi_mode.num_alt, GFP_KERNEL);
+
+        if (dev->vbi_mode.alt_max_pkt_size == NULL) {
+                cx231xx_errdev("out of memory!\n");
+                clear_bit(dev->devno, &cx231xx_devused);
+                v4l2_device_unregister(&dev->v4l2_dev);
+                kfree(dev);
+                dev = NULL;
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < dev->vbi_mode.num_alt; i++) {
+                u16 tmp =
+                    le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
+                                desc.wMaxPacketSize);
+                dev->vbi_mode.alt_max_pkt_size[i] =
+                    (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
+                cx231xx_info("Alternate setting %i, max size= %i\n", i,
+                             dev->vbi_mode.alt_max_pkt_size[i]);
+        }
+
+        /* compute alternate max packet sizes for sliced CC */
+        uif = udev->actconfig->interface[dev->current_pcb_config.
+                                       hs_config_info[0].interface_info.
+                                       hanc_index + 1];
+
+        dev->sliced_cc_mode.end_point_addr =
+            le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
+                        bEndpointAddress);
+
+        dev->sliced_cc_mode.num_alt = uif->num_altsetting;
+        cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
+                     dev->sliced_cc_mode.end_point_addr,
+                     dev->sliced_cc_mode.num_alt);
+        dev->sliced_cc_mode.alt_max_pkt_size =
+                kmalloc(32 * dev->sliced_cc_mode.num_alt, GFP_KERNEL);
+
+        if (dev->sliced_cc_mode.alt_max_pkt_size == NULL) {
+                cx231xx_errdev("out of memory!\n");
+                clear_bit(dev->devno, &cx231xx_devused);
+                v4l2_device_unregister(&dev->v4l2_dev);
+                kfree(dev);
+                dev = NULL;
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < dev->sliced_cc_mode.num_alt; i++) {
+                u16 tmp = le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
+                                desc.wMaxPacketSize);
+                dev->sliced_cc_mode.alt_max_pkt_size[i] =
+                    (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
+                cx231xx_info("Alternate setting %i, max size= %i\n", i,
+                             dev->sliced_cc_mode.alt_max_pkt_size[i]);
+        }
+
+        if (dev->current_pcb_config.ts1_source != 0xff) {
+                /* compute alternate max packet sizes for TS1 */
+                uif = udev->actconfig->interface[dev->current_pcb_config.
+                                               hs_config_info[0].
+                                               interface_info.
+                                               ts1_index + 1];
+
+                dev->ts1_mode.end_point_addr =
+                    le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].
+                                desc.bEndpointAddress);
+
+                dev->ts1_mode.num_alt = uif->num_altsetting;
+                cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
+                             dev->ts1_mode.end_point_addr,
+                             dev->ts1_mode.num_alt);
+                dev->ts1_mode.alt_max_pkt_size =
+                        kmalloc(32 * dev->ts1_mode.num_alt, GFP_KERNEL);
+
+                if (dev->ts1_mode.alt_max_pkt_size == NULL) {
+                        cx231xx_errdev("out of memory!\n");
+                        clear_bit(dev->devno, &cx231xx_devused);
+                        v4l2_device_unregister(&dev->v4l2_dev);
+                        kfree(dev);
+                        dev = NULL;
+                        return -ENOMEM;
+                }
+
+                for (i = 0; i < dev->ts1_mode.num_alt; i++) {
+                        u16 tmp = le16_to_cpu(uif->altsetting[i].
+                                                endpoint[isoc_pipe].desc.
+                                                wMaxPacketSize);
+                        dev->ts1_mode.alt_max_pkt_size[i] =
+                            (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
+                        cx231xx_info("Alternate setting %i, max size= %i\n", i,
+                                     dev->ts1_mode.alt_max_pkt_size[i]);
+                }
+        }
+
+        if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
+                cx231xx_enable_OSC(dev);
+                cx231xx_reset_out(dev);
+                cx231xx_set_alt_setting(dev, INDEX_VIDEO, 3);
+        }
+
+        if (dev->model == CX231XX_BOARD_CNXT_RDE_253S)
+                cx231xx_sleep_s5h1432(dev);
+
+        /* load other modules required */
+        request_modules(dev);
+
+        return 0;
+}
+
+/*
+ * cx231xx_usb_disconnect()
+ * called when the device gets diconencted
+ * video device will be unregistered on v4l2_close in case it is still open
+ */
+static void cx231xx_usb_disconnect(struct usb_interface *interface)
+{
+        struct cx231xx *dev;
+
+        dev = usb_get_intfdata(interface);
+        usb_set_intfdata(interface, NULL);
+
+        if (!dev)
+                return;
+
+        if (!dev->udev)
+                return;
+
+        dev->state |= DEV_DISCONNECTED;
+
+        flush_request_modules(dev);
+
+        /* wait until all current v4l2 io is finished then deallocate
+           resources */
+        mutex_lock(&dev->lock);
+
+        wake_up_interruptible_all(&dev->open);
+
+        if (dev->users) {
+                cx231xx_warn
+                    ("device %s is open! Deregistration and memory "
+                     "deallocation are deferred on close.\n",
+                     video_device_node_name(dev->vdev));
+
+                /* Even having users, it is safe to remove the RC i2c driver */
+                cx231xx_ir_exit(dev);
+
+                if (dev->USE_ISO)
+                        cx231xx_uninit_isoc(dev);
+                else
+                        cx231xx_uninit_bulk(dev);
+                wake_up_interruptible(&dev->wait_frame);
+                wake_up_interruptible(&dev->wait_stream);
+        } else {
+        }
+
+        cx231xx_close_extension(dev);
+
+        mutex_unlock(&dev->lock);
+
+        if (!dev->users)
+                cx231xx_release_resources(dev);
+}
+
+static struct usb_driver cx231xx_usb_driver = {
+        .name = "cx231xx",
+        .probe = cx231xx_usb_probe,
+        .disconnect = cx231xx_usb_disconnect,
+        .id_table = cx231xx_id_table,
+};
+
+module_usb_driver(cx231xx_usb_driver);
diff --git a/drivers/media/usb/cx231xx/cx231xx-conf-reg.h b/drivers/media/usb/cx231xx/cx231xx-conf-reg.h
new file mode 100644
index 000000000000..25593f212abf
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-conf-reg.h
@@ -0,0 +1,495 @@
+/*
+   cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
+                        video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _POLARIS_REG_H_
+#define _POLARIS_REG_H_
+
+#define BOARD_CFG_STAT          0x0
+#define TS_MODE_REG             0x4
+#define TS1_CFG_REG             0x8
+#define TS1_LENGTH_REG          0xc
+#define TS2_CFG_REG             0x10
+#define TS2_LENGTH_REG          0x14
+#define EP_MODE_SET             0x18
+#define CIR_PWR_PTN1            0x1c
+#define CIR_PWR_PTN2            0x20
+#define CIR_PWR_PTN3            0x24
+#define CIR_PWR_MASK0           0x28
+#define CIR_PWR_MASK1           0x2c
+#define CIR_PWR_MASK2           0x30
+#define CIR_GAIN                0x34
+#define CIR_CAR_REG             0x38
+#define CIR_OT_CFG1             0x40
+#define CIR_OT_CFG2             0x44
+#define GBULK_BIT_EN            0x68
+#define PWR_CTL_EN              0x74
+
+/* Polaris Endpoints capture mask for register EP_MODE_SET */
+#define ENABLE_EP1              0x01   /* Bit[0]=1 */
+#define ENABLE_EP2              0x02   /* Bit[1]=1 */
+#define ENABLE_EP3              0x04   /* Bit[2]=1 */
+#define ENABLE_EP4              0x08   /* Bit[3]=1 */
+#define ENABLE_EP5              0x10   /* Bit[4]=1 */
+#define ENABLE_EP6              0x20   /* Bit[5]=1 */
+
+/* Bit definition for register PWR_CTL_EN */
+#define PWR_MODE_MASK           0x17f
+#define PWR_AV_EN               0x08   /* bit3 */
+#define PWR_ISO_EN              0x40   /* bit6 */
+#define PWR_AV_MODE             0x30   /* bit4,5  */
+#define PWR_TUNER_EN            0x04   /* bit2 */
+#define PWR_DEMOD_EN            0x02   /* bit1 */
+#define I2C_DEMOD_EN            0x01   /* bit0 */
+#define PWR_RESETOUT_EN         0x100  /* bit8 */
+
+enum AV_MODE{
+        POLARIS_AVMODE_DEFAULT = 0,
+        POLARIS_AVMODE_DIGITAL = 0x10,
+        POLARIS_AVMODE_ANALOGT_TV = 0x20,
+        POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
+
+};
+
+/* Colibri Registers */
+
+#define SINGLE_ENDED            0x0
+#define LOW_IF                  0x4
+#define EU_IF                   0x9
+#define US_IF                   0xa
+
+#define SUP_BLK_TUNE1           0x00
+#define SUP_BLK_TUNE2           0x01
+#define SUP_BLK_TUNE3           0x02
+#define SUP_BLK_XTAL            0x03
+#define SUP_BLK_PLL1            0x04
+#define SUP_BLK_PLL2            0x05
+#define SUP_BLK_PLL3            0x06
+#define SUP_BLK_REF             0x07
+#define SUP_BLK_PWRDN           0x08
+#define SUP_BLK_TESTPAD         0x09
+#define ADC_COM_INT5_STAB_REF   0x0a
+#define ADC_COM_QUANT           0x0b
+#define ADC_COM_BIAS1           0x0c
+#define ADC_COM_BIAS2           0x0d
+#define ADC_COM_BIAS3           0x0e
+#define TESTBUS_CTRL            0x12
+
+#define FLD_PWRDN_TUNING_BIAS   0x10
+#define FLD_PWRDN_ENABLE_PLL    0x08
+#define FLD_PWRDN_PD_BANDGAP    0x04
+#define FLD_PWRDN_PD_BIAS       0x02
+#define FLD_PWRDN_PD_TUNECK     0x01
+
+
+#define ADC_STATUS_CH1          0x20
+#define ADC_STATUS_CH2          0x40
+#define ADC_STATUS_CH3          0x60
+
+#define ADC_STATUS2_CH1         0x21
+#define ADC_STATUS2_CH2         0x41
+#define ADC_STATUS2_CH3         0x61
+
+#define ADC_CAL_ATEST_CH1       0x22
+#define ADC_CAL_ATEST_CH2       0x42
+#define ADC_CAL_ATEST_CH3       0x62
+
+#define ADC_PWRDN_CLAMP_CH1     0x23
+#define ADC_PWRDN_CLAMP_CH2     0x43
+#define ADC_PWRDN_CLAMP_CH3     0x63
+
+#define ADC_CTRL_DAC23_CH1      0x24
+#define ADC_CTRL_DAC23_CH2      0x44
+#define ADC_CTRL_DAC23_CH3      0x64
+
+#define ADC_CTRL_DAC1_CH1       0x25
+#define ADC_CTRL_DAC1_CH2       0x45
+#define ADC_CTRL_DAC1_CH3       0x65
+
+#define ADC_DCSERVO_DEM_CH1     0x26
+#define ADC_DCSERVO_DEM_CH2     0x46
+#define ADC_DCSERVO_DEM_CH3     0x66
+
+#define ADC_FB_FRCRST_CH1       0x27
+#define ADC_FB_FRCRST_CH2       0x47
+#define ADC_FB_FRCRST_CH3       0x67
+
+#define ADC_INPUT_CH1           0x28
+#define ADC_INPUT_CH2           0x48
+#define ADC_INPUT_CH3           0x68
+#define INPUT_SEL_MASK          0x30   /* [5:4] in_sel */
+
+#define ADC_NTF_PRECLMP_EN_CH1  0x29
+#define ADC_NTF_PRECLMP_EN_CH2  0x49
+#define ADC_NTF_PRECLMP_EN_CH3  0x69
+
+#define ADC_QGAIN_RES_TRM_CH1   0x2a
+#define ADC_QGAIN_RES_TRM_CH2   0x4a
+#define ADC_QGAIN_RES_TRM_CH3   0x6a
+
+#define ADC_SOC_PRECLMP_TERM_CH1    0x2b
+#define ADC_SOC_PRECLMP_TERM_CH2    0x4b
+#define ADC_SOC_PRECLMP_TERM_CH3    0x6b
+
+#define TESTBUS_CTRL_CH1        0x32
+#define TESTBUS_CTRL_CH2        0x52
+#define TESTBUS_CTRL_CH3        0x72
+
+/******************************************************************************
+                            * DIF registers *
+ ******************************************************************************/
+#define      DIRECT_IF_REVB_BASE  0x00300
+
+/*****************************************************************************/
+#define      DIF_PLL_FREQ_WORD        (DIRECT_IF_REVB_BASE + 0x00000000)
+/*****************************************************************************/
+#define      FLD_DIF_PLL_LOCK                           0x80000000
+/*  Reserved                                [30:29] */
+#define      FLD_DIF_PLL_FREE_RUN                       0x10000000
+#define      FLD_DIF_PLL_FREQ                           0x0fffffff
+
+/*****************************************************************************/
+#define      DIF_PLL_CTRL             (DIRECT_IF_REVB_BASE + 0x00000004)
+/*****************************************************************************/
+#define      FLD_DIF_KD_PD                              0xff000000
+/*  Reserved                             [23:20] */
+#define      FLD_DIF_KDS_PD                             0x000f0000
+#define      FLD_DIF_KI_PD                              0x0000ff00
+/*  Reserved                             [7:4] */
+#define      FLD_DIF_KIS_PD                             0x0000000f
+
+/*****************************************************************************/
+#define      DIF_PLL_CTRL1            (DIRECT_IF_REVB_BASE + 0x00000008)
+/*****************************************************************************/
+#define      FLD_DIF_KD_FD                              0xff000000
+/*  Reserved                             [23:20] */
+#define      FLD_DIF_KDS_FD                             0x000f0000
+#define      FLD_DIF_KI_FD                              0x0000ff00
+#define      FLD_DIF_SIG_PROP_SZ                        0x000000f0
+#define      FLD_DIF_KIS_FD                             0x0000000f
+
+/*****************************************************************************/
+#define      DIF_PLL_CTRL2            (DIRECT_IF_REVB_BASE + 0x0000000c)
+/*****************************************************************************/
+#define      FLD_DIF_PLL_AGC_REF                        0xfff00000
+#define      FLD_DIF_PLL_AGC_KI                         0x000f0000
+/*  Reserved                             [15] */
+#define      FLD_DIF_FREQ_LIMIT                         0x00007000
+#define      FLD_DIF_K_FD                               0x00000f00
+#define      FLD_DIF_DOWNSMPL_FD                        0x000000ff
+
+/*****************************************************************************/
+#define      DIF_PLL_CTRL3            (DIRECT_IF_REVB_BASE + 0x00000010)
+/*****************************************************************************/
+/*  Reserved                             [31:16] */
+#define      FLD_DIF_PLL_AGC_EN                         0x00008000
+/*  Reserved                             [14:12] */
+#define      FLD_DIF_PLL_MAN_GAIN                       0x00000fff
+
+/*****************************************************************************/
+#define      DIF_AGC_IF_REF           (DIRECT_IF_REVB_BASE + 0x00000014)
+/*****************************************************************************/
+#define      FLD_DIF_K_AGC_RF                           0xf0000000
+#define      FLD_DIF_K_AGC_IF                           0x0f000000
+#define      FLD_DIF_K_AGC_INT                          0x00f00000
+/*  Reserved                             [19:12] */
+#define      FLD_DIF_IF_REF                             0x00000fff
+
+/*****************************************************************************/
+#define      DIF_AGC_CTRL_IF          (DIRECT_IF_REVB_BASE + 0x00000018)
+/*****************************************************************************/
+#define      FLD_DIF_IF_MAX                             0xff000000
+#define      FLD_DIF_IF_MIN                             0x00ff0000
+#define      FLD_DIF_IF_AGC                             0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_AGC_CTRL_INT         (DIRECT_IF_REVB_BASE + 0x0000001c)
+/*****************************************************************************/
+#define      FLD_DIF_INT_MAX                            0xff000000
+#define      FLD_DIF_INT_MIN                            0x00ff0000
+#define      FLD_DIF_INT_AGC                            0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_AGC_CTRL_RF          (DIRECT_IF_REVB_BASE + 0x00000020)
+/*****************************************************************************/
+#define      FLD_DIF_RF_MAX                             0xff000000
+#define      FLD_DIF_RF_MIN                             0x00ff0000
+#define      FLD_DIF_RF_AGC                             0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_AGC_IF_INT_CURRENT   (DIRECT_IF_REVB_BASE + 0x00000024)
+/*****************************************************************************/
+#define      FLD_DIF_IF_AGC_IN                          0xffff0000
+#define      FLD_DIF_INT_AGC_IN                         0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_AGC_RF_CURRENT       (DIRECT_IF_REVB_BASE + 0x00000028)
+/*****************************************************************************/
+/*  Reserved                            [31:16] */
+#define      FLD_DIF_RF_AGC_IN                          0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_VIDEO_AGC_CTRL       (DIRECT_IF_REVB_BASE + 0x0000002c)
+/*****************************************************************************/
+#define      FLD_DIF_AFD                                0xc0000000
+#define      FLD_DIF_K_VID_AGC                          0x30000000
+#define      FLD_DIF_LINE_LENGTH                        0x0fff0000
+#define      FLD_DIF_AGC_GAIN                           0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_VID_AUD_OVERRIDE     (DIRECT_IF_REVB_BASE + 0x00000030)
+/*****************************************************************************/
+#define      FLD_DIF_AUDIO_AGC_OVERRIDE                 0x80000000
+/*  Reserved                             [30:30] */
+#define      FLD_DIF_AUDIO_MAN_GAIN                     0x3f000000
+/*  Reserved                             [23:17] */
+#define      FLD_DIF_VID_AGC_OVERRIDE                   0x00010000
+#define      FLD_DIF_VID_MAN_GAIN                       0x0000ffff
+
+/*****************************************************************************/
+#define      DIF_AV_SEP_CTRL          (DIRECT_IF_REVB_BASE + 0x00000034)
+/*****************************************************************************/
+#define      FLD_DIF_LPF_FREQ                           0xc0000000
+#define      FLD_DIF_AV_PHASE_INC                       0x3f000000
+#define      FLD_DIF_AUDIO_FREQ                         0x00ffffff
+
+/*****************************************************************************/
+#define      DIF_COMP_FLT_CTRL        (DIRECT_IF_REVB_BASE + 0x00000038)
+/*****************************************************************************/
+/*  Reserved                            [31:24] */
+#define      FLD_DIF_IIR23_R2                           0x00ff0000
+#define      FLD_DIF_IIR23_R1                           0x0000ff00
+#define      FLD_DIF_IIR1_R1                            0x000000ff
+
+/*****************************************************************************/
+#define      DIF_MISC_CTRL            (DIRECT_IF_REVB_BASE + 0x0000003c)
+/*****************************************************************************/
+#define      FLD_DIF_DIF_BYPASS                         0x80000000
+#define      FLD_DIF_FM_NYQ_GAIN                        0x40000000
+#define      FLD_DIF_RF_AGC_ENA                         0x20000000
+#define      FLD_DIF_INT_AGC_ENA                        0x10000000
+#define      FLD_DIF_IF_AGC_ENA                         0x08000000
+#define      FLD_DIF_FORCE_RF_IF_LOCK                   0x04000000
+#define      FLD_DIF_VIDEO_AGC_ENA                      0x02000000
+#define      FLD_DIF_RF_AGC_INV                         0x01000000
+#define      FLD_DIF_INT_AGC_INV                        0x00800000
+#define      FLD_DIF_IF_AGC_INV                         0x00400000
+#define      FLD_DIF_SPEC_INV                           0x00200000
+#define      FLD_DIF_AUD_FULL_BW                        0x00100000
+#define      FLD_DIF_AUD_SRC_SEL                        0x00080000
+/*  Reserved                             [18] */
+#define      FLD_DIF_IF_FREQ                            0x00030000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_TIP_OFFSET                         0x00003f00
+/*  Reserved                             [7:5] */
+#define      FLD_DIF_DITHER_ENA                         0x00000010
+/*  Reserved                             [3:1] */
+#define      FLD_DIF_RF_IF_LOCK                         0x00000001
+
+/*****************************************************************************/
+#define      DIF_SRC_PHASE_INC        (DIRECT_IF_REVB_BASE + 0x00000040)
+/*****************************************************************************/
+/*  Reserved                             [31:29] */
+#define      FLD_DIF_PHASE_INC                          0x1fffffff
+
+/*****************************************************************************/
+#define      DIF_SRC_GAIN_CONTROL     (DIRECT_IF_REVB_BASE + 0x00000044)
+/*****************************************************************************/
+/*  Reserved                             [31:16] */
+#define      FLD_DIF_SRC_KI                             0x0000ff00
+#define      FLD_DIF_SRC_KD                             0x000000ff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF01          (DIRECT_IF_REVB_BASE + 0x00000048)
+/*****************************************************************************/
+/*  Reserved                             [31:19] */
+#define      FLD_DIF_BPF_COEFF_0                        0x00070000
+/*  Reserved                             [15:4] */
+#define      FLD_DIF_BPF_COEFF_1                        0x0000000f
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF23          (DIRECT_IF_REVB_BASE + 0x0000004c)
+/*****************************************************************************/
+/*  Reserved                             [31:22] */
+#define      FLD_DIF_BPF_COEFF_2                        0x003f0000
+/*  Reserved                             [15:7] */
+#define      FLD_DIF_BPF_COEFF_3                        0x0000007f
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF45          (DIRECT_IF_REVB_BASE + 0x00000050)
+/*****************************************************************************/
+/*  Reserved                             [31:24] */
+#define      FLD_DIF_BPF_COEFF_4                        0x00ff0000
+/*  Reserved                             [15:8] */
+#define      FLD_DIF_BPF_COEFF_5                        0x000000ff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF67          (DIRECT_IF_REVB_BASE + 0x00000054)
+/*****************************************************************************/
+/*  Reserved                             [31:25] */
+#define      FLD_DIF_BPF_COEFF_6                        0x01ff0000
+/*  Reserved                             [15:9] */
+#define      FLD_DIF_BPF_COEFF_7                        0x000001ff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF89          (DIRECT_IF_REVB_BASE + 0x00000058)
+/*****************************************************************************/
+/*  Reserved                             [31:26] */
+#define      FLD_DIF_BPF_COEFF_8                        0x03ff0000
+/*  Reserved                             [15:10] */
+#define      FLD_DIF_BPF_COEFF_9                        0x000003ff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF1011        (DIRECT_IF_REVB_BASE + 0x0000005c)
+/*****************************************************************************/
+/*  Reserved                             [31:27] */
+#define      FLD_DIF_BPF_COEFF_10                       0x07ff0000
+/*  Reserved                             [15:11] */
+#define      FLD_DIF_BPF_COEFF_11                       0x000007ff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF1213        (DIRECT_IF_REVB_BASE + 0x00000060)
+/*****************************************************************************/
+/*  Reserved                             [31:27] */
+#define      FLD_DIF_BPF_COEFF_12                       0x07ff0000
+/*  Reserved                             [15:12] */
+#define      FLD_DIF_BPF_COEFF_13                       0x00000fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF1415        (DIRECT_IF_REVB_BASE + 0x00000064)
+/*****************************************************************************/
+/*  Reserved                             [31:28] */
+#define      FLD_DIF_BPF_COEFF_14                       0x0fff0000
+/*  Reserved                             [15:12] */
+#define      FLD_DIF_BPF_COEFF_15                       0x00000fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF1617        (DIRECT_IF_REVB_BASE + 0x00000068)
+/*****************************************************************************/
+/*  Reserved                             [31:29] */
+#define      FLD_DIF_BPF_COEFF_16                       0x1fff0000
+/*  Reserved                             [15:13] */
+#define      FLD_DIF_BPF_COEFF_17                       0x00001fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF1819        (DIRECT_IF_REVB_BASE + 0x0000006c)
+/*****************************************************************************/
+/*  Reserved                             [31:29] */
+#define      FLD_DIF_BPF_COEFF_18                       0x1fff0000
+/*  Reserved                             [15:13] */
+#define      FLD_DIF_BPF_COEFF_19                       0x00001fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF2021        (DIRECT_IF_REVB_BASE + 0x00000070)
+/*****************************************************************************/
+/*  Reserved                             [31:29] */
+#define      FLD_DIF_BPF_COEFF_20                       0x1fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_21                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF2223        (DIRECT_IF_REVB_BASE + 0x00000074)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_22                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_23                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF2425        (DIRECT_IF_REVB_BASE + 0x00000078)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_24                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_25                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF2627        (DIRECT_IF_REVB_BASE + 0x0000007c)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_26                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_27                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF2829        (DIRECT_IF_REVB_BASE + 0x00000080)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_28                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_29                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF3031        (DIRECT_IF_REVB_BASE + 0x00000084)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_30                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_31                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF3233        (DIRECT_IF_REVB_BASE + 0x00000088)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_32                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_33                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF3435        (DIRECT_IF_REVB_BASE + 0x0000008c)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_34                       0x3fff0000
+/*  Reserved                             [15:14] */
+#define      FLD_DIF_BPF_COEFF_35                       0x00003fff
+
+/*****************************************************************************/
+#define      DIF_BPF_COEFF36          (DIRECT_IF_REVB_BASE + 0x00000090)
+/*****************************************************************************/
+/*  Reserved                             [31:30] */
+#define      FLD_DIF_BPF_COEFF_36                       0x3fff0000
+/*  Reserved                             [15:0] */
+
+/*****************************************************************************/
+#define      DIF_RPT_VARIANCE         (DIRECT_IF_REVB_BASE + 0x00000094)
+/*****************************************************************************/
+/*  Reserved                             [31:20] */
+#define      FLD_DIF_RPT_VARIANCE                       0x000fffff
+
+/*****************************************************************************/
+#define      DIF_SOFT_RST_CTRL_REVB       (DIRECT_IF_REVB_BASE + 0x00000098)
+/*****************************************************************************/
+/*  Reserved                             [31:8] */
+#define      FLD_DIF_DIF_SOFT_RST                       0x00000080
+#define      FLD_DIF_DIF_REG_RST_MSK                    0x00000040
+#define      FLD_DIF_AGC_RST_MSK                        0x00000020
+#define      FLD_DIF_CMP_RST_MSK                        0x00000010
+#define      FLD_DIF_AVS_RST_MSK                        0x00000008
+#define      FLD_DIF_NYQ_RST_MSK                        0x00000004
+#define      FLD_DIF_DIF_SRC_RST_MSK                    0x00000002
+#define      FLD_DIF_PLL_RST_MSK                        0x00000001
+
+/*****************************************************************************/
+#define      DIF_PLL_FREQ_ERR         (DIRECT_IF_REVB_BASE + 0x0000009c)
+/*****************************************************************************/
+/*  Reserved                             [31:25] */
+#define      FLD_DIF_CTL_IP                             0x01ffffff
+
+#endif
diff --git a/drivers/media/usb/cx231xx/cx231xx-core.c b/drivers/media/usb/cx231xx/cx231xx-core.c
new file mode 100644
index 000000000000..05358d486135
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-core.c
@@ -0,0 +1,1736 @@
+/*
+   cx231xx-core.c - driver for Conexant Cx23100/101/102
+                                USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+                                Based on em28xx driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/usb.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-common.h>
+#include <media/tuner.h>
+
+#include "cx231xx.h"
+#include "cx231xx-reg.h"
+
+/* #define ENABLE_DEBUG_ISOC_FRAMES */
+
+static unsigned int core_debug;
+module_param(core_debug, int, 0644);
+MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
+
+#define cx231xx_coredbg(fmt, arg...) do {\
+        if (core_debug) \
+                printk(KERN_INFO "%s %s :"fmt, \
+                         dev->name, __func__ , ##arg); } while (0)
+
+static unsigned int reg_debug;
+module_param(reg_debug, int, 0644);
+MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
+
+static int alt = CX231XX_PINOUT;
+module_param(alt, int, 0644);
+MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
+
+#define cx231xx_isocdbg(fmt, arg...) do {\
+        if (core_debug) \
+                printk(KERN_INFO "%s %s :"fmt, \
+                         dev->name, __func__ , ##arg); } while (0)
+
+/*****************************************************************
+*             Device control list functions                                      *
+******************************************************************/
+
+LIST_HEAD(cx231xx_devlist);
+static DEFINE_MUTEX(cx231xx_devlist_mutex);
+
+/*
+ * cx231xx_realease_resources()
+ * unregisters the v4l2,i2c and usb devices
+ * called when the device gets disconected or at module unload
+*/
+void cx231xx_remove_from_devlist(struct cx231xx *dev)
+{
+        if (dev == NULL)
+                return;
+        if (dev->udev == NULL)
+                return;
+
+        if (atomic_read(&dev->devlist_count) > 0) {
+                mutex_lock(&cx231xx_devlist_mutex);
+                list_del(&dev->devlist);
+                atomic_dec(&dev->devlist_count);
+                mutex_unlock(&cx231xx_devlist_mutex);
+        }
+};
+
+void cx231xx_add_into_devlist(struct cx231xx *dev)
+{
+        mutex_lock(&cx231xx_devlist_mutex);
+        list_add_tail(&dev->devlist, &cx231xx_devlist);
+        atomic_inc(&dev->devlist_count);
+        mutex_unlock(&cx231xx_devlist_mutex);
+};
+
+static LIST_HEAD(cx231xx_extension_devlist);
+
+int cx231xx_register_extension(struct cx231xx_ops *ops)
+{
+        struct cx231xx *dev = NULL;
+
+        mutex_lock(&cx231xx_devlist_mutex);
+        list_add_tail(&ops->next, &cx231xx_extension_devlist);
+        list_for_each_entry(dev, &cx231xx_devlist, devlist)
+                ops->init(dev);
+
+        printk(KERN_INFO DRIVER_NAME ": %s initialized\n", ops->name);
+        mutex_unlock(&cx231xx_devlist_mutex);
+        return 0;
+}
+EXPORT_SYMBOL(cx231xx_register_extension);
+
+void cx231xx_unregister_extension(struct cx231xx_ops *ops)
+{
+        struct cx231xx *dev = NULL;
+
+        mutex_lock(&cx231xx_devlist_mutex);
+        list_for_each_entry(dev, &cx231xx_devlist, devlist)
+                ops->fini(dev);
+
+
+        printk(KERN_INFO DRIVER_NAME ": %s removed\n", ops->name);
+        list_del(&ops->next);
+        mutex_unlock(&cx231xx_devlist_mutex);
+}
+EXPORT_SYMBOL(cx231xx_unregister_extension);
+
+void cx231xx_init_extension(struct cx231xx *dev)
+{
+        struct cx231xx_ops *ops = NULL;
+
+        mutex_lock(&cx231xx_devlist_mutex);
+        if (!list_empty(&cx231xx_extension_devlist)) {
+                list_for_each_entry(ops, &cx231xx_extension_devlist, next) {
+                        if (ops->init)
+                                ops->init(dev);
+                }
+        }
+        mutex_unlock(&cx231xx_devlist_mutex);
+}
+
+void cx231xx_close_extension(struct cx231xx *dev)
+{
+        struct cx231xx_ops *ops = NULL;
+
+        mutex_lock(&cx231xx_devlist_mutex);
+        if (!list_empty(&cx231xx_extension_devlist)) {
+                list_for_each_entry(ops, &cx231xx_extension_devlist, next) {
+                        if (ops->fini)
+                                ops->fini(dev);
+                }
+        }
+        mutex_unlock(&cx231xx_devlist_mutex);
+}
+
+/****************************************************************
+*               U S B related functions                         *
+*****************************************************************/
+int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
+                             struct cx231xx_i2c_xfer_data *req_data)
+{
+        int status = 0;
+        struct cx231xx *dev = i2c_bus->dev;
+        struct VENDOR_REQUEST_IN ven_req;
+
+        u8 saddr_len = 0;
+        u8 _i2c_period = 0;
+        u8 _i2c_nostop = 0;
+        u8 _i2c_reserve = 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        /* Get the I2C period, nostop and reserve parameters */
+        _i2c_period = i2c_bus->i2c_period;
+        _i2c_nostop = i2c_bus->i2c_nostop;
+        _i2c_reserve = i2c_bus->i2c_reserve;
+
+        saddr_len = req_data->saddr_len;
+
+        /* Set wValue */
+        if (saddr_len == 1)     /* need check saddr_len == 0  */
+                ven_req.wValue =
+                    req_data->
+                    dev_addr << 9 | _i2c_period << 4 | saddr_len << 2 |
+                    _i2c_nostop << 1 | I2C_SYNC | _i2c_reserve << 6;
+        else
+                ven_req.wValue =
+                    req_data->
+                    dev_addr << 9 | _i2c_period << 4 | saddr_len << 2 |
+                    _i2c_nostop << 1 | I2C_SYNC | _i2c_reserve << 6;
+
+        /* set channel number */
+        if (req_data->direction & I2C_M_RD) {
+                /* channel number, for read,spec required channel_num +4 */
+                ven_req.bRequest = i2c_bus->nr + 4;
+        } else
+                ven_req.bRequest = i2c_bus->nr; /* channel number,  */
+
+        /* set index value */
+        switch (saddr_len) {
+        case 0:
+                ven_req.wIndex = 0;     /* need check */
+                break;
+        case 1:
+                ven_req.wIndex = (req_data->saddr_dat & 0xff);
+                break;
+        case 2:
+                ven_req.wIndex = req_data->saddr_dat;
+                break;
+        }
+
+        /* set wLength value */
+        ven_req.wLength = req_data->buf_size;
+
+        /* set bData value */
+        ven_req.bData = 0;
+
+        /* set the direction */
+        if (req_data->direction) {
+                ven_req.direction = USB_DIR_IN;
+                memset(req_data->p_buffer, 0x00, ven_req.wLength);
+        } else
+                ven_req.direction = USB_DIR_OUT;
+
+        /* set the buffer for read / write */
+        ven_req.pBuff = req_data->p_buffer;
+
+
+        /* call common vendor command request */
+        status = cx231xx_send_vendor_cmd(dev, &ven_req);
+        if (status < 0) {
+                cx231xx_info
+                    ("UsbInterface::sendCommand, failed with status -%d\n",
+                     status);
+        }
+
+        return status;
+}
+EXPORT_SYMBOL_GPL(cx231xx_send_usb_command);
+
+/*
+ * Sends/Receives URB control messages, assuring to use a kalloced buffer
+ * for all operations (dev->urb_buf), to avoid using stacked buffers, as
+ * they aren't safe for usage with USB, due to DMA restrictions.
+ * Also implements the debug code for control URB's.
+ */
+static int __usb_control_msg(struct cx231xx *dev, unsigned int pipe,
+        __u8 request, __u8 requesttype, __u16 value, __u16 index,
+        void *data, __u16 size, int timeout)
+{
+        int rc, i;
+
+        if (reg_debug) {
+                printk(KERN_DEBUG "%s: (pipe 0x%08x): "
+                                "%s:  %02x %02x %02x %02x %02x %02x %02x %02x ",
+                                dev->name,
+                                pipe,
+                                (requesttype & USB_DIR_IN) ? "IN" : "OUT",
+                                requesttype,
+                                request,
+                                value & 0xff, value >> 8,
+                                index & 0xff, index >> 8,
+                                size & 0xff, size >> 8);
+                if (!(requesttype & USB_DIR_IN)) {
+                        printk(KERN_CONT ">>>");
+                        for (i = 0; i < size; i++)
+                                printk(KERN_CONT " %02x",
+                                       ((unsigned char *)data)[i]);
+                }
+        }
+
+        /* Do the real call to usb_control_msg */
+        mutex_lock(&dev->ctrl_urb_lock);
+        if (!(requesttype & USB_DIR_IN) && size)
+                memcpy(dev->urb_buf, data, size);
+        rc = usb_control_msg(dev->udev, pipe, request, requesttype, value,
+                             index, dev->urb_buf, size, timeout);
+        if ((requesttype & USB_DIR_IN) && size)
+                memcpy(data, dev->urb_buf, size);
+        mutex_unlock(&dev->ctrl_urb_lock);
+
+        if (reg_debug) {
+                if (unlikely(rc < 0)) {
+                        printk(KERN_CONT "FAILED!\n");
+                        return rc;
+                }
+
+                if ((requesttype & USB_DIR_IN)) {
+                        printk(KERN_CONT "<<<");
+                        for (i = 0; i < size; i++)
+                                printk(KERN_CONT " %02x",
+                                       ((unsigned char *)data)[i]);
+                }
+                printk(KERN_CONT "\n");
+        }
+
+        return rc;
+}
+
+
+/*
+ * cx231xx_read_ctrl_reg()
+ * reads data from the usb device specifying bRequest and wValue
+ */
+int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
+                          char *buf, int len)
+{
+        u8 val = 0;
+        int ret;
+        int pipe = usb_rcvctrlpipe(dev->udev, 0);
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        if (len > URB_MAX_CTRL_SIZE)
+                return -EINVAL;
+
+        switch (len) {
+        case 1:
+                val = ENABLE_ONE_BYTE;
+                break;
+        case 2:
+                val = ENABLE_TWE_BYTE;
+                break;
+        case 3:
+                val = ENABLE_THREE_BYTE;
+                break;
+        case 4:
+                val = ENABLE_FOUR_BYTE;
+                break;
+        default:
+                val = 0xFF;     /* invalid option */
+        }
+
+        if (val == 0xFF)
+                return -EINVAL;
+
+        ret = __usb_control_msg(dev, pipe, req,
+                              USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                              val, reg, buf, len, HZ);
+        return ret;
+}
+
+int cx231xx_send_vendor_cmd(struct cx231xx *dev,
+                                struct VENDOR_REQUEST_IN *ven_req)
+{
+        int ret;
+        int pipe = 0;
+        int unsend_size = 0;
+        u8 *pdata;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        if ((ven_req->wLength > URB_MAX_CTRL_SIZE))
+                return -EINVAL;
+
+        if (ven_req->direction)
+                pipe = usb_rcvctrlpipe(dev->udev, 0);
+        else
+                pipe = usb_sndctrlpipe(dev->udev, 0);
+
+        /*
+         * If the cx23102 read more than 4 bytes with i2c bus,
+         * need chop to 4 byte per request
+         */
+        if ((ven_req->wLength > 4) && ((ven_req->bRequest == 0x4) ||
+                                        (ven_req->bRequest == 0x5) ||
+                                        (ven_req->bRequest == 0x6))) {
+                unsend_size = 0;
+                pdata = ven_req->pBuff;
+
+
+                unsend_size = ven_req->wLength;
+
+                /* the first package */
+                ven_req->wValue = ven_req->wValue & 0xFFFB;
+                ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x2;
+                ret = __usb_control_msg(dev, pipe, ven_req->bRequest,
+                        ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                        ven_req->wValue, ven_req->wIndex, pdata,
+                        0x0004, HZ);
+                unsend_size = unsend_size - 4;
+
+                /* the middle package */
+                ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x42;
+                while (unsend_size - 4 > 0) {
+                        pdata = pdata + 4;
+                        ret = __usb_control_msg(dev, pipe,
+                                ven_req->bRequest,
+                                ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                                ven_req->wValue, ven_req->wIndex, pdata,
+                                0x0004, HZ);
+                        unsend_size = unsend_size - 4;
+                }
+
+                /* the last package */
+                ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x40;
+                pdata = pdata + 4;
+                ret = __usb_control_msg(dev, pipe, ven_req->bRequest,
+                        ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                        ven_req->wValue, ven_req->wIndex, pdata,
+                        unsend_size, HZ);
+        } else {
+                ret = __usb_control_msg(dev, pipe, ven_req->bRequest,
+                                ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                                ven_req->wValue, ven_req->wIndex,
+                                ven_req->pBuff, ven_req->wLength, HZ);
+        }
+
+        return ret;
+}
+
+/*
+ * cx231xx_write_ctrl_reg()
+ * sends data to the usb device, specifying bRequest
+ */
+int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf,
+                           int len)
+{
+        u8 val = 0;
+        int ret;
+        int pipe = usb_sndctrlpipe(dev->udev, 0);
+
+        if (dev->state & DEV_DISCONNECTED)
+                return -ENODEV;
+
+        if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
+                return -EINVAL;
+
+        switch (len) {
+        case 1:
+                val = ENABLE_ONE_BYTE;
+                break;
+        case 2:
+                val = ENABLE_TWE_BYTE;
+                break;
+        case 3:
+                val = ENABLE_THREE_BYTE;
+                break;
+        case 4:
+                val = ENABLE_FOUR_BYTE;
+                break;
+        default:
+                val = 0xFF;     /* invalid option */
+        }
+
+        if (val == 0xFF)
+                return -EINVAL;
+
+        if (reg_debug) {
+                int byte;
+
+                cx231xx_isocdbg("(pipe 0x%08x): "
+                        "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
+                        pipe,
+                        USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                        req, 0, val, reg & 0xff,
+                        reg >> 8, len & 0xff, len >> 8);
+
+                for (byte = 0; byte < len; byte++)
+                        cx231xx_isocdbg(" %02x", (unsigned char)buf[byte]);
+                cx231xx_isocdbg("\n");
+        }
+
+        ret = __usb_control_msg(dev, pipe, req,
+                              USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                              val, reg, buf, len, HZ);
+
+        return ret;
+}
+
+/****************************************************************
+*           USB Alternate Setting functions                     *
+*****************************************************************/
+
+int cx231xx_set_video_alternate(struct cx231xx *dev)
+{
+        int errCode, prev_alt = dev->video_mode.alt;
+        unsigned int min_pkt_size = dev->width * 2 + 4;
+        u32 usb_interface_index = 0;
+
+        /* When image size is bigger than a certain value,
+           the frame size should be increased, otherwise, only
+           green screen will be received.
+         */
+        if (dev->width * 2 * dev->height > 720 * 240 * 2)
+                min_pkt_size *= 2;
+
+        if (dev->width > 360) {
+                /* resolutions: 720,704,640 */
+                dev->video_mode.alt = 3;
+        } else if (dev->width > 180) {
+                /* resolutions: 360,352,320,240 */
+                dev->video_mode.alt = 2;
+        } else if (dev->width > 0) {
+                /* resolutions: 180,176,160,128,88 */
+                dev->video_mode.alt = 1;
+        } else {
+                /* Change to alt0 BULK to release USB bandwidth */
+                dev->video_mode.alt = 0;
+        }
+
+        if (dev->USE_ISO == 0)
+                dev->video_mode.alt = 0;
+
+        cx231xx_coredbg("dev->video_mode.alt= %d\n", dev->video_mode.alt);
+
+        /* Get the correct video interface Index */
+        usb_interface_index =
+            dev->current_pcb_config.hs_config_info[0].interface_info.
+            video_index + 1;
+
+        if (dev->video_mode.alt != prev_alt) {
+                cx231xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
+                                min_pkt_size, dev->video_mode.alt);
+
+                if (dev->video_mode.alt_max_pkt_size != NULL)
+                        dev->video_mode.max_pkt_size =
+                        dev->video_mode.alt_max_pkt_size[dev->video_mode.alt];
+                cx231xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
+                                dev->video_mode.alt,
+                                dev->video_mode.max_pkt_size);
+                errCode =
+                    usb_set_interface(dev->udev, usb_interface_index,
+                                      dev->video_mode.alt);
+                if (errCode < 0) {
+                        cx231xx_errdev
+                            ("cannot change alt number to %d (error=%i)\n",
+                             dev->video_mode.alt, errCode);
+                        return errCode;
+                }
+        }
+        return 0;
+}
+
+int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt)
+{
+        int status = 0;
+        u32 usb_interface_index = 0;
+        u32 max_pkt_size = 0;
+
+        switch (index) {
+        case INDEX_TS1:
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    ts1_index + 1;
+                dev->ts1_mode.alt = alt;
+                if (dev->ts1_mode.alt_max_pkt_size != NULL)
+                        max_pkt_size = dev->ts1_mode.max_pkt_size =
+                            dev->ts1_mode.alt_max_pkt_size[dev->ts1_mode.alt];
+                break;
+        case INDEX_TS2:
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    ts2_index + 1;
+                break;
+        case INDEX_AUDIO:
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    audio_index + 1;
+                dev->adev.alt = alt;
+                if (dev->adev.alt_max_pkt_size != NULL)
+                        max_pkt_size = dev->adev.max_pkt_size =
+                            dev->adev.alt_max_pkt_size[dev->adev.alt];
+                break;
+        case INDEX_VIDEO:
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    video_index + 1;
+                dev->video_mode.alt = alt;
+                if (dev->video_mode.alt_max_pkt_size != NULL)
+                        max_pkt_size = dev->video_mode.max_pkt_size =
+                            dev->video_mode.alt_max_pkt_size[dev->video_mode.
+                                                             alt];
+                break;
+        case INDEX_VANC:
+                if (dev->board.no_alt_vanc)
+                        return 0;
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    vanc_index + 1;
+                dev->vbi_mode.alt = alt;
+                if (dev->vbi_mode.alt_max_pkt_size != NULL)
+                        max_pkt_size = dev->vbi_mode.max_pkt_size =
+                            dev->vbi_mode.alt_max_pkt_size[dev->vbi_mode.alt];
+                break;
+        case INDEX_HANC:
+                usb_interface_index =
+                    dev->current_pcb_config.hs_config_info[0].interface_info.
+                    hanc_index + 1;
+                dev->sliced_cc_mode.alt = alt;
+                if (dev->sliced_cc_mode.alt_max_pkt_size != NULL)
+                        max_pkt_size = dev->sliced_cc_mode.max_pkt_size =
+                            dev->sliced_cc_mode.alt_max_pkt_size[dev->
+                                                                 sliced_cc_mode.
+                                                                 alt];
+                break;
+        default:
+                break;
+        }
+
+        if (alt > 0 && max_pkt_size == 0) {
+                cx231xx_errdev
+                ("can't change interface %d alt no. to %d: Max. Pkt size = 0\n",
+                usb_interface_index, alt);
+                /*To workaround error number=-71 on EP0 for videograbber,
+                 need add following codes.*/
+                if (dev->board.no_alt_vanc)
+                        return -1;
+        }
+
+        cx231xx_coredbg("setting alternate %d with wMaxPacketSize=%u,"
+                        "Interface = %d\n", alt, max_pkt_size,
+                        usb_interface_index);
+
+        if (usb_interface_index > 0) {
+                status = usb_set_interface(dev->udev, usb_interface_index, alt);
+                if (status < 0) {
+                        cx231xx_errdev
+                        ("can't change interface %d alt no. to %d (err=%i)\n",
+                        usb_interface_index, alt, status);
+                        return status;
+                }
+        }
+
+        return status;
+}
+EXPORT_SYMBOL_GPL(cx231xx_set_alt_setting);
+
+int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio)
+{
+        int rc = 0;
+
+        if (!gpio)
+                return rc;
+
+        /* Send GPIO reset sequences specified at board entry */
+        while (gpio->sleep >= 0) {
+                rc = cx231xx_set_gpio_value(dev, gpio->bit, gpio->val);
+                if (rc < 0)
+                        return rc;
+
+                if (gpio->sleep > 0)
+                        msleep(gpio->sleep);
+
+                gpio++;
+        }
+        return rc;
+}
+
+int cx231xx_demod_reset(struct cx231xx *dev)
+{
+
+        u8 status = 0;
+        u8 value[4] = { 0, 0, 0, 0 };
+
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
+                                 value, 4);
+
+        cx231xx_coredbg("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN,
+                        value[0], value[1], value[2], value[3]);
+
+        cx231xx_coredbg("Enter cx231xx_demod_reset()\n");
+
+                value[1] = (u8) 0x3;
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                        msleep(10);
+
+                value[1] = (u8) 0x0;
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                        msleep(10);
+
+                value[1] = (u8) 0x3;
+                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                                                PWR_CTL_EN, value, 4);
+                        msleep(10);
+
+
+
+        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
+                                 value, 4);
+
+        cx231xx_coredbg("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN,
+                        value[0], value[1], value[2], value[3]);
+
+        return status;
+}
+EXPORT_SYMBOL_GPL(cx231xx_demod_reset);
+int is_fw_load(struct cx231xx *dev)
+{
+        return cx231xx_check_fw(dev);
+}
+EXPORT_SYMBOL_GPL(is_fw_load);
+
+int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode)
+{
+        int errCode = 0;
+
+        if (dev->mode == set_mode)
+                return 0;
+
+        if (set_mode == CX231XX_SUSPEND) {
+                /* Set the chip in power saving mode */
+                dev->mode = set_mode;
+        }
+
+        /* Resource is locked */
+        if (dev->mode != CX231XX_SUSPEND)
+                return -EINVAL;
+
+        dev->mode = set_mode;
+
+        if (dev->mode == CX231XX_DIGITAL_MODE)/* Set Digital power mode */ {
+        /* set AGC mode to Digital */
+                switch (dev->model) {
+                case CX231XX_BOARD_CNXT_CARRAERA:
+                case CX231XX_BOARD_CNXT_RDE_250:
+                case CX231XX_BOARD_CNXT_SHELBY:
+                case CX231XX_BOARD_CNXT_RDU_250:
+                errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
+                        break;
+                case CX231XX_BOARD_CNXT_RDE_253S:
+                case CX231XX_BOARD_CNXT_RDU_253S:
+                        errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
+                        break;
+                case CX231XX_BOARD_HAUPPAUGE_EXETER:
+                        errCode = cx231xx_set_power_mode(dev,
+                                                POLARIS_AVMODE_DIGITAL);
+                        break;
+                default:
+                        break;
+                }
+        } else/* Set Analog Power mode */ {
+        /* set AGC mode to Analog */
+                switch (dev->model) {
+                case CX231XX_BOARD_CNXT_CARRAERA:
+                case CX231XX_BOARD_CNXT_RDE_250:
+                case CX231XX_BOARD_CNXT_SHELBY:
+                case CX231XX_BOARD_CNXT_RDU_250:
+                errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
+                        break;
+                case CX231XX_BOARD_CNXT_RDE_253S:
+                case CX231XX_BOARD_CNXT_RDU_253S:
+                case CX231XX_BOARD_HAUPPAUGE_EXETER:
+                case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
+                case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
+                case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
+                errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
+                        break;
+                default:
+                        break;
+                }
+        }
+
+        return errCode ? -EINVAL : 0;
+}
+EXPORT_SYMBOL_GPL(cx231xx_set_mode);
+
+int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size)
+{
+        int errCode = 0;
+        int actlen, ret = -ENOMEM;
+        u32 *buffer;
+
+        buffer = kzalloc(4096, GFP_KERNEL);
+        if (buffer == NULL) {
+                cx231xx_info("out of mem\n");
+                return -ENOMEM;
+        }
+        memcpy(&buffer[0], firmware, 4096);
+
+        ret = usb_bulk_msg(dev->udev, usb_sndbulkpipe(dev->udev, 5),
+                        buffer, 4096, &actlen, 2000);
+
+        if (ret)
+                cx231xx_info("bulk message failed: %d (%d/%d)", ret,
+                                size, actlen);
+        else {
+                errCode = actlen != size ? -1 : 0;
+        }
+        kfree(buffer);
+        return errCode;
+}
+
+/*****************************************************************
+*                URB Streaming functions                         *
+******************************************************************/
+
+/*
+ * IRQ callback, called by URB callback
+ */
+static void cx231xx_isoc_irq_callback(struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        struct cx231xx_video_mode *vmode =
+            container_of(dma_q, struct cx231xx_video_mode, vidq);
+        struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
+        int i;
+
+        switch (urb->status) {
+        case 0:         /* success */
+        case -ETIMEDOUT:        /* NAK */
+                break;
+        case -ECONNRESET:       /* kill */
+        case -ENOENT:
+        case -ESHUTDOWN:
+                return;
+        default:                /* error */
+                cx231xx_isocdbg("urb completition error %d.\n", urb->status);
+                break;
+        }
+
+        /* Copy data from URB */
+        spin_lock(&dev->video_mode.slock);
+        dev->video_mode.isoc_ctl.isoc_copy(dev, urb);
+        spin_unlock(&dev->video_mode.slock);
+
+        /* Reset urb buffers */
+        for (i = 0; i < urb->number_of_packets; i++) {
+                urb->iso_frame_desc[i].status = 0;
+                urb->iso_frame_desc[i].actual_length = 0;
+        }
+
+        urb->status = usb_submit_urb(urb, GFP_ATOMIC);
+        if (urb->status) {
+                cx231xx_isocdbg("urb resubmit failed (error=%i)\n",
+                                urb->status);
+        }
+}
+/*****************************************************************
+*                URB Streaming functions                         *
+******************************************************************/
+
+/*
+ * IRQ callback, called by URB callback
+ */
+static void cx231xx_bulk_irq_callback(struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        struct cx231xx_video_mode *vmode =
+            container_of(dma_q, struct cx231xx_video_mode, vidq);
+        struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
+
+        switch (urb->status) {
+        case 0:         /* success */
+        case -ETIMEDOUT:        /* NAK */
+                break;
+        case -ECONNRESET:       /* kill */
+        case -ENOENT:
+        case -ESHUTDOWN:
+                return;
+        default:                /* error */
+                cx231xx_isocdbg("urb completition error %d.\n", urb->status);
+                break;
+        }
+
+        /* Copy data from URB */
+        spin_lock(&dev->video_mode.slock);
+        dev->video_mode.bulk_ctl.bulk_copy(dev, urb);
+        spin_unlock(&dev->video_mode.slock);
+
+        /* Reset urb buffers */
+        urb->status = usb_submit_urb(urb, GFP_ATOMIC);
+        if (urb->status) {
+                cx231xx_isocdbg("urb resubmit failed (error=%i)\n",
+                                urb->status);
+        }
+}
+/*
+ * Stop and Deallocate URBs
+ */
+void cx231xx_uninit_isoc(struct cx231xx *dev)
+{
+        struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
+        struct urb *urb;
+        int i;
+
+        cx231xx_isocdbg("cx231xx: called cx231xx_uninit_isoc\n");
+
+        dev->video_mode.isoc_ctl.nfields = -1;
+        for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
+                urb = dev->video_mode.isoc_ctl.urb[i];
+                if (urb) {
+                        if (!irqs_disabled())
+                                usb_kill_urb(urb);
+                        else
+                                usb_unlink_urb(urb);
+
+                        if (dev->video_mode.isoc_ctl.transfer_buffer[i]) {
+                                usb_free_coherent(dev->udev,
+                                                  urb->transfer_buffer_length,
+                                                  dev->video_mode.isoc_ctl.
+                                                  transfer_buffer[i],
+                                                  urb->transfer_dma);
+                        }
+                        usb_free_urb(urb);
+                        dev->video_mode.isoc_ctl.urb[i] = NULL;
+                }
+                dev->video_mode.isoc_ctl.transfer_buffer[i] = NULL;
+        }
+
+        kfree(dev->video_mode.isoc_ctl.urb);
+        kfree(dev->video_mode.isoc_ctl.transfer_buffer);
+        kfree(dma_q->p_left_data);
+
+        dev->video_mode.isoc_ctl.urb = NULL;
+        dev->video_mode.isoc_ctl.transfer_buffer = NULL;
+        dev->video_mode.isoc_ctl.num_bufs = 0;
+        dma_q->p_left_data = NULL;
+
+        if (dev->mode_tv == 0)
+                cx231xx_capture_start(dev, 0, Raw_Video);
+        else
+                cx231xx_capture_start(dev, 0, TS1_serial_mode);
+
+
+}
+EXPORT_SYMBOL_GPL(cx231xx_uninit_isoc);
+
+/*
+ * Stop and Deallocate URBs
+ */
+void cx231xx_uninit_bulk(struct cx231xx *dev)
+{
+        struct urb *urb;
+        int i;
+
+        cx231xx_isocdbg("cx231xx: called cx231xx_uninit_bulk\n");
+
+        dev->video_mode.bulk_ctl.nfields = -1;
+        for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
+                urb = dev->video_mode.bulk_ctl.urb[i];
+                if (urb) {
+                        if (!irqs_disabled())
+                                usb_kill_urb(urb);
+                        else
+                                usb_unlink_urb(urb);
+
+                        if (dev->video_mode.bulk_ctl.transfer_buffer[i]) {
+                                usb_free_coherent(dev->udev,
+                                                urb->transfer_buffer_length,
+                                                dev->video_mode.isoc_ctl.
+                                                transfer_buffer[i],
+                                                urb->transfer_dma);
+                        }
+                        usb_free_urb(urb);
+                        dev->video_mode.bulk_ctl.urb[i] = NULL;
+                }
+                dev->video_mode.bulk_ctl.transfer_buffer[i] = NULL;
+        }
+
+        kfree(dev->video_mode.bulk_ctl.urb);
+        kfree(dev->video_mode.bulk_ctl.transfer_buffer);
+
+        dev->video_mode.bulk_ctl.urb = NULL;
+        dev->video_mode.bulk_ctl.transfer_buffer = NULL;
+        dev->video_mode.bulk_ctl.num_bufs = 0;
+
+        if (dev->mode_tv == 0)
+                cx231xx_capture_start(dev, 0, Raw_Video);
+        else
+                cx231xx_capture_start(dev, 0, TS1_serial_mode);
+
+
+}
+EXPORT_SYMBOL_GPL(cx231xx_uninit_bulk);
+
+/*
+ * Allocate URBs and start IRQ
+ */
+int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
+                      int num_bufs, int max_pkt_size,
+                      int (*isoc_copy) (struct cx231xx *dev, struct urb *urb))
+{
+        struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
+        int i;
+        int sb_size, pipe;
+        struct urb *urb;
+        int j, k;
+        int rc;
+
+        /* De-allocates all pending stuff */
+        cx231xx_uninit_isoc(dev);
+
+        dma_q->p_left_data = kzalloc(4096, GFP_KERNEL);
+        if (dma_q->p_left_data == NULL) {
+                cx231xx_info("out of mem\n");
+                return -ENOMEM;
+        }
+
+
+
+        dev->video_mode.isoc_ctl.isoc_copy = isoc_copy;
+        dev->video_mode.isoc_ctl.num_bufs = num_bufs;
+        dma_q->pos = 0;
+        dma_q->is_partial_line = 0;
+        dma_q->last_sav = 0;
+        dma_q->current_field = -1;
+        dma_q->field1_done = 0;
+        dma_q->lines_per_field = dev->height / 2;
+        dma_q->bytes_left_in_line = dev->width << 1;
+        dma_q->lines_completed = 0;
+        dma_q->mpeg_buffer_done = 0;
+        dma_q->left_data_count = 0;
+        dma_q->mpeg_buffer_completed = 0;
+        dma_q->add_ps_package_head = CX231XX_NEED_ADD_PS_PACKAGE_HEAD;
+        dma_q->ps_head[0] = 0x00;
+        dma_q->ps_head[1] = 0x00;
+        dma_q->ps_head[2] = 0x01;
+        dma_q->ps_head[3] = 0xBA;
+        for (i = 0; i < 8; i++)
+                dma_q->partial_buf[i] = 0;
+
+        dev->video_mode.isoc_ctl.urb =
+            kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
+        if (!dev->video_mode.isoc_ctl.urb) {
+                cx231xx_errdev("cannot alloc memory for usb buffers\n");
+                return -ENOMEM;
+        }
+
+        dev->video_mode.isoc_ctl.transfer_buffer =
+            kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
+        if (!dev->video_mode.isoc_ctl.transfer_buffer) {
+                cx231xx_errdev("cannot allocate memory for usbtransfer\n");
+                kfree(dev->video_mode.isoc_ctl.urb);
+                return -ENOMEM;
+        }
+
+        dev->video_mode.isoc_ctl.max_pkt_size = max_pkt_size;
+        dev->video_mode.isoc_ctl.buf = NULL;
+
+        sb_size = max_packets * dev->video_mode.isoc_ctl.max_pkt_size;
+
+        if (dev->mode_tv == 1)
+                dev->video_mode.end_point_addr = 0x81;
+        else
+                dev->video_mode.end_point_addr = 0x84;
+
+
+        /* allocate urbs and transfer buffers */
+        for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
+                urb = usb_alloc_urb(max_packets, GFP_KERNEL);
+                if (!urb) {
+                        cx231xx_err("cannot alloc isoc_ctl.urb %i\n", i);
+                        cx231xx_uninit_isoc(dev);
+                        return -ENOMEM;
+                }
+                dev->video_mode.isoc_ctl.urb[i] = urb;
+
+                dev->video_mode.isoc_ctl.transfer_buffer[i] =
+                    usb_alloc_coherent(dev->udev, sb_size, GFP_KERNEL,
+                                       &urb->transfer_dma);
+                if (!dev->video_mode.isoc_ctl.transfer_buffer[i]) {
+                        cx231xx_err("unable to allocate %i bytes for transfer"
+                                    " buffer %i%s\n",
+                                    sb_size, i,
+                                    in_interrupt() ? " while in int" : "");
+                        cx231xx_uninit_isoc(dev);
+                        return -ENOMEM;
+                }
+                memset(dev->video_mode.isoc_ctl.transfer_buffer[i], 0, sb_size);
+
+                pipe =
+                    usb_rcvisocpipe(dev->udev, dev->video_mode.end_point_addr);
+
+                usb_fill_int_urb(urb, dev->udev, pipe,
+                                 dev->video_mode.isoc_ctl.transfer_buffer[i],
+                                 sb_size, cx231xx_isoc_irq_callback, dma_q, 1);
+
+                urb->number_of_packets = max_packets;
+                urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
+
+                k = 0;
+                for (j = 0; j < max_packets; j++) {
+                        urb->iso_frame_desc[j].offset = k;
+                        urb->iso_frame_desc[j].length =
+                            dev->video_mode.isoc_ctl.max_pkt_size;
+                        k += dev->video_mode.isoc_ctl.max_pkt_size;
+                }
+        }
+
+        init_waitqueue_head(&dma_q->wq);
+
+        /* submit urbs and enables IRQ */
+        for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
+                rc = usb_submit_urb(dev->video_mode.isoc_ctl.urb[i],
+                                    GFP_ATOMIC);
+                if (rc) {
+                        cx231xx_err("submit of urb %i failed (error=%i)\n", i,
+                                    rc);
+                        cx231xx_uninit_isoc(dev);
+                        return rc;
+                }
+        }
+
+        if (dev->mode_tv == 0)
+                cx231xx_capture_start(dev, 1, Raw_Video);
+        else
+                cx231xx_capture_start(dev, 1, TS1_serial_mode);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(cx231xx_init_isoc);
+
+/*
+ * Allocate URBs and start IRQ
+ */
+int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
+                      int num_bufs, int max_pkt_size,
+                      int (*bulk_copy) (struct cx231xx *dev, struct urb *urb))
+{
+        struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
+        int i;
+        int sb_size, pipe;
+        struct urb *urb;
+        int rc;
+
+        dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
+
+        cx231xx_coredbg("Setting Video mux to %d\n", dev->video_input);
+
+        video_mux(dev, dev->video_input);
+
+        /* De-allocates all pending stuff */
+        cx231xx_uninit_bulk(dev);
+
+        dev->video_mode.bulk_ctl.bulk_copy = bulk_copy;
+        dev->video_mode.bulk_ctl.num_bufs = num_bufs;
+        dma_q->pos = 0;
+        dma_q->is_partial_line = 0;
+        dma_q->last_sav = 0;
+        dma_q->current_field = -1;
+        dma_q->field1_done = 0;
+        dma_q->lines_per_field = dev->height / 2;
+        dma_q->bytes_left_in_line = dev->width << 1;
+        dma_q->lines_completed = 0;
+        dma_q->mpeg_buffer_done = 0;
+        dma_q->left_data_count = 0;
+        dma_q->mpeg_buffer_completed = 0;
+        dma_q->ps_head[0] = 0x00;
+        dma_q->ps_head[1] = 0x00;
+        dma_q->ps_head[2] = 0x01;
+        dma_q->ps_head[3] = 0xBA;
+        for (i = 0; i < 8; i++)
+                dma_q->partial_buf[i] = 0;
+
+        dev->video_mode.bulk_ctl.urb =
+            kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
+        if (!dev->video_mode.bulk_ctl.urb) {
+                cx231xx_errdev("cannot alloc memory for usb buffers\n");
+                return -ENOMEM;
+        }
+
+        dev->video_mode.bulk_ctl.transfer_buffer =
+            kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
+        if (!dev->video_mode.bulk_ctl.transfer_buffer) {
+                cx231xx_errdev("cannot allocate memory for usbtransfer\n");
+                kfree(dev->video_mode.bulk_ctl.urb);
+                return -ENOMEM;
+        }
+
+        dev->video_mode.bulk_ctl.max_pkt_size = max_pkt_size;
+        dev->video_mode.bulk_ctl.buf = NULL;
+
+        sb_size = max_packets * dev->video_mode.bulk_ctl.max_pkt_size;
+
+        if (dev->mode_tv == 1)
+                dev->video_mode.end_point_addr = 0x81;
+        else
+                dev->video_mode.end_point_addr = 0x84;
+
+
+        /* allocate urbs and transfer buffers */
+        for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
+                urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (!urb) {
+                        cx231xx_err("cannot alloc bulk_ctl.urb %i\n", i);
+                        cx231xx_uninit_bulk(dev);
+                        return -ENOMEM;
+                }
+                dev->video_mode.bulk_ctl.urb[i] = urb;
+                urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
+
+                dev->video_mode.bulk_ctl.transfer_buffer[i] =
+                    usb_alloc_coherent(dev->udev, sb_size, GFP_KERNEL,
+                                     &urb->transfer_dma);
+                if (!dev->video_mode.bulk_ctl.transfer_buffer[i]) {
+                        cx231xx_err("unable to allocate %i bytes for transfer"
+                                    " buffer %i%s\n",
+                                    sb_size, i,
+                                    in_interrupt() ? " while in int" : "");
+                        cx231xx_uninit_bulk(dev);
+                        return -ENOMEM;
+                }
+                memset(dev->video_mode.bulk_ctl.transfer_buffer[i], 0, sb_size);
+
+                pipe = usb_rcvbulkpipe(dev->udev,
+                                 dev->video_mode.end_point_addr);
+                usb_fill_bulk_urb(urb, dev->udev, pipe,
+                                  dev->video_mode.bulk_ctl.transfer_buffer[i],
+                                  sb_size, cx231xx_bulk_irq_callback, dma_q);
+        }
+
+        init_waitqueue_head(&dma_q->wq);
+
+        /* submit urbs and enables IRQ */
+        for (i = 0; i < dev->video_mode.bulk_ctl.num_bufs; i++) {
+                rc = usb_submit_urb(dev->video_mode.bulk_ctl.urb[i],
+                                    GFP_ATOMIC);
+                if (rc) {
+                        cx231xx_err("submit of urb %i failed (error=%i)\n", i,
+                                    rc);
+                        cx231xx_uninit_bulk(dev);
+                        return rc;
+                }
+        }
+
+        if (dev->mode_tv == 0)
+                cx231xx_capture_start(dev, 1, Raw_Video);
+        else
+                cx231xx_capture_start(dev, 1, TS1_serial_mode);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(cx231xx_init_bulk);
+void cx231xx_stop_TS1(struct cx231xx *dev)
+{
+        u8 val[4] = { 0, 0, 0, 0 };
+
+        val[0] = 0x00;
+        val[1] = 0x03;
+        val[2] = 0x00;
+        val[3] = 0x00;
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                        TS_MODE_REG, val, 4);
+
+        val[0] = 0x00;
+        val[1] = 0x70;
+        val[2] = 0x04;
+        val[3] = 0x00;
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                        TS1_CFG_REG, val, 4);
+}
+/* EXPORT_SYMBOL_GPL(cx231xx_stop_TS1); */
+void cx231xx_start_TS1(struct cx231xx *dev)
+{
+        u8 val[4] = { 0, 0, 0, 0 };
+
+        val[0] = 0x03;
+        val[1] = 0x03;
+        val[2] = 0x00;
+        val[3] = 0x00;
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                        TS_MODE_REG, val, 4);
+
+        val[0] = 0x04;
+        val[1] = 0xA3;
+        val[2] = 0x3B;
+        val[3] = 0x00;
+        cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
+                        TS1_CFG_REG, val, 4);
+}
+/* EXPORT_SYMBOL_GPL(cx231xx_start_TS1); */
+/*****************************************************************
+*             Device Init/UnInit functions                       *
+******************************************************************/
+int cx231xx_dev_init(struct cx231xx *dev)
+{
+        int errCode = 0;
+
+        /* Initialize I2C bus */
+
+        /* External Master 1 Bus */
+        dev->i2c_bus[0].nr = 0;
+        dev->i2c_bus[0].dev = dev;
+        dev->i2c_bus[0].i2c_period = I2C_SPEED_100K;    /* 100 KHz */
+        dev->i2c_bus[0].i2c_nostop = 0;
+        dev->i2c_bus[0].i2c_reserve = 0;
+
+        /* External Master 2 Bus */
+        dev->i2c_bus[1].nr = 1;
+        dev->i2c_bus[1].dev = dev;
+        dev->i2c_bus[1].i2c_period = I2C_SPEED_100K;    /* 100 KHz */
+        dev->i2c_bus[1].i2c_nostop = 0;
+        dev->i2c_bus[1].i2c_reserve = 0;
+
+        /* Internal Master 3 Bus */
+        dev->i2c_bus[2].nr = 2;
+        dev->i2c_bus[2].dev = dev;
+        dev->i2c_bus[2].i2c_period = I2C_SPEED_100K;    /* 100kHz */
+        dev->i2c_bus[2].i2c_nostop = 0;
+        dev->i2c_bus[2].i2c_reserve = 0;
+
+        /* register I2C buses */
+        cx231xx_i2c_register(&dev->i2c_bus[0]);
+        cx231xx_i2c_register(&dev->i2c_bus[1]);
+        cx231xx_i2c_register(&dev->i2c_bus[2]);
+
+        /* init hardware */
+        /* Note : with out calling set power mode function,
+        afe can not be set up correctly */
+        if (dev->board.external_av) {
+                errCode = cx231xx_set_power_mode(dev,
+                                 POLARIS_AVMODE_ENXTERNAL_AV);
+                if (errCode < 0) {
+                        cx231xx_errdev
+                        ("%s: Failed to set Power - errCode [%d]!\n",
+                        __func__, errCode);
+                        return errCode;
+                }
+        } else {
+                errCode = cx231xx_set_power_mode(dev,
+                                 POLARIS_AVMODE_ANALOGT_TV);
+                if (errCode < 0) {
+                        cx231xx_errdev
+                        ("%s: Failed to set Power - errCode [%d]!\n",
+                        __func__, errCode);
+                        return errCode;
+                }
+        }
+
+        /* reset the Tuner, if it is a Xceive tuner */
+        if ((dev->board.tuner_type == TUNER_XC5000) ||
+            (dev->board.tuner_type == TUNER_XC2028))
+                        cx231xx_gpio_set(dev, dev->board.tuner_gpio);
+
+        /* initialize Colibri block */
+        errCode = cx231xx_afe_init_super_block(dev, 0x23c);
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("%s: cx231xx_afe init super block - errCode [%d]!\n",
+                     __func__, errCode);
+                return errCode;
+        }
+        errCode = cx231xx_afe_init_channels(dev);
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("%s: cx231xx_afe init channels - errCode [%d]!\n",
+                     __func__, errCode);
+                return errCode;
+        }
+
+        /* Set DIF in By pass mode */
+        errCode = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
+                     __func__, errCode);
+                return errCode;
+        }
+
+        /* I2S block related functions */
+        errCode = cx231xx_i2s_blk_initialize(dev);
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("%s: cx231xx_i2s block initialize - errCode [%d]!\n",
+                     __func__, errCode);
+                return errCode;
+        }
+
+        /* init control pins */
+        errCode = cx231xx_init_ctrl_pin_status(dev);
+        if (errCode < 0) {
+                cx231xx_errdev("%s: cx231xx_init ctrl pins - errCode [%d]!\n",
+                               __func__, errCode);
+                return errCode;
+        }
+
+        /* set AGC mode to Analog */
+        switch (dev->model) {
+        case CX231XX_BOARD_CNXT_CARRAERA:
+        case CX231XX_BOARD_CNXT_RDE_250:
+        case CX231XX_BOARD_CNXT_SHELBY:
+        case CX231XX_BOARD_CNXT_RDU_250:
+        errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
+                break;
+        case CX231XX_BOARD_CNXT_RDE_253S:
+        case CX231XX_BOARD_CNXT_RDU_253S:
+        case CX231XX_BOARD_HAUPPAUGE_EXETER:
+        case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
+        case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
+        errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0);
+                break;
+        default:
+                break;
+        }
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("%s: cx231xx_AGC mode to Analog - errCode [%d]!\n",
+                     __func__, errCode);
+                return errCode;
+        }
+
+        /* set all alternate settings to zero initially */
+        cx231xx_set_alt_setting(dev, INDEX_VIDEO, 0);
+        cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
+        cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
+        if (dev->board.has_dvb)
+                cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
+
+        /* set the I2C master port to 3 on channel 1 */
+        errCode = cx231xx_enable_i2c_port_3(dev, true);
+
+        return errCode;
+}
+EXPORT_SYMBOL_GPL(cx231xx_dev_init);
+
+void cx231xx_dev_uninit(struct cx231xx *dev)
+{
+        /* Un Initialize I2C bus */
+        cx231xx_i2c_unregister(&dev->i2c_bus[2]);
+        cx231xx_i2c_unregister(&dev->i2c_bus[1]);
+        cx231xx_i2c_unregister(&dev->i2c_bus[0]);
+}
+EXPORT_SYMBOL_GPL(cx231xx_dev_uninit);
+
+/*****************************************************************
+*              G P I O related functions                         *
+******************************************************************/
+int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
+                          u8 len, u8 request, u8 direction)
+{
+        int status = 0;
+        struct VENDOR_REQUEST_IN ven_req;
+
+        /* Set wValue */
+        ven_req.wValue = (u16) (gpio_bit >> 16 & 0xffff);
+
+        /* set request */
+        if (!request) {
+                if (direction)
+                        ven_req.bRequest = VRT_GET_GPIO;        /* 0x8 gpio */
+                else
+                        ven_req.bRequest = VRT_SET_GPIO;        /* 0x9 gpio */
+        } else {
+                if (direction)
+                        ven_req.bRequest = VRT_GET_GPIE;        /* 0xa gpie */
+                else
+                        ven_req.bRequest = VRT_SET_GPIE;        /* 0xb gpie */
+        }
+
+        /* set index value */
+        ven_req.wIndex = (u16) (gpio_bit & 0xffff);
+
+        /* set wLength value */
+        ven_req.wLength = len;
+
+        /* set bData value */
+        ven_req.bData = 0;
+
+        /* set the buffer for read / write */
+        ven_req.pBuff = gpio_val;
+
+        /* set the direction */
+        if (direction) {
+                ven_req.direction = USB_DIR_IN;
+                memset(ven_req.pBuff, 0x00, ven_req.wLength);
+        } else
+                ven_req.direction = USB_DIR_OUT;
+
+
+        /* call common vendor command request */
+        status = cx231xx_send_vendor_cmd(dev, &ven_req);
+        if (status < 0) {
+                cx231xx_info
+                    ("UsbInterface::sendCommand, failed with status -%d\n",
+                     status);
+        }
+
+        return status;
+}
+EXPORT_SYMBOL_GPL(cx231xx_send_gpio_cmd);
+
+/*****************************************************************
+ *    C O N T R O L - Register R E A D / W R I T E functions     *
+ *****************************************************************/
+int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode)
+{
+        u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
+        u32 tmp = 0;
+        int status = 0;
+
+        status =
+            cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, address, value, 4);
+        if (status < 0)
+                return status;
+
+        tmp = *((u32 *) value);
+        tmp |= mode;
+
+        value[0] = (u8) tmp;
+        value[1] = (u8) (tmp >> 8);
+        value[2] = (u8) (tmp >> 16);
+        value[3] = (u8) (tmp >> 24);
+
+        status =
+            cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, address, value, 4);
+
+        return status;
+}
+
+/*****************************************************************
+ *            I 2 C Internal C O N T R O L   functions           *
+ *****************************************************************/
+int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                          u8 saddr_len, u32 *data, u8 data_len, int master)
+{
+        int status = 0;
+        struct cx231xx_i2c_xfer_data req_data;
+        u8 value[64] = "0";
+
+        if (saddr_len == 0)
+                saddr = 0;
+        else if (saddr_len == 1)
+                saddr &= 0xff;
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = dev_addr >> 1;
+        req_data.direction = I2C_M_RD;
+        req_data.saddr_len = saddr_len;
+        req_data.saddr_dat = saddr;
+        req_data.buf_size = data_len;
+        req_data.p_buffer = (u8 *) value;
+
+        /* usb send command */
+        if (master == 0)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0],
+                                         &req_data);
+        else if (master == 1)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[1],
+                                         &req_data);
+        else if (master == 2)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[2],
+                                         &req_data);
+
+        if (status >= 0) {
+                /* Copy the data read back to main buffer */
+                if (data_len == 1)
+                        *data = value[0];
+                else if (data_len == 4)
+                        *data =
+                            value[0] | value[1] << 8 | value[2] << 16 | value[3]
+                            << 24;
+                else if (data_len > 4)
+                        *data = value[saddr];
+        }
+
+        return status;
+}
+
+int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                           u8 saddr_len, u32 data, u8 data_len, int master)
+{
+        int status = 0;
+        u8 value[4] = { 0, 0, 0, 0 };
+        struct cx231xx_i2c_xfer_data req_data;
+
+        value[0] = (u8) data;
+        value[1] = (u8) (data >> 8);
+        value[2] = (u8) (data >> 16);
+        value[3] = (u8) (data >> 24);
+
+        if (saddr_len == 0)
+                saddr = 0;
+        else if (saddr_len == 1)
+                saddr &= 0xff;
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = dev_addr >> 1;
+        req_data.direction = 0;
+        req_data.saddr_len = saddr_len;
+        req_data.saddr_dat = saddr;
+        req_data.buf_size = data_len;
+        req_data.p_buffer = value;
+
+        /* usb send command */
+        if (master == 0)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0],
+                                 &req_data);
+        else if (master == 1)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[1],
+                                 &req_data);
+        else if (master == 2)
+                status = dev->cx231xx_send_usb_command(&dev->i2c_bus[2],
+                                 &req_data);
+
+        return status;
+}
+
+int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                          u8 saddr_len, u32 *data, u8 data_len)
+{
+        int status = 0;
+        struct cx231xx_i2c_xfer_data req_data;
+        u8 value[4] = { 0, 0, 0, 0 };
+
+        if (saddr_len == 0)
+                saddr = 0;
+        else if (saddr_len == 1)
+                saddr &= 0xff;
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = dev_addr >> 1;
+        req_data.direction = I2C_M_RD;
+        req_data.saddr_len = saddr_len;
+        req_data.saddr_dat = saddr;
+        req_data.buf_size = data_len;
+        req_data.p_buffer = (u8 *) value;
+
+        /* usb send command */
+        status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0], &req_data);
+
+        if (status >= 0) {
+                /* Copy the data read back to main buffer */
+                if (data_len == 1)
+                        *data = value[0];
+                else
+                        *data =
+                            value[0] | value[1] << 8 | value[2] << 16 | value[3]
+                            << 24;
+        }
+
+        return status;
+}
+
+int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                           u8 saddr_len, u32 data, u8 data_len)
+{
+        int status = 0;
+        u8 value[4] = { 0, 0, 0, 0 };
+        struct cx231xx_i2c_xfer_data req_data;
+
+        value[0] = (u8) data;
+        value[1] = (u8) (data >> 8);
+        value[2] = (u8) (data >> 16);
+        value[3] = (u8) (data >> 24);
+
+        if (saddr_len == 0)
+                saddr = 0;
+        else if (saddr_len == 1)
+                saddr &= 0xff;
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = dev_addr >> 1;
+        req_data.direction = 0;
+        req_data.saddr_len = saddr_len;
+        req_data.saddr_dat = saddr;
+        req_data.buf_size = data_len;
+        req_data.p_buffer = value;
+
+        /* usb send command */
+        status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0], &req_data);
+
+        return status;
+}
+
+int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
+                           u16 register_address, u8 bit_start, u8 bit_end,
+                           u32 value)
+{
+        int status = 0;
+        u32 tmp;
+        u32 mask = 0;
+        int i;
+
+        if (bit_start > (size - 1) || bit_end > (size - 1))
+                return -1;
+
+        if (size == 8) {
+                status =
+                    cx231xx_read_i2c_data(dev, dev_addr, register_address, 2,
+                                          &tmp, 1);
+        } else {
+                status =
+                    cx231xx_read_i2c_data(dev, dev_addr, register_address, 2,
+                                          &tmp, 4);
+        }
+
+        if (status < 0)
+                return status;
+
+        mask = 1 << bit_end;
+        for (i = bit_end; i > bit_start && i > 0; i--)
+                mask = mask + (1 << (i - 1));
+
+        value <<= bit_start;
+
+        if (size == 8) {
+                tmp &= ~mask;
+                tmp |= value;
+                tmp &= 0xff;
+                status =
+                    cx231xx_write_i2c_data(dev, dev_addr, register_address, 2,
+                                           tmp, 1);
+        } else {
+                tmp &= ~mask;
+                tmp |= value;
+                status =
+                    cx231xx_write_i2c_data(dev, dev_addr, register_address, 2,
+                                           tmp, 4);
+        }
+
+        return status;
+}
+
+int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
+                                        u16 saddr, u32 mask, u32 value)
+{
+        u32 temp;
+        int status = 0;
+
+        status = cx231xx_read_i2c_data(dev, dev_addr, saddr, 2, &temp, 4);
+
+        if (status < 0)
+                return status;
+
+        temp &= ~mask;
+        temp |= value;
+
+        status = cx231xx_write_i2c_data(dev, dev_addr, saddr, 2, temp, 4);
+
+        return status;
+}
+
+u32 cx231xx_set_field(u32 field_mask, u32 data)
+{
+        u32 temp;
+
+        for (temp = field_mask; (temp & 1) == 0; temp >>= 1)
+                data <<= 1;
+
+        return data;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-dif.h b/drivers/media/usb/cx231xx/cx231xx-dif.h
new file mode 100644
index 000000000000..2b63c2f6d3b0
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-dif.h
@@ -0,0 +1,3178 @@
+/*
+ *  cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices
+ *
+ *  Copyright {C} 2009 <Bill.Liu@conexant.com>
+ *
+ *  This program is free software, you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY, without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program, if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _CX231XX_DIF_H
+#define _CX231XX_DIF_H
+
+#include "cx231xx-reg.h"
+
+struct dif_settings{
+        u32 if_freq;
+        u32 register_address;
+        u32 value;
+};
+
+static struct dif_settings Dif_set_array[] = {
+
+/*case 3000000:*/
+/* BEGIN - DIF BPF register values from 30_quant.dat*/
+{3000000, DIF_BPF_COEFF01,    0x00000002},
+{3000000, DIF_BPF_COEFF23,    0x00080012},
+{3000000, DIF_BPF_COEFF45,    0x001e0024},
+{3000000, DIF_BPF_COEFF67,    0x001bfff8},
+{3000000, DIF_BPF_COEFF89,    0xffb4ff50},
+{3000000, DIF_BPF_COEFF1011,  0xfed8fe68},
+{3000000, DIF_BPF_COEFF1213,  0xfe24fe34},
+{3000000, DIF_BPF_COEFF1415,  0xfebaffc7},
+{3000000, DIF_BPF_COEFF1617,  0x014d031f},
+{3000000, DIF_BPF_COEFF1819,  0x04f0065d},
+{3000000, DIF_BPF_COEFF2021,  0x07010688},
+{3000000, DIF_BPF_COEFF2223,  0x04c901d6},
+{3000000, DIF_BPF_COEFF2425,  0xfe00f9d3},
+{3000000, DIF_BPF_COEFF2627,  0xf600f342},
+{3000000, DIF_BPF_COEFF2829,  0xf235f337},
+{3000000, DIF_BPF_COEFF3031,  0xf64efb22},
+{3000000, DIF_BPF_COEFF3233,  0x0105070f},
+{3000000, DIF_BPF_COEFF3435,  0x0c460fce},
+{3000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 30_quant.dat*/
+
+
+/*case 3100000:*/
+/* BEGIN - DIF BPF register values from 31_quant.dat*/
+{3100000, DIF_BPF_COEFF01,    0x00000001},
+{3100000, DIF_BPF_COEFF23,    0x00070012},
+{3100000, DIF_BPF_COEFF45,    0x00220032},
+{3100000, DIF_BPF_COEFF67,    0x00370026},
+{3100000, DIF_BPF_COEFF89,    0xfff0ff91},
+{3100000, DIF_BPF_COEFF1011,  0xff0efe7c},
+{3100000, DIF_BPF_COEFF1213,  0xfe01fdcc},
+{3100000, DIF_BPF_COEFF1415,  0xfe0afedb},
+{3100000, DIF_BPF_COEFF1617,  0x00440224},
+{3100000, DIF_BPF_COEFF1819,  0x0434060c},
+{3100000, DIF_BPF_COEFF2021,  0x0738074e},
+{3100000, DIF_BPF_COEFF2223,  0x06090361},
+{3100000, DIF_BPF_COEFF2425,  0xff99fb39},
+{3100000, DIF_BPF_COEFF2627,  0xf6fef3b6},
+{3100000, DIF_BPF_COEFF2829,  0xf21af2a5},
+{3100000, DIF_BPF_COEFF3031,  0xf573fa33},
+{3100000, DIF_BPF_COEFF3233,  0x0034067d},
+{3100000, DIF_BPF_COEFF3435,  0x0bfb0fb9},
+{3100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 31_quant.dat*/
+
+
+/*case 3200000:*/
+/* BEGIN - DIF BPF register values from 32_quant.dat*/
+{3200000, DIF_BPF_COEFF01,    0x00000000},
+{3200000, DIF_BPF_COEFF23,    0x0004000e},
+{3200000, DIF_BPF_COEFF45,    0x00200038},
+{3200000, DIF_BPF_COEFF67,    0x004c004f},
+{3200000, DIF_BPF_COEFF89,    0x002fffdf},
+{3200000, DIF_BPF_COEFF1011,  0xff5cfeb6},
+{3200000, DIF_BPF_COEFF1213,  0xfe0dfd92},
+{3200000, DIF_BPF_COEFF1415,  0xfd7ffe03},
+{3200000, DIF_BPF_COEFF1617,  0xff36010a},
+{3200000, DIF_BPF_COEFF1819,  0x03410575},
+{3200000, DIF_BPF_COEFF2021,  0x072607d2},
+{3200000, DIF_BPF_COEFF2223,  0x071804d5},
+{3200000, DIF_BPF_COEFF2425,  0x0134fcb7},
+{3200000, DIF_BPF_COEFF2627,  0xf81ff451},
+{3200000, DIF_BPF_COEFF2829,  0xf223f22e},
+{3200000, DIF_BPF_COEFF3031,  0xf4a7f94b},
+{3200000, DIF_BPF_COEFF3233,  0xff6405e8},
+{3200000, DIF_BPF_COEFF3435,  0x0bae0fa4},
+{3200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 32_quant.dat*/
+
+
+/*case 3300000:*/
+/* BEGIN - DIF BPF register values from 33_quant.dat*/
+{3300000, DIF_BPF_COEFF01,    0x0000ffff},
+{3300000, DIF_BPF_COEFF23,    0x00000008},
+{3300000, DIF_BPF_COEFF45,    0x001a0036},
+{3300000, DIF_BPF_COEFF67,    0x0056006d},
+{3300000, DIF_BPF_COEFF89,    0x00670030},
+{3300000, DIF_BPF_COEFF1011,  0xffbdff10},
+{3300000, DIF_BPF_COEFF1213,  0xfe46fd8d},
+{3300000, DIF_BPF_COEFF1415,  0xfd25fd4f},
+{3300000, DIF_BPF_COEFF1617,  0xfe35ffe0},
+{3300000, DIF_BPF_COEFF1819,  0x0224049f},
+{3300000, DIF_BPF_COEFF2021,  0x06c9080e},
+{3300000, DIF_BPF_COEFF2223,  0x07ef0627},
+{3300000, DIF_BPF_COEFF2425,  0x02c9fe45},
+{3300000, DIF_BPF_COEFF2627,  0xf961f513},
+{3300000, DIF_BPF_COEFF2829,  0xf250f1d2},
+{3300000, DIF_BPF_COEFF3031,  0xf3ecf869},
+{3300000, DIF_BPF_COEFF3233,  0xfe930552},
+{3300000, DIF_BPF_COEFF3435,  0x0b5f0f8f},
+{3300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 33_quant.dat*/
+
+
+/*case 3400000:*/
+/* BEGIN - DIF BPF register values from 34_quant.dat*/
+{3400000, DIF_BPF_COEFF01,    0xfffffffe},
+{3400000, DIF_BPF_COEFF23,    0xfffd0001},
+{3400000, DIF_BPF_COEFF45,    0x000f002c},
+{3400000, DIF_BPF_COEFF67,    0x0054007d},
+{3400000, DIF_BPF_COEFF89,    0x0093007c},
+{3400000, DIF_BPF_COEFF1011,  0x0024ff82},
+{3400000, DIF_BPF_COEFF1213,  0xfea6fdbb},
+{3400000, DIF_BPF_COEFF1415,  0xfd03fcca},
+{3400000, DIF_BPF_COEFF1617,  0xfd51feb9},
+{3400000, DIF_BPF_COEFF1819,  0x00eb0392},
+{3400000, DIF_BPF_COEFF2021,  0x06270802},
+{3400000, DIF_BPF_COEFF2223,  0x08880750},
+{3400000, DIF_BPF_COEFF2425,  0x044dffdb},
+{3400000, DIF_BPF_COEFF2627,  0xfabdf5f8},
+{3400000, DIF_BPF_COEFF2829,  0xf2a0f193},
+{3400000, DIF_BPF_COEFF3031,  0xf342f78f},
+{3400000, DIF_BPF_COEFF3233,  0xfdc404b9},
+{3400000, DIF_BPF_COEFF3435,  0x0b0e0f78},
+{3400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 34_quant.dat*/
+
+
+/*case 3500000:*/
+/* BEGIN - DIF BPF register values from 35_quant.dat*/
+{3500000, DIF_BPF_COEFF01,    0xfffffffd},
+{3500000, DIF_BPF_COEFF23,    0xfffafff9},
+{3500000, DIF_BPF_COEFF45,    0x0002001b},
+{3500000, DIF_BPF_COEFF67,    0x0046007d},
+{3500000, DIF_BPF_COEFF89,    0x00ad00ba},
+{3500000, DIF_BPF_COEFF1011,  0x00870000},
+{3500000, DIF_BPF_COEFF1213,  0xff26fe1a},
+{3500000, DIF_BPF_COEFF1415,  0xfd1bfc7e},
+{3500000, DIF_BPF_COEFF1617,  0xfc99fda4},
+{3500000, DIF_BPF_COEFF1819,  0xffa5025c},
+{3500000, DIF_BPF_COEFF2021,  0x054507ad},
+{3500000, DIF_BPF_COEFF2223,  0x08dd0847},
+{3500000, DIF_BPF_COEFF2425,  0x05b80172},
+{3500000, DIF_BPF_COEFF2627,  0xfc2ef6ff},
+{3500000, DIF_BPF_COEFF2829,  0xf313f170},
+{3500000, DIF_BPF_COEFF3031,  0xf2abf6bd},
+{3500000, DIF_BPF_COEFF3233,  0xfcf6041f},
+{3500000, DIF_BPF_COEFF3435,  0x0abc0f61},
+{3500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 35_quant.dat*/
+
+
+/*case 3600000:*/
+/* BEGIN - DIF BPF register values from 36_quant.dat*/
+{3600000, DIF_BPF_COEFF01,    0xfffffffd},
+{3600000, DIF_BPF_COEFF23,    0xfff8fff3},
+{3600000, DIF_BPF_COEFF45,    0xfff50006},
+{3600000, DIF_BPF_COEFF67,    0x002f006c},
+{3600000, DIF_BPF_COEFF89,    0x00b200e3},
+{3600000, DIF_BPF_COEFF1011,  0x00dc007e},
+{3600000, DIF_BPF_COEFF1213,  0xffb9fea0},
+{3600000, DIF_BPF_COEFF1415,  0xfd6bfc71},
+{3600000, DIF_BPF_COEFF1617,  0xfc17fcb1},
+{3600000, DIF_BPF_COEFF1819,  0xfe65010b},
+{3600000, DIF_BPF_COEFF2021,  0x042d0713},
+{3600000, DIF_BPF_COEFF2223,  0x08ec0906},
+{3600000, DIF_BPF_COEFF2425,  0x07020302},
+{3600000, DIF_BPF_COEFF2627,  0xfdaff823},
+{3600000, DIF_BPF_COEFF2829,  0xf3a7f16a},
+{3600000, DIF_BPF_COEFF3031,  0xf228f5f5},
+{3600000, DIF_BPF_COEFF3233,  0xfc2a0384},
+{3600000, DIF_BPF_COEFF3435,  0x0a670f4a},
+{3600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 36_quant.dat*/
+
+
+/*case 3700000:*/
+/* BEGIN - DIF BPF register values from 37_quant.dat*/
+{3700000, DIF_BPF_COEFF01,    0x0000fffd},
+{3700000, DIF_BPF_COEFF23,    0xfff7ffef},
+{3700000, DIF_BPF_COEFF45,    0xffe9fff1},
+{3700000, DIF_BPF_COEFF67,    0x0010004d},
+{3700000, DIF_BPF_COEFF89,    0x00a100f2},
+{3700000, DIF_BPF_COEFF1011,  0x011a00f0},
+{3700000, DIF_BPF_COEFF1213,  0x0053ff44},
+{3700000, DIF_BPF_COEFF1415,  0xfdedfca2},
+{3700000, DIF_BPF_COEFF1617,  0xfbd3fbef},
+{3700000, DIF_BPF_COEFF1819,  0xfd39ffae},
+{3700000, DIF_BPF_COEFF2021,  0x02ea0638},
+{3700000, DIF_BPF_COEFF2223,  0x08b50987},
+{3700000, DIF_BPF_COEFF2425,  0x08230483},
+{3700000, DIF_BPF_COEFF2627,  0xff39f960},
+{3700000, DIF_BPF_COEFF2829,  0xf45bf180},
+{3700000, DIF_BPF_COEFF3031,  0xf1b8f537},
+{3700000, DIF_BPF_COEFF3233,  0xfb6102e7},
+{3700000, DIF_BPF_COEFF3435,  0x0a110f32},
+{3700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 37_quant.dat*/
+
+
+/*case 3800000:*/
+/* BEGIN - DIF BPF register values from 38_quant.dat*/
+{3800000, DIF_BPF_COEFF01,    0x0000fffe},
+{3800000, DIF_BPF_COEFF23,    0xfff9ffee},
+{3800000, DIF_BPF_COEFF45,    0xffe1ffdd},
+{3800000, DIF_BPF_COEFF67,    0xfff00024},
+{3800000, DIF_BPF_COEFF89,    0x007c00e5},
+{3800000, DIF_BPF_COEFF1011,  0x013a014a},
+{3800000, DIF_BPF_COEFF1213,  0x00e6fff8},
+{3800000, DIF_BPF_COEFF1415,  0xfe98fd0f},
+{3800000, DIF_BPF_COEFF1617,  0xfbd3fb67},
+{3800000, DIF_BPF_COEFF1819,  0xfc32fe54},
+{3800000, DIF_BPF_COEFF2021,  0x01880525},
+{3800000, DIF_BPF_COEFF2223,  0x083909c7},
+{3800000, DIF_BPF_COEFF2425,  0x091505ee},
+{3800000, DIF_BPF_COEFF2627,  0x00c7fab3},
+{3800000, DIF_BPF_COEFF2829,  0xf52df1b4},
+{3800000, DIF_BPF_COEFF3031,  0xf15df484},
+{3800000, DIF_BPF_COEFF3233,  0xfa9b0249},
+{3800000, DIF_BPF_COEFF3435,  0x09ba0f19},
+{3800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 38_quant.dat*/
+
+
+/*case 3900000:*/
+/* BEGIN - DIF BPF register values from 39_quant.dat*/
+{3900000, DIF_BPF_COEFF01,    0x00000000},
+{3900000, DIF_BPF_COEFF23,    0xfffbfff0},
+{3900000, DIF_BPF_COEFF45,    0xffdeffcf},
+{3900000, DIF_BPF_COEFF67,    0xffd1fff6},
+{3900000, DIF_BPF_COEFF89,    0x004800be},
+{3900000, DIF_BPF_COEFF1011,  0x01390184},
+{3900000, DIF_BPF_COEFF1213,  0x016300ac},
+{3900000, DIF_BPF_COEFF1415,  0xff5efdb1},
+{3900000, DIF_BPF_COEFF1617,  0xfc17fb23},
+{3900000, DIF_BPF_COEFF1819,  0xfb5cfd0d},
+{3900000, DIF_BPF_COEFF2021,  0x001703e4},
+{3900000, DIF_BPF_COEFF2223,  0x077b09c4},
+{3900000, DIF_BPF_COEFF2425,  0x09d2073c},
+{3900000, DIF_BPF_COEFF2627,  0x0251fc18},
+{3900000, DIF_BPF_COEFF2829,  0xf61cf203},
+{3900000, DIF_BPF_COEFF3031,  0xf118f3dc},
+{3900000, DIF_BPF_COEFF3233,  0xf9d801aa},
+{3900000, DIF_BPF_COEFF3435,  0x09600eff},
+{3900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 39_quant.dat*/
+
+
+/*case 4000000:*/
+/* BEGIN - DIF BPF register values from 40_quant.dat*/
+{4000000, DIF_BPF_COEFF01,    0x00000001},
+{4000000, DIF_BPF_COEFF23,    0xfffefff4},
+{4000000, DIF_BPF_COEFF45,    0xffe1ffc8},
+{4000000, DIF_BPF_COEFF67,    0xffbaffca},
+{4000000, DIF_BPF_COEFF89,    0x000b0082},
+{4000000, DIF_BPF_COEFF1011,  0x01170198},
+{4000000, DIF_BPF_COEFF1213,  0x01c10152},
+{4000000, DIF_BPF_COEFF1415,  0x0030fe7b},
+{4000000, DIF_BPF_COEFF1617,  0xfc99fb24},
+{4000000, DIF_BPF_COEFF1819,  0xfac3fbe9},
+{4000000, DIF_BPF_COEFF2021,  0xfea5027f},
+{4000000, DIF_BPF_COEFF2223,  0x0683097f},
+{4000000, DIF_BPF_COEFF2425,  0x0a560867},
+{4000000, DIF_BPF_COEFF2627,  0x03d2fd89},
+{4000000, DIF_BPF_COEFF2829,  0xf723f26f},
+{4000000, DIF_BPF_COEFF3031,  0xf0e8f341},
+{4000000, DIF_BPF_COEFF3233,  0xf919010a},
+{4000000, DIF_BPF_COEFF3435,  0x09060ee5},
+{4000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 40_quant.dat*/
+
+
+/*case 4100000:*/
+/* BEGIN - DIF BPF register values from 41_quant.dat*/
+{4100000, DIF_BPF_COEFF01,    0x00010002},
+{4100000, DIF_BPF_COEFF23,    0x0002fffb},
+{4100000, DIF_BPF_COEFF45,    0xffe8ffca},
+{4100000, DIF_BPF_COEFF67,    0xffacffa4},
+{4100000, DIF_BPF_COEFF89,    0xffcd0036},
+{4100000, DIF_BPF_COEFF1011,  0x00d70184},
+{4100000, DIF_BPF_COEFF1213,  0x01f601dc},
+{4100000, DIF_BPF_COEFF1415,  0x00ffff60},
+{4100000, DIF_BPF_COEFF1617,  0xfd51fb6d},
+{4100000, DIF_BPF_COEFF1819,  0xfa6efaf5},
+{4100000, DIF_BPF_COEFF2021,  0xfd410103},
+{4100000, DIF_BPF_COEFF2223,  0x055708f9},
+{4100000, DIF_BPF_COEFF2425,  0x0a9e0969},
+{4100000, DIF_BPF_COEFF2627,  0x0543ff02},
+{4100000, DIF_BPF_COEFF2829,  0xf842f2f5},
+{4100000, DIF_BPF_COEFF3031,  0xf0cef2b2},
+{4100000, DIF_BPF_COEFF3233,  0xf85e006b},
+{4100000, DIF_BPF_COEFF3435,  0x08aa0ecb},
+{4100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 41_quant.dat*/
+
+
+/*case 4200000:*/
+/* BEGIN - DIF BPF register values from 42_quant.dat*/
+{4200000, DIF_BPF_COEFF01,    0x00010003},
+{4200000, DIF_BPF_COEFF23,    0x00050003},
+{4200000, DIF_BPF_COEFF45,    0xfff3ffd3},
+{4200000, DIF_BPF_COEFF67,    0xffaaff8b},
+{4200000, DIF_BPF_COEFF89,    0xff95ffe5},
+{4200000, DIF_BPF_COEFF1011,  0x0080014a},
+{4200000, DIF_BPF_COEFF1213,  0x01fe023f},
+{4200000, DIF_BPF_COEFF1415,  0x01ba0050},
+{4200000, DIF_BPF_COEFF1617,  0xfe35fbf8},
+{4200000, DIF_BPF_COEFF1819,  0xfa62fa3b},
+{4200000, DIF_BPF_COEFF2021,  0xfbf9ff7e},
+{4200000, DIF_BPF_COEFF2223,  0x04010836},
+{4200000, DIF_BPF_COEFF2425,  0x0aa90a3d},
+{4200000, DIF_BPF_COEFF2627,  0x069f007f},
+{4200000, DIF_BPF_COEFF2829,  0xf975f395},
+{4200000, DIF_BPF_COEFF3031,  0xf0cbf231},
+{4200000, DIF_BPF_COEFF3233,  0xf7a9ffcb},
+{4200000, DIF_BPF_COEFF3435,  0x084c0eaf},
+{4200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 42_quant.dat*/
+
+
+/*case 4300000:*/
+/* BEGIN - DIF BPF register values from 43_quant.dat*/
+{4300000, DIF_BPF_COEFF01,    0x00010003},
+{4300000, DIF_BPF_COEFF23,    0x0008000a},
+{4300000, DIF_BPF_COEFF45,    0x0000ffe4},
+{4300000, DIF_BPF_COEFF67,    0xffb4ff81},
+{4300000, DIF_BPF_COEFF89,    0xff6aff96},
+{4300000, DIF_BPF_COEFF1011,  0x001c00f0},
+{4300000, DIF_BPF_COEFF1213,  0x01d70271},
+{4300000, DIF_BPF_COEFF1415,  0x0254013b},
+{4300000, DIF_BPF_COEFF1617,  0xff36fcbd},
+{4300000, DIF_BPF_COEFF1819,  0xfa9ff9c5},
+{4300000, DIF_BPF_COEFF2021,  0xfadbfdfe},
+{4300000, DIF_BPF_COEFF2223,  0x028c073b},
+{4300000, DIF_BPF_COEFF2425,  0x0a750adf},
+{4300000, DIF_BPF_COEFF2627,  0x07e101fa},
+{4300000, DIF_BPF_COEFF2829,  0xfab8f44e},
+{4300000, DIF_BPF_COEFF3031,  0xf0ddf1be},
+{4300000, DIF_BPF_COEFF3233,  0xf6f9ff2b},
+{4300000, DIF_BPF_COEFF3435,  0x07ed0e94},
+{4300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 43_quant.dat*/
+
+
+/*case 4400000:*/
+/* BEGIN - DIF BPF register values from 44_quant.dat*/
+{4400000, DIF_BPF_COEFF01,    0x00000003},
+{4400000, DIF_BPF_COEFF23,    0x0009000f},
+{4400000, DIF_BPF_COEFF45,    0x000efff8},
+{4400000, DIF_BPF_COEFF67,    0xffc9ff87},
+{4400000, DIF_BPF_COEFF89,    0xff52ff54},
+{4400000, DIF_BPF_COEFF1011,  0xffb5007e},
+{4400000, DIF_BPF_COEFF1213,  0x01860270},
+{4400000, DIF_BPF_COEFF1415,  0x02c00210},
+{4400000, DIF_BPF_COEFF1617,  0x0044fdb2},
+{4400000, DIF_BPF_COEFF1819,  0xfb22f997},
+{4400000, DIF_BPF_COEFF2021,  0xf9f2fc90},
+{4400000, DIF_BPF_COEFF2223,  0x0102060f},
+{4400000, DIF_BPF_COEFF2425,  0x0a050b4c},
+{4400000, DIF_BPF_COEFF2627,  0x0902036e},
+{4400000, DIF_BPF_COEFF2829,  0xfc0af51e},
+{4400000, DIF_BPF_COEFF3031,  0xf106f15a},
+{4400000, DIF_BPF_COEFF3233,  0xf64efe8b},
+{4400000, DIF_BPF_COEFF3435,  0x078d0e77},
+{4400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 44_quant.dat*/
+
+
+/*case 4500000:*/
+/* BEGIN - DIF BPF register values from 45_quant.dat*/
+{4500000, DIF_BPF_COEFF01,    0x00000002},
+{4500000, DIF_BPF_COEFF23,    0x00080012},
+{4500000, DIF_BPF_COEFF45,    0x0019000e},
+{4500000, DIF_BPF_COEFF67,    0xffe5ff9e},
+{4500000, DIF_BPF_COEFF89,    0xff4fff25},
+{4500000, DIF_BPF_COEFF1011,  0xff560000},
+{4500000, DIF_BPF_COEFF1213,  0x0112023b},
+{4500000, DIF_BPF_COEFF1415,  0x02f702c0},
+{4500000, DIF_BPF_COEFF1617,  0x014dfec8},
+{4500000, DIF_BPF_COEFF1819,  0xfbe5f9b3},
+{4500000, DIF_BPF_COEFF2021,  0xf947fb41},
+{4500000, DIF_BPF_COEFF2223,  0xff7004b9},
+{4500000, DIF_BPF_COEFF2425,  0x095a0b81},
+{4500000, DIF_BPF_COEFF2627,  0x0a0004d8},
+{4500000, DIF_BPF_COEFF2829,  0xfd65f603},
+{4500000, DIF_BPF_COEFF3031,  0xf144f104},
+{4500000, DIF_BPF_COEFF3233,  0xf5aafdec},
+{4500000, DIF_BPF_COEFF3435,  0x072b0e5a},
+{4500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 45_quant.dat*/
+
+
+/*case 4600000:*/
+/* BEGIN - DIF BPF register values from 46_quant.dat*/
+{4600000, DIF_BPF_COEFF01,    0x00000001},
+{4600000, DIF_BPF_COEFF23,    0x00060012},
+{4600000, DIF_BPF_COEFF45,    0x00200022},
+{4600000, DIF_BPF_COEFF67,    0x0005ffc1},
+{4600000, DIF_BPF_COEFF89,    0xff61ff10},
+{4600000, DIF_BPF_COEFF1011,  0xff09ff82},
+{4600000, DIF_BPF_COEFF1213,  0x008601d7},
+{4600000, DIF_BPF_COEFF1415,  0x02f50340},
+{4600000, DIF_BPF_COEFF1617,  0x0241fff0},
+{4600000, DIF_BPF_COEFF1819,  0xfcddfa19},
+{4600000, DIF_BPF_COEFF2021,  0xf8e2fa1e},
+{4600000, DIF_BPF_COEFF2223,  0xfde30343},
+{4600000, DIF_BPF_COEFF2425,  0x08790b7f},
+{4600000, DIF_BPF_COEFF2627,  0x0ad50631},
+{4600000, DIF_BPF_COEFF2829,  0xfec7f6fc},
+{4600000, DIF_BPF_COEFF3031,  0xf198f0bd},
+{4600000, DIF_BPF_COEFF3233,  0xf50dfd4e},
+{4600000, DIF_BPF_COEFF3435,  0x06c90e3d},
+{4600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 46_quant.dat*/
+
+
+/*case 4700000:*/
+/* BEGIN - DIF BPF register values from 47_quant.dat*/
+{4700000, DIF_BPF_COEFF01,    0x0000ffff},
+{4700000, DIF_BPF_COEFF23,    0x0003000f},
+{4700000, DIF_BPF_COEFF45,    0x00220030},
+{4700000, DIF_BPF_COEFF67,    0x0025ffed},
+{4700000, DIF_BPF_COEFF89,    0xff87ff15},
+{4700000, DIF_BPF_COEFF1011,  0xfed6ff10},
+{4700000, DIF_BPF_COEFF1213,  0xffed014c},
+{4700000, DIF_BPF_COEFF1415,  0x02b90386},
+{4700000, DIF_BPF_COEFF1617,  0x03110119},
+{4700000, DIF_BPF_COEFF1819,  0xfdfefac4},
+{4700000, DIF_BPF_COEFF2021,  0xf8c6f92f},
+{4700000, DIF_BPF_COEFF2223,  0xfc6701b7},
+{4700000, DIF_BPF_COEFF2425,  0x07670b44},
+{4700000, DIF_BPF_COEFF2627,  0x0b7e0776},
+{4700000, DIF_BPF_COEFF2829,  0x002df807},
+{4700000, DIF_BPF_COEFF3031,  0xf200f086},
+{4700000, DIF_BPF_COEFF3233,  0xf477fcb1},
+{4700000, DIF_BPF_COEFF3435,  0x06650e1e},
+{4700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 47_quant.dat*/
+
+
+/*case 4800000:*/
+/* BEGIN - DIF BPF register values from 48_quant.dat*/
+{4800000, DIF_BPF_COEFF01,    0xfffffffe},
+{4800000, DIF_BPF_COEFF23,    0xffff0009},
+{4800000, DIF_BPF_COEFF45,    0x001e0038},
+{4800000, DIF_BPF_COEFF67,    0x003f001b},
+{4800000, DIF_BPF_COEFF89,    0xffbcff36},
+{4800000, DIF_BPF_COEFF1011,  0xfec2feb6},
+{4800000, DIF_BPF_COEFF1213,  0xff5600a5},
+{4800000, DIF_BPF_COEFF1415,  0x0248038d},
+{4800000, DIF_BPF_COEFF1617,  0x03b00232},
+{4800000, DIF_BPF_COEFF1819,  0xff39fbab},
+{4800000, DIF_BPF_COEFF2021,  0xf8f4f87f},
+{4800000, DIF_BPF_COEFF2223,  0xfb060020},
+{4800000, DIF_BPF_COEFF2425,  0x062a0ad2},
+{4800000, DIF_BPF_COEFF2627,  0x0bf908a3},
+{4800000, DIF_BPF_COEFF2829,  0x0192f922},
+{4800000, DIF_BPF_COEFF3031,  0xf27df05e},
+{4800000, DIF_BPF_COEFF3233,  0xf3e8fc14},
+{4800000, DIF_BPF_COEFF3435,  0x06000e00},
+{4800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 48_quant.dat*/
+
+
+/*case 4900000:*/
+/* BEGIN - DIF BPF register values from 49_quant.dat*/
+{4900000, DIF_BPF_COEFF01,    0xfffffffd},
+{4900000, DIF_BPF_COEFF23,    0xfffc0002},
+{4900000, DIF_BPF_COEFF45,    0x00160037},
+{4900000, DIF_BPF_COEFF67,    0x00510046},
+{4900000, DIF_BPF_COEFF89,    0xfff9ff6d},
+{4900000, DIF_BPF_COEFF1011,  0xfed0fe7c},
+{4900000, DIF_BPF_COEFF1213,  0xfecefff0},
+{4900000, DIF_BPF_COEFF1415,  0x01aa0356},
+{4900000, DIF_BPF_COEFF1617,  0x0413032b},
+{4900000, DIF_BPF_COEFF1819,  0x007ffcc5},
+{4900000, DIF_BPF_COEFF2021,  0xf96cf812},
+{4900000, DIF_BPF_COEFF2223,  0xf9cefe87},
+{4900000, DIF_BPF_COEFF2425,  0x04c90a2c},
+{4900000, DIF_BPF_COEFF2627,  0x0c4309b4},
+{4900000, DIF_BPF_COEFF2829,  0x02f3fa4a},
+{4900000, DIF_BPF_COEFF3031,  0xf30ef046},
+{4900000, DIF_BPF_COEFF3233,  0xf361fb7a},
+{4900000, DIF_BPF_COEFF3435,  0x059b0de0},
+{4900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 49_quant.dat*/
+
+
+/*case 5000000:*/
+/* BEGIN - DIF BPF register values from 50_quant.dat*/
+{5000000, DIF_BPF_COEFF01,    0xfffffffd},
+{5000000, DIF_BPF_COEFF23,    0xfff9fffa},
+{5000000, DIF_BPF_COEFF45,    0x000a002d},
+{5000000, DIF_BPF_COEFF67,    0x00570067},
+{5000000, DIF_BPF_COEFF89,    0x0037ffb5},
+{5000000, DIF_BPF_COEFF1011,  0xfefffe68},
+{5000000, DIF_BPF_COEFF1213,  0xfe62ff3d},
+{5000000, DIF_BPF_COEFF1415,  0x00ec02e3},
+{5000000, DIF_BPF_COEFF1617,  0x043503f6},
+{5000000, DIF_BPF_COEFF1819,  0x01befe05},
+{5000000, DIF_BPF_COEFF2021,  0xfa27f7ee},
+{5000000, DIF_BPF_COEFF2223,  0xf8c6fcf8},
+{5000000, DIF_BPF_COEFF2425,  0x034c0954},
+{5000000, DIF_BPF_COEFF2627,  0x0c5c0aa4},
+{5000000, DIF_BPF_COEFF2829,  0x044cfb7e},
+{5000000, DIF_BPF_COEFF3031,  0xf3b1f03f},
+{5000000, DIF_BPF_COEFF3233,  0xf2e2fae1},
+{5000000, DIF_BPF_COEFF3435,  0x05340dc0},
+{5000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 50_quant.dat*/
+
+
+/*case 5100000:*/
+/* BEGIN - DIF BPF register values from 51_quant.dat*/
+{5100000, DIF_BPF_COEFF01,    0x0000fffd},
+{5100000, DIF_BPF_COEFF23,    0xfff8fff4},
+{5100000, DIF_BPF_COEFF45,    0xfffd001e},
+{5100000, DIF_BPF_COEFF67,    0x0051007b},
+{5100000, DIF_BPF_COEFF89,    0x006e0006},
+{5100000, DIF_BPF_COEFF1011,  0xff48fe7c},
+{5100000, DIF_BPF_COEFF1213,  0xfe1bfe9a},
+{5100000, DIF_BPF_COEFF1415,  0x001d023e},
+{5100000, DIF_BPF_COEFF1617,  0x04130488},
+{5100000, DIF_BPF_COEFF1819,  0x02e6ff5b},
+{5100000, DIF_BPF_COEFF2021,  0xfb1ef812},
+{5100000, DIF_BPF_COEFF2223,  0xf7f7fb7f},
+{5100000, DIF_BPF_COEFF2425,  0x01bc084e},
+{5100000, DIF_BPF_COEFF2627,  0x0c430b72},
+{5100000, DIF_BPF_COEFF2829,  0x059afcba},
+{5100000, DIF_BPF_COEFF3031,  0xf467f046},
+{5100000, DIF_BPF_COEFF3233,  0xf26cfa4a},
+{5100000, DIF_BPF_COEFF3435,  0x04cd0da0},
+{5100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 51_quant.dat*/
+
+
+/*case 5200000:*/
+/* BEGIN - DIF BPF register values from 52_quant.dat*/
+{5200000, DIF_BPF_COEFF01,    0x0000fffe},
+{5200000, DIF_BPF_COEFF23,    0xfff8ffef},
+{5200000, DIF_BPF_COEFF45,    0xfff00009},
+{5200000, DIF_BPF_COEFF67,    0x003f007f},
+{5200000, DIF_BPF_COEFF89,    0x00980056},
+{5200000, DIF_BPF_COEFF1011,  0xffa5feb6},
+{5200000, DIF_BPF_COEFF1213,  0xfe00fe15},
+{5200000, DIF_BPF_COEFF1415,  0xff4b0170},
+{5200000, DIF_BPF_COEFF1617,  0x03b004d7},
+{5200000, DIF_BPF_COEFF1819,  0x03e800b9},
+{5200000, DIF_BPF_COEFF2021,  0xfc48f87f},
+{5200000, DIF_BPF_COEFF2223,  0xf768fa23},
+{5200000, DIF_BPF_COEFF2425,  0x0022071f},
+{5200000, DIF_BPF_COEFF2627,  0x0bf90c1b},
+{5200000, DIF_BPF_COEFF2829,  0x06dafdfd},
+{5200000, DIF_BPF_COEFF3031,  0xf52df05e},
+{5200000, DIF_BPF_COEFF3233,  0xf1fef9b5},
+{5200000, DIF_BPF_COEFF3435,  0x04640d7f},
+{5200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 52_quant.dat*/
+
+
+/*case 5300000:*/
+/* BEGIN - DIF BPF register values from 53_quant.dat*/
+{5300000, DIF_BPF_COEFF01,    0x0000ffff},
+{5300000, DIF_BPF_COEFF23,    0xfff9ffee},
+{5300000, DIF_BPF_COEFF45,    0xffe6fff3},
+{5300000, DIF_BPF_COEFF67,    0x00250072},
+{5300000, DIF_BPF_COEFF89,    0x00af009c},
+{5300000, DIF_BPF_COEFF1011,  0x000cff10},
+{5300000, DIF_BPF_COEFF1213,  0xfe13fdb8},
+{5300000, DIF_BPF_COEFF1415,  0xfe870089},
+{5300000, DIF_BPF_COEFF1617,  0x031104e1},
+{5300000, DIF_BPF_COEFF1819,  0x04b8020f},
+{5300000, DIF_BPF_COEFF2021,  0xfd98f92f},
+{5300000, DIF_BPF_COEFF2223,  0xf71df8f0},
+{5300000, DIF_BPF_COEFF2425,  0xfe8805ce},
+{5300000, DIF_BPF_COEFF2627,  0x0b7e0c9c},
+{5300000, DIF_BPF_COEFF2829,  0x0808ff44},
+{5300000, DIF_BPF_COEFF3031,  0xf603f086},
+{5300000, DIF_BPF_COEFF3233,  0xf19af922},
+{5300000, DIF_BPF_COEFF3435,  0x03fb0d5e},
+{5300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 53_quant.dat*/
+
+
+/*case 5400000:*/
+/* BEGIN - DIF BPF register values from 54_quant.dat*/
+{5400000, DIF_BPF_COEFF01,    0x00000001},
+{5400000, DIF_BPF_COEFF23,    0xfffcffef},
+{5400000, DIF_BPF_COEFF45,    0xffe0ffe0},
+{5400000, DIF_BPF_COEFF67,    0x00050056},
+{5400000, DIF_BPF_COEFF89,    0x00b000d1},
+{5400000, DIF_BPF_COEFF1011,  0x0071ff82},
+{5400000, DIF_BPF_COEFF1213,  0xfe53fd8c},
+{5400000, DIF_BPF_COEFF1415,  0xfddfff99},
+{5400000, DIF_BPF_COEFF1617,  0x024104a3},
+{5400000, DIF_BPF_COEFF1819,  0x054a034d},
+{5400000, DIF_BPF_COEFF2021,  0xff01fa1e},
+{5400000, DIF_BPF_COEFF2223,  0xf717f7ed},
+{5400000, DIF_BPF_COEFF2425,  0xfcf50461},
+{5400000, DIF_BPF_COEFF2627,  0x0ad50cf4},
+{5400000, DIF_BPF_COEFF2829,  0x0921008d},
+{5400000, DIF_BPF_COEFF3031,  0xf6e7f0bd},
+{5400000, DIF_BPF_COEFF3233,  0xf13ff891},
+{5400000, DIF_BPF_COEFF3435,  0x03920d3b},
+{5400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 54_quant.dat*/
+
+
+/*case 5500000:*/
+/* BEGIN - DIF BPF register values from 55_quant.dat*/
+{5500000, DIF_BPF_COEFF01,    0x00010002},
+{5500000, DIF_BPF_COEFF23,    0xfffffff3},
+{5500000, DIF_BPF_COEFF45,    0xffdeffd1},
+{5500000, DIF_BPF_COEFF67,    0xffe5002f},
+{5500000, DIF_BPF_COEFF89,    0x009c00ed},
+{5500000, DIF_BPF_COEFF1011,  0x00cb0000},
+{5500000, DIF_BPF_COEFF1213,  0xfebafd94},
+{5500000, DIF_BPF_COEFF1415,  0xfd61feb0},
+{5500000, DIF_BPF_COEFF1617,  0x014d0422},
+{5500000, DIF_BPF_COEFF1819,  0x05970464},
+{5500000, DIF_BPF_COEFF2021,  0x0074fb41},
+{5500000, DIF_BPF_COEFF2223,  0xf759f721},
+{5500000, DIF_BPF_COEFF2425,  0xfb7502de},
+{5500000, DIF_BPF_COEFF2627,  0x0a000d21},
+{5500000, DIF_BPF_COEFF2829,  0x0a2201d4},
+{5500000, DIF_BPF_COEFF3031,  0xf7d9f104},
+{5500000, DIF_BPF_COEFF3233,  0xf0edf804},
+{5500000, DIF_BPF_COEFF3435,  0x03280d19},
+{5500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 55_quant.dat*/
+
+
+/*case 5600000:*/
+/* BEGIN - DIF BPF register values from 56_quant.dat*/
+{5600000, DIF_BPF_COEFF01,    0x00010003},
+{5600000, DIF_BPF_COEFF23,    0x0003fffa},
+{5600000, DIF_BPF_COEFF45,    0xffe3ffc9},
+{5600000, DIF_BPF_COEFF67,    0xffc90002},
+{5600000, DIF_BPF_COEFF89,    0x007500ef},
+{5600000, DIF_BPF_COEFF1011,  0x010e007e},
+{5600000, DIF_BPF_COEFF1213,  0xff3dfdcf},
+{5600000, DIF_BPF_COEFF1415,  0xfd16fddd},
+{5600000, DIF_BPF_COEFF1617,  0x00440365},
+{5600000, DIF_BPF_COEFF1819,  0x059b0548},
+{5600000, DIF_BPF_COEFF2021,  0x01e3fc90},
+{5600000, DIF_BPF_COEFF2223,  0xf7dff691},
+{5600000, DIF_BPF_COEFF2425,  0xfa0f014d},
+{5600000, DIF_BPF_COEFF2627,  0x09020d23},
+{5600000, DIF_BPF_COEFF2829,  0x0b0a0318},
+{5600000, DIF_BPF_COEFF3031,  0xf8d7f15a},
+{5600000, DIF_BPF_COEFF3233,  0xf0a5f779},
+{5600000, DIF_BPF_COEFF3435,  0x02bd0cf6},
+{5600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 56_quant.dat*/
+
+
+/*case 5700000:*/
+/* BEGIN - DIF BPF register values from 57_quant.dat*/
+{5700000, DIF_BPF_COEFF01,    0x00010003},
+{5700000, DIF_BPF_COEFF23,    0x00060001},
+{5700000, DIF_BPF_COEFF45,    0xffecffc9},
+{5700000, DIF_BPF_COEFF67,    0xffb4ffd4},
+{5700000, DIF_BPF_COEFF89,    0x004000d5},
+{5700000, DIF_BPF_COEFF1011,  0x013600f0},
+{5700000, DIF_BPF_COEFF1213,  0xffd3fe39},
+{5700000, DIF_BPF_COEFF1415,  0xfd04fd31},
+{5700000, DIF_BPF_COEFF1617,  0xff360277},
+{5700000, DIF_BPF_COEFF1819,  0x055605ef},
+{5700000, DIF_BPF_COEFF2021,  0x033efdfe},
+{5700000, DIF_BPF_COEFF2223,  0xf8a5f642},
+{5700000, DIF_BPF_COEFF2425,  0xf8cbffb6},
+{5700000, DIF_BPF_COEFF2627,  0x07e10cfb},
+{5700000, DIF_BPF_COEFF2829,  0x0bd50456},
+{5700000, DIF_BPF_COEFF3031,  0xf9dff1be},
+{5700000, DIF_BPF_COEFF3233,  0xf067f6f2},
+{5700000, DIF_BPF_COEFF3435,  0x02520cd2},
+{5700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 57_quant.dat*/
+
+
+/*case 5800000:*/
+/* BEGIN - DIF BPF register values from 58_quant.dat*/
+{5800000, DIF_BPF_COEFF01,    0x00000003},
+{5800000, DIF_BPF_COEFF23,    0x00080009},
+{5800000, DIF_BPF_COEFF45,    0xfff8ffd2},
+{5800000, DIF_BPF_COEFF67,    0xffaaffac},
+{5800000, DIF_BPF_COEFF89,    0x000200a3},
+{5800000, DIF_BPF_COEFF1011,  0x013c014a},
+{5800000, DIF_BPF_COEFF1213,  0x006dfec9},
+{5800000, DIF_BPF_COEFF1415,  0xfd2bfcb7},
+{5800000, DIF_BPF_COEFF1617,  0xfe350165},
+{5800000, DIF_BPF_COEFF1819,  0x04cb0651},
+{5800000, DIF_BPF_COEFF2021,  0x0477ff7e},
+{5800000, DIF_BPF_COEFF2223,  0xf9a5f635},
+{5800000, DIF_BPF_COEFF2425,  0xf7b1fe20},
+{5800000, DIF_BPF_COEFF2627,  0x069f0ca8},
+{5800000, DIF_BPF_COEFF2829,  0x0c81058b},
+{5800000, DIF_BPF_COEFF3031,  0xfaf0f231},
+{5800000, DIF_BPF_COEFF3233,  0xf033f66d},
+{5800000, DIF_BPF_COEFF3435,  0x01e60cae},
+{5800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 58_quant.dat*/
+
+
+/*case 5900000:*/
+/* BEGIN - DIF BPF register values from 59_quant.dat*/
+{5900000, DIF_BPF_COEFF01,    0x00000002},
+{5900000, DIF_BPF_COEFF23,    0x0009000e},
+{5900000, DIF_BPF_COEFF45,    0x0005ffe1},
+{5900000, DIF_BPF_COEFF67,    0xffacff90},
+{5900000, DIF_BPF_COEFF89,    0xffc5005f},
+{5900000, DIF_BPF_COEFF1011,  0x01210184},
+{5900000, DIF_BPF_COEFF1213,  0x00fcff72},
+{5900000, DIF_BPF_COEFF1415,  0xfd8afc77},
+{5900000, DIF_BPF_COEFF1617,  0xfd51003f},
+{5900000, DIF_BPF_COEFF1819,  0x04020669},
+{5900000, DIF_BPF_COEFF2021,  0x05830103},
+{5900000, DIF_BPF_COEFF2223,  0xfad7f66b},
+{5900000, DIF_BPF_COEFF2425,  0xf6c8fc93},
+{5900000, DIF_BPF_COEFF2627,  0x05430c2b},
+{5900000, DIF_BPF_COEFF2829,  0x0d0d06b5},
+{5900000, DIF_BPF_COEFF3031,  0xfc08f2b2},
+{5900000, DIF_BPF_COEFF3233,  0xf00af5ec},
+{5900000, DIF_BPF_COEFF3435,  0x017b0c89},
+{5900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 59_quant.dat*/
+
+
+/*case 6000000:*/
+/* BEGIN - DIF BPF register values from 60_quant.dat*/
+{6000000, DIF_BPF_COEFF01,    0x00000001},
+{6000000, DIF_BPF_COEFF23,    0x00070012},
+{6000000, DIF_BPF_COEFF45,    0x0012fff5},
+{6000000, DIF_BPF_COEFF67,    0xffbaff82},
+{6000000, DIF_BPF_COEFF89,    0xff8e000f},
+{6000000, DIF_BPF_COEFF1011,  0x00e80198},
+{6000000, DIF_BPF_COEFF1213,  0x01750028},
+{6000000, DIF_BPF_COEFF1415,  0xfe18fc75},
+{6000000, DIF_BPF_COEFF1617,  0xfc99ff15},
+{6000000, DIF_BPF_COEFF1819,  0x03050636},
+{6000000, DIF_BPF_COEFF2021,  0x0656027f},
+{6000000, DIF_BPF_COEFF2223,  0xfc32f6e2},
+{6000000, DIF_BPF_COEFF2425,  0xf614fb17},
+{6000000, DIF_BPF_COEFF2627,  0x03d20b87},
+{6000000, DIF_BPF_COEFF2829,  0x0d7707d2},
+{6000000, DIF_BPF_COEFF3031,  0xfd26f341},
+{6000000, DIF_BPF_COEFF3233,  0xefeaf56f},
+{6000000, DIF_BPF_COEFF3435,  0x010f0c64},
+{6000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 60_quant.dat*/
+
+
+/*case 6100000:*/
+/* BEGIN - DIF BPF register values from 61_quant.dat*/
+{6100000, DIF_BPF_COEFF01,    0xffff0000},
+{6100000, DIF_BPF_COEFF23,    0x00050012},
+{6100000, DIF_BPF_COEFF45,    0x001c000b},
+{6100000, DIF_BPF_COEFF67,    0xffd1ff84},
+{6100000, DIF_BPF_COEFF89,    0xff66ffbe},
+{6100000, DIF_BPF_COEFF1011,  0x00960184},
+{6100000, DIF_BPF_COEFF1213,  0x01cd00da},
+{6100000, DIF_BPF_COEFF1415,  0xfeccfcb2},
+{6100000, DIF_BPF_COEFF1617,  0xfc17fdf9},
+{6100000, DIF_BPF_COEFF1819,  0x01e005bc},
+{6100000, DIF_BPF_COEFF2021,  0x06e703e4},
+{6100000, DIF_BPF_COEFF2223,  0xfdabf798},
+{6100000, DIF_BPF_COEFF2425,  0xf599f9b3},
+{6100000, DIF_BPF_COEFF2627,  0x02510abd},
+{6100000, DIF_BPF_COEFF2829,  0x0dbf08df},
+{6100000, DIF_BPF_COEFF3031,  0xfe48f3dc},
+{6100000, DIF_BPF_COEFF3233,  0xefd5f4f6},
+{6100000, DIF_BPF_COEFF3435,  0x00a20c3e},
+{6100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 61_quant.dat*/
+
+
+/*case 6200000:*/
+/* BEGIN - DIF BPF register values from 62_quant.dat*/
+{6200000, DIF_BPF_COEFF01,    0xfffffffe},
+{6200000, DIF_BPF_COEFF23,    0x0002000f},
+{6200000, DIF_BPF_COEFF45,    0x0021001f},
+{6200000, DIF_BPF_COEFF67,    0xfff0ff97},
+{6200000, DIF_BPF_COEFF89,    0xff50ff74},
+{6200000, DIF_BPF_COEFF1011,  0x0034014a},
+{6200000, DIF_BPF_COEFF1213,  0x01fa0179},
+{6200000, DIF_BPF_COEFF1415,  0xff97fd2a},
+{6200000, DIF_BPF_COEFF1617,  0xfbd3fcfa},
+{6200000, DIF_BPF_COEFF1819,  0x00a304fe},
+{6200000, DIF_BPF_COEFF2021,  0x07310525},
+{6200000, DIF_BPF_COEFF2223,  0xff37f886},
+{6200000, DIF_BPF_COEFF2425,  0xf55cf86e},
+{6200000, DIF_BPF_COEFF2627,  0x00c709d0},
+{6200000, DIF_BPF_COEFF2829,  0x0de209db},
+{6200000, DIF_BPF_COEFF3031,  0xff6df484},
+{6200000, DIF_BPF_COEFF3233,  0xefcbf481},
+{6200000, DIF_BPF_COEFF3435,  0x00360c18},
+{6200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 62_quant.dat*/
+
+
+/*case 6300000:*/
+/* BEGIN - DIF BPF register values from 63_quant.dat*/
+{6300000, DIF_BPF_COEFF01,    0xfffffffd},
+{6300000, DIF_BPF_COEFF23,    0xfffe000a},
+{6300000, DIF_BPF_COEFF45,    0x0021002f},
+{6300000, DIF_BPF_COEFF67,    0x0010ffb8},
+{6300000, DIF_BPF_COEFF89,    0xff50ff3b},
+{6300000, DIF_BPF_COEFF1011,  0xffcc00f0},
+{6300000, DIF_BPF_COEFF1213,  0x01fa01fa},
+{6300000, DIF_BPF_COEFF1415,  0x0069fdd4},
+{6300000, DIF_BPF_COEFF1617,  0xfbd3fc26},
+{6300000, DIF_BPF_COEFF1819,  0xff5d0407},
+{6300000, DIF_BPF_COEFF2021,  0x07310638},
+{6300000, DIF_BPF_COEFF2223,  0x00c9f9a8},
+{6300000, DIF_BPF_COEFF2425,  0xf55cf74e},
+{6300000, DIF_BPF_COEFF2627,  0xff3908c3},
+{6300000, DIF_BPF_COEFF2829,  0x0de20ac3},
+{6300000, DIF_BPF_COEFF3031,  0x0093f537},
+{6300000, DIF_BPF_COEFF3233,  0xefcbf410},
+{6300000, DIF_BPF_COEFF3435,  0xffca0bf2},
+{6300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 63_quant.dat*/
+
+
+/*case 6400000:*/
+/* BEGIN - DIF BPF register values from 64_quant.dat*/
+{6400000, DIF_BPF_COEFF01,    0xfffffffd},
+{6400000, DIF_BPF_COEFF23,    0xfffb0003},
+{6400000, DIF_BPF_COEFF45,    0x001c0037},
+{6400000, DIF_BPF_COEFF67,    0x002fffe2},
+{6400000, DIF_BPF_COEFF89,    0xff66ff17},
+{6400000, DIF_BPF_COEFF1011,  0xff6a007e},
+{6400000, DIF_BPF_COEFF1213,  0x01cd0251},
+{6400000, DIF_BPF_COEFF1415,  0x0134fea5},
+{6400000, DIF_BPF_COEFF1617,  0xfc17fb8b},
+{6400000, DIF_BPF_COEFF1819,  0xfe2002e0},
+{6400000, DIF_BPF_COEFF2021,  0x06e70713},
+{6400000, DIF_BPF_COEFF2223,  0x0255faf5},
+{6400000, DIF_BPF_COEFF2425,  0xf599f658},
+{6400000, DIF_BPF_COEFF2627,  0xfdaf0799},
+{6400000, DIF_BPF_COEFF2829,  0x0dbf0b96},
+{6400000, DIF_BPF_COEFF3031,  0x01b8f5f5},
+{6400000, DIF_BPF_COEFF3233,  0xefd5f3a3},
+{6400000, DIF_BPF_COEFF3435,  0xff5e0bca},
+{6400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 64_quant.dat*/
+
+
+/*case 6500000:*/
+/* BEGIN - DIF BPF register values from 65_quant.dat*/
+{6500000, DIF_BPF_COEFF01,    0x0000fffd},
+{6500000, DIF_BPF_COEFF23,    0xfff9fffb},
+{6500000, DIF_BPF_COEFF45,    0x00120037},
+{6500000, DIF_BPF_COEFF67,    0x00460010},
+{6500000, DIF_BPF_COEFF89,    0xff8eff0f},
+{6500000, DIF_BPF_COEFF1011,  0xff180000},
+{6500000, DIF_BPF_COEFF1213,  0x01750276},
+{6500000, DIF_BPF_COEFF1415,  0x01e8ff8d},
+{6500000, DIF_BPF_COEFF1617,  0xfc99fb31},
+{6500000, DIF_BPF_COEFF1819,  0xfcfb0198},
+{6500000, DIF_BPF_COEFF2021,  0x065607ad},
+{6500000, DIF_BPF_COEFF2223,  0x03cefc64},
+{6500000, DIF_BPF_COEFF2425,  0xf614f592},
+{6500000, DIF_BPF_COEFF2627,  0xfc2e0656},
+{6500000, DIF_BPF_COEFF2829,  0x0d770c52},
+{6500000, DIF_BPF_COEFF3031,  0x02daf6bd},
+{6500000, DIF_BPF_COEFF3233,  0xefeaf33b},
+{6500000, DIF_BPF_COEFF3435,  0xfef10ba3},
+{6500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 65_quant.dat*/
+
+
+/*case 6600000:*/
+/* BEGIN - DIF BPF register values from 66_quant.dat*/
+{6600000, DIF_BPF_COEFF01,    0x0000fffe},
+{6600000, DIF_BPF_COEFF23,    0xfff7fff5},
+{6600000, DIF_BPF_COEFF45,    0x0005002f},
+{6600000, DIF_BPF_COEFF67,    0x0054003c},
+{6600000, DIF_BPF_COEFF89,    0xffc5ff22},
+{6600000, DIF_BPF_COEFF1011,  0xfedfff82},
+{6600000, DIF_BPF_COEFF1213,  0x00fc0267},
+{6600000, DIF_BPF_COEFF1415,  0x0276007e},
+{6600000, DIF_BPF_COEFF1617,  0xfd51fb1c},
+{6600000, DIF_BPF_COEFF1819,  0xfbfe003e},
+{6600000, DIF_BPF_COEFF2021,  0x05830802},
+{6600000, DIF_BPF_COEFF2223,  0x0529fdec},
+{6600000, DIF_BPF_COEFF2425,  0xf6c8f4fe},
+{6600000, DIF_BPF_COEFF2627,  0xfabd04ff},
+{6600000, DIF_BPF_COEFF2829,  0x0d0d0cf6},
+{6600000, DIF_BPF_COEFF3031,  0x03f8f78f},
+{6600000, DIF_BPF_COEFF3233,  0xf00af2d7},
+{6600000, DIF_BPF_COEFF3435,  0xfe850b7b},
+{6600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 66_quant.dat*/
+
+
+/*case 6700000:*/
+/* BEGIN - DIF BPF register values from 67_quant.dat*/
+{6700000, DIF_BPF_COEFF01,    0x0000ffff},
+{6700000, DIF_BPF_COEFF23,    0xfff8fff0},
+{6700000, DIF_BPF_COEFF45,    0xfff80020},
+{6700000, DIF_BPF_COEFF67,    0x00560060},
+{6700000, DIF_BPF_COEFF89,    0x0002ff4e},
+{6700000, DIF_BPF_COEFF1011,  0xfec4ff10},
+{6700000, DIF_BPF_COEFF1213,  0x006d0225},
+{6700000, DIF_BPF_COEFF1415,  0x02d50166},
+{6700000, DIF_BPF_COEFF1617,  0xfe35fb4e},
+{6700000, DIF_BPF_COEFF1819,  0xfb35fee1},
+{6700000, DIF_BPF_COEFF2021,  0x0477080e},
+{6700000, DIF_BPF_COEFF2223,  0x065bff82},
+{6700000, DIF_BPF_COEFF2425,  0xf7b1f4a0},
+{6700000, DIF_BPF_COEFF2627,  0xf9610397},
+{6700000, DIF_BPF_COEFF2829,  0x0c810d80},
+{6700000, DIF_BPF_COEFF3031,  0x0510f869},
+{6700000, DIF_BPF_COEFF3233,  0xf033f278},
+{6700000, DIF_BPF_COEFF3435,  0xfe1a0b52},
+{6700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 67_quant.dat*/
+
+
+/*case 6800000:*/
+/* BEGIN - DIF BPF register values from 68_quant.dat*/
+{6800000, DIF_BPF_COEFF01,    0x00010000},
+{6800000, DIF_BPF_COEFF23,    0xfffaffee},
+{6800000, DIF_BPF_COEFF45,    0xffec000c},
+{6800000, DIF_BPF_COEFF67,    0x004c0078},
+{6800000, DIF_BPF_COEFF89,    0x0040ff8e},
+{6800000, DIF_BPF_COEFF1011,  0xfecafeb6},
+{6800000, DIF_BPF_COEFF1213,  0xffd301b6},
+{6800000, DIF_BPF_COEFF1415,  0x02fc0235},
+{6800000, DIF_BPF_COEFF1617,  0xff36fbc5},
+{6800000, DIF_BPF_COEFF1819,  0xfaaafd90},
+{6800000, DIF_BPF_COEFF2021,  0x033e07d2},
+{6800000, DIF_BPF_COEFF2223,  0x075b011b},
+{6800000, DIF_BPF_COEFF2425,  0xf8cbf47a},
+{6800000, DIF_BPF_COEFF2627,  0xf81f0224},
+{6800000, DIF_BPF_COEFF2829,  0x0bd50def},
+{6800000, DIF_BPF_COEFF3031,  0x0621f94b},
+{6800000, DIF_BPF_COEFF3233,  0xf067f21e},
+{6800000, DIF_BPF_COEFF3435,  0xfdae0b29},
+{6800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 68_quant.dat*/
+
+
+/*case 6900000:*/
+/* BEGIN - DIF BPF register values from 69_quant.dat*/
+{6900000, DIF_BPF_COEFF01,    0x00010001},
+{6900000, DIF_BPF_COEFF23,    0xfffdffef},
+{6900000, DIF_BPF_COEFF45,    0xffe3fff6},
+{6900000, DIF_BPF_COEFF67,    0x0037007f},
+{6900000, DIF_BPF_COEFF89,    0x0075ffdc},
+{6900000, DIF_BPF_COEFF1011,  0xfef2fe7c},
+{6900000, DIF_BPF_COEFF1213,  0xff3d0122},
+{6900000, DIF_BPF_COEFF1415,  0x02ea02dd},
+{6900000, DIF_BPF_COEFF1617,  0x0044fc79},
+{6900000, DIF_BPF_COEFF1819,  0xfa65fc5d},
+{6900000, DIF_BPF_COEFF2021,  0x01e3074e},
+{6900000, DIF_BPF_COEFF2223,  0x082102ad},
+{6900000, DIF_BPF_COEFF2425,  0xfa0ff48c},
+{6900000, DIF_BPF_COEFF2627,  0xf6fe00a9},
+{6900000, DIF_BPF_COEFF2829,  0x0b0a0e43},
+{6900000, DIF_BPF_COEFF3031,  0x0729fa33},
+{6900000, DIF_BPF_COEFF3233,  0xf0a5f1c9},
+{6900000, DIF_BPF_COEFF3435,  0xfd430b00},
+{6900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 69_quant.dat*/
+
+
+/*case 7000000:*/
+/* BEGIN - DIF BPF register values from 70_quant.dat*/
+{7000000, DIF_BPF_COEFF01,    0x00010002},
+{7000000, DIF_BPF_COEFF23,    0x0001fff3},
+{7000000, DIF_BPF_COEFF45,    0xffdeffe2},
+{7000000, DIF_BPF_COEFF67,    0x001b0076},
+{7000000, DIF_BPF_COEFF89,    0x009c002d},
+{7000000, DIF_BPF_COEFF1011,  0xff35fe68},
+{7000000, DIF_BPF_COEFF1213,  0xfeba0076},
+{7000000, DIF_BPF_COEFF1415,  0x029f0352},
+{7000000, DIF_BPF_COEFF1617,  0x014dfd60},
+{7000000, DIF_BPF_COEFF1819,  0xfa69fb53},
+{7000000, DIF_BPF_COEFF2021,  0x00740688},
+{7000000, DIF_BPF_COEFF2223,  0x08a7042d},
+{7000000, DIF_BPF_COEFF2425,  0xfb75f4d6},
+{7000000, DIF_BPF_COEFF2627,  0xf600ff2d},
+{7000000, DIF_BPF_COEFF2829,  0x0a220e7a},
+{7000000, DIF_BPF_COEFF3031,  0x0827fb22},
+{7000000, DIF_BPF_COEFF3233,  0xf0edf17a},
+{7000000, DIF_BPF_COEFF3435,  0xfcd80ad6},
+{7000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 70_quant.dat*/
+
+
+/*case 7100000:*/
+/* BEGIN - DIF BPF register values from 71_quant.dat*/
+{7100000, DIF_BPF_COEFF01,    0x00000003},
+{7100000, DIF_BPF_COEFF23,    0x0004fff9},
+{7100000, DIF_BPF_COEFF45,    0xffe0ffd2},
+{7100000, DIF_BPF_COEFF67,    0xfffb005e},
+{7100000, DIF_BPF_COEFF89,    0x00b0007a},
+{7100000, DIF_BPF_COEFF1011,  0xff8ffe7c},
+{7100000, DIF_BPF_COEFF1213,  0xfe53ffc1},
+{7100000, DIF_BPF_COEFF1415,  0x0221038c},
+{7100000, DIF_BPF_COEFF1617,  0x0241fe6e},
+{7100000, DIF_BPF_COEFF1819,  0xfab6fa80},
+{7100000, DIF_BPF_COEFF2021,  0xff010587},
+{7100000, DIF_BPF_COEFF2223,  0x08e90590},
+{7100000, DIF_BPF_COEFF2425,  0xfcf5f556},
+{7100000, DIF_BPF_COEFF2627,  0xf52bfdb3},
+{7100000, DIF_BPF_COEFF2829,  0x09210e95},
+{7100000, DIF_BPF_COEFF3031,  0x0919fc15},
+{7100000, DIF_BPF_COEFF3233,  0xf13ff12f},
+{7100000, DIF_BPF_COEFF3435,  0xfc6e0aab},
+{7100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 71_quant.dat*/
+
+
+/*case 7200000:*/
+/* BEGIN - DIF BPF register values from 72_quant.dat*/
+{7200000, DIF_BPF_COEFF01,    0x00000003},
+{7200000, DIF_BPF_COEFF23,    0x00070000},
+{7200000, DIF_BPF_COEFF45,    0xffe6ffc9},
+{7200000, DIF_BPF_COEFF67,    0xffdb0039},
+{7200000, DIF_BPF_COEFF89,    0x00af00b8},
+{7200000, DIF_BPF_COEFF1011,  0xfff4feb6},
+{7200000, DIF_BPF_COEFF1213,  0xfe13ff10},
+{7200000, DIF_BPF_COEFF1415,  0x01790388},
+{7200000, DIF_BPF_COEFF1617,  0x0311ff92},
+{7200000, DIF_BPF_COEFF1819,  0xfb48f9ed},
+{7200000, DIF_BPF_COEFF2021,  0xfd980453},
+{7200000, DIF_BPF_COEFF2223,  0x08e306cd},
+{7200000, DIF_BPF_COEFF2425,  0xfe88f60a},
+{7200000, DIF_BPF_COEFF2627,  0xf482fc40},
+{7200000, DIF_BPF_COEFF2829,  0x08080e93},
+{7200000, DIF_BPF_COEFF3031,  0x09fdfd0c},
+{7200000, DIF_BPF_COEFF3233,  0xf19af0ea},
+{7200000, DIF_BPF_COEFF3435,  0xfc050a81},
+{7200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 72_quant.dat*/
+
+
+/*case 7300000:*/
+/* BEGIN - DIF BPF register values from 73_quant.dat*/
+{7300000, DIF_BPF_COEFF01,    0x00000002},
+{7300000, DIF_BPF_COEFF23,    0x00080008},
+{7300000, DIF_BPF_COEFF45,    0xfff0ffc9},
+{7300000, DIF_BPF_COEFF67,    0xffc1000d},
+{7300000, DIF_BPF_COEFF89,    0x009800e2},
+{7300000, DIF_BPF_COEFF1011,  0x005bff10},
+{7300000, DIF_BPF_COEFF1213,  0xfe00fe74},
+{7300000, DIF_BPF_COEFF1415,  0x00b50345},
+{7300000, DIF_BPF_COEFF1617,  0x03b000bc},
+{7300000, DIF_BPF_COEFF1819,  0xfc18f9a1},
+{7300000, DIF_BPF_COEFF2021,  0xfc4802f9},
+{7300000, DIF_BPF_COEFF2223,  0x089807dc},
+{7300000, DIF_BPF_COEFF2425,  0x0022f6f0},
+{7300000, DIF_BPF_COEFF2627,  0xf407fada},
+{7300000, DIF_BPF_COEFF2829,  0x06da0e74},
+{7300000, DIF_BPF_COEFF3031,  0x0ad3fe06},
+{7300000, DIF_BPF_COEFF3233,  0xf1fef0ab},
+{7300000, DIF_BPF_COEFF3435,  0xfb9c0a55},
+{7300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 73_quant.dat*/
+
+
+/*case 7400000:*/
+/* BEGIN - DIF BPF register values from 74_quant.dat*/
+{7400000, DIF_BPF_COEFF01,    0x00000001},
+{7400000, DIF_BPF_COEFF23,    0x0008000e},
+{7400000, DIF_BPF_COEFF45,    0xfffdffd0},
+{7400000, DIF_BPF_COEFF67,    0xffafffdf},
+{7400000, DIF_BPF_COEFF89,    0x006e00f2},
+{7400000, DIF_BPF_COEFF1011,  0x00b8ff82},
+{7400000, DIF_BPF_COEFF1213,  0xfe1bfdf8},
+{7400000, DIF_BPF_COEFF1415,  0xffe302c8},
+{7400000, DIF_BPF_COEFF1617,  0x041301dc},
+{7400000, DIF_BPF_COEFF1819,  0xfd1af99e},
+{7400000, DIF_BPF_COEFF2021,  0xfb1e0183},
+{7400000, DIF_BPF_COEFF2223,  0x080908b5},
+{7400000, DIF_BPF_COEFF2425,  0x01bcf801},
+{7400000, DIF_BPF_COEFF2627,  0xf3bdf985},
+{7400000, DIF_BPF_COEFF2829,  0x059a0e38},
+{7400000, DIF_BPF_COEFF3031,  0x0b99ff03},
+{7400000, DIF_BPF_COEFF3233,  0xf26cf071},
+{7400000, DIF_BPF_COEFF3435,  0xfb330a2a},
+{7400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 74_quant.dat*/
+
+
+/*case 7500000:*/
+/* BEGIN - DIF BPF register values from 75_quant.dat*/
+{7500000, DIF_BPF_COEFF01,    0xffff0000},
+{7500000, DIF_BPF_COEFF23,    0x00070011},
+{7500000, DIF_BPF_COEFF45,    0x000affdf},
+{7500000, DIF_BPF_COEFF67,    0xffa9ffb5},
+{7500000, DIF_BPF_COEFF89,    0x003700e6},
+{7500000, DIF_BPF_COEFF1011,  0x01010000},
+{7500000, DIF_BPF_COEFF1213,  0xfe62fda8},
+{7500000, DIF_BPF_COEFF1415,  0xff140219},
+{7500000, DIF_BPF_COEFF1617,  0x043502e1},
+{7500000, DIF_BPF_COEFF1819,  0xfe42f9e6},
+{7500000, DIF_BPF_COEFF2021,  0xfa270000},
+{7500000, DIF_BPF_COEFF2223,  0x073a0953},
+{7500000, DIF_BPF_COEFF2425,  0x034cf939},
+{7500000, DIF_BPF_COEFF2627,  0xf3a4f845},
+{7500000, DIF_BPF_COEFF2829,  0x044c0de1},
+{7500000, DIF_BPF_COEFF3031,  0x0c4f0000},
+{7500000, DIF_BPF_COEFF3233,  0xf2e2f03c},
+{7500000, DIF_BPF_COEFF3435,  0xfacc09fe},
+{7500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 75_quant.dat*/
+
+
+/*case 7600000:*/
+/* BEGIN - DIF BPF register values from 76_quant.dat*/
+{7600000, DIF_BPF_COEFF01,    0xffffffff},
+{7600000, DIF_BPF_COEFF23,    0x00040012},
+{7600000, DIF_BPF_COEFF45,    0x0016fff3},
+{7600000, DIF_BPF_COEFF67,    0xffafff95},
+{7600000, DIF_BPF_COEFF89,    0xfff900c0},
+{7600000, DIF_BPF_COEFF1011,  0x0130007e},
+{7600000, DIF_BPF_COEFF1213,  0xfecefd89},
+{7600000, DIF_BPF_COEFF1415,  0xfe560146},
+{7600000, DIF_BPF_COEFF1617,  0x041303bc},
+{7600000, DIF_BPF_COEFF1819,  0xff81fa76},
+{7600000, DIF_BPF_COEFF2021,  0xf96cfe7d},
+{7600000, DIF_BPF_COEFF2223,  0x063209b1},
+{7600000, DIF_BPF_COEFF2425,  0x04c9fa93},
+{7600000, DIF_BPF_COEFF2627,  0xf3bdf71e},
+{7600000, DIF_BPF_COEFF2829,  0x02f30d6e},
+{7600000, DIF_BPF_COEFF3031,  0x0cf200fd},
+{7600000, DIF_BPF_COEFF3233,  0xf361f00e},
+{7600000, DIF_BPF_COEFF3435,  0xfa6509d1},
+{7600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 76_quant.dat*/
+
+
+/*case 7700000:*/
+/* BEGIN - DIF BPF register values from 77_quant.dat*/
+{7700000, DIF_BPF_COEFF01,    0xfffffffe},
+{7700000, DIF_BPF_COEFF23,    0x00010010},
+{7700000, DIF_BPF_COEFF45,    0x001e0008},
+{7700000, DIF_BPF_COEFF67,    0xffc1ff84},
+{7700000, DIF_BPF_COEFF89,    0xffbc0084},
+{7700000, DIF_BPF_COEFF1011,  0x013e00f0},
+{7700000, DIF_BPF_COEFF1213,  0xff56fd9f},
+{7700000, DIF_BPF_COEFF1415,  0xfdb8005c},
+{7700000, DIF_BPF_COEFF1617,  0x03b00460},
+{7700000, DIF_BPF_COEFF1819,  0x00c7fb45},
+{7700000, DIF_BPF_COEFF2021,  0xf8f4fd07},
+{7700000, DIF_BPF_COEFF2223,  0x04fa09ce},
+{7700000, DIF_BPF_COEFF2425,  0x062afc07},
+{7700000, DIF_BPF_COEFF2627,  0xf407f614},
+{7700000, DIF_BPF_COEFF2829,  0x01920ce0},
+{7700000, DIF_BPF_COEFF3031,  0x0d8301fa},
+{7700000, DIF_BPF_COEFF3233,  0xf3e8efe5},
+{7700000, DIF_BPF_COEFF3435,  0xfa0009a4},
+{7700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 77_quant.dat*/
+
+
+/*case 7800000:*/
+/* BEGIN - DIF BPF register values from 78_quant.dat*/
+{7800000, DIF_BPF_COEFF01,    0x0000fffd},
+{7800000, DIF_BPF_COEFF23,    0xfffd000b},
+{7800000, DIF_BPF_COEFF45,    0x0022001d},
+{7800000, DIF_BPF_COEFF67,    0xffdbff82},
+{7800000, DIF_BPF_COEFF89,    0xff870039},
+{7800000, DIF_BPF_COEFF1011,  0x012a014a},
+{7800000, DIF_BPF_COEFF1213,  0xffedfde7},
+{7800000, DIF_BPF_COEFF1415,  0xfd47ff6b},
+{7800000, DIF_BPF_COEFF1617,  0x031104c6},
+{7800000, DIF_BPF_COEFF1819,  0x0202fc4c},
+{7800000, DIF_BPF_COEFF2021,  0xf8c6fbad},
+{7800000, DIF_BPF_COEFF2223,  0x039909a7},
+{7800000, DIF_BPF_COEFF2425,  0x0767fd8e},
+{7800000, DIF_BPF_COEFF2627,  0xf482f52b},
+{7800000, DIF_BPF_COEFF2829,  0x002d0c39},
+{7800000, DIF_BPF_COEFF3031,  0x0e0002f4},
+{7800000, DIF_BPF_COEFF3233,  0xf477efc2},
+{7800000, DIF_BPF_COEFF3435,  0xf99b0977},
+{7800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 78_quant.dat*/
+
+
+/*case 7900000:*/
+/* BEGIN - DIF BPF register values from 79_quant.dat*/
+{7900000, DIF_BPF_COEFF01,    0x0000fffd},
+{7900000, DIF_BPF_COEFF23,    0xfffa0004},
+{7900000, DIF_BPF_COEFF45,    0x0020002d},
+{7900000, DIF_BPF_COEFF67,    0xfffbff91},
+{7900000, DIF_BPF_COEFF89,    0xff61ffe8},
+{7900000, DIF_BPF_COEFF1011,  0x00f70184},
+{7900000, DIF_BPF_COEFF1213,  0x0086fe5c},
+{7900000, DIF_BPF_COEFF1415,  0xfd0bfe85},
+{7900000, DIF_BPF_COEFF1617,  0x024104e5},
+{7900000, DIF_BPF_COEFF1819,  0x0323fd7d},
+{7900000, DIF_BPF_COEFF2021,  0xf8e2fa79},
+{7900000, DIF_BPF_COEFF2223,  0x021d093f},
+{7900000, DIF_BPF_COEFF2425,  0x0879ff22},
+{7900000, DIF_BPF_COEFF2627,  0xf52bf465},
+{7900000, DIF_BPF_COEFF2829,  0xfec70b79},
+{7900000, DIF_BPF_COEFF3031,  0x0e6803eb},
+{7900000, DIF_BPF_COEFF3233,  0xf50defa5},
+{7900000, DIF_BPF_COEFF3435,  0xf937094a},
+{7900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 79_quant.dat*/
+
+
+/*case 8000000:*/
+/* BEGIN - DIF BPF register values from 80_quant.dat*/
+{8000000, DIF_BPF_COEFF01,    0x0000fffe},
+{8000000, DIF_BPF_COEFF23,    0xfff8fffd},
+{8000000, DIF_BPF_COEFF45,    0x00190036},
+{8000000, DIF_BPF_COEFF67,    0x001bffaf},
+{8000000, DIF_BPF_COEFF89,    0xff4fff99},
+{8000000, DIF_BPF_COEFF1011,  0x00aa0198},
+{8000000, DIF_BPF_COEFF1213,  0x0112fef3},
+{8000000, DIF_BPF_COEFF1415,  0xfd09fdb9},
+{8000000, DIF_BPF_COEFF1617,  0x014d04be},
+{8000000, DIF_BPF_COEFF1819,  0x041bfecc},
+{8000000, DIF_BPF_COEFF2021,  0xf947f978},
+{8000000, DIF_BPF_COEFF2223,  0x00900897},
+{8000000, DIF_BPF_COEFF2425,  0x095a00b9},
+{8000000, DIF_BPF_COEFF2627,  0xf600f3c5},
+{8000000, DIF_BPF_COEFF2829,  0xfd650aa3},
+{8000000, DIF_BPF_COEFF3031,  0x0ebc04de},
+{8000000, DIF_BPF_COEFF3233,  0xf5aaef8e},
+{8000000, DIF_BPF_COEFF3435,  0xf8d5091c},
+{8000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 80_quant.dat*/
+
+
+/*case 8100000:*/
+/* BEGIN - DIF BPF register values from 81_quant.dat*/
+{8100000, DIF_BPF_COEFF01,    0x0000ffff},
+{8100000, DIF_BPF_COEFF23,    0xfff7fff6},
+{8100000, DIF_BPF_COEFF45,    0x000e0038},
+{8100000, DIF_BPF_COEFF67,    0x0037ffd7},
+{8100000, DIF_BPF_COEFF89,    0xff52ff56},
+{8100000, DIF_BPF_COEFF1011,  0x004b0184},
+{8100000, DIF_BPF_COEFF1213,  0x0186ffa1},
+{8100000, DIF_BPF_COEFF1415,  0xfd40fd16},
+{8100000, DIF_BPF_COEFF1617,  0x00440452},
+{8100000, DIF_BPF_COEFF1819,  0x04de0029},
+{8100000, DIF_BPF_COEFF2021,  0xf9f2f8b2},
+{8100000, DIF_BPF_COEFF2223,  0xfefe07b5},
+{8100000, DIF_BPF_COEFF2425,  0x0a05024d},
+{8100000, DIF_BPF_COEFF2627,  0xf6fef34d},
+{8100000, DIF_BPF_COEFF2829,  0xfc0a09b8},
+{8100000, DIF_BPF_COEFF3031,  0x0efa05cd},
+{8100000, DIF_BPF_COEFF3233,  0xf64eef7d},
+{8100000, DIF_BPF_COEFF3435,  0xf87308ed},
+{8100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 81_quant.dat*/
+
+
+/*case 8200000:*/
+/* BEGIN - DIF BPF register values from 82_quant.dat*/
+{8200000, DIF_BPF_COEFF01,    0x00010000},
+{8200000, DIF_BPF_COEFF23,    0xfff8fff0},
+{8200000, DIF_BPF_COEFF45,    0x00000031},
+{8200000, DIF_BPF_COEFF67,    0x004c0005},
+{8200000, DIF_BPF_COEFF89,    0xff6aff27},
+{8200000, DIF_BPF_COEFF1011,  0xffe4014a},
+{8200000, DIF_BPF_COEFF1213,  0x01d70057},
+{8200000, DIF_BPF_COEFF1415,  0xfdacfca6},
+{8200000, DIF_BPF_COEFF1617,  0xff3603a7},
+{8200000, DIF_BPF_COEFF1819,  0x05610184},
+{8200000, DIF_BPF_COEFF2021,  0xfadbf82e},
+{8200000, DIF_BPF_COEFF2223,  0xfd74069f},
+{8200000, DIF_BPF_COEFF2425,  0x0a7503d6},
+{8200000, DIF_BPF_COEFF2627,  0xf81ff2ff},
+{8200000, DIF_BPF_COEFF2829,  0xfab808b9},
+{8200000, DIF_BPF_COEFF3031,  0x0f2306b5},
+{8200000, DIF_BPF_COEFF3233,  0xf6f9ef72},
+{8200000, DIF_BPF_COEFF3435,  0xf81308bf},
+{8200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 82_quant.dat*/
+
+
+/*case 8300000:*/
+/* BEGIN - DIF BPF register values from 83_quant.dat*/
+{8300000, DIF_BPF_COEFF01,    0x00010001},
+{8300000, DIF_BPF_COEFF23,    0xfffbffee},
+{8300000, DIF_BPF_COEFF45,    0xfff30022},
+{8300000, DIF_BPF_COEFF67,    0x00560032},
+{8300000, DIF_BPF_COEFF89,    0xff95ff10},
+{8300000, DIF_BPF_COEFF1011,  0xff8000f0},
+{8300000, DIF_BPF_COEFF1213,  0x01fe0106},
+{8300000, DIF_BPF_COEFF1415,  0xfe46fc71},
+{8300000, DIF_BPF_COEFF1617,  0xfe3502c7},
+{8300000, DIF_BPF_COEFF1819,  0x059e02ce},
+{8300000, DIF_BPF_COEFF2021,  0xfbf9f7f2},
+{8300000, DIF_BPF_COEFF2223,  0xfbff055b},
+{8300000, DIF_BPF_COEFF2425,  0x0aa9054c},
+{8300000, DIF_BPF_COEFF2627,  0xf961f2db},
+{8300000, DIF_BPF_COEFF2829,  0xf97507aa},
+{8300000, DIF_BPF_COEFF3031,  0x0f350797},
+{8300000, DIF_BPF_COEFF3233,  0xf7a9ef6d},
+{8300000, DIF_BPF_COEFF3435,  0xf7b40890},
+{8300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 83_quant.dat*/
+
+
+/*case 8400000:*/
+/* BEGIN - DIF BPF register values from 84_quant.dat*/
+{8400000, DIF_BPF_COEFF01,    0x00010002},
+{8400000, DIF_BPF_COEFF23,    0xfffeffee},
+{8400000, DIF_BPF_COEFF45,    0xffe8000f},
+{8400000, DIF_BPF_COEFF67,    0x00540058},
+{8400000, DIF_BPF_COEFF89,    0xffcdff14},
+{8400000, DIF_BPF_COEFF1011,  0xff29007e},
+{8400000, DIF_BPF_COEFF1213,  0x01f6019e},
+{8400000, DIF_BPF_COEFF1415,  0xff01fc7c},
+{8400000, DIF_BPF_COEFF1617,  0xfd5101bf},
+{8400000, DIF_BPF_COEFF1819,  0x059203f6},
+{8400000, DIF_BPF_COEFF2021,  0xfd41f7fe},
+{8400000, DIF_BPF_COEFF2223,  0xfaa903f3},
+{8400000, DIF_BPF_COEFF2425,  0x0a9e06a9},
+{8400000, DIF_BPF_COEFF2627,  0xfabdf2e2},
+{8400000, DIF_BPF_COEFF2829,  0xf842068b},
+{8400000, DIF_BPF_COEFF3031,  0x0f320871},
+{8400000, DIF_BPF_COEFF3233,  0xf85eef6e},
+{8400000, DIF_BPF_COEFF3435,  0xf7560860},
+{8400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 84_quant.dat*/
+
+
+/*case 8500000:*/
+/* BEGIN - DIF BPF register values from 85_quant.dat*/
+{8500000, DIF_BPF_COEFF01,    0x00000003},
+{8500000, DIF_BPF_COEFF23,    0x0002fff2},
+{8500000, DIF_BPF_COEFF45,    0xffe1fff9},
+{8500000, DIF_BPF_COEFF67,    0x00460073},
+{8500000, DIF_BPF_COEFF89,    0x000bff34},
+{8500000, DIF_BPF_COEFF1011,  0xfee90000},
+{8500000, DIF_BPF_COEFF1213,  0x01c10215},
+{8500000, DIF_BPF_COEFF1415,  0xffd0fcc5},
+{8500000, DIF_BPF_COEFF1617,  0xfc99009d},
+{8500000, DIF_BPF_COEFF1819,  0x053d04f1},
+{8500000, DIF_BPF_COEFF2021,  0xfea5f853},
+{8500000, DIF_BPF_COEFF2223,  0xf97d0270},
+{8500000, DIF_BPF_COEFF2425,  0x0a5607e4},
+{8500000, DIF_BPF_COEFF2627,  0xfc2ef314},
+{8500000, DIF_BPF_COEFF2829,  0xf723055f},
+{8500000, DIF_BPF_COEFF3031,  0x0f180943},
+{8500000, DIF_BPF_COEFF3233,  0xf919ef75},
+{8500000, DIF_BPF_COEFF3435,  0xf6fa0830},
+{8500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 85_quant.dat*/
+
+
+/*case 8600000:*/
+/* BEGIN - DIF BPF register values from 86_quant.dat*/
+{8600000, DIF_BPF_COEFF01,    0x00000003},
+{8600000, DIF_BPF_COEFF23,    0x0005fff8},
+{8600000, DIF_BPF_COEFF45,    0xffdeffe4},
+{8600000, DIF_BPF_COEFF67,    0x002f007f},
+{8600000, DIF_BPF_COEFF89,    0x0048ff6b},
+{8600000, DIF_BPF_COEFF1011,  0xfec7ff82},
+{8600000, DIF_BPF_COEFF1213,  0x0163025f},
+{8600000, DIF_BPF_COEFF1415,  0x00a2fd47},
+{8600000, DIF_BPF_COEFF1617,  0xfc17ff73},
+{8600000, DIF_BPF_COEFF1819,  0x04a405b2},
+{8600000, DIF_BPF_COEFF2021,  0x0017f8ed},
+{8600000, DIF_BPF_COEFF2223,  0xf88500dc},
+{8600000, DIF_BPF_COEFF2425,  0x09d208f9},
+{8600000, DIF_BPF_COEFF2627,  0xfdaff370},
+{8600000, DIF_BPF_COEFF2829,  0xf61c0429},
+{8600000, DIF_BPF_COEFF3031,  0x0ee80a0b},
+{8600000, DIF_BPF_COEFF3233,  0xf9d8ef82},
+{8600000, DIF_BPF_COEFF3435,  0xf6a00800},
+{8600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 86_quant.dat*/
+
+
+/*case 8700000:*/
+/* BEGIN - DIF BPF register values from 87_quant.dat*/
+{8700000, DIF_BPF_COEFF01,    0x00000003},
+{8700000, DIF_BPF_COEFF23,    0x0007ffff},
+{8700000, DIF_BPF_COEFF45,    0xffe1ffd4},
+{8700000, DIF_BPF_COEFF67,    0x0010007a},
+{8700000, DIF_BPF_COEFF89,    0x007cffb2},
+{8700000, DIF_BPF_COEFF1011,  0xfec6ff10},
+{8700000, DIF_BPF_COEFF1213,  0x00e60277},
+{8700000, DIF_BPF_COEFF1415,  0x0168fdf9},
+{8700000, DIF_BPF_COEFF1617,  0xfbd3fe50},
+{8700000, DIF_BPF_COEFF1819,  0x03ce0631},
+{8700000, DIF_BPF_COEFF2021,  0x0188f9c8},
+{8700000, DIF_BPF_COEFF2223,  0xf7c7ff43},
+{8700000, DIF_BPF_COEFF2425,  0x091509e3},
+{8700000, DIF_BPF_COEFF2627,  0xff39f3f6},
+{8700000, DIF_BPF_COEFF2829,  0xf52d02ea},
+{8700000, DIF_BPF_COEFF3031,  0x0ea30ac9},
+{8700000, DIF_BPF_COEFF3233,  0xfa9bef95},
+{8700000, DIF_BPF_COEFF3435,  0xf64607d0},
+{8700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 87_quant.dat*/
+
+
+/*case 8800000:*/
+/* BEGIN - DIF BPF register values from 88_quant.dat*/
+{8800000, DIF_BPF_COEFF01,    0x00000002},
+{8800000, DIF_BPF_COEFF23,    0x00090007},
+{8800000, DIF_BPF_COEFF45,    0xffe9ffca},
+{8800000, DIF_BPF_COEFF67,    0xfff00065},
+{8800000, DIF_BPF_COEFF89,    0x00a10003},
+{8800000, DIF_BPF_COEFF1011,  0xfee6feb6},
+{8800000, DIF_BPF_COEFF1213,  0x0053025b},
+{8800000, DIF_BPF_COEFF1415,  0x0213fed0},
+{8800000, DIF_BPF_COEFF1617,  0xfbd3fd46},
+{8800000, DIF_BPF_COEFF1819,  0x02c70668},
+{8800000, DIF_BPF_COEFF2021,  0x02eafadb},
+{8800000, DIF_BPF_COEFF2223,  0xf74bfdae},
+{8800000, DIF_BPF_COEFF2425,  0x08230a9c},
+{8800000, DIF_BPF_COEFF2627,  0x00c7f4a3},
+{8800000, DIF_BPF_COEFF2829,  0xf45b01a6},
+{8800000, DIF_BPF_COEFF3031,  0x0e480b7c},
+{8800000, DIF_BPF_COEFF3233,  0xfb61efae},
+{8800000, DIF_BPF_COEFF3435,  0xf5ef079f},
+{8800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 88_quant.dat*/
+
+
+/*case 8900000:*/
+/* BEGIN - DIF BPF register values from 89_quant.dat*/
+{8900000, DIF_BPF_COEFF01,    0xffff0000},
+{8900000, DIF_BPF_COEFF23,    0x0008000d},
+{8900000, DIF_BPF_COEFF45,    0xfff5ffc8},
+{8900000, DIF_BPF_COEFF67,    0xffd10043},
+{8900000, DIF_BPF_COEFF89,    0x00b20053},
+{8900000, DIF_BPF_COEFF1011,  0xff24fe7c},
+{8900000, DIF_BPF_COEFF1213,  0xffb9020c},
+{8900000, DIF_BPF_COEFF1415,  0x0295ffbb},
+{8900000, DIF_BPF_COEFF1617,  0xfc17fc64},
+{8900000, DIF_BPF_COEFF1819,  0x019b0654},
+{8900000, DIF_BPF_COEFF2021,  0x042dfc1c},
+{8900000, DIF_BPF_COEFF2223,  0xf714fc2a},
+{8900000, DIF_BPF_COEFF2425,  0x07020b21},
+{8900000, DIF_BPF_COEFF2627,  0x0251f575},
+{8900000, DIF_BPF_COEFF2829,  0xf3a7005e},
+{8900000, DIF_BPF_COEFF3031,  0x0dd80c24},
+{8900000, DIF_BPF_COEFF3233,  0xfc2aefcd},
+{8900000, DIF_BPF_COEFF3435,  0xf599076e},
+{8900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 89_quant.dat*/
+
+
+/*case 9000000:*/
+/* BEGIN - DIF BPF register values from 90_quant.dat*/
+{9000000, DIF_BPF_COEFF01,    0xffffffff},
+{9000000, DIF_BPF_COEFF23,    0x00060011},
+{9000000, DIF_BPF_COEFF45,    0x0002ffcf},
+{9000000, DIF_BPF_COEFF67,    0xffba0018},
+{9000000, DIF_BPF_COEFF89,    0x00ad009a},
+{9000000, DIF_BPF_COEFF1011,  0xff79fe68},
+{9000000, DIF_BPF_COEFF1213,  0xff260192},
+{9000000, DIF_BPF_COEFF1415,  0x02e500ab},
+{9000000, DIF_BPF_COEFF1617,  0xfc99fbb6},
+{9000000, DIF_BPF_COEFF1819,  0x005b05f7},
+{9000000, DIF_BPF_COEFF2021,  0x0545fd81},
+{9000000, DIF_BPF_COEFF2223,  0xf723fabf},
+{9000000, DIF_BPF_COEFF2425,  0x05b80b70},
+{9000000, DIF_BPF_COEFF2627,  0x03d2f669},
+{9000000, DIF_BPF_COEFF2829,  0xf313ff15},
+{9000000, DIF_BPF_COEFF3031,  0x0d550cbf},
+{9000000, DIF_BPF_COEFF3233,  0xfcf6eff2},
+{9000000, DIF_BPF_COEFF3435,  0xf544073d},
+{9000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 90_quant.dat*/
+
+
+/*case 9100000:*/
+/* BEGIN - DIF BPF register values from 91_quant.dat*/
+{9100000, DIF_BPF_COEFF01,    0xfffffffe},
+{9100000, DIF_BPF_COEFF23,    0x00030012},
+{9100000, DIF_BPF_COEFF45,    0x000fffdd},
+{9100000, DIF_BPF_COEFF67,    0xffacffea},
+{9100000, DIF_BPF_COEFF89,    0x009300cf},
+{9100000, DIF_BPF_COEFF1011,  0xffdcfe7c},
+{9100000, DIF_BPF_COEFF1213,  0xfea600f7},
+{9100000, DIF_BPF_COEFF1415,  0x02fd0190},
+{9100000, DIF_BPF_COEFF1617,  0xfd51fb46},
+{9100000, DIF_BPF_COEFF1819,  0xff150554},
+{9100000, DIF_BPF_COEFF2021,  0x0627fefd},
+{9100000, DIF_BPF_COEFF2223,  0xf778f978},
+{9100000, DIF_BPF_COEFF2425,  0x044d0b87},
+{9100000, DIF_BPF_COEFF2627,  0x0543f77d},
+{9100000, DIF_BPF_COEFF2829,  0xf2a0fdcf},
+{9100000, DIF_BPF_COEFF3031,  0x0cbe0d4e},
+{9100000, DIF_BPF_COEFF3233,  0xfdc4f01d},
+{9100000, DIF_BPF_COEFF3435,  0xf4f2070b},
+{9100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 91_quant.dat*/
+
+
+/*case 9200000:*/
+/* BEGIN - DIF BPF register values from 92_quant.dat*/
+{9200000, DIF_BPF_COEFF01,    0x0000fffd},
+{9200000, DIF_BPF_COEFF23,    0x00000010},
+{9200000, DIF_BPF_COEFF45,    0x001afff0},
+{9200000, DIF_BPF_COEFF67,    0xffaaffbf},
+{9200000, DIF_BPF_COEFF89,    0x006700ed},
+{9200000, DIF_BPF_COEFF1011,  0x0043feb6},
+{9200000, DIF_BPF_COEFF1213,  0xfe460047},
+{9200000, DIF_BPF_COEFF1415,  0x02db0258},
+{9200000, DIF_BPF_COEFF1617,  0xfe35fb1b},
+{9200000, DIF_BPF_COEFF1819,  0xfddc0473},
+{9200000, DIF_BPF_COEFF2021,  0x06c90082},
+{9200000, DIF_BPF_COEFF2223,  0xf811f85e},
+{9200000, DIF_BPF_COEFF2425,  0x02c90b66},
+{9200000, DIF_BPF_COEFF2627,  0x069ff8ad},
+{9200000, DIF_BPF_COEFF2829,  0xf250fc8d},
+{9200000, DIF_BPF_COEFF3031,  0x0c140dcf},
+{9200000, DIF_BPF_COEFF3233,  0xfe93f04d},
+{9200000, DIF_BPF_COEFF3435,  0xf4a106d9},
+{9200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 92_quant.dat*/
+
+
+/*case 9300000:*/
+/* BEGIN - DIF BPF register values from 93_quant.dat*/
+{9300000, DIF_BPF_COEFF01,    0x0000fffd},
+{9300000, DIF_BPF_COEFF23,    0xfffc000c},
+{9300000, DIF_BPF_COEFF45,    0x00200006},
+{9300000, DIF_BPF_COEFF67,    0xffb4ff9c},
+{9300000, DIF_BPF_COEFF89,    0x002f00ef},
+{9300000, DIF_BPF_COEFF1011,  0x00a4ff10},
+{9300000, DIF_BPF_COEFF1213,  0xfe0dff92},
+{9300000, DIF_BPF_COEFF1415,  0x028102f7},
+{9300000, DIF_BPF_COEFF1617,  0xff36fb37},
+{9300000, DIF_BPF_COEFF1819,  0xfcbf035e},
+{9300000, DIF_BPF_COEFF2021,  0x07260202},
+{9300000, DIF_BPF_COEFF2223,  0xf8e8f778},
+{9300000, DIF_BPF_COEFF2425,  0x01340b0d},
+{9300000, DIF_BPF_COEFF2627,  0x07e1f9f4},
+{9300000, DIF_BPF_COEFF2829,  0xf223fb51},
+{9300000, DIF_BPF_COEFF3031,  0x0b590e42},
+{9300000, DIF_BPF_COEFF3233,  0xff64f083},
+{9300000, DIF_BPF_COEFF3435,  0xf45206a7},
+{9300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 93_quant.dat*/
+
+
+/*case 9400000:*/
+/* BEGIN - DIF BPF register values from 94_quant.dat*/
+{9400000, DIF_BPF_COEFF01,    0x0000fffd},
+{9400000, DIF_BPF_COEFF23,    0xfff90005},
+{9400000, DIF_BPF_COEFF45,    0x0022001a},
+{9400000, DIF_BPF_COEFF67,    0xffc9ff86},
+{9400000, DIF_BPF_COEFF89,    0xfff000d7},
+{9400000, DIF_BPF_COEFF1011,  0x00f2ff82},
+{9400000, DIF_BPF_COEFF1213,  0xfe01fee5},
+{9400000, DIF_BPF_COEFF1415,  0x01f60362},
+{9400000, DIF_BPF_COEFF1617,  0x0044fb99},
+{9400000, DIF_BPF_COEFF1819,  0xfbcc0222},
+{9400000, DIF_BPF_COEFF2021,  0x07380370},
+{9400000, DIF_BPF_COEFF2223,  0xf9f7f6cc},
+{9400000, DIF_BPF_COEFF2425,  0xff990a7e},
+{9400000, DIF_BPF_COEFF2627,  0x0902fb50},
+{9400000, DIF_BPF_COEFF2829,  0xf21afa1f},
+{9400000, DIF_BPF_COEFF3031,  0x0a8d0ea6},
+{9400000, DIF_BPF_COEFF3233,  0x0034f0bf},
+{9400000, DIF_BPF_COEFF3435,  0xf4050675},
+{9400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 94_quant.dat*/
+
+
+/*case 9500000:*/
+/* BEGIN - DIF BPF register values from 95_quant.dat*/
+{9500000, DIF_BPF_COEFF01,    0x0000fffe},
+{9500000, DIF_BPF_COEFF23,    0xfff8fffe},
+{9500000, DIF_BPF_COEFF45,    0x001e002b},
+{9500000, DIF_BPF_COEFF67,    0xffe5ff81},
+{9500000, DIF_BPF_COEFF89,    0xffb400a5},
+{9500000, DIF_BPF_COEFF1011,  0x01280000},
+{9500000, DIF_BPF_COEFF1213,  0xfe24fe50},
+{9500000, DIF_BPF_COEFF1415,  0x01460390},
+{9500000, DIF_BPF_COEFF1617,  0x014dfc3a},
+{9500000, DIF_BPF_COEFF1819,  0xfb1000ce},
+{9500000, DIF_BPF_COEFF2021,  0x070104bf},
+{9500000, DIF_BPF_COEFF2223,  0xfb37f65f},
+{9500000, DIF_BPF_COEFF2425,  0xfe0009bc},
+{9500000, DIF_BPF_COEFF2627,  0x0a00fcbb},
+{9500000, DIF_BPF_COEFF2829,  0xf235f8f8},
+{9500000, DIF_BPF_COEFF3031,  0x09b20efc},
+{9500000, DIF_BPF_COEFF3233,  0x0105f101},
+{9500000, DIF_BPF_COEFF3435,  0xf3ba0642},
+{9500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 95_quant.dat*/
+
+
+/*case 9600000:*/
+/* BEGIN - DIF BPF register values from 96_quant.dat*/
+{9600000, DIF_BPF_COEFF01,    0x0001ffff},
+{9600000, DIF_BPF_COEFF23,    0xfff8fff7},
+{9600000, DIF_BPF_COEFF45,    0x00150036},
+{9600000, DIF_BPF_COEFF67,    0x0005ff8c},
+{9600000, DIF_BPF_COEFF89,    0xff810061},
+{9600000, DIF_BPF_COEFF1011,  0x013d007e},
+{9600000, DIF_BPF_COEFF1213,  0xfe71fddf},
+{9600000, DIF_BPF_COEFF1415,  0x007c0380},
+{9600000, DIF_BPF_COEFF1617,  0x0241fd13},
+{9600000, DIF_BPF_COEFF1819,  0xfa94ff70},
+{9600000, DIF_BPF_COEFF2021,  0x068005e2},
+{9600000, DIF_BPF_COEFF2223,  0xfc9bf633},
+{9600000, DIF_BPF_COEFF2425,  0xfc7308ca},
+{9600000, DIF_BPF_COEFF2627,  0x0ad5fe30},
+{9600000, DIF_BPF_COEFF2829,  0xf274f7e0},
+{9600000, DIF_BPF_COEFF3031,  0x08c90f43},
+{9600000, DIF_BPF_COEFF3233,  0x01d4f147},
+{9600000, DIF_BPF_COEFF3435,  0xf371060f},
+{9600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 96_quant.dat*/
+
+
+/*case 9700000:*/
+/* BEGIN - DIF BPF register values from 97_quant.dat*/
+{9700000, DIF_BPF_COEFF01,    0x00010001},
+{9700000, DIF_BPF_COEFF23,    0xfff9fff1},
+{9700000, DIF_BPF_COEFF45,    0x00090038},
+{9700000, DIF_BPF_COEFF67,    0x0025ffa7},
+{9700000, DIF_BPF_COEFF89,    0xff5e0012},
+{9700000, DIF_BPF_COEFF1011,  0x013200f0},
+{9700000, DIF_BPF_COEFF1213,  0xfee3fd9b},
+{9700000, DIF_BPF_COEFF1415,  0xffaa0331},
+{9700000, DIF_BPF_COEFF1617,  0x0311fe15},
+{9700000, DIF_BPF_COEFF1819,  0xfa60fe18},
+{9700000, DIF_BPF_COEFF2021,  0x05bd06d1},
+{9700000, DIF_BPF_COEFF2223,  0xfe1bf64a},
+{9700000, DIF_BPF_COEFF2425,  0xfafa07ae},
+{9700000, DIF_BPF_COEFF2627,  0x0b7effab},
+{9700000, DIF_BPF_COEFF2829,  0xf2d5f6d7},
+{9700000, DIF_BPF_COEFF3031,  0x07d30f7a},
+{9700000, DIF_BPF_COEFF3233,  0x02a3f194},
+{9700000, DIF_BPF_COEFF3435,  0xf32905dc},
+{9700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 97_quant.dat*/
+
+
+/*case 9800000:*/
+/* BEGIN - DIF BPF register values from 98_quant.dat*/
+{9800000, DIF_BPF_COEFF01,    0x00010002},
+{9800000, DIF_BPF_COEFF23,    0xfffcffee},
+{9800000, DIF_BPF_COEFF45,    0xfffb0032},
+{9800000, DIF_BPF_COEFF67,    0x003fffcd},
+{9800000, DIF_BPF_COEFF89,    0xff4effc1},
+{9800000, DIF_BPF_COEFF1011,  0x0106014a},
+{9800000, DIF_BPF_COEFF1213,  0xff6efd8a},
+{9800000, DIF_BPF_COEFF1415,  0xfedd02aa},
+{9800000, DIF_BPF_COEFF1617,  0x03b0ff34},
+{9800000, DIF_BPF_COEFF1819,  0xfa74fcd7},
+{9800000, DIF_BPF_COEFF2021,  0x04bf0781},
+{9800000, DIF_BPF_COEFF2223,  0xffaaf6a3},
+{9800000, DIF_BPF_COEFF2425,  0xf99e066b},
+{9800000, DIF_BPF_COEFF2627,  0x0bf90128},
+{9800000, DIF_BPF_COEFF2829,  0xf359f5e1},
+{9800000, DIF_BPF_COEFF3031,  0x06d20fa2},
+{9800000, DIF_BPF_COEFF3233,  0x0370f1e5},
+{9800000, DIF_BPF_COEFF3435,  0xf2e405a8},
+{9800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 98_quant.dat*/
+
+
+/*case 9900000:*/
+/* BEGIN - DIF BPF register values from 99_quant.dat*/
+{9900000, DIF_BPF_COEFF01,    0x00000003},
+{9900000, DIF_BPF_COEFF23,    0xffffffee},
+{9900000, DIF_BPF_COEFF45,    0xffef0024},
+{9900000, DIF_BPF_COEFF67,    0x0051fffa},
+{9900000, DIF_BPF_COEFF89,    0xff54ff77},
+{9900000, DIF_BPF_COEFF1011,  0x00be0184},
+{9900000, DIF_BPF_COEFF1213,  0x0006fdad},
+{9900000, DIF_BPF_COEFF1415,  0xfe2701f3},
+{9900000, DIF_BPF_COEFF1617,  0x0413005e},
+{9900000, DIF_BPF_COEFF1819,  0xfad1fbba},
+{9900000, DIF_BPF_COEFF2021,  0x039007ee},
+{9900000, DIF_BPF_COEFF2223,  0x013bf73d},
+{9900000, DIF_BPF_COEFF2425,  0xf868050a},
+{9900000, DIF_BPF_COEFF2627,  0x0c4302a1},
+{9900000, DIF_BPF_COEFF2829,  0xf3fdf4fe},
+{9900000, DIF_BPF_COEFF3031,  0x05c70fba},
+{9900000, DIF_BPF_COEFF3233,  0x043bf23c},
+{9900000, DIF_BPF_COEFF3435,  0xf2a10575},
+{9900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 99_quant.dat*/
+
+
+/*case 10000000:*/
+/* BEGIN - DIF BPF register values from 100_quant.dat*/
+{10000000, DIF_BPF_COEFF01,    0x00000003},
+{10000000, DIF_BPF_COEFF23,    0x0003fff1},
+{10000000, DIF_BPF_COEFF45,    0xffe50011},
+{10000000, DIF_BPF_COEFF67,    0x00570027},
+{10000000, DIF_BPF_COEFF89,    0xff70ff3c},
+{10000000, DIF_BPF_COEFF1011,  0x00620198},
+{10000000, DIF_BPF_COEFF1213,  0x009efe01},
+{10000000, DIF_BPF_COEFF1415,  0xfd95011a},
+{10000000, DIF_BPF_COEFF1617,  0x04350183},
+{10000000, DIF_BPF_COEFF1819,  0xfb71fad0},
+{10000000, DIF_BPF_COEFF2021,  0x023c0812},
+{10000000, DIF_BPF_COEFF2223,  0x02c3f811},
+{10000000, DIF_BPF_COEFF2425,  0xf75e0390},
+{10000000, DIF_BPF_COEFF2627,  0x0c5c0411},
+{10000000, DIF_BPF_COEFF2829,  0xf4c1f432},
+{10000000, DIF_BPF_COEFF3031,  0x04b30fc1},
+{10000000, DIF_BPF_COEFF3233,  0x0503f297},
+{10000000, DIF_BPF_COEFF3435,  0xf2610541},
+{10000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 100_quant.dat*/
+
+
+/*case 10100000:*/
+/* BEGIN - DIF BPF register values from 101_quant.dat*/
+{10100000, DIF_BPF_COEFF01,    0x00000003},
+{10100000, DIF_BPF_COEFF23,    0x0006fff7},
+{10100000, DIF_BPF_COEFF45,    0xffdffffc},
+{10100000, DIF_BPF_COEFF67,    0x00510050},
+{10100000, DIF_BPF_COEFF89,    0xff9dff18},
+{10100000, DIF_BPF_COEFF1011,  0xfffc0184},
+{10100000, DIF_BPF_COEFF1213,  0x0128fe80},
+{10100000, DIF_BPF_COEFF1415,  0xfd32002e},
+{10100000, DIF_BPF_COEFF1617,  0x04130292},
+{10100000, DIF_BPF_COEFF1819,  0xfc4dfa21},
+{10100000, DIF_BPF_COEFF2021,  0x00d107ee},
+{10100000, DIF_BPF_COEFF2223,  0x0435f91c},
+{10100000, DIF_BPF_COEFF2425,  0xf6850205},
+{10100000, DIF_BPF_COEFF2627,  0x0c430573},
+{10100000, DIF_BPF_COEFF2829,  0xf5a1f37d},
+{10100000, DIF_BPF_COEFF3031,  0x03990fba},
+{10100000, DIF_BPF_COEFF3233,  0x05c7f2f8},
+{10100000, DIF_BPF_COEFF3435,  0xf222050d},
+{10100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 101_quant.dat*/
+
+
+/*case 10200000:*/
+/* BEGIN - DIF BPF register values from 102_quant.dat*/
+{10200000, DIF_BPF_COEFF01,    0x00000002},
+{10200000, DIF_BPF_COEFF23,    0x0008fffe},
+{10200000, DIF_BPF_COEFF45,    0xffdfffe7},
+{10200000, DIF_BPF_COEFF67,    0x003f006e},
+{10200000, DIF_BPF_COEFF89,    0xffd6ff0f},
+{10200000, DIF_BPF_COEFF1011,  0xff96014a},
+{10200000, DIF_BPF_COEFF1213,  0x0197ff1f},
+{10200000, DIF_BPF_COEFF1415,  0xfd05ff3e},
+{10200000, DIF_BPF_COEFF1617,  0x03b0037c},
+{10200000, DIF_BPF_COEFF1819,  0xfd59f9b7},
+{10200000, DIF_BPF_COEFF2021,  0xff5d0781},
+{10200000, DIF_BPF_COEFF2223,  0x0585fa56},
+{10200000, DIF_BPF_COEFF2425,  0xf5e4006f},
+{10200000, DIF_BPF_COEFF2627,  0x0bf906c4},
+{10200000, DIF_BPF_COEFF2829,  0xf69df2e0},
+{10200000, DIF_BPF_COEFF3031,  0x02790fa2},
+{10200000, DIF_BPF_COEFF3233,  0x0688f35d},
+{10200000, DIF_BPF_COEFF3435,  0xf1e604d8},
+{10200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 102_quant.dat*/
+
+
+/*case 10300000:*/
+/* BEGIN - DIF BPF register values from 103_quant.dat*/
+{10300000, DIF_BPF_COEFF01,    0xffff0001},
+{10300000, DIF_BPF_COEFF23,    0x00090005},
+{10300000, DIF_BPF_COEFF45,    0xffe4ffd6},
+{10300000, DIF_BPF_COEFF67,    0x0025007e},
+{10300000, DIF_BPF_COEFF89,    0x0014ff20},
+{10300000, DIF_BPF_COEFF1011,  0xff3c00f0},
+{10300000, DIF_BPF_COEFF1213,  0x01e1ffd0},
+{10300000, DIF_BPF_COEFF1415,  0xfd12fe5c},
+{10300000, DIF_BPF_COEFF1617,  0x03110433},
+{10300000, DIF_BPF_COEFF1819,  0xfe88f996},
+{10300000, DIF_BPF_COEFF2021,  0xfdf106d1},
+{10300000, DIF_BPF_COEFF2223,  0x06aafbb7},
+{10300000, DIF_BPF_COEFF2425,  0xf57efed8},
+{10300000, DIF_BPF_COEFF2627,  0x0b7e07ff},
+{10300000, DIF_BPF_COEFF2829,  0xf7b0f25e},
+{10300000, DIF_BPF_COEFF3031,  0x01560f7a},
+{10300000, DIF_BPF_COEFF3233,  0x0745f3c7},
+{10300000, DIF_BPF_COEFF3435,  0xf1ac04a4},
+{10300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 103_quant.dat*/
+
+
+/*case 10400000:*/
+/* BEGIN - DIF BPF register values from 104_quant.dat*/
+{10400000, DIF_BPF_COEFF01,    0xffffffff},
+{10400000, DIF_BPF_COEFF23,    0x0008000c},
+{10400000, DIF_BPF_COEFF45,    0xffedffcb},
+{10400000, DIF_BPF_COEFF67,    0x0005007d},
+{10400000, DIF_BPF_COEFF89,    0x0050ff4c},
+{10400000, DIF_BPF_COEFF1011,  0xfef6007e},
+{10400000, DIF_BPF_COEFF1213,  0x01ff0086},
+{10400000, DIF_BPF_COEFF1415,  0xfd58fd97},
+{10400000, DIF_BPF_COEFF1617,  0x024104ad},
+{10400000, DIF_BPF_COEFF1819,  0xffcaf9c0},
+{10400000, DIF_BPF_COEFF2021,  0xfc9905e2},
+{10400000, DIF_BPF_COEFF2223,  0x079afd35},
+{10400000, DIF_BPF_COEFF2425,  0xf555fd46},
+{10400000, DIF_BPF_COEFF2627,  0x0ad50920},
+{10400000, DIF_BPF_COEFF2829,  0xf8d9f1f6},
+{10400000, DIF_BPF_COEFF3031,  0x00310f43},
+{10400000, DIF_BPF_COEFF3233,  0x07fdf435},
+{10400000, DIF_BPF_COEFF3435,  0xf174046f},
+{10400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 104_quant.dat*/
+
+
+/*case 10500000:*/
+/* BEGIN - DIF BPF register values from 105_quant.dat*/
+{10500000, DIF_BPF_COEFF01,    0xfffffffe},
+{10500000, DIF_BPF_COEFF23,    0x00050011},
+{10500000, DIF_BPF_COEFF45,    0xfffaffc8},
+{10500000, DIF_BPF_COEFF67,    0xffe5006b},
+{10500000, DIF_BPF_COEFF89,    0x0082ff8c},
+{10500000, DIF_BPF_COEFF1011,  0xfecc0000},
+{10500000, DIF_BPF_COEFF1213,  0x01f00130},
+{10500000, DIF_BPF_COEFF1415,  0xfdd2fcfc},
+{10500000, DIF_BPF_COEFF1617,  0x014d04e3},
+{10500000, DIF_BPF_COEFF1819,  0x010efa32},
+{10500000, DIF_BPF_COEFF2021,  0xfb6404bf},
+{10500000, DIF_BPF_COEFF2223,  0x084efec5},
+{10500000, DIF_BPF_COEFF2425,  0xf569fbc2},
+{10500000, DIF_BPF_COEFF2627,  0x0a000a23},
+{10500000, DIF_BPF_COEFF2829,  0xfa15f1ab},
+{10500000, DIF_BPF_COEFF3031,  0xff0b0efc},
+{10500000, DIF_BPF_COEFF3233,  0x08b0f4a7},
+{10500000, DIF_BPF_COEFF3435,  0xf13f043a},
+{10500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 105_quant.dat*/
+
+
+/*case 10600000:*/
+/* BEGIN - DIF BPF register values from 106_quant.dat*/
+{10600000, DIF_BPF_COEFF01,    0x0000fffd},
+{10600000, DIF_BPF_COEFF23,    0x00020012},
+{10600000, DIF_BPF_COEFF45,    0x0007ffcd},
+{10600000, DIF_BPF_COEFF67,    0xffc9004c},
+{10600000, DIF_BPF_COEFF89,    0x00a4ffd9},
+{10600000, DIF_BPF_COEFF1011,  0xfec3ff82},
+{10600000, DIF_BPF_COEFF1213,  0x01b401c1},
+{10600000, DIF_BPF_COEFF1415,  0xfe76fc97},
+{10600000, DIF_BPF_COEFF1617,  0x004404d2},
+{10600000, DIF_BPF_COEFF1819,  0x0245fae8},
+{10600000, DIF_BPF_COEFF2021,  0xfa5f0370},
+{10600000, DIF_BPF_COEFF2223,  0x08c1005f},
+{10600000, DIF_BPF_COEFF2425,  0xf5bcfa52},
+{10600000, DIF_BPF_COEFF2627,  0x09020b04},
+{10600000, DIF_BPF_COEFF2829,  0xfb60f17b},
+{10600000, DIF_BPF_COEFF3031,  0xfde70ea6},
+{10600000, DIF_BPF_COEFF3233,  0x095df51e},
+{10600000, DIF_BPF_COEFF3435,  0xf10c0405},
+{10600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 106_quant.dat*/
+
+
+/*case 10700000:*/
+/* BEGIN - DIF BPF register values from 107_quant.dat*/
+{10700000, DIF_BPF_COEFF01,    0x0000fffd},
+{10700000, DIF_BPF_COEFF23,    0xffff0011},
+{10700000, DIF_BPF_COEFF45,    0x0014ffdb},
+{10700000, DIF_BPF_COEFF67,    0xffb40023},
+{10700000, DIF_BPF_COEFF89,    0x00b2002a},
+{10700000, DIF_BPF_COEFF1011,  0xfedbff10},
+{10700000, DIF_BPF_COEFF1213,  0x0150022d},
+{10700000, DIF_BPF_COEFF1415,  0xff38fc6f},
+{10700000, DIF_BPF_COEFF1617,  0xff36047b},
+{10700000, DIF_BPF_COEFF1819,  0x035efbda},
+{10700000, DIF_BPF_COEFF2021,  0xf9940202},
+{10700000, DIF_BPF_COEFF2223,  0x08ee01f5},
+{10700000, DIF_BPF_COEFF2425,  0xf649f8fe},
+{10700000, DIF_BPF_COEFF2627,  0x07e10bc2},
+{10700000, DIF_BPF_COEFF2829,  0xfcb6f169},
+{10700000, DIF_BPF_COEFF3031,  0xfcc60e42},
+{10700000, DIF_BPF_COEFF3233,  0x0a04f599},
+{10700000, DIF_BPF_COEFF3435,  0xf0db03d0},
+{10700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 107_quant.dat*/
+
+
+/*case 10800000:*/
+/* BEGIN - DIF BPF register values from 108_quant.dat*/
+{10800000, DIF_BPF_COEFF01,    0x0000fffd},
+{10800000, DIF_BPF_COEFF23,    0xfffb000d},
+{10800000, DIF_BPF_COEFF45,    0x001dffed},
+{10800000, DIF_BPF_COEFF67,    0xffaafff5},
+{10800000, DIF_BPF_COEFF89,    0x00aa0077},
+{10800000, DIF_BPF_COEFF1011,  0xff13feb6},
+{10800000, DIF_BPF_COEFF1213,  0x00ce026b},
+{10800000, DIF_BPF_COEFF1415,  0x000afc85},
+{10800000, DIF_BPF_COEFF1617,  0xfe3503e3},
+{10800000, DIF_BPF_COEFF1819,  0x044cfcfb},
+{10800000, DIF_BPF_COEFF2021,  0xf90c0082},
+{10800000, DIF_BPF_COEFF2223,  0x08d5037f},
+{10800000, DIF_BPF_COEFF2425,  0xf710f7cc},
+{10800000, DIF_BPF_COEFF2627,  0x069f0c59},
+{10800000, DIF_BPF_COEFF2829,  0xfe16f173},
+{10800000, DIF_BPF_COEFF3031,  0xfbaa0dcf},
+{10800000, DIF_BPF_COEFF3233,  0x0aa5f617},
+{10800000, DIF_BPF_COEFF3435,  0xf0ad039b},
+{10800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 108_quant.dat*/
+
+
+/*case 10900000:*/
+/* BEGIN - DIF BPF register values from 109_quant.dat*/
+{10900000, DIF_BPF_COEFF01,    0x0000fffe},
+{10900000, DIF_BPF_COEFF23,    0xfff90006},
+{10900000, DIF_BPF_COEFF45,    0x00210003},
+{10900000, DIF_BPF_COEFF67,    0xffacffc8},
+{10900000, DIF_BPF_COEFF89,    0x008e00b6},
+{10900000, DIF_BPF_COEFF1011,  0xff63fe7c},
+{10900000, DIF_BPF_COEFF1213,  0x003a0275},
+{10900000, DIF_BPF_COEFF1415,  0x00dafcda},
+{10900000, DIF_BPF_COEFF1617,  0xfd510313},
+{10900000, DIF_BPF_COEFF1819,  0x0501fe40},
+{10900000, DIF_BPF_COEFF2021,  0xf8cbfefd},
+{10900000, DIF_BPF_COEFF2223,  0x087604f0},
+{10900000, DIF_BPF_COEFF2425,  0xf80af6c2},
+{10900000, DIF_BPF_COEFF2627,  0x05430cc8},
+{10900000, DIF_BPF_COEFF2829,  0xff7af19a},
+{10900000, DIF_BPF_COEFF3031,  0xfa940d4e},
+{10900000, DIF_BPF_COEFF3233,  0x0b3ff699},
+{10900000, DIF_BPF_COEFF3435,  0xf0810365},
+{10900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 109_quant.dat*/
+
+
+/*case 11000000:*/
+/* BEGIN - DIF BPF register values from 110_quant.dat*/
+{11000000, DIF_BPF_COEFF01,    0x0001ffff},
+{11000000, DIF_BPF_COEFF23,    0xfff8ffff},
+{11000000, DIF_BPF_COEFF45,    0x00210018},
+{11000000, DIF_BPF_COEFF67,    0xffbaffa3},
+{11000000, DIF_BPF_COEFF89,    0x006000e1},
+{11000000, DIF_BPF_COEFF1011,  0xffc4fe68},
+{11000000, DIF_BPF_COEFF1213,  0xffa0024b},
+{11000000, DIF_BPF_COEFF1415,  0x019afd66},
+{11000000, DIF_BPF_COEFF1617,  0xfc990216},
+{11000000, DIF_BPF_COEFF1819,  0x0575ff99},
+{11000000, DIF_BPF_COEFF2021,  0xf8d4fd81},
+{11000000, DIF_BPF_COEFF2223,  0x07d40640},
+{11000000, DIF_BPF_COEFF2425,  0xf932f5e6},
+{11000000, DIF_BPF_COEFF2627,  0x03d20d0d},
+{11000000, DIF_BPF_COEFF2829,  0x00dff1de},
+{11000000, DIF_BPF_COEFF3031,  0xf9860cbf},
+{11000000, DIF_BPF_COEFF3233,  0x0bd1f71e},
+{11000000, DIF_BPF_COEFF3435,  0xf058032f},
+{11000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 110_quant.dat*/
+
+
+/*case 11100000:*/
+/* BEGIN - DIF BPF register values from 111_quant.dat*/
+{11100000, DIF_BPF_COEFF01,    0x00010000},
+{11100000, DIF_BPF_COEFF23,    0xfff8fff8},
+{11100000, DIF_BPF_COEFF45,    0x001b0029},
+{11100000, DIF_BPF_COEFF67,    0xffd1ff8a},
+{11100000, DIF_BPF_COEFF89,    0x002600f2},
+{11100000, DIF_BPF_COEFF1011,  0x002cfe7c},
+{11100000, DIF_BPF_COEFF1213,  0xff0f01f0},
+{11100000, DIF_BPF_COEFF1415,  0x023bfe20},
+{11100000, DIF_BPF_COEFF1617,  0xfc1700fa},
+{11100000, DIF_BPF_COEFF1819,  0x05a200f7},
+{11100000, DIF_BPF_COEFF2021,  0xf927fc1c},
+{11100000, DIF_BPF_COEFF2223,  0x06f40765},
+{11100000, DIF_BPF_COEFF2425,  0xfa82f53b},
+{11100000, DIF_BPF_COEFF2627,  0x02510d27},
+{11100000, DIF_BPF_COEFF2829,  0x0243f23d},
+{11100000, DIF_BPF_COEFF3031,  0xf8810c24},
+{11100000, DIF_BPF_COEFF3233,  0x0c5cf7a7},
+{11100000, DIF_BPF_COEFF3435,  0xf03102fa},
+{11100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 111_quant.dat*/
+
+
+/*case 11200000:*/
+/* BEGIN - DIF BPF register values from 112_quant.dat*/
+{11200000, DIF_BPF_COEFF01,    0x00010002},
+{11200000, DIF_BPF_COEFF23,    0xfffafff2},
+{11200000, DIF_BPF_COEFF45,    0x00110035},
+{11200000, DIF_BPF_COEFF67,    0xfff0ff81},
+{11200000, DIF_BPF_COEFF89,    0xffe700e7},
+{11200000, DIF_BPF_COEFF1011,  0x008ffeb6},
+{11200000, DIF_BPF_COEFF1213,  0xfe94016d},
+{11200000, DIF_BPF_COEFF1415,  0x02b0fefb},
+{11200000, DIF_BPF_COEFF1617,  0xfbd3ffd1},
+{11200000, DIF_BPF_COEFF1819,  0x05850249},
+{11200000, DIF_BPF_COEFF2021,  0xf9c1fadb},
+{11200000, DIF_BPF_COEFF2223,  0x05de0858},
+{11200000, DIF_BPF_COEFF2425,  0xfbf2f4c4},
+{11200000, DIF_BPF_COEFF2627,  0x00c70d17},
+{11200000, DIF_BPF_COEFF2829,  0x03a0f2b8},
+{11200000, DIF_BPF_COEFF3031,  0xf7870b7c},
+{11200000, DIF_BPF_COEFF3233,  0x0cdff833},
+{11200000, DIF_BPF_COEFF3435,  0xf00d02c4},
+{11200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 112_quant.dat*/
+
+
+/*case 11300000:*/
+/* BEGIN - DIF BPF register values from 113_quant.dat*/
+{11300000, DIF_BPF_COEFF01,    0x00000003},
+{11300000, DIF_BPF_COEFF23,    0xfffdffee},
+{11300000, DIF_BPF_COEFF45,    0x00040038},
+{11300000, DIF_BPF_COEFF67,    0x0010ff88},
+{11300000, DIF_BPF_COEFF89,    0xffac00c2},
+{11300000, DIF_BPF_COEFF1011,  0x00e2ff10},
+{11300000, DIF_BPF_COEFF1213,  0xfe3900cb},
+{11300000, DIF_BPF_COEFF1415,  0x02f1ffe9},
+{11300000, DIF_BPF_COEFF1617,  0xfbd3feaa},
+{11300000, DIF_BPF_COEFF1819,  0x05210381},
+{11300000, DIF_BPF_COEFF2021,  0xfa9cf9c8},
+{11300000, DIF_BPF_COEFF2223,  0x04990912},
+{11300000, DIF_BPF_COEFF2425,  0xfd7af484},
+{11300000, DIF_BPF_COEFF2627,  0xff390cdb},
+{11300000, DIF_BPF_COEFF2829,  0x04f4f34d},
+{11300000, DIF_BPF_COEFF3031,  0xf69a0ac9},
+{11300000, DIF_BPF_COEFF3233,  0x0d5af8c1},
+{11300000, DIF_BPF_COEFF3435,  0xefec028e},
+{11300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 113_quant.dat*/
+
+
+/*case 11400000:*/
+/* BEGIN - DIF BPF register values from 114_quant.dat*/
+{11400000, DIF_BPF_COEFF01,    0x00000003},
+{11400000, DIF_BPF_COEFF23,    0x0000ffee},
+{11400000, DIF_BPF_COEFF45,    0xfff60033},
+{11400000, DIF_BPF_COEFF67,    0x002fff9f},
+{11400000, DIF_BPF_COEFF89,    0xff7b0087},
+{11400000, DIF_BPF_COEFF1011,  0x011eff82},
+{11400000, DIF_BPF_COEFF1213,  0xfe080018},
+{11400000, DIF_BPF_COEFF1415,  0x02f900d8},
+{11400000, DIF_BPF_COEFF1617,  0xfc17fd96},
+{11400000, DIF_BPF_COEFF1819,  0x04790490},
+{11400000, DIF_BPF_COEFF2021,  0xfbadf8ed},
+{11400000, DIF_BPF_COEFF2223,  0x032f098e},
+{11400000, DIF_BPF_COEFF2425,  0xff10f47d},
+{11400000, DIF_BPF_COEFF2627,  0xfdaf0c75},
+{11400000, DIF_BPF_COEFF2829,  0x063cf3fc},
+{11400000, DIF_BPF_COEFF3031,  0xf5ba0a0b},
+{11400000, DIF_BPF_COEFF3233,  0x0dccf952},
+{11400000, DIF_BPF_COEFF3435,  0xefcd0258},
+{11400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 114_quant.dat*/
+
+
+/*case 11500000:*/
+/* BEGIN - DIF BPF register values from 115_quant.dat*/
+{11500000, DIF_BPF_COEFF01,    0x00000003},
+{11500000, DIF_BPF_COEFF23,    0x0004fff1},
+{11500000, DIF_BPF_COEFF45,    0xffea0026},
+{11500000, DIF_BPF_COEFF67,    0x0046ffc3},
+{11500000, DIF_BPF_COEFF89,    0xff5a003c},
+{11500000, DIF_BPF_COEFF1011,  0x013b0000},
+{11500000, DIF_BPF_COEFF1213,  0xfe04ff63},
+{11500000, DIF_BPF_COEFF1415,  0x02c801b8},
+{11500000, DIF_BPF_COEFF1617,  0xfc99fca6},
+{11500000, DIF_BPF_COEFF1819,  0x0397056a},
+{11500000, DIF_BPF_COEFF2021,  0xfcecf853},
+{11500000, DIF_BPF_COEFF2223,  0x01ad09c9},
+{11500000, DIF_BPF_COEFF2425,  0x00acf4ad},
+{11500000, DIF_BPF_COEFF2627,  0xfc2e0be7},
+{11500000, DIF_BPF_COEFF2829,  0x0773f4c2},
+{11500000, DIF_BPF_COEFF3031,  0xf4e90943},
+{11500000, DIF_BPF_COEFF3233,  0x0e35f9e6},
+{11500000, DIF_BPF_COEFF3435,  0xefb10221},
+{11500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 115_quant.dat*/
+
+
+/*case 11600000:*/
+/* BEGIN - DIF BPF register values from 116_quant.dat*/
+{11600000, DIF_BPF_COEFF01,    0x00000002},
+{11600000, DIF_BPF_COEFF23,    0x0007fff6},
+{11600000, DIF_BPF_COEFF45,    0xffe20014},
+{11600000, DIF_BPF_COEFF67,    0x0054ffee},
+{11600000, DIF_BPF_COEFF89,    0xff4effeb},
+{11600000, DIF_BPF_COEFF1011,  0x0137007e},
+{11600000, DIF_BPF_COEFF1213,  0xfe2efebb},
+{11600000, DIF_BPF_COEFF1415,  0x0260027a},
+{11600000, DIF_BPF_COEFF1617,  0xfd51fbe6},
+{11600000, DIF_BPF_COEFF1819,  0x02870605},
+{11600000, DIF_BPF_COEFF2021,  0xfe4af7fe},
+{11600000, DIF_BPF_COEFF2223,  0x001d09c1},
+{11600000, DIF_BPF_COEFF2425,  0x0243f515},
+{11600000, DIF_BPF_COEFF2627,  0xfabd0b32},
+{11600000, DIF_BPF_COEFF2829,  0x0897f59e},
+{11600000, DIF_BPF_COEFF3031,  0xf4280871},
+{11600000, DIF_BPF_COEFF3233,  0x0e95fa7c},
+{11600000, DIF_BPF_COEFF3435,  0xef9701eb},
+{11600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 116_quant.dat*/
+
+
+/*case 11700000:*/
+/* BEGIN - DIF BPF register values from 117_quant.dat*/
+{11700000, DIF_BPF_COEFF01,    0xffff0001},
+{11700000, DIF_BPF_COEFF23,    0x0008fffd},
+{11700000, DIF_BPF_COEFF45,    0xffdeffff},
+{11700000, DIF_BPF_COEFF67,    0x0056001d},
+{11700000, DIF_BPF_COEFF89,    0xff57ff9c},
+{11700000, DIF_BPF_COEFF1011,  0x011300f0},
+{11700000, DIF_BPF_COEFF1213,  0xfe82fe2e},
+{11700000, DIF_BPF_COEFF1415,  0x01ca0310},
+{11700000, DIF_BPF_COEFF1617,  0xfe35fb62},
+{11700000, DIF_BPF_COEFF1819,  0x0155065a},
+{11700000, DIF_BPF_COEFF2021,  0xffbaf7f2},
+{11700000, DIF_BPF_COEFF2223,  0xfe8c0977},
+{11700000, DIF_BPF_COEFF2425,  0x03cef5b2},
+{11700000, DIF_BPF_COEFF2627,  0xf9610a58},
+{11700000, DIF_BPF_COEFF2829,  0x09a5f68f},
+{11700000, DIF_BPF_COEFF3031,  0xf3790797},
+{11700000, DIF_BPF_COEFF3233,  0x0eebfb14},
+{11700000, DIF_BPF_COEFF3435,  0xef8001b5},
+{11700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 117_quant.dat*/
+
+
+/*case 11800000:*/
+/* BEGIN - DIF BPF register values from 118_quant.dat*/
+{11800000, DIF_BPF_COEFF01,    0xffff0000},
+{11800000, DIF_BPF_COEFF23,    0x00080004},
+{11800000, DIF_BPF_COEFF45,    0xffe0ffe9},
+{11800000, DIF_BPF_COEFF67,    0x004c0047},
+{11800000, DIF_BPF_COEFF89,    0xff75ff58},
+{11800000, DIF_BPF_COEFF1011,  0x00d1014a},
+{11800000, DIF_BPF_COEFF1213,  0xfef9fdc8},
+{11800000, DIF_BPF_COEFF1415,  0x0111036f},
+{11800000, DIF_BPF_COEFF1617,  0xff36fb21},
+{11800000, DIF_BPF_COEFF1819,  0x00120665},
+{11800000, DIF_BPF_COEFF2021,  0x012df82e},
+{11800000, DIF_BPF_COEFF2223,  0xfd0708ec},
+{11800000, DIF_BPF_COEFF2425,  0x0542f682},
+{11800000, DIF_BPF_COEFF2627,  0xf81f095c},
+{11800000, DIF_BPF_COEFF2829,  0x0a9af792},
+{11800000, DIF_BPF_COEFF3031,  0xf2db06b5},
+{11800000, DIF_BPF_COEFF3233,  0x0f38fbad},
+{11800000, DIF_BPF_COEFF3435,  0xef6c017e},
+{11800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 118_quant.dat*/
+
+
+/*case 11900000:*/
+/* BEGIN - DIF BPF register values from 119_quant.dat*/
+{11900000, DIF_BPF_COEFF01,    0xffffffff},
+{11900000, DIF_BPF_COEFF23,    0x0007000b},
+{11900000, DIF_BPF_COEFF45,    0xffe7ffd8},
+{11900000, DIF_BPF_COEFF67,    0x00370068},
+{11900000, DIF_BPF_COEFF89,    0xffa4ff28},
+{11900000, DIF_BPF_COEFF1011,  0x00790184},
+{11900000, DIF_BPF_COEFF1213,  0xff87fd91},
+{11900000, DIF_BPF_COEFF1415,  0x00430392},
+{11900000, DIF_BPF_COEFF1617,  0x0044fb26},
+{11900000, DIF_BPF_COEFF1819,  0xfece0626},
+{11900000, DIF_BPF_COEFF2021,  0x0294f8b2},
+{11900000, DIF_BPF_COEFF2223,  0xfb990825},
+{11900000, DIF_BPF_COEFF2425,  0x0698f77f},
+{11900000, DIF_BPF_COEFF2627,  0xf6fe0842},
+{11900000, DIF_BPF_COEFF2829,  0x0b73f8a7},
+{11900000, DIF_BPF_COEFF3031,  0xf25105cd},
+{11900000, DIF_BPF_COEFF3233,  0x0f7bfc48},
+{11900000, DIF_BPF_COEFF3435,  0xef5a0148},
+{11900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 119_quant.dat*/
+
+
+/*case 12000000:*/
+/* BEGIN - DIF BPF register values from 120_quant.dat*/
+{12000000, DIF_BPF_COEFF01,    0x0000fffe},
+{12000000, DIF_BPF_COEFF23,    0x00050010},
+{12000000, DIF_BPF_COEFF45,    0xfff2ffcc},
+{12000000, DIF_BPF_COEFF67,    0x001b007b},
+{12000000, DIF_BPF_COEFF89,    0xffdfff10},
+{12000000, DIF_BPF_COEFF1011,  0x00140198},
+{12000000, DIF_BPF_COEFF1213,  0x0020fd8e},
+{12000000, DIF_BPF_COEFF1415,  0xff710375},
+{12000000, DIF_BPF_COEFF1617,  0x014dfb73},
+{12000000, DIF_BPF_COEFF1819,  0xfd9a059f},
+{12000000, DIF_BPF_COEFF2021,  0x03e0f978},
+{12000000, DIF_BPF_COEFF2223,  0xfa4e0726},
+{12000000, DIF_BPF_COEFF2425,  0x07c8f8a7},
+{12000000, DIF_BPF_COEFF2627,  0xf600070c},
+{12000000, DIF_BPF_COEFF2829,  0x0c2ff9c9},
+{12000000, DIF_BPF_COEFF3031,  0xf1db04de},
+{12000000, DIF_BPF_COEFF3233,  0x0fb4fce5},
+{12000000, DIF_BPF_COEFF3435,  0xef4b0111},
+{12000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 120_quant.dat*/
+
+
+/*case 12100000:*/
+/* BEGIN - DIF BPF register values from 121_quant.dat*/
+{12100000, DIF_BPF_COEFF01,    0x0000fffd},
+{12100000, DIF_BPF_COEFF23,    0x00010012},
+{12100000, DIF_BPF_COEFF45,    0xffffffc8},
+{12100000, DIF_BPF_COEFF67,    0xfffb007e},
+{12100000, DIF_BPF_COEFF89,    0x001dff14},
+{12100000, DIF_BPF_COEFF1011,  0xffad0184},
+{12100000, DIF_BPF_COEFF1213,  0x00b7fdbe},
+{12100000, DIF_BPF_COEFF1415,  0xfea9031b},
+{12100000, DIF_BPF_COEFF1617,  0x0241fc01},
+{12100000, DIF_BPF_COEFF1819,  0xfc8504d6},
+{12100000, DIF_BPF_COEFF2021,  0x0504fa79},
+{12100000, DIF_BPF_COEFF2223,  0xf93005f6},
+{12100000, DIF_BPF_COEFF2425,  0x08caf9f2},
+{12100000, DIF_BPF_COEFF2627,  0xf52b05c0},
+{12100000, DIF_BPF_COEFF2829,  0x0ccbfaf9},
+{12100000, DIF_BPF_COEFF3031,  0xf17903eb},
+{12100000, DIF_BPF_COEFF3233,  0x0fe3fd83},
+{12100000, DIF_BPF_COEFF3435,  0xef3f00db},
+{12100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 121_quant.dat*/
+
+
+/*case 12200000:*/
+/* BEGIN - DIF BPF register values from 122_quant.dat*/
+{12200000, DIF_BPF_COEFF01,    0x0000fffd},
+{12200000, DIF_BPF_COEFF23,    0xfffe0011},
+{12200000, DIF_BPF_COEFF45,    0x000cffcc},
+{12200000, DIF_BPF_COEFF67,    0xffdb0071},
+{12200000, DIF_BPF_COEFF89,    0x0058ff32},
+{12200000, DIF_BPF_COEFF1011,  0xff4f014a},
+{12200000, DIF_BPF_COEFF1213,  0x013cfe1f},
+{12200000, DIF_BPF_COEFF1415,  0xfdfb028a},
+{12200000, DIF_BPF_COEFF1617,  0x0311fcc9},
+{12200000, DIF_BPF_COEFF1819,  0xfb9d03d6},
+{12200000, DIF_BPF_COEFF2021,  0x05f4fbad},
+{12200000, DIF_BPF_COEFF2223,  0xf848049d},
+{12200000, DIF_BPF_COEFF2425,  0x0999fb5b},
+{12200000, DIF_BPF_COEFF2627,  0xf4820461},
+{12200000, DIF_BPF_COEFF2829,  0x0d46fc32},
+{12200000, DIF_BPF_COEFF3031,  0xf12d02f4},
+{12200000, DIF_BPF_COEFF3233,  0x1007fe21},
+{12200000, DIF_BPF_COEFF3435,  0xef3600a4},
+{12200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 122_quant.dat*/
+
+
+/*case 12300000:*/
+/* BEGIN - DIF BPF register values from 123_quant.dat*/
+{12300000, DIF_BPF_COEFF01,    0x0000fffe},
+{12300000, DIF_BPF_COEFF23,    0xfffa000e},
+{12300000, DIF_BPF_COEFF45,    0x0017ffd9},
+{12300000, DIF_BPF_COEFF67,    0xffc10055},
+{12300000, DIF_BPF_COEFF89,    0x0088ff68},
+{12300000, DIF_BPF_COEFF1011,  0xff0400f0},
+{12300000, DIF_BPF_COEFF1213,  0x01a6fea7},
+{12300000, DIF_BPF_COEFF1415,  0xfd7501cc},
+{12300000, DIF_BPF_COEFF1617,  0x03b0fdc0},
+{12300000, DIF_BPF_COEFF1819,  0xfaef02a8},
+{12300000, DIF_BPF_COEFF2021,  0x06a7fd07},
+{12300000, DIF_BPF_COEFF2223,  0xf79d0326},
+{12300000, DIF_BPF_COEFF2425,  0x0a31fcda},
+{12300000, DIF_BPF_COEFF2627,  0xf40702f3},
+{12300000, DIF_BPF_COEFF2829,  0x0d9ffd72},
+{12300000, DIF_BPF_COEFF3031,  0xf0f601fa},
+{12300000, DIF_BPF_COEFF3233,  0x1021fec0},
+{12300000, DIF_BPF_COEFF3435,  0xef2f006d},
+{12300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 123_quant.dat*/
+
+
+/*case 12400000:*/
+/* BEGIN - DIF BPF register values from 124_quant.dat*/
+{12400000, DIF_BPF_COEFF01,    0x0001ffff},
+{12400000, DIF_BPF_COEFF23,    0xfff80007},
+{12400000, DIF_BPF_COEFF45,    0x001fffeb},
+{12400000, DIF_BPF_COEFF67,    0xffaf002d},
+{12400000, DIF_BPF_COEFF89,    0x00a8ffb0},
+{12400000, DIF_BPF_COEFF1011,  0xfed3007e},
+{12400000, DIF_BPF_COEFF1213,  0x01e9ff4c},
+{12400000, DIF_BPF_COEFF1415,  0xfd2000ee},
+{12400000, DIF_BPF_COEFF1617,  0x0413fed8},
+{12400000, DIF_BPF_COEFF1819,  0xfa82015c},
+{12400000, DIF_BPF_COEFF2021,  0x0715fe7d},
+{12400000, DIF_BPF_COEFF2223,  0xf7340198},
+{12400000, DIF_BPF_COEFF2425,  0x0a8dfe69},
+{12400000, DIF_BPF_COEFF2627,  0xf3bd017c},
+{12400000, DIF_BPF_COEFF2829,  0x0dd5feb8},
+{12400000, DIF_BPF_COEFF3031,  0xf0d500fd},
+{12400000, DIF_BPF_COEFF3233,  0x1031ff60},
+{12400000, DIF_BPF_COEFF3435,  0xef2b0037},
+{12400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 124_quant.dat*/
+
+
+/*case 12500000:*/
+/* BEGIN - DIF BPF register values from 125_quant.dat*/
+{12500000, DIF_BPF_COEFF01,    0x00010000},
+{12500000, DIF_BPF_COEFF23,    0xfff70000},
+{12500000, DIF_BPF_COEFF45,    0x00220000},
+{12500000, DIF_BPF_COEFF67,    0xffa90000},
+{12500000, DIF_BPF_COEFF89,    0x00b30000},
+{12500000, DIF_BPF_COEFF1011,  0xfec20000},
+{12500000, DIF_BPF_COEFF1213,  0x02000000},
+{12500000, DIF_BPF_COEFF1415,  0xfd030000},
+{12500000, DIF_BPF_COEFF1617,  0x04350000},
+{12500000, DIF_BPF_COEFF1819,  0xfa5e0000},
+{12500000, DIF_BPF_COEFF2021,  0x073b0000},
+{12500000, DIF_BPF_COEFF2223,  0xf7110000},
+{12500000, DIF_BPF_COEFF2425,  0x0aac0000},
+{12500000, DIF_BPF_COEFF2627,  0xf3a40000},
+{12500000, DIF_BPF_COEFF2829,  0x0de70000},
+{12500000, DIF_BPF_COEFF3031,  0xf0c90000},
+{12500000, DIF_BPF_COEFF3233,  0x10360000},
+{12500000, DIF_BPF_COEFF3435,  0xef290000},
+{12500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 125_quant.dat*/
+
+
+/*case 12600000:*/
+/* BEGIN - DIF BPF register values from 126_quant.dat*/
+{12600000, DIF_BPF_COEFF01,    0x00010001},
+{12600000, DIF_BPF_COEFF23,    0xfff8fff9},
+{12600000, DIF_BPF_COEFF45,    0x001f0015},
+{12600000, DIF_BPF_COEFF67,    0xffafffd3},
+{12600000, DIF_BPF_COEFF89,    0x00a80050},
+{12600000, DIF_BPF_COEFF1011,  0xfed3ff82},
+{12600000, DIF_BPF_COEFF1213,  0x01e900b4},
+{12600000, DIF_BPF_COEFF1415,  0xfd20ff12},
+{12600000, DIF_BPF_COEFF1617,  0x04130128},
+{12600000, DIF_BPF_COEFF1819,  0xfa82fea4},
+{12600000, DIF_BPF_COEFF2021,  0x07150183},
+{12600000, DIF_BPF_COEFF2223,  0xf734fe68},
+{12600000, DIF_BPF_COEFF2425,  0x0a8d0197},
+{12600000, DIF_BPF_COEFF2627,  0xf3bdfe84},
+{12600000, DIF_BPF_COEFF2829,  0x0dd50148},
+{12600000, DIF_BPF_COEFF3031,  0xf0d5ff03},
+{12600000, DIF_BPF_COEFF3233,  0x103100a0},
+{12600000, DIF_BPF_COEFF3435,  0xef2bffc9},
+{12600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 126_quant.dat*/
+
+
+/*case 12700000:*/
+/* BEGIN - DIF BPF register values from 127_quant.dat*/
+{12700000, DIF_BPF_COEFF01,    0x00000002},
+{12700000, DIF_BPF_COEFF23,    0xfffafff2},
+{12700000, DIF_BPF_COEFF45,    0x00170027},
+{12700000, DIF_BPF_COEFF67,    0xffc1ffab},
+{12700000, DIF_BPF_COEFF89,    0x00880098},
+{12700000, DIF_BPF_COEFF1011,  0xff04ff10},
+{12700000, DIF_BPF_COEFF1213,  0x01a60159},
+{12700000, DIF_BPF_COEFF1415,  0xfd75fe34},
+{12700000, DIF_BPF_COEFF1617,  0x03b00240},
+{12700000, DIF_BPF_COEFF1819,  0xfaeffd58},
+{12700000, DIF_BPF_COEFF2021,  0x06a702f9},
+{12700000, DIF_BPF_COEFF2223,  0xf79dfcda},
+{12700000, DIF_BPF_COEFF2425,  0x0a310326},
+{12700000, DIF_BPF_COEFF2627,  0xf407fd0d},
+{12700000, DIF_BPF_COEFF2829,  0x0d9f028e},
+{12700000, DIF_BPF_COEFF3031,  0xf0f6fe06},
+{12700000, DIF_BPF_COEFF3233,  0x10210140},
+{12700000, DIF_BPF_COEFF3435,  0xef2fff93},
+{12700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 127_quant.dat*/
+
+
+/*case 12800000:*/
+/* BEGIN - DIF BPF register values from 128_quant.dat*/
+{12800000, DIF_BPF_COEFF01,    0x00000003},
+{12800000, DIF_BPF_COEFF23,    0xfffeffef},
+{12800000, DIF_BPF_COEFF45,    0x000c0034},
+{12800000, DIF_BPF_COEFF67,    0xffdbff8f},
+{12800000, DIF_BPF_COEFF89,    0x005800ce},
+{12800000, DIF_BPF_COEFF1011,  0xff4ffeb6},
+{12800000, DIF_BPF_COEFF1213,  0x013c01e1},
+{12800000, DIF_BPF_COEFF1415,  0xfdfbfd76},
+{12800000, DIF_BPF_COEFF1617,  0x03110337},
+{12800000, DIF_BPF_COEFF1819,  0xfb9dfc2a},
+{12800000, DIF_BPF_COEFF2021,  0x05f40453},
+{12800000, DIF_BPF_COEFF2223,  0xf848fb63},
+{12800000, DIF_BPF_COEFF2425,  0x099904a5},
+{12800000, DIF_BPF_COEFF2627,  0xf482fb9f},
+{12800000, DIF_BPF_COEFF2829,  0x0d4603ce},
+{12800000, DIF_BPF_COEFF3031,  0xf12dfd0c},
+{12800000, DIF_BPF_COEFF3233,  0x100701df},
+{12800000, DIF_BPF_COEFF3435,  0xef36ff5c},
+{12800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 128_quant.dat*/
+
+
+/*case 12900000:*/
+/* BEGIN - DIF BPF register values from 129_quant.dat*/
+{12900000, DIF_BPF_COEFF01,    0x00000003},
+{12900000, DIF_BPF_COEFF23,    0x0001ffee},
+{12900000, DIF_BPF_COEFF45,    0xffff0038},
+{12900000, DIF_BPF_COEFF67,    0xfffbff82},
+{12900000, DIF_BPF_COEFF89,    0x001d00ec},
+{12900000, DIF_BPF_COEFF1011,  0xffadfe7c},
+{12900000, DIF_BPF_COEFF1213,  0x00b70242},
+{12900000, DIF_BPF_COEFF1415,  0xfea9fce5},
+{12900000, DIF_BPF_COEFF1617,  0x024103ff},
+{12900000, DIF_BPF_COEFF1819,  0xfc85fb2a},
+{12900000, DIF_BPF_COEFF2021,  0x05040587},
+{12900000, DIF_BPF_COEFF2223,  0xf930fa0a},
+{12900000, DIF_BPF_COEFF2425,  0x08ca060e},
+{12900000, DIF_BPF_COEFF2627,  0xf52bfa40},
+{12900000, DIF_BPF_COEFF2829,  0x0ccb0507},
+{12900000, DIF_BPF_COEFF3031,  0xf179fc15},
+{12900000, DIF_BPF_COEFF3233,  0x0fe3027d},
+{12900000, DIF_BPF_COEFF3435,  0xef3fff25},
+{12900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 129_quant.dat*/
+
+
+/*case 113000000:*/
+/* BEGIN - DIF BPF register values from 130_quant.dat*/
+{13000000, DIF_BPF_COEFF01,    0x00000002},
+{13000000, DIF_BPF_COEFF23,    0x0005fff0},
+{13000000, DIF_BPF_COEFF45,    0xfff20034},
+{13000000, DIF_BPF_COEFF67,    0x001bff85},
+{13000000, DIF_BPF_COEFF89,    0xffdf00f0},
+{13000000, DIF_BPF_COEFF1011,  0x0014fe68},
+{13000000, DIF_BPF_COEFF1213,  0x00200272},
+{13000000, DIF_BPF_COEFF1415,  0xff71fc8b},
+{13000000, DIF_BPF_COEFF1617,  0x014d048d},
+{13000000, DIF_BPF_COEFF1819,  0xfd9afa61},
+{13000000, DIF_BPF_COEFF2021,  0x03e00688},
+{13000000, DIF_BPF_COEFF2223,  0xfa4ef8da},
+{13000000, DIF_BPF_COEFF2425,  0x07c80759},
+{13000000, DIF_BPF_COEFF2627,  0xf600f8f4},
+{13000000, DIF_BPF_COEFF2829,  0x0c2f0637},
+{13000000, DIF_BPF_COEFF3031,  0xf1dbfb22},
+{13000000, DIF_BPF_COEFF3233,  0x0fb4031b},
+{13000000, DIF_BPF_COEFF3435,  0xef4bfeef},
+{13000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 130_quant.dat*/
+
+
+/*case 13100000:*/
+/* BEGIN - DIF BPF register values from 131_quant.dat*/
+{13100000, DIF_BPF_COEFF01,    0xffff0001},
+{13100000, DIF_BPF_COEFF23,    0x0007fff5},
+{13100000, DIF_BPF_COEFF45,    0xffe70028},
+{13100000, DIF_BPF_COEFF67,    0x0037ff98},
+{13100000, DIF_BPF_COEFF89,    0xffa400d8},
+{13100000, DIF_BPF_COEFF1011,  0x0079fe7c},
+{13100000, DIF_BPF_COEFF1213,  0xff87026f},
+{13100000, DIF_BPF_COEFF1415,  0x0043fc6e},
+{13100000, DIF_BPF_COEFF1617,  0x004404da},
+{13100000, DIF_BPF_COEFF1819,  0xfecef9da},
+{13100000, DIF_BPF_COEFF2021,  0x0294074e},
+{13100000, DIF_BPF_COEFF2223,  0xfb99f7db},
+{13100000, DIF_BPF_COEFF2425,  0x06980881},
+{13100000, DIF_BPF_COEFF2627,  0xf6fef7be},
+{13100000, DIF_BPF_COEFF2829,  0x0b730759},
+{13100000, DIF_BPF_COEFF3031,  0xf251fa33},
+{13100000, DIF_BPF_COEFF3233,  0x0f7b03b8},
+{13100000, DIF_BPF_COEFF3435,  0xef5afeb8},
+{13100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 131_quant.dat*/
+
+
+/*case 13200000:*/
+/* BEGIN - DIF BPF register values from 132_quant.dat*/
+{13200000, DIF_BPF_COEFF01,    0xffff0000},
+{13200000, DIF_BPF_COEFF23,    0x0008fffc},
+{13200000, DIF_BPF_COEFF45,    0xffe00017},
+{13200000, DIF_BPF_COEFF67,    0x004cffb9},
+{13200000, DIF_BPF_COEFF89,    0xff7500a8},
+{13200000, DIF_BPF_COEFF1011,  0x00d1feb6},
+{13200000, DIF_BPF_COEFF1213,  0xfef90238},
+{13200000, DIF_BPF_COEFF1415,  0x0111fc91},
+{13200000, DIF_BPF_COEFF1617,  0xff3604df},
+{13200000, DIF_BPF_COEFF1819,  0x0012f99b},
+{13200000, DIF_BPF_COEFF2021,  0x012d07d2},
+{13200000, DIF_BPF_COEFF2223,  0xfd07f714},
+{13200000, DIF_BPF_COEFF2425,  0x0542097e},
+{13200000, DIF_BPF_COEFF2627,  0xf81ff6a4},
+{13200000, DIF_BPF_COEFF2829,  0x0a9a086e},
+{13200000, DIF_BPF_COEFF3031,  0xf2dbf94b},
+{13200000, DIF_BPF_COEFF3233,  0x0f380453},
+{13200000, DIF_BPF_COEFF3435,  0xef6cfe82},
+{13200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 132_quant.dat*/
+
+
+/*case 13300000:*/
+/* BEGIN - DIF BPF register values from 133_quant.dat*/
+{13300000, DIF_BPF_COEFF01,    0xffffffff},
+{13300000, DIF_BPF_COEFF23,    0x00080003},
+{13300000, DIF_BPF_COEFF45,    0xffde0001},
+{13300000, DIF_BPF_COEFF67,    0x0056ffe3},
+{13300000, DIF_BPF_COEFF89,    0xff570064},
+{13300000, DIF_BPF_COEFF1011,  0x0113ff10},
+{13300000, DIF_BPF_COEFF1213,  0xfe8201d2},
+{13300000, DIF_BPF_COEFF1415,  0x01cafcf0},
+{13300000, DIF_BPF_COEFF1617,  0xfe35049e},
+{13300000, DIF_BPF_COEFF1819,  0x0155f9a6},
+{13300000, DIF_BPF_COEFF2021,  0xffba080e},
+{13300000, DIF_BPF_COEFF2223,  0xfe8cf689},
+{13300000, DIF_BPF_COEFF2425,  0x03ce0a4e},
+{13300000, DIF_BPF_COEFF2627,  0xf961f5a8},
+{13300000, DIF_BPF_COEFF2829,  0x09a50971},
+{13300000, DIF_BPF_COEFF3031,  0xf379f869},
+{13300000, DIF_BPF_COEFF3233,  0x0eeb04ec},
+{13300000, DIF_BPF_COEFF3435,  0xef80fe4b},
+{13300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 133_quant.dat*/
+
+
+/*case 13400000:*/
+/* BEGIN - DIF BPF register values from 134_quant.dat*/
+{13400000, DIF_BPF_COEFF01,    0x0000fffe},
+{13400000, DIF_BPF_COEFF23,    0x0007000a},
+{13400000, DIF_BPF_COEFF45,    0xffe2ffec},
+{13400000, DIF_BPF_COEFF67,    0x00540012},
+{13400000, DIF_BPF_COEFF89,    0xff4e0015},
+{13400000, DIF_BPF_COEFF1011,  0x0137ff82},
+{13400000, DIF_BPF_COEFF1213,  0xfe2e0145},
+{13400000, DIF_BPF_COEFF1415,  0x0260fd86},
+{13400000, DIF_BPF_COEFF1617,  0xfd51041a},
+{13400000, DIF_BPF_COEFF1819,  0x0287f9fb},
+{13400000, DIF_BPF_COEFF2021,  0xfe4a0802},
+{13400000, DIF_BPF_COEFF2223,  0x001df63f},
+{13400000, DIF_BPF_COEFF2425,  0x02430aeb},
+{13400000, DIF_BPF_COEFF2627,  0xfabdf4ce},
+{13400000, DIF_BPF_COEFF2829,  0x08970a62},
+{13400000, DIF_BPF_COEFF3031,  0xf428f78f},
+{13400000, DIF_BPF_COEFF3233,  0x0e950584},
+{13400000, DIF_BPF_COEFF3435,  0xef97fe15},
+{13400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 134_quant.dat*/
+
+
+/*case 13500000:*/
+/* BEGIN - DIF BPF register values from 135_quant.dat*/
+{13500000, DIF_BPF_COEFF01,    0x0000fffd},
+{13500000, DIF_BPF_COEFF23,    0x0004000f},
+{13500000, DIF_BPF_COEFF45,    0xffeaffda},
+{13500000, DIF_BPF_COEFF67,    0x0046003d},
+{13500000, DIF_BPF_COEFF89,    0xff5affc4},
+{13500000, DIF_BPF_COEFF1011,  0x013b0000},
+{13500000, DIF_BPF_COEFF1213,  0xfe04009d},
+{13500000, DIF_BPF_COEFF1415,  0x02c8fe48},
+{13500000, DIF_BPF_COEFF1617,  0xfc99035a},
+{13500000, DIF_BPF_COEFF1819,  0x0397fa96},
+{13500000, DIF_BPF_COEFF2021,  0xfcec07ad},
+{13500000, DIF_BPF_COEFF2223,  0x01adf637},
+{13500000, DIF_BPF_COEFF2425,  0x00ac0b53},
+{13500000, DIF_BPF_COEFF2627,  0xfc2ef419},
+{13500000, DIF_BPF_COEFF2829,  0x07730b3e},
+{13500000, DIF_BPF_COEFF3031,  0xf4e9f6bd},
+{13500000, DIF_BPF_COEFF3233,  0x0e35061a},
+{13500000, DIF_BPF_COEFF3435,  0xefb1fddf},
+{13500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 135_quant.dat*/
+
+
+/*case 13600000:*/
+/* BEGIN - DIF BPF register values from 136_quant.dat*/
+{13600000, DIF_BPF_COEFF01,    0x0000fffd},
+{13600000, DIF_BPF_COEFF23,    0x00000012},
+{13600000, DIF_BPF_COEFF45,    0xfff6ffcd},
+{13600000, DIF_BPF_COEFF67,    0x002f0061},
+{13600000, DIF_BPF_COEFF89,    0xff7bff79},
+{13600000, DIF_BPF_COEFF1011,  0x011e007e},
+{13600000, DIF_BPF_COEFF1213,  0xfe08ffe8},
+{13600000, DIF_BPF_COEFF1415,  0x02f9ff28},
+{13600000, DIF_BPF_COEFF1617,  0xfc17026a},
+{13600000, DIF_BPF_COEFF1819,  0x0479fb70},
+{13600000, DIF_BPF_COEFF2021,  0xfbad0713},
+{13600000, DIF_BPF_COEFF2223,  0x032ff672},
+{13600000, DIF_BPF_COEFF2425,  0xff100b83},
+{13600000, DIF_BPF_COEFF2627,  0xfdaff38b},
+{13600000, DIF_BPF_COEFF2829,  0x063c0c04},
+{13600000, DIF_BPF_COEFF3031,  0xf5baf5f5},
+{13600000, DIF_BPF_COEFF3233,  0x0dcc06ae},
+{13600000, DIF_BPF_COEFF3435,  0xefcdfda8},
+{13600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 136_quant.dat*/
+
+
+/*case 13700000:*/
+/* BEGIN - DIF BPF register values from 137_quant.dat*/
+{13700000, DIF_BPF_COEFF01,    0x0000fffd},
+{13700000, DIF_BPF_COEFF23,    0xfffd0012},
+{13700000, DIF_BPF_COEFF45,    0x0004ffc8},
+{13700000, DIF_BPF_COEFF67,    0x00100078},
+{13700000, DIF_BPF_COEFF89,    0xffacff3e},
+{13700000, DIF_BPF_COEFF1011,  0x00e200f0},
+{13700000, DIF_BPF_COEFF1213,  0xfe39ff35},
+{13700000, DIF_BPF_COEFF1415,  0x02f10017},
+{13700000, DIF_BPF_COEFF1617,  0xfbd30156},
+{13700000, DIF_BPF_COEFF1819,  0x0521fc7f},
+{13700000, DIF_BPF_COEFF2021,  0xfa9c0638},
+{13700000, DIF_BPF_COEFF2223,  0x0499f6ee},
+{13700000, DIF_BPF_COEFF2425,  0xfd7a0b7c},
+{13700000, DIF_BPF_COEFF2627,  0xff39f325},
+{13700000, DIF_BPF_COEFF2829,  0x04f40cb3},
+{13700000, DIF_BPF_COEFF3031,  0xf69af537},
+{13700000, DIF_BPF_COEFF3233,  0x0d5a073f},
+{13700000, DIF_BPF_COEFF3435,  0xefecfd72},
+{13700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 137_quant.dat*/
+
+
+/*case 13800000:*/
+/* BEGIN - DIF BPF register values from 138_quant.dat*/
+{13800000, DIF_BPF_COEFF01,    0x0001fffe},
+{13800000, DIF_BPF_COEFF23,    0xfffa000e},
+{13800000, DIF_BPF_COEFF45,    0x0011ffcb},
+{13800000, DIF_BPF_COEFF67,    0xfff0007f},
+{13800000, DIF_BPF_COEFF89,    0xffe7ff19},
+{13800000, DIF_BPF_COEFF1011,  0x008f014a},
+{13800000, DIF_BPF_COEFF1213,  0xfe94fe93},
+{13800000, DIF_BPF_COEFF1415,  0x02b00105},
+{13800000, DIF_BPF_COEFF1617,  0xfbd3002f},
+{13800000, DIF_BPF_COEFF1819,  0x0585fdb7},
+{13800000, DIF_BPF_COEFF2021,  0xf9c10525},
+{13800000, DIF_BPF_COEFF2223,  0x05def7a8},
+{13800000, DIF_BPF_COEFF2425,  0xfbf20b3c},
+{13800000, DIF_BPF_COEFF2627,  0x00c7f2e9},
+{13800000, DIF_BPF_COEFF2829,  0x03a00d48},
+{13800000, DIF_BPF_COEFF3031,  0xf787f484},
+{13800000, DIF_BPF_COEFF3233,  0x0cdf07cd},
+{13800000, DIF_BPF_COEFF3435,  0xf00dfd3c},
+{13800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 138_quant.dat*/
+
+
+/*case 13900000:*/
+/* BEGIN - DIF BPF register values from 139_quant.dat*/
+{13900000, DIF_BPF_COEFF01,    0x00010000},
+{13900000, DIF_BPF_COEFF23,    0xfff80008},
+{13900000, DIF_BPF_COEFF45,    0x001bffd7},
+{13900000, DIF_BPF_COEFF67,    0xffd10076},
+{13900000, DIF_BPF_COEFF89,    0x0026ff0e},
+{13900000, DIF_BPF_COEFF1011,  0x002c0184},
+{13900000, DIF_BPF_COEFF1213,  0xff0ffe10},
+{13900000, DIF_BPF_COEFF1415,  0x023b01e0},
+{13900000, DIF_BPF_COEFF1617,  0xfc17ff06},
+{13900000, DIF_BPF_COEFF1819,  0x05a2ff09},
+{13900000, DIF_BPF_COEFF2021,  0xf92703e4},
+{13900000, DIF_BPF_COEFF2223,  0x06f4f89b},
+{13900000, DIF_BPF_COEFF2425,  0xfa820ac5},
+{13900000, DIF_BPF_COEFF2627,  0x0251f2d9},
+{13900000, DIF_BPF_COEFF2829,  0x02430dc3},
+{13900000, DIF_BPF_COEFF3031,  0xf881f3dc},
+{13900000, DIF_BPF_COEFF3233,  0x0c5c0859},
+{13900000, DIF_BPF_COEFF3435,  0xf031fd06},
+{13900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 139_quant.dat*/
+
+
+/*case 14000000:*/
+/* BEGIN - DIF BPF register values from 140_quant.dat*/
+{14000000, DIF_BPF_COEFF01,    0x00010001},
+{14000000, DIF_BPF_COEFF23,    0xfff80001},
+{14000000, DIF_BPF_COEFF45,    0x0021ffe8},
+{14000000, DIF_BPF_COEFF67,    0xffba005d},
+{14000000, DIF_BPF_COEFF89,    0x0060ff1f},
+{14000000, DIF_BPF_COEFF1011,  0xffc40198},
+{14000000, DIF_BPF_COEFF1213,  0xffa0fdb5},
+{14000000, DIF_BPF_COEFF1415,  0x019a029a},
+{14000000, DIF_BPF_COEFF1617,  0xfc99fdea},
+{14000000, DIF_BPF_COEFF1819,  0x05750067},
+{14000000, DIF_BPF_COEFF2021,  0xf8d4027f},
+{14000000, DIF_BPF_COEFF2223,  0x07d4f9c0},
+{14000000, DIF_BPF_COEFF2425,  0xf9320a1a},
+{14000000, DIF_BPF_COEFF2627,  0x03d2f2f3},
+{14000000, DIF_BPF_COEFF2829,  0x00df0e22},
+{14000000, DIF_BPF_COEFF3031,  0xf986f341},
+{14000000, DIF_BPF_COEFF3233,  0x0bd108e2},
+{14000000, DIF_BPF_COEFF3435,  0xf058fcd1},
+{14000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 140_quant.dat*/
+
+
+/*case 14100000:*/
+/* BEGIN - DIF BPF register values from 141_quant.dat*/
+{14100000, DIF_BPF_COEFF01,    0x00000002},
+{14100000, DIF_BPF_COEFF23,    0xfff9fffa},
+{14100000, DIF_BPF_COEFF45,    0x0021fffd},
+{14100000, DIF_BPF_COEFF67,    0xffac0038},
+{14100000, DIF_BPF_COEFF89,    0x008eff4a},
+{14100000, DIF_BPF_COEFF1011,  0xff630184},
+{14100000, DIF_BPF_COEFF1213,  0x003afd8b},
+{14100000, DIF_BPF_COEFF1415,  0x00da0326},
+{14100000, DIF_BPF_COEFF1617,  0xfd51fced},
+{14100000, DIF_BPF_COEFF1819,  0x050101c0},
+{14100000, DIF_BPF_COEFF2021,  0xf8cb0103},
+{14100000, DIF_BPF_COEFF2223,  0x0876fb10},
+{14100000, DIF_BPF_COEFF2425,  0xf80a093e},
+{14100000, DIF_BPF_COEFF2627,  0x0543f338},
+{14100000, DIF_BPF_COEFF2829,  0xff7a0e66},
+{14100000, DIF_BPF_COEFF3031,  0xfa94f2b2},
+{14100000, DIF_BPF_COEFF3233,  0x0b3f0967},
+{14100000, DIF_BPF_COEFF3435,  0xf081fc9b},
+{14100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 141_quant.dat*/
+
+
+/*case 14200000:*/
+/* BEGIN - DIF BPF register values from 142_quant.dat*/
+{14200000, DIF_BPF_COEFF01,    0x00000003},
+{14200000, DIF_BPF_COEFF23,    0xfffbfff3},
+{14200000, DIF_BPF_COEFF45,    0x001d0013},
+{14200000, DIF_BPF_COEFF67,    0xffaa000b},
+{14200000, DIF_BPF_COEFF89,    0x00aaff89},
+{14200000, DIF_BPF_COEFF1011,  0xff13014a},
+{14200000, DIF_BPF_COEFF1213,  0x00cefd95},
+{14200000, DIF_BPF_COEFF1415,  0x000a037b},
+{14200000, DIF_BPF_COEFF1617,  0xfe35fc1d},
+{14200000, DIF_BPF_COEFF1819,  0x044c0305},
+{14200000, DIF_BPF_COEFF2021,  0xf90cff7e},
+{14200000, DIF_BPF_COEFF2223,  0x08d5fc81},
+{14200000, DIF_BPF_COEFF2425,  0xf7100834},
+{14200000, DIF_BPF_COEFF2627,  0x069ff3a7},
+{14200000, DIF_BPF_COEFF2829,  0xfe160e8d},
+{14200000, DIF_BPF_COEFF3031,  0xfbaaf231},
+{14200000, DIF_BPF_COEFF3233,  0x0aa509e9},
+{14200000, DIF_BPF_COEFF3435,  0xf0adfc65},
+{14200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 142_quant.dat*/
+
+
+/*case 14300000:*/
+/* BEGIN - DIF BPF register values from 143_quant.dat*/
+{14300000, DIF_BPF_COEFF01,    0x00000003},
+{14300000, DIF_BPF_COEFF23,    0xffffffef},
+{14300000, DIF_BPF_COEFF45,    0x00140025},
+{14300000, DIF_BPF_COEFF67,    0xffb4ffdd},
+{14300000, DIF_BPF_COEFF89,    0x00b2ffd6},
+{14300000, DIF_BPF_COEFF1011,  0xfedb00f0},
+{14300000, DIF_BPF_COEFF1213,  0x0150fdd3},
+{14300000, DIF_BPF_COEFF1415,  0xff380391},
+{14300000, DIF_BPF_COEFF1617,  0xff36fb85},
+{14300000, DIF_BPF_COEFF1819,  0x035e0426},
+{14300000, DIF_BPF_COEFF2021,  0xf994fdfe},
+{14300000, DIF_BPF_COEFF2223,  0x08eefe0b},
+{14300000, DIF_BPF_COEFF2425,  0xf6490702},
+{14300000, DIF_BPF_COEFF2627,  0x07e1f43e},
+{14300000, DIF_BPF_COEFF2829,  0xfcb60e97},
+{14300000, DIF_BPF_COEFF3031,  0xfcc6f1be},
+{14300000, DIF_BPF_COEFF3233,  0x0a040a67},
+{14300000, DIF_BPF_COEFF3435,  0xf0dbfc30},
+{14300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 143_quant.dat*/
+
+
+/*case 14400000:*/
+/* BEGIN - DIF BPF register values from 144_quant.dat*/
+{14400000, DIF_BPF_COEFF01,    0x00000003},
+{14400000, DIF_BPF_COEFF23,    0x0002ffee},
+{14400000, DIF_BPF_COEFF45,    0x00070033},
+{14400000, DIF_BPF_COEFF67,    0xffc9ffb4},
+{14400000, DIF_BPF_COEFF89,    0x00a40027},
+{14400000, DIF_BPF_COEFF1011,  0xfec3007e},
+{14400000, DIF_BPF_COEFF1213,  0x01b4fe3f},
+{14400000, DIF_BPF_COEFF1415,  0xfe760369},
+{14400000, DIF_BPF_COEFF1617,  0x0044fb2e},
+{14400000, DIF_BPF_COEFF1819,  0x02450518},
+{14400000, DIF_BPF_COEFF2021,  0xfa5ffc90},
+{14400000, DIF_BPF_COEFF2223,  0x08c1ffa1},
+{14400000, DIF_BPF_COEFF2425,  0xf5bc05ae},
+{14400000, DIF_BPF_COEFF2627,  0x0902f4fc},
+{14400000, DIF_BPF_COEFF2829,  0xfb600e85},
+{14400000, DIF_BPF_COEFF3031,  0xfde7f15a},
+{14400000, DIF_BPF_COEFF3233,  0x095d0ae2},
+{14400000, DIF_BPF_COEFF3435,  0xf10cfbfb},
+{14400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 144_quant.dat*/
+
+
+/*case 14500000:*/
+/* BEGIN - DIF BPF register values from 145_quant.dat*/
+{14500000, DIF_BPF_COEFF01,    0xffff0002},
+{14500000, DIF_BPF_COEFF23,    0x0005ffef},
+{14500000, DIF_BPF_COEFF45,    0xfffa0038},
+{14500000, DIF_BPF_COEFF67,    0xffe5ff95},
+{14500000, DIF_BPF_COEFF89,    0x00820074},
+{14500000, DIF_BPF_COEFF1011,  0xfecc0000},
+{14500000, DIF_BPF_COEFF1213,  0x01f0fed0},
+{14500000, DIF_BPF_COEFF1415,  0xfdd20304},
+{14500000, DIF_BPF_COEFF1617,  0x014dfb1d},
+{14500000, DIF_BPF_COEFF1819,  0x010e05ce},
+{14500000, DIF_BPF_COEFF2021,  0xfb64fb41},
+{14500000, DIF_BPF_COEFF2223,  0x084e013b},
+{14500000, DIF_BPF_COEFF2425,  0xf569043e},
+{14500000, DIF_BPF_COEFF2627,  0x0a00f5dd},
+{14500000, DIF_BPF_COEFF2829,  0xfa150e55},
+{14500000, DIF_BPF_COEFF3031,  0xff0bf104},
+{14500000, DIF_BPF_COEFF3233,  0x08b00b59},
+{14500000, DIF_BPF_COEFF3435,  0xf13ffbc6},
+{14500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 145_quant.dat*/
+
+
+/*case 14600000:*/
+/* BEGIN - DIF BPF register values from 146_quant.dat*/
+{14600000, DIF_BPF_COEFF01,    0xffff0001},
+{14600000, DIF_BPF_COEFF23,    0x0008fff4},
+{14600000, DIF_BPF_COEFF45,    0xffed0035},
+{14600000, DIF_BPF_COEFF67,    0x0005ff83},
+{14600000, DIF_BPF_COEFF89,    0x005000b4},
+{14600000, DIF_BPF_COEFF1011,  0xfef6ff82},
+{14600000, DIF_BPF_COEFF1213,  0x01ffff7a},
+{14600000, DIF_BPF_COEFF1415,  0xfd580269},
+{14600000, DIF_BPF_COEFF1617,  0x0241fb53},
+{14600000, DIF_BPF_COEFF1819,  0xffca0640},
+{14600000, DIF_BPF_COEFF2021,  0xfc99fa1e},
+{14600000, DIF_BPF_COEFF2223,  0x079a02cb},
+{14600000, DIF_BPF_COEFF2425,  0xf55502ba},
+{14600000, DIF_BPF_COEFF2627,  0x0ad5f6e0},
+{14600000, DIF_BPF_COEFF2829,  0xf8d90e0a},
+{14600000, DIF_BPF_COEFF3031,  0x0031f0bd},
+{14600000, DIF_BPF_COEFF3233,  0x07fd0bcb},
+{14600000, DIF_BPF_COEFF3435,  0xf174fb91},
+{14600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 146_quant.dat*/
+
+
+/*case 14700000:*/
+/* BEGIN - DIF BPF register values from 147_quant.dat*/
+{14700000, DIF_BPF_COEFF01,    0xffffffff},
+{14700000, DIF_BPF_COEFF23,    0x0009fffb},
+{14700000, DIF_BPF_COEFF45,    0xffe4002a},
+{14700000, DIF_BPF_COEFF67,    0x0025ff82},
+{14700000, DIF_BPF_COEFF89,    0x001400e0},
+{14700000, DIF_BPF_COEFF1011,  0xff3cff10},
+{14700000, DIF_BPF_COEFF1213,  0x01e10030},
+{14700000, DIF_BPF_COEFF1415,  0xfd1201a4},
+{14700000, DIF_BPF_COEFF1617,  0x0311fbcd},
+{14700000, DIF_BPF_COEFF1819,  0xfe88066a},
+{14700000, DIF_BPF_COEFF2021,  0xfdf1f92f},
+{14700000, DIF_BPF_COEFF2223,  0x06aa0449},
+{14700000, DIF_BPF_COEFF2425,  0xf57e0128},
+{14700000, DIF_BPF_COEFF2627,  0x0b7ef801},
+{14700000, DIF_BPF_COEFF2829,  0xf7b00da2},
+{14700000, DIF_BPF_COEFF3031,  0x0156f086},
+{14700000, DIF_BPF_COEFF3233,  0x07450c39},
+{14700000, DIF_BPF_COEFF3435,  0xf1acfb5c},
+{14700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 147_quant.dat*/
+
+
+/*case 14800000:*/
+/* BEGIN - DIF BPF register values from 148_quant.dat*/
+{14800000, DIF_BPF_COEFF01,    0x0000fffe},
+{14800000, DIF_BPF_COEFF23,    0x00080002},
+{14800000, DIF_BPF_COEFF45,    0xffdf0019},
+{14800000, DIF_BPF_COEFF67,    0x003fff92},
+{14800000, DIF_BPF_COEFF89,    0xffd600f1},
+{14800000, DIF_BPF_COEFF1011,  0xff96feb6},
+{14800000, DIF_BPF_COEFF1213,  0x019700e1},
+{14800000, DIF_BPF_COEFF1415,  0xfd0500c2},
+{14800000, DIF_BPF_COEFF1617,  0x03b0fc84},
+{14800000, DIF_BPF_COEFF1819,  0xfd590649},
+{14800000, DIF_BPF_COEFF2021,  0xff5df87f},
+{14800000, DIF_BPF_COEFF2223,  0x058505aa},
+{14800000, DIF_BPF_COEFF2425,  0xf5e4ff91},
+{14800000, DIF_BPF_COEFF2627,  0x0bf9f93c},
+{14800000, DIF_BPF_COEFF2829,  0xf69d0d20},
+{14800000, DIF_BPF_COEFF3031,  0x0279f05e},
+{14800000, DIF_BPF_COEFF3233,  0x06880ca3},
+{14800000, DIF_BPF_COEFF3435,  0xf1e6fb28},
+{14800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 148_quant.dat*/
+
+
+/*case 14900000:*/
+/* BEGIN - DIF BPF register values from 149_quant.dat*/
+{14900000, DIF_BPF_COEFF01,    0x0000fffd},
+{14900000, DIF_BPF_COEFF23,    0x00060009},
+{14900000, DIF_BPF_COEFF45,    0xffdf0004},
+{14900000, DIF_BPF_COEFF67,    0x0051ffb0},
+{14900000, DIF_BPF_COEFF89,    0xff9d00e8},
+{14900000, DIF_BPF_COEFF1011,  0xfffcfe7c},
+{14900000, DIF_BPF_COEFF1213,  0x01280180},
+{14900000, DIF_BPF_COEFF1415,  0xfd32ffd2},
+{14900000, DIF_BPF_COEFF1617,  0x0413fd6e},
+{14900000, DIF_BPF_COEFF1819,  0xfc4d05df},
+{14900000, DIF_BPF_COEFF2021,  0x00d1f812},
+{14900000, DIF_BPF_COEFF2223,  0x043506e4},
+{14900000, DIF_BPF_COEFF2425,  0xf685fdfb},
+{14900000, DIF_BPF_COEFF2627,  0x0c43fa8d},
+{14900000, DIF_BPF_COEFF2829,  0xf5a10c83},
+{14900000, DIF_BPF_COEFF3031,  0x0399f046},
+{14900000, DIF_BPF_COEFF3233,  0x05c70d08},
+{14900000, DIF_BPF_COEFF3435,  0xf222faf3},
+{14900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 149_quant.dat*/
+
+
+/*case 15000000:*/
+/* BEGIN - DIF BPF register values from 150_quant.dat*/
+{15000000, DIF_BPF_COEFF01,    0x0000fffd},
+{15000000, DIF_BPF_COEFF23,    0x0003000f},
+{15000000, DIF_BPF_COEFF45,    0xffe5ffef},
+{15000000, DIF_BPF_COEFF67,    0x0057ffd9},
+{15000000, DIF_BPF_COEFF89,    0xff7000c4},
+{15000000, DIF_BPF_COEFF1011,  0x0062fe68},
+{15000000, DIF_BPF_COEFF1213,  0x009e01ff},
+{15000000, DIF_BPF_COEFF1415,  0xfd95fee6},
+{15000000, DIF_BPF_COEFF1617,  0x0435fe7d},
+{15000000, DIF_BPF_COEFF1819,  0xfb710530},
+{15000000, DIF_BPF_COEFF2021,  0x023cf7ee},
+{15000000, DIF_BPF_COEFF2223,  0x02c307ef},
+{15000000, DIF_BPF_COEFF2425,  0xf75efc70},
+{15000000, DIF_BPF_COEFF2627,  0x0c5cfbef},
+{15000000, DIF_BPF_COEFF2829,  0xf4c10bce},
+{15000000, DIF_BPF_COEFF3031,  0x04b3f03f},
+{15000000, DIF_BPF_COEFF3233,  0x05030d69},
+{15000000, DIF_BPF_COEFF3435,  0xf261fabf},
+{15000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 150_quant.dat*/
+
+
+/*case 15100000:*/
+/* BEGIN - DIF BPF register values from 151_quant.dat*/
+{15100000, DIF_BPF_COEFF01,    0x0000fffd},
+{15100000, DIF_BPF_COEFF23,    0xffff0012},
+{15100000, DIF_BPF_COEFF45,    0xffefffdc},
+{15100000, DIF_BPF_COEFF67,    0x00510006},
+{15100000, DIF_BPF_COEFF89,    0xff540089},
+{15100000, DIF_BPF_COEFF1011,  0x00befe7c},
+{15100000, DIF_BPF_COEFF1213,  0x00060253},
+{15100000, DIF_BPF_COEFF1415,  0xfe27fe0d},
+{15100000, DIF_BPF_COEFF1617,  0x0413ffa2},
+{15100000, DIF_BPF_COEFF1819,  0xfad10446},
+{15100000, DIF_BPF_COEFF2021,  0x0390f812},
+{15100000, DIF_BPF_COEFF2223,  0x013b08c3},
+{15100000, DIF_BPF_COEFF2425,  0xf868faf6},
+{15100000, DIF_BPF_COEFF2627,  0x0c43fd5f},
+{15100000, DIF_BPF_COEFF2829,  0xf3fd0b02},
+{15100000, DIF_BPF_COEFF3031,  0x05c7f046},
+{15100000, DIF_BPF_COEFF3233,  0x043b0dc4},
+{15100000, DIF_BPF_COEFF3435,  0xf2a1fa8b},
+{15100000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 151_quant.dat*/
+
+
+/*case 15200000:*/
+/* BEGIN - DIF BPF register values from 152_quant.dat*/
+{15200000, DIF_BPF_COEFF01,    0x0001fffe},
+{15200000, DIF_BPF_COEFF23,    0xfffc0012},
+{15200000, DIF_BPF_COEFF45,    0xfffbffce},
+{15200000, DIF_BPF_COEFF67,    0x003f0033},
+{15200000, DIF_BPF_COEFF89,    0xff4e003f},
+{15200000, DIF_BPF_COEFF1011,  0x0106feb6},
+{15200000, DIF_BPF_COEFF1213,  0xff6e0276},
+{15200000, DIF_BPF_COEFF1415,  0xfeddfd56},
+{15200000, DIF_BPF_COEFF1617,  0x03b000cc},
+{15200000, DIF_BPF_COEFF1819,  0xfa740329},
+{15200000, DIF_BPF_COEFF2021,  0x04bff87f},
+{15200000, DIF_BPF_COEFF2223,  0xffaa095d},
+{15200000, DIF_BPF_COEFF2425,  0xf99ef995},
+{15200000, DIF_BPF_COEFF2627,  0x0bf9fed8},
+{15200000, DIF_BPF_COEFF2829,  0xf3590a1f},
+{15200000, DIF_BPF_COEFF3031,  0x06d2f05e},
+{15200000, DIF_BPF_COEFF3233,  0x03700e1b},
+{15200000, DIF_BPF_COEFF3435,  0xf2e4fa58},
+{15200000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 152_quant.dat*/
+
+
+/*case 115300000:*/
+/* BEGIN - DIF BPF register values from 153_quant.dat*/
+{15300000, DIF_BPF_COEFF01,    0x0001ffff},
+{15300000, DIF_BPF_COEFF23,    0xfff9000f},
+{15300000, DIF_BPF_COEFF45,    0x0009ffc8},
+{15300000, DIF_BPF_COEFF67,    0x00250059},
+{15300000, DIF_BPF_COEFF89,    0xff5effee},
+{15300000, DIF_BPF_COEFF1011,  0x0132ff10},
+{15300000, DIF_BPF_COEFF1213,  0xfee30265},
+{15300000, DIF_BPF_COEFF1415,  0xffaafccf},
+{15300000, DIF_BPF_COEFF1617,  0x031101eb},
+{15300000, DIF_BPF_COEFF1819,  0xfa6001e8},
+{15300000, DIF_BPF_COEFF2021,  0x05bdf92f},
+{15300000, DIF_BPF_COEFF2223,  0xfe1b09b6},
+{15300000, DIF_BPF_COEFF2425,  0xfafaf852},
+{15300000, DIF_BPF_COEFF2627,  0x0b7e0055},
+{15300000, DIF_BPF_COEFF2829,  0xf2d50929},
+{15300000, DIF_BPF_COEFF3031,  0x07d3f086},
+{15300000, DIF_BPF_COEFF3233,  0x02a30e6c},
+{15300000, DIF_BPF_COEFF3435,  0xf329fa24},
+{15300000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 153_quant.dat*/
+
+
+/*case 115400000:*/
+/* BEGIN - DIF BPF register values from 154_quant.dat*/
+{15400000, DIF_BPF_COEFF01,    0x00010001},
+{15400000, DIF_BPF_COEFF23,    0xfff80009},
+{15400000, DIF_BPF_COEFF45,    0x0015ffca},
+{15400000, DIF_BPF_COEFF67,    0x00050074},
+{15400000, DIF_BPF_COEFF89,    0xff81ff9f},
+{15400000, DIF_BPF_COEFF1011,  0x013dff82},
+{15400000, DIF_BPF_COEFF1213,  0xfe710221},
+{15400000, DIF_BPF_COEFF1415,  0x007cfc80},
+{15400000, DIF_BPF_COEFF1617,  0x024102ed},
+{15400000, DIF_BPF_COEFF1819,  0xfa940090},
+{15400000, DIF_BPF_COEFF2021,  0x0680fa1e},
+{15400000, DIF_BPF_COEFF2223,  0xfc9b09cd},
+{15400000, DIF_BPF_COEFF2425,  0xfc73f736},
+{15400000, DIF_BPF_COEFF2627,  0x0ad501d0},
+{15400000, DIF_BPF_COEFF2829,  0xf2740820},
+{15400000, DIF_BPF_COEFF3031,  0x08c9f0bd},
+{15400000, DIF_BPF_COEFF3233,  0x01d40eb9},
+{15400000, DIF_BPF_COEFF3435,  0xf371f9f1},
+{15400000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 154_quant.dat*/
+
+
+/*case 115500000:*/
+/* BEGIN - DIF BPF register values from 155_quant.dat*/
+{15500000, DIF_BPF_COEFF01,    0x00000002},
+{15500000, DIF_BPF_COEFF23,    0xfff80002},
+{15500000, DIF_BPF_COEFF45,    0x001effd5},
+{15500000, DIF_BPF_COEFF67,    0xffe5007f},
+{15500000, DIF_BPF_COEFF89,    0xffb4ff5b},
+{15500000, DIF_BPF_COEFF1011,  0x01280000},
+{15500000, DIF_BPF_COEFF1213,  0xfe2401b0},
+{15500000, DIF_BPF_COEFF1415,  0x0146fc70},
+{15500000, DIF_BPF_COEFF1617,  0x014d03c6},
+{15500000, DIF_BPF_COEFF1819,  0xfb10ff32},
+{15500000, DIF_BPF_COEFF2021,  0x0701fb41},
+{15500000, DIF_BPF_COEFF2223,  0xfb3709a1},
+{15500000, DIF_BPF_COEFF2425,  0xfe00f644},
+{15500000, DIF_BPF_COEFF2627,  0x0a000345},
+{15500000, DIF_BPF_COEFF2829,  0xf2350708},
+{15500000, DIF_BPF_COEFF3031,  0x09b2f104},
+{15500000, DIF_BPF_COEFF3233,  0x01050eff},
+{15500000, DIF_BPF_COEFF3435,  0xf3baf9be},
+{15500000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 155_quant.dat*/
+
+
+/*case 115600000:*/
+/* BEGIN - DIF BPF register values from 156_quant.dat*/
+{15600000, DIF_BPF_COEFF01,    0x00000003},
+{15600000, DIF_BPF_COEFF23,    0xfff9fffb},
+{15600000, DIF_BPF_COEFF45,    0x0022ffe6},
+{15600000, DIF_BPF_COEFF67,    0xffc9007a},
+{15600000, DIF_BPF_COEFF89,    0xfff0ff29},
+{15600000, DIF_BPF_COEFF1011,  0x00f2007e},
+{15600000, DIF_BPF_COEFF1213,  0xfe01011b},
+{15600000, DIF_BPF_COEFF1415,  0x01f6fc9e},
+{15600000, DIF_BPF_COEFF1617,  0x00440467},
+{15600000, DIF_BPF_COEFF1819,  0xfbccfdde},
+{15600000, DIF_BPF_COEFF2021,  0x0738fc90},
+{15600000, DIF_BPF_COEFF2223,  0xf9f70934},
+{15600000, DIF_BPF_COEFF2425,  0xff99f582},
+{15600000, DIF_BPF_COEFF2627,  0x090204b0},
+{15600000, DIF_BPF_COEFF2829,  0xf21a05e1},
+{15600000, DIF_BPF_COEFF3031,  0x0a8df15a},
+{15600000, DIF_BPF_COEFF3233,  0x00340f41},
+{15600000, DIF_BPF_COEFF3435,  0xf405f98b},
+{15600000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 156_quant.dat*/
+
+
+/*case 115700000:*/
+/* BEGIN - DIF BPF register values from 157_quant.dat*/
+{15700000, DIF_BPF_COEFF01,    0x00000003},
+{15700000, DIF_BPF_COEFF23,    0xfffcfff4},
+{15700000, DIF_BPF_COEFF45,    0x0020fffa},
+{15700000, DIF_BPF_COEFF67,    0xffb40064},
+{15700000, DIF_BPF_COEFF89,    0x002fff11},
+{15700000, DIF_BPF_COEFF1011,  0x00a400f0},
+{15700000, DIF_BPF_COEFF1213,  0xfe0d006e},
+{15700000, DIF_BPF_COEFF1415,  0x0281fd09},
+{15700000, DIF_BPF_COEFF1617,  0xff3604c9},
+{15700000, DIF_BPF_COEFF1819,  0xfcbffca2},
+{15700000, DIF_BPF_COEFF2021,  0x0726fdfe},
+{15700000, DIF_BPF_COEFF2223,  0xf8e80888},
+{15700000, DIF_BPF_COEFF2425,  0x0134f4f3},
+{15700000, DIF_BPF_COEFF2627,  0x07e1060c},
+{15700000, DIF_BPF_COEFF2829,  0xf22304af},
+{15700000, DIF_BPF_COEFF3031,  0x0b59f1be},
+{15700000, DIF_BPF_COEFF3233,  0xff640f7d},
+{15700000, DIF_BPF_COEFF3435,  0xf452f959},
+{15700000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 157_quant.dat*/
+
+
+/*case 115800000:*/
+/* BEGIN - DIF BPF register values from 158_quant.dat*/
+{15800000, DIF_BPF_COEFF01,    0x00000003},
+{15800000, DIF_BPF_COEFF23,    0x0000fff0},
+{15800000, DIF_BPF_COEFF45,    0x001a0010},
+{15800000, DIF_BPF_COEFF67,    0xffaa0041},
+{15800000, DIF_BPF_COEFF89,    0x0067ff13},
+{15800000, DIF_BPF_COEFF1011,  0x0043014a},
+{15800000, DIF_BPF_COEFF1213,  0xfe46ffb9},
+{15800000, DIF_BPF_COEFF1415,  0x02dbfda8},
+{15800000, DIF_BPF_COEFF1617,  0xfe3504e5},
+{15800000, DIF_BPF_COEFF1819,  0xfddcfb8d},
+{15800000, DIF_BPF_COEFF2021,  0x06c9ff7e},
+{15800000, DIF_BPF_COEFF2223,  0xf81107a2},
+{15800000, DIF_BPF_COEFF2425,  0x02c9f49a},
+{15800000, DIF_BPF_COEFF2627,  0x069f0753},
+{15800000, DIF_BPF_COEFF2829,  0xf2500373},
+{15800000, DIF_BPF_COEFF3031,  0x0c14f231},
+{15800000, DIF_BPF_COEFF3233,  0xfe930fb3},
+{15800000, DIF_BPF_COEFF3435,  0xf4a1f927},
+{15800000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 158_quant.dat*/
+
+
+/*case 115900000:*/
+/* BEGIN - DIF BPF register values from 159_quant.dat*/
+{15900000, DIF_BPF_COEFF01,    0xffff0002},
+{15900000, DIF_BPF_COEFF23,    0x0003ffee},
+{15900000, DIF_BPF_COEFF45,    0x000f0023},
+{15900000, DIF_BPF_COEFF67,    0xffac0016},
+{15900000, DIF_BPF_COEFF89,    0x0093ff31},
+{15900000, DIF_BPF_COEFF1011,  0xffdc0184},
+{15900000, DIF_BPF_COEFF1213,  0xfea6ff09},
+{15900000, DIF_BPF_COEFF1415,  0x02fdfe70},
+{15900000, DIF_BPF_COEFF1617,  0xfd5104ba},
+{15900000, DIF_BPF_COEFF1819,  0xff15faac},
+{15900000, DIF_BPF_COEFF2021,  0x06270103},
+{15900000, DIF_BPF_COEFF2223,  0xf7780688},
+{15900000, DIF_BPF_COEFF2425,  0x044df479},
+{15900000, DIF_BPF_COEFF2627,  0x05430883},
+{15900000, DIF_BPF_COEFF2829,  0xf2a00231},
+{15900000, DIF_BPF_COEFF3031,  0x0cbef2b2},
+{15900000, DIF_BPF_COEFF3233,  0xfdc40fe3},
+{15900000, DIF_BPF_COEFF3435,  0xf4f2f8f5},
+{15900000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 159_quant.dat*/
+
+
+/*case 116000000:*/
+/* BEGIN - DIF BPF register values from 160_quant.dat*/
+{16000000, DIF_BPF_COEFF01,    0xffff0001},
+{16000000, DIF_BPF_COEFF23,    0x0006ffef},
+{16000000, DIF_BPF_COEFF45,    0x00020031},
+{16000000, DIF_BPF_COEFF67,    0xffbaffe8},
+{16000000, DIF_BPF_COEFF89,    0x00adff66},
+{16000000, DIF_BPF_COEFF1011,  0xff790198},
+{16000000, DIF_BPF_COEFF1213,  0xff26fe6e},
+{16000000, DIF_BPF_COEFF1415,  0x02e5ff55},
+{16000000, DIF_BPF_COEFF1617,  0xfc99044a},
+{16000000, DIF_BPF_COEFF1819,  0x005bfa09},
+{16000000, DIF_BPF_COEFF2021,  0x0545027f},
+{16000000, DIF_BPF_COEFF2223,  0xf7230541},
+{16000000, DIF_BPF_COEFF2425,  0x05b8f490},
+{16000000, DIF_BPF_COEFF2627,  0x03d20997},
+{16000000, DIF_BPF_COEFF2829,  0xf31300eb},
+{16000000, DIF_BPF_COEFF3031,  0x0d55f341},
+{16000000, DIF_BPF_COEFF3233,  0xfcf6100e},
+{16000000, DIF_BPF_COEFF3435,  0xf544f8c3},
+{16000000, DIF_BPF_COEFF36,    0x110d0000},
+/* END - DIF BPF register values from 160_quant.dat*/
+};
+
+#endif
diff --git a/drivers/media/usb/cx231xx/cx231xx-dvb.c b/drivers/media/usb/cx231xx/cx231xx-dvb.c
new file mode 100644
index 000000000000..7c4e360ba9bc
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-dvb.c
@@ -0,0 +1,796 @@
+/*
+ DVB device driver for cx231xx
+
+ Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+                Based on em28xx driver
+
+ This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/usb.h>
+
+#include "cx231xx.h"
+#include <media/v4l2-common.h>
+#include <media/videobuf-vmalloc.h>
+
+#include "xc5000.h"
+#include "s5h1432.h"
+#include "tda18271.h"
+#include "s5h1411.h"
+#include "lgdt3305.h"
+#include "mb86a20s.h"
+
+MODULE_DESCRIPTION("driver for cx231xx based DVB cards");
+MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>");
+MODULE_LICENSE("GPL");
+
+static unsigned int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
+
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+#define dprintk(level, fmt, arg...) do {                        \
+if (debug >= level)                                             \
+        printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->name, ## arg); \
+} while (0)
+
+#define CX231XX_DVB_NUM_BUFS 5
+#define CX231XX_DVB_MAX_PACKETSIZE 564
+#define CX231XX_DVB_MAX_PACKETS 64
+
+struct cx231xx_dvb {
+        struct dvb_frontend *frontend;
+
+        /* feed count management */
+        struct mutex lock;
+        int nfeeds;
+
+        /* general boilerplate stuff */
+        struct dvb_adapter adapter;
+        struct dvb_demux demux;
+        struct dmxdev dmxdev;
+        struct dmx_frontend fe_hw;
+        struct dmx_frontend fe_mem;
+        struct dvb_net net;
+};
+
+static struct s5h1432_config dvico_s5h1432_config = {
+        .output_mode   = S5H1432_SERIAL_OUTPUT,
+        .gpio          = S5H1432_GPIO_ON,
+        .qam_if        = S5H1432_IF_4000,
+        .vsb_if        = S5H1432_IF_4000,
+        .inversion     = S5H1432_INVERSION_OFF,
+        .status_mode   = S5H1432_DEMODLOCKING,
+        .mpeg_timing   = S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
+};
+
+static struct tda18271_std_map cnxt_rde253s_tda18271_std_map = {
+        .dvbt_6   = { .if_freq = 4000, .agc_mode = 3, .std = 4,
+                      .if_lvl = 1, .rfagc_top = 0x37, },
+        .dvbt_7   = { .if_freq = 4000, .agc_mode = 3, .std = 5,
+                      .if_lvl = 1, .rfagc_top = 0x37, },
+        .dvbt_8   = { .if_freq = 4000, .agc_mode = 3, .std = 6,
+                      .if_lvl = 1, .rfagc_top = 0x37, },
+};
+
+static struct tda18271_std_map mb86a20s_tda18271_config = {
+        .dvbt_6   = { .if_freq = 3300, .agc_mode = 3, .std = 4,
+                      .if_lvl = 7, .rfagc_top = 0x37, },
+};
+
+static struct tda18271_config cnxt_rde253s_tunerconfig = {
+        .std_map = &cnxt_rde253s_tda18271_std_map,
+        .gate    = TDA18271_GATE_ANALOG,
+};
+
+static struct s5h1411_config tda18271_s5h1411_config = {
+        .output_mode   = S5H1411_SERIAL_OUTPUT,
+        .gpio          = S5H1411_GPIO_OFF,
+        .vsb_if        = S5H1411_IF_3250,
+        .qam_if        = S5H1411_IF_4000,
+        .inversion     = S5H1411_INVERSION_ON,
+        .status_mode   = S5H1411_DEMODLOCKING,
+        .mpeg_timing   = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
+};
+static struct s5h1411_config xc5000_s5h1411_config = {
+        .output_mode   = S5H1411_SERIAL_OUTPUT,
+        .gpio          = S5H1411_GPIO_OFF,
+        .vsb_if        = S5H1411_IF_3250,
+        .qam_if        = S5H1411_IF_3250,
+        .inversion     = S5H1411_INVERSION_OFF,
+        .status_mode   = S5H1411_DEMODLOCKING,
+        .mpeg_timing   = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
+};
+
+static struct lgdt3305_config hcw_lgdt3305_config = {
+        .i2c_addr           = 0x0e,
+        .mpeg_mode          = LGDT3305_MPEG_SERIAL,
+        .tpclk_edge         = LGDT3305_TPCLK_FALLING_EDGE,
+        .tpvalid_polarity   = LGDT3305_TP_VALID_HIGH,
+        .deny_i2c_rptr      = 1,
+        .spectral_inversion = 1,
+        .qam_if_khz         = 4000,
+        .vsb_if_khz         = 3250,
+};
+
+static struct tda18271_std_map hauppauge_tda18271_std_map = {
+        .atsc_6   = { .if_freq = 3250, .agc_mode = 3, .std = 4,
+                      .if_lvl = 1, .rfagc_top = 0x58, },
+        .qam_6    = { .if_freq = 4000, .agc_mode = 3, .std = 5,
+                      .if_lvl = 1, .rfagc_top = 0x58, },
+};
+
+static struct tda18271_config hcw_tda18271_config = {
+        .std_map = &hauppauge_tda18271_std_map,
+        .gate    = TDA18271_GATE_DIGITAL,
+};
+
+static const struct mb86a20s_config pv_mb86a20s_config = {
+        .demod_address = 0x10,
+        .is_serial = true,
+};
+
+static struct tda18271_config pv_tda18271_config = {
+        .std_map = &mb86a20s_tda18271_config,
+        .gate    = TDA18271_GATE_DIGITAL,
+        .small_i2c = TDA18271_03_BYTE_CHUNK_INIT,
+};
+
+static inline void print_err_status(struct cx231xx *dev, int packet, int status)
+{
+        char *errmsg = "Unknown";
+
+        switch (status) {
+        case -ENOENT:
+                errmsg = "unlinked synchronuously";
+                break;
+        case -ECONNRESET:
+                errmsg = "unlinked asynchronuously";
+                break;
+        case -ENOSR:
+                errmsg = "Buffer error (overrun)";
+                break;
+        case -EPIPE:
+                errmsg = "Stalled (device not responding)";
+                break;
+        case -EOVERFLOW:
+                errmsg = "Babble (bad cable?)";
+                break;
+        case -EPROTO:
+                errmsg = "Bit-stuff error (bad cable?)";
+                break;
+        case -EILSEQ:
+                errmsg = "CRC/Timeout (could be anything)";
+                break;
+        case -ETIME:
+                errmsg = "Device does not respond";
+                break;
+        }
+        if (packet < 0) {
+                dprintk(1, "URB status %d [%s].\n", status, errmsg);
+        } else {
+                dprintk(1, "URB packet %d, status %d [%s].\n",
+                        packet, status, errmsg);
+        }
+}
+
+static inline int dvb_isoc_copy(struct cx231xx *dev, struct urb *urb)
+{
+        int i;
+
+        if (!dev)
+                return 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return 0;
+
+        if (urb->status < 0) {
+                print_err_status(dev, -1, urb->status);
+                if (urb->status == -ENOENT)
+                        return 0;
+        }
+
+        for (i = 0; i < urb->number_of_packets; i++) {
+                int status = urb->iso_frame_desc[i].status;
+
+                if (status < 0) {
+                        print_err_status(dev, i, status);
+                        if (urb->iso_frame_desc[i].status != -EPROTO)
+                                continue;
+                }
+
+                dvb_dmx_swfilter(&dev->dvb->demux,
+                                 urb->transfer_buffer +
+                                urb->iso_frame_desc[i].offset,
+                                urb->iso_frame_desc[i].actual_length);
+        }
+
+        return 0;
+}
+
+static inline int dvb_bulk_copy(struct cx231xx *dev, struct urb *urb)
+{
+        if (!dev)
+                return 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return 0;
+
+        if (urb->status < 0) {
+                print_err_status(dev, -1, urb->status);
+                if (urb->status == -ENOENT)
+                        return 0;
+        }
+
+        /* Feed the transport payload into the kernel demux */
+        dvb_dmx_swfilter(&dev->dvb->demux,
+                urb->transfer_buffer, urb->actual_length);
+
+        return 0;
+}
+
+static int start_streaming(struct cx231xx_dvb *dvb)
+{
+        int rc;
+        struct cx231xx *dev = dvb->adapter.priv;
+
+        if (dev->USE_ISO) {
+                cx231xx_info("DVB transfer mode is ISO.\n");
+                mutex_lock(&dev->i2c_lock);
+                cx231xx_enable_i2c_port_3(dev, false);
+                cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
+                cx231xx_enable_i2c_port_3(dev, true);
+                mutex_unlock(&dev->i2c_lock);
+                rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+                if (rc < 0)
+                        return rc;
+                dev->mode_tv = 1;
+                return cx231xx_init_isoc(dev, CX231XX_DVB_MAX_PACKETS,
+                                        CX231XX_DVB_NUM_BUFS,
+                                        dev->ts1_mode.max_pkt_size,
+                                        dvb_isoc_copy);
+        } else {
+                cx231xx_info("DVB transfer mode is BULK.\n");
+                cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
+                rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+                if (rc < 0)
+                        return rc;
+                dev->mode_tv = 1;
+                return cx231xx_init_bulk(dev, CX231XX_DVB_MAX_PACKETS,
+                                        CX231XX_DVB_NUM_BUFS,
+                                        dev->ts1_mode.max_pkt_size,
+                                        dvb_bulk_copy);
+        }
+
+}
+
+static int stop_streaming(struct cx231xx_dvb *dvb)
+{
+        struct cx231xx *dev = dvb->adapter.priv;
+
+        if (dev->USE_ISO)
+                cx231xx_uninit_isoc(dev);
+        else
+                cx231xx_uninit_bulk(dev);
+
+        cx231xx_set_mode(dev, CX231XX_SUSPEND);
+
+        return 0;
+}
+
+static int start_feed(struct dvb_demux_feed *feed)
+{
+        struct dvb_demux *demux = feed->demux;
+        struct cx231xx_dvb *dvb = demux->priv;
+        int rc, ret;
+
+        if (!demux->dmx.frontend)
+                return -EINVAL;
+
+        mutex_lock(&dvb->lock);
+        dvb->nfeeds++;
+        rc = dvb->nfeeds;
+
+        if (dvb->nfeeds == 1) {
+                ret = start_streaming(dvb);
+                if (ret < 0)
+                        rc = ret;
+        }
+
+        mutex_unlock(&dvb->lock);
+        return rc;
+}
+
+static int stop_feed(struct dvb_demux_feed *feed)
+{
+        struct dvb_demux *demux = feed->demux;
+        struct cx231xx_dvb *dvb = demux->priv;
+        int err = 0;
+
+        mutex_lock(&dvb->lock);
+        dvb->nfeeds--;
+
+        if (0 == dvb->nfeeds)
+                err = stop_streaming(dvb);
+
+        mutex_unlock(&dvb->lock);
+        return err;
+}
+
+/* ------------------------------------------------------------------ */
+static int cx231xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
+{
+        struct cx231xx *dev = fe->dvb->priv;
+
+        if (acquire)
+                return cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+        else
+                return cx231xx_set_mode(dev, CX231XX_SUSPEND);
+}
+
+/* ------------------------------------------------------------------ */
+
+static struct xc5000_config cnxt_rde250_tunerconfig = {
+        .i2c_address = 0x61,
+        .if_khz = 4000,
+};
+static struct xc5000_config cnxt_rdu250_tunerconfig = {
+        .i2c_address = 0x61,
+        .if_khz = 3250,
+};
+
+/* ------------------------------------------------------------------ */
+#if 0
+static int attach_xc5000(u8 addr, struct cx231xx *dev)
+{
+
+        struct dvb_frontend *fe;
+        struct xc5000_config cfg;
+
+        memset(&cfg, 0, sizeof(cfg));
+        cfg.i2c_adap = &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap;
+        cfg.i2c_addr = addr;
+
+        if (!dev->dvb->frontend) {
+                printk(KERN_ERR "%s/2: dvb frontend not attached. "
+                       "Can't attach xc5000\n", dev->name);
+                return -EINVAL;
+        }
+
+        fe = dvb_attach(xc5000_attach, dev->dvb->frontend, &cfg);
+        if (!fe) {
+                printk(KERN_ERR "%s/2: xc5000 attach failed\n", dev->name);
+                dvb_frontend_detach(dev->dvb->frontend);
+                dev->dvb->frontend = NULL;
+                return -EINVAL;
+        }
+
+        printk(KERN_INFO "%s/2: xc5000 attached\n", dev->name);
+
+        return 0;
+}
+#endif
+
+int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq)
+{
+        int status = 0;
+
+        if ((dev->dvb != NULL) && (dev->dvb->frontend != NULL)) {
+
+                struct dvb_tuner_ops *dops = &dev->dvb->frontend->ops.tuner_ops;
+
+                if (dops->set_analog_params != NULL) {
+                        struct analog_parameters params;
+
+                        params.frequency = freq;
+                        params.std = dev->norm;
+                        params.mode = 0;        /* 0- Air; 1 - cable */
+                        /*params.audmode = ;       */
+
+                        /* Set the analog parameters to set the frequency */
+                        dops->set_analog_params(dev->dvb->frontend, &params);
+                }
+
+        }
+
+        return status;
+}
+
+int cx231xx_reset_analog_tuner(struct cx231xx *dev)
+{
+        int status = 0;
+
+        if ((dev->dvb != NULL) && (dev->dvb->frontend != NULL)) {
+
+                struct dvb_tuner_ops *dops = &dev->dvb->frontend->ops.tuner_ops;
+
+                if (dops->init != NULL && !dev->xc_fw_load_done) {
+
+                        cx231xx_info("Reloading firmware for XC5000\n");
+                        status = dops->init(dev->dvb->frontend);
+                        if (status == 0) {
+                                dev->xc_fw_load_done = 1;
+                                cx231xx_info
+                                    ("XC5000 firmware download completed\n");
+                        } else {
+                                dev->xc_fw_load_done = 0;
+                                cx231xx_info
+                                    ("XC5000 firmware download failed !!!\n");
+                        }
+                }
+
+        }
+
+        return status;
+}
+
+/* ------------------------------------------------------------------ */
+
+static int register_dvb(struct cx231xx_dvb *dvb,
+                        struct module *module,
+                        struct cx231xx *dev, struct device *device)
+{
+        int result;
+
+        mutex_init(&dvb->lock);
+
+        /* register adapter */
+        result = dvb_register_adapter(&dvb->adapter, dev->name, module, device,
+                                      adapter_nr);
+        if (result < 0) {
+                printk(KERN_WARNING
+                       "%s: dvb_register_adapter failed (errno = %d)\n",
+                       dev->name, result);
+                goto fail_adapter;
+        }
+
+        /* Ensure all frontends negotiate bus access */
+        dvb->frontend->ops.ts_bus_ctrl = cx231xx_dvb_bus_ctrl;
+
+        dvb->adapter.priv = dev;
+
+        /* register frontend */
+        result = dvb_register_frontend(&dvb->adapter, dvb->frontend);
+        if (result < 0) {
+                printk(KERN_WARNING
+                       "%s: dvb_register_frontend failed (errno = %d)\n",
+                       dev->name, result);
+                goto fail_frontend;
+        }
+
+        /* register demux stuff */
+        dvb->demux.dmx.capabilities =
+            DMX_TS_FILTERING | DMX_SECTION_FILTERING |
+            DMX_MEMORY_BASED_FILTERING;
+        dvb->demux.priv = dvb;
+        dvb->demux.filternum = 256;
+        dvb->demux.feednum = 256;
+        dvb->demux.start_feed = start_feed;
+        dvb->demux.stop_feed = stop_feed;
+
+        result = dvb_dmx_init(&dvb->demux);
+        if (result < 0) {
+                printk(KERN_WARNING "%s: dvb_dmx_init failed (errno = %d)\n",
+                       dev->name, result);
+                goto fail_dmx;
+        }
+
+        dvb->dmxdev.filternum = 256;
+        dvb->dmxdev.demux = &dvb->demux.dmx;
+        dvb->dmxdev.capabilities = 0;
+        result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter);
+        if (result < 0) {
+                printk(KERN_WARNING "%s: dvb_dmxdev_init failed (errno = %d)\n",
+                       dev->name, result);
+                goto fail_dmxdev;
+        }
+
+        dvb->fe_hw.source = DMX_FRONTEND_0;
+        result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw);
+        if (result < 0) {
+                printk(KERN_WARNING
+                       "%s: add_frontend failed (DMX_FRONTEND_0, errno = %d)\n",
+                       dev->name, result);
+                goto fail_fe_hw;
+        }
+
+        dvb->fe_mem.source = DMX_MEMORY_FE;
+        result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem);
+        if (result < 0) {
+                printk(KERN_WARNING
+                       "%s: add_frontend failed (DMX_MEMORY_FE, errno = %d)\n",
+                       dev->name, result);
+                goto fail_fe_mem;
+        }
+
+        result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw);
+        if (result < 0) {
+                printk(KERN_WARNING
+                       "%s: connect_frontend failed (errno = %d)\n", dev->name,
+                       result);
+                goto fail_fe_conn;
+        }
+
+        /* register network adapter */
+        dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx);
+        return 0;
+
+fail_fe_conn:
+        dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
+fail_fe_mem:
+        dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
+fail_fe_hw:
+        dvb_dmxdev_release(&dvb->dmxdev);
+fail_dmxdev:
+        dvb_dmx_release(&dvb->demux);
+fail_dmx:
+        dvb_unregister_frontend(dvb->frontend);
+fail_frontend:
+        dvb_frontend_detach(dvb->frontend);
+        dvb_unregister_adapter(&dvb->adapter);
+fail_adapter:
+        return result;
+}
+
+static void unregister_dvb(struct cx231xx_dvb *dvb)
+{
+        dvb_net_release(&dvb->net);
+        dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
+        dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
+        dvb_dmxdev_release(&dvb->dmxdev);
+        dvb_dmx_release(&dvb->demux);
+        dvb_unregister_frontend(dvb->frontend);
+        dvb_frontend_detach(dvb->frontend);
+        dvb_unregister_adapter(&dvb->adapter);
+}
+
+static int dvb_init(struct cx231xx *dev)
+{
+        int result = 0;
+        struct cx231xx_dvb *dvb;
+
+        if (!dev->board.has_dvb) {
+                /* This device does not support the extension */
+                return 0;
+        }
+
+        dvb = kzalloc(sizeof(struct cx231xx_dvb), GFP_KERNEL);
+
+        if (dvb == NULL) {
+                printk(KERN_INFO "cx231xx_dvb: memory allocation failed\n");
+                return -ENOMEM;
+        }
+        dev->dvb = dvb;
+        dev->cx231xx_set_analog_freq = cx231xx_set_analog_freq;
+        dev->cx231xx_reset_analog_tuner = cx231xx_reset_analog_tuner;
+
+        mutex_lock(&dev->lock);
+        cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
+        cx231xx_demod_reset(dev);
+        /* init frontend */
+        switch (dev->model) {
+        case CX231XX_BOARD_CNXT_CARRAERA:
+        case CX231XX_BOARD_CNXT_RDE_250:
+
+                dev->dvb->frontend = dvb_attach(s5h1432_attach,
+                                        &dvico_s5h1432_config,
+                                        &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach s5h1432 front end\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                if (!dvb_attach(xc5000_attach, dev->dvb->frontend,
+                               &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                               &cnxt_rde250_tunerconfig)) {
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                break;
+        case CX231XX_BOARD_CNXT_SHELBY:
+        case CX231XX_BOARD_CNXT_RDU_250:
+
+                dev->dvb->frontend = dvb_attach(s5h1411_attach,
+                                               &xc5000_s5h1411_config,
+                                               &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach s5h1411 front end\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                if (!dvb_attach(xc5000_attach, dev->dvb->frontend,
+                               &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                               &cnxt_rdu250_tunerconfig)) {
+                        result = -EINVAL;
+                        goto out_free;
+                }
+                break;
+        case CX231XX_BOARD_CNXT_RDE_253S:
+
+                dev->dvb->frontend = dvb_attach(s5h1432_attach,
+                                        &dvico_s5h1432_config,
+                                        &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach s5h1432 front end\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                if (!dvb_attach(tda18271_attach, dev->dvb->frontend,
+                               0x60, &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                               &cnxt_rde253s_tunerconfig)) {
+                        result = -EINVAL;
+                        goto out_free;
+                }
+                break;
+        case CX231XX_BOARD_CNXT_RDU_253S:
+
+                dev->dvb->frontend = dvb_attach(s5h1411_attach,
+                                               &tda18271_s5h1411_config,
+                                               &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach s5h1411 front end\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                if (!dvb_attach(tda18271_attach, dev->dvb->frontend,
+                               0x60, &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                               &cnxt_rde253s_tunerconfig)) {
+                        result = -EINVAL;
+                        goto out_free;
+                }
+                break;
+        case CX231XX_BOARD_HAUPPAUGE_EXETER:
+
+                printk(KERN_INFO "%s: looking for tuner / demod on i2c bus: %d\n",
+                       __func__, i2c_adapter_id(&dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap));
+
+                dev->dvb->frontend = dvb_attach(lgdt3305_attach,
+                                                &hcw_lgdt3305_config,
+                                                &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach LG3305 front end\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                dvb_attach(tda18271_attach, dev->dvb->frontend,
+                           0x60, &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                           &hcw_tda18271_config);
+                break;
+
+        case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
+        case CX231XX_BOARD_KWORLD_UB430_USB_HYBRID:
+
+                printk(KERN_INFO "%s: looking for demod on i2c bus: %d\n",
+                       __func__, i2c_adapter_id(&dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap));
+
+                dev->dvb->frontend = dvb_attach(mb86a20s_attach,
+                                                &pv_mb86a20s_config,
+                                                &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap);
+
+                if (dev->dvb->frontend == NULL) {
+                        printk(DRIVER_NAME
+                               ": Failed to attach mb86a20s demod\n");
+                        result = -EINVAL;
+                        goto out_free;
+                }
+
+                /* define general-purpose callback pointer */
+                dvb->frontend->callback = cx231xx_tuner_callback;
+
+                dvb_attach(tda18271_attach, dev->dvb->frontend,
+                           0x60, &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap,
+                           &pv_tda18271_config);
+                break;
+
+        default:
+                printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card"
+                       " isn't supported yet\n", dev->name);
+                break;
+        }
+        if (NULL == dvb->frontend) {
+                printk(KERN_ERR
+                       "%s/2: frontend initialization failed\n", dev->name);
+                result = -EINVAL;
+                goto out_free;
+        }
+
+        /* register everything */
+        result = register_dvb(dvb, THIS_MODULE, dev, &dev->udev->dev);
+
+        if (result < 0)
+                goto out_free;
+
+
+        printk(KERN_INFO "Successfully loaded cx231xx-dvb\n");
+
+ret:
+        cx231xx_set_mode(dev, CX231XX_SUSPEND);
+        mutex_unlock(&dev->lock);
+        return result;
+
+out_free:
+        kfree(dvb);
+        dev->dvb = NULL;
+        goto ret;
+}
+
+static int dvb_fini(struct cx231xx *dev)
+{
+        if (!dev->board.has_dvb) {
+                /* This device does not support the extension */
+                return 0;
+        }
+
+        if (dev->dvb) {
+                unregister_dvb(dev->dvb);
+                dev->dvb = NULL;
+        }
+
+        return 0;
+}
+
+static struct cx231xx_ops dvb_ops = {
+        .id = CX231XX_DVB,
+        .name = "Cx231xx dvb Extension",
+        .init = dvb_init,
+        .fini = dvb_fini,
+};
+
+static int __init cx231xx_dvb_register(void)
+{
+        return cx231xx_register_extension(&dvb_ops);
+}
+
+static void __exit cx231xx_dvb_unregister(void)
+{
+        cx231xx_unregister_extension(&dvb_ops);
+}
+
+module_init(cx231xx_dvb_register);
+module_exit(cx231xx_dvb_unregister);
diff --git a/drivers/media/usb/cx231xx/cx231xx-i2c.c b/drivers/media/usb/cx231xx/cx231xx-i2c.c
new file mode 100644
index 000000000000..781feed406f7
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-i2c.c
@@ -0,0 +1,532 @@
+/*
+   cx231xx-i2c.c - driver for Conexant Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+                Based on em28xx driver
+                Based on Cx23885 driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/usb.h>
+#include <linux/i2c.h>
+#include <media/v4l2-common.h>
+#include <media/tuner.h>
+
+#include "cx231xx.h"
+
+/* ----------------------------------------------------------- */
+
+static unsigned int i2c_scan;
+module_param(i2c_scan, int, 0444);
+MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
+
+static unsigned int i2c_debug;
+module_param(i2c_debug, int, 0644);
+MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
+
+#define dprintk1(lvl, fmt, args...)                     \
+do {                                                    \
+        if (i2c_debug >= lvl) {                         \
+                printk(fmt, ##args);                    \
+                }                                       \
+} while (0)
+
+#define dprintk2(lvl, fmt, args...)                     \
+do {                                                    \
+        if (i2c_debug >= lvl) {                         \
+                printk(KERN_DEBUG "%s at %s: " fmt,     \
+                       dev->name, __func__ , ##args);   \
+      }                                                 \
+} while (0)
+
+static inline bool is_tuner(struct cx231xx *dev, struct cx231xx_i2c *bus,
+                        const struct i2c_msg *msg, int tuner_type)
+{
+        if (bus->nr != dev->board.tuner_i2c_master)
+                return false;
+
+        if (msg->addr != dev->board.tuner_addr)
+                return false;
+
+        if (dev->tuner_type != tuner_type)
+                return false;
+
+        return true;
+}
+
+/*
+ * cx231xx_i2c_send_bytes()
+ */
+int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
+                           const struct i2c_msg *msg)
+{
+        struct cx231xx_i2c *bus = i2c_adap->algo_data;
+        struct cx231xx *dev = bus->dev;
+        struct cx231xx_i2c_xfer_data req_data;
+        int status = 0;
+        u16 size = 0;
+        u8 loop = 0;
+        u8 saddr_len = 1;
+        u8 *buf_ptr = NULL;
+        u16 saddr = 0;
+        u8 need_gpio = 0;
+
+        if (is_tuner(dev, bus, msg, TUNER_XC5000)) {
+                size = msg->len;
+
+                if (size == 2) {        /* register write sub addr */
+                        /* Just writing sub address will cause problem
+                        * to XC5000. So ignore the request */
+                        return 0;
+                } else if (size == 4) { /* register write with sub addr */
+                        if (msg->len >= 2)
+                                saddr = msg->buf[0] << 8 | msg->buf[1];
+                        else if (msg->len == 1)
+                                saddr = msg->buf[0];
+
+                        switch (saddr) {
+                        case 0x0000:    /* start tuner calibration mode */
+                                need_gpio = 1;
+                                /* FW Loading is done */
+                                dev->xc_fw_load_done = 1;
+                                break;
+                        case 0x000D:    /* Set signal source */
+                        case 0x0001:    /* Set TV standard - Video */
+                        case 0x0002:    /* Set TV standard - Audio */
+                        case 0x0003:    /* Set RF Frequency */
+                                need_gpio = 1;
+                                break;
+                        default:
+                                if (dev->xc_fw_load_done)
+                                        need_gpio = 1;
+                                break;
+                        }
+
+                        if (need_gpio) {
+                                dprintk1(1,
+                                "GPIO WRITE: addr 0x%x, len %d, saddr 0x%x\n",
+                                msg->addr, msg->len, saddr);
+
+                                return dev->cx231xx_gpio_i2c_write(dev,
+                                                                   msg->addr,
+                                                                   msg->buf,
+                                                                   msg->len);
+                        }
+                }
+
+                /* special case for Xc5000 tuner case */
+                saddr_len = 1;
+
+                /* adjust the length to correct length */
+                size -= saddr_len;
+                buf_ptr = (u8 *) (msg->buf + 1);
+
+                do {
+                        /* prepare xfer_data struct */
+                        req_data.dev_addr = msg->addr;
+                        req_data.direction = msg->flags;
+                        req_data.saddr_len = saddr_len;
+                        req_data.saddr_dat = msg->buf[0];
+                        req_data.buf_size = size > 16 ? 16 : size;
+                        req_data.p_buffer = (u8 *) (buf_ptr + loop * 16);
+
+                        bus->i2c_nostop = (size > 16) ? 1 : 0;
+                        bus->i2c_reserve = (loop == 0) ? 0 : 1;
+
+                        /* usb send command */
+                        status = dev->cx231xx_send_usb_command(bus, &req_data);
+                        loop++;
+
+                        if (size >= 16)
+                                size -= 16;
+                        else
+                                size = 0;
+
+                } while (size > 0);
+
+                bus->i2c_nostop = 0;
+                bus->i2c_reserve = 0;
+
+        } else {                /* regular case */
+
+                /* prepare xfer_data struct */
+                req_data.dev_addr = msg->addr;
+                req_data.direction = msg->flags;
+                req_data.saddr_len = 0;
+                req_data.saddr_dat = 0;
+                req_data.buf_size = msg->len;
+                req_data.p_buffer = msg->buf;
+
+                /* usb send command */
+                status = dev->cx231xx_send_usb_command(bus, &req_data);
+        }
+
+        return status < 0 ? status : 0;
+}
+
+/*
+ * cx231xx_i2c_recv_bytes()
+ * read a byte from the i2c device
+ */
+static int cx231xx_i2c_recv_bytes(struct i2c_adapter *i2c_adap,
+                                  const struct i2c_msg *msg)
+{
+        struct cx231xx_i2c *bus = i2c_adap->algo_data;
+        struct cx231xx *dev = bus->dev;
+        struct cx231xx_i2c_xfer_data req_data;
+        int status = 0;
+        u16 saddr = 0;
+        u8 need_gpio = 0;
+
+        if (is_tuner(dev, bus, msg, TUNER_XC5000)) {
+                if (msg->len == 2)
+                        saddr = msg->buf[0] << 8 | msg->buf[1];
+                else if (msg->len == 1)
+                        saddr = msg->buf[0];
+
+                if (dev->xc_fw_load_done) {
+
+                        switch (saddr) {
+                        case 0x0009:    /* BUSY check */
+                                dprintk1(1,
+                                "GPIO R E A D: Special case BUSY check \n");
+                                /*Try read BUSY register, just set it to zero*/
+                                msg->buf[0] = 0;
+                                if (msg->len == 2)
+                                        msg->buf[1] = 0;
+                                return 0;
+                        case 0x0004:    /* read Lock status */
+                                need_gpio = 1;
+                                break;
+
+                        }
+
+                        if (need_gpio) {
+                                /* this is a special case to handle Xceive tuner
+                                clock stretch issue with gpio based I2C */
+
+                                dprintk1(1,
+                                "GPIO R E A D: addr 0x%x, len %d, saddr 0x%x\n",
+                                msg->addr, msg->len,
+                                msg->buf[0] << 8 | msg->buf[1]);
+
+                                status =
+                                    dev->cx231xx_gpio_i2c_write(dev, msg->addr,
+                                                                msg->buf,
+                                                                msg->len);
+                                status =
+                                    dev->cx231xx_gpio_i2c_read(dev, msg->addr,
+                                                               msg->buf,
+                                                               msg->len);
+                                return status;
+                        }
+                }
+
+                /* prepare xfer_data struct */
+                req_data.dev_addr = msg->addr;
+                req_data.direction = msg->flags;
+                req_data.saddr_len = msg->len;
+                req_data.saddr_dat = msg->buf[0] << 8 | msg->buf[1];
+                req_data.buf_size = msg->len;
+                req_data.p_buffer = msg->buf;
+
+                /* usb send command */
+                status = dev->cx231xx_send_usb_command(bus, &req_data);
+
+        } else {
+
+                /* prepare xfer_data struct */
+                req_data.dev_addr = msg->addr;
+                req_data.direction = msg->flags;
+                req_data.saddr_len = 0;
+                req_data.saddr_dat = 0;
+                req_data.buf_size = msg->len;
+                req_data.p_buffer = msg->buf;
+
+                /* usb send command */
+                status = dev->cx231xx_send_usb_command(bus, &req_data);
+        }
+
+        return status < 0 ? status : 0;
+}
+
+/*
+ * cx231xx_i2c_recv_bytes_with_saddr()
+ * read a byte from the i2c device
+ */
+static int cx231xx_i2c_recv_bytes_with_saddr(struct i2c_adapter *i2c_adap,
+                                             const struct i2c_msg *msg1,
+                                             const struct i2c_msg *msg2)
+{
+        struct cx231xx_i2c *bus = i2c_adap->algo_data;
+        struct cx231xx *dev = bus->dev;
+        struct cx231xx_i2c_xfer_data req_data;
+        int status = 0;
+        u16 saddr = 0;
+        u8 need_gpio = 0;
+
+        if (msg1->len == 2)
+                saddr = msg1->buf[0] << 8 | msg1->buf[1];
+        else if (msg1->len == 1)
+                saddr = msg1->buf[0];
+
+        if (is_tuner(dev, bus, msg2, TUNER_XC5000)) {
+                if ((msg2->len < 16)) {
+
+                        dprintk1(1,
+                        "i2c_read: addr 0x%x, len %d, saddr 0x%x, len %d\n",
+                        msg2->addr, msg2->len, saddr, msg1->len);
+
+                        switch (saddr) {
+                        case 0x0008:    /* read FW load status */
+                                need_gpio = 1;
+                                break;
+                        case 0x0004:    /* read Lock status */
+                                need_gpio = 1;
+                                break;
+                        }
+
+                        if (need_gpio) {
+                                status =
+                                    dev->cx231xx_gpio_i2c_write(dev, msg1->addr,
+                                                                msg1->buf,
+                                                                msg1->len);
+                                status =
+                                    dev->cx231xx_gpio_i2c_read(dev, msg2->addr,
+                                                               msg2->buf,
+                                                               msg2->len);
+                                return status;
+                        }
+                }
+        }
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = msg2->addr;
+        req_data.direction = msg2->flags;
+        req_data.saddr_len = msg1->len;
+        req_data.saddr_dat = saddr;
+        req_data.buf_size = msg2->len;
+        req_data.p_buffer = msg2->buf;
+
+        /* usb send command */
+        status = dev->cx231xx_send_usb_command(bus, &req_data);
+
+        return status < 0 ? status : 0;
+}
+
+/*
+ * cx231xx_i2c_check_for_device()
+ * check if there is a i2c_device at the supplied address
+ */
+static int cx231xx_i2c_check_for_device(struct i2c_adapter *i2c_adap,
+                                        const struct i2c_msg *msg)
+{
+        struct cx231xx_i2c *bus = i2c_adap->algo_data;
+        struct cx231xx *dev = bus->dev;
+        struct cx231xx_i2c_xfer_data req_data;
+        int status = 0;
+
+        /* prepare xfer_data struct */
+        req_data.dev_addr = msg->addr;
+        req_data.direction = msg->flags;
+        req_data.saddr_len = 0;
+        req_data.saddr_dat = 0;
+        req_data.buf_size = 0;
+        req_data.p_buffer = NULL;
+
+        /* usb send command */
+        status = dev->cx231xx_send_usb_command(bus, &req_data);
+
+        return status < 0 ? status : 0;
+}
+
+/*
+ * cx231xx_i2c_xfer()
+ * the main i2c transfer function
+ */
+static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
+                            struct i2c_msg msgs[], int num)
+{
+        struct cx231xx_i2c *bus = i2c_adap->algo_data;
+        struct cx231xx *dev = bus->dev;
+        int addr, rc, i, byte;
+
+        if (num <= 0)
+                return 0;
+        mutex_lock(&dev->i2c_lock);
+        for (i = 0; i < num; i++) {
+
+                addr = msgs[i].addr >> 1;
+
+                dprintk2(2, "%s %s addr=%x len=%d:",
+                         (msgs[i].flags & I2C_M_RD) ? "read" : "write",
+                         i == num - 1 ? "stop" : "nonstop", addr, msgs[i].len);
+                if (!msgs[i].len) {
+                        /* no len: check only for device presence */
+                        rc = cx231xx_i2c_check_for_device(i2c_adap, &msgs[i]);
+                        if (rc < 0) {
+                                dprintk2(2, " no device\n");
+                                mutex_unlock(&dev->i2c_lock);
+                                return rc;
+                        }
+
+                } else if (msgs[i].flags & I2C_M_RD) {
+                        /* read bytes */
+                        rc = cx231xx_i2c_recv_bytes(i2c_adap, &msgs[i]);
+                        if (i2c_debug >= 2) {
+                                for (byte = 0; byte < msgs[i].len; byte++)
+                                        printk(" %02x", msgs[i].buf[byte]);
+                        }
+                } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
+                           msgs[i].addr == msgs[i + 1].addr
+                           && (msgs[i].len <= 2) && (bus->nr < 3)) {
+                        /* read bytes */
+                        rc = cx231xx_i2c_recv_bytes_with_saddr(i2c_adap,
+                                                               &msgs[i],
+                                                               &msgs[i + 1]);
+                        if (i2c_debug >= 2) {
+                                for (byte = 0; byte < msgs[i].len; byte++)
+                                        printk(" %02x", msgs[i].buf[byte]);
+                        }
+                        i++;
+                } else {
+                        /* write bytes */
+                        if (i2c_debug >= 2) {
+                                for (byte = 0; byte < msgs[i].len; byte++)
+                                        printk(" %02x", msgs[i].buf[byte]);
+                        }
+                        rc = cx231xx_i2c_send_bytes(i2c_adap, &msgs[i]);
+                }
+                if (rc < 0)
+                        goto err;
+                if (i2c_debug >= 2)
+                        printk("\n");
+        }
+        mutex_unlock(&dev->i2c_lock);
+        return num;
+err:
+        dprintk2(2, " ERROR: %i\n", rc);
+        mutex_unlock(&dev->i2c_lock);
+        return rc;
+}
+
+/* ----------------------------------------------------------- */
+
+/*
+ * functionality()
+ */
+static u32 functionality(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm cx231xx_algo = {
+        .master_xfer = cx231xx_i2c_xfer,
+        .functionality = functionality,
+};
+
+static struct i2c_adapter cx231xx_adap_template = {
+        .owner = THIS_MODULE,
+        .name = "cx231xx",
+        .algo = &cx231xx_algo,
+};
+
+static struct i2c_client cx231xx_client_template = {
+        .name = "cx231xx internal",
+};
+
+/* ----------------------------------------------------------- */
+
+/*
+ * i2c_devs
+ * incomplete list of known devices
+ */
+static char *i2c_devs[128] = {
+        [0x60 >> 1] = "colibri",
+        [0x88 >> 1] = "hammerhead",
+        [0x8e >> 1] = "CIR",
+        [0x32 >> 1] = "GeminiIII",
+        [0x02 >> 1] = "Aquarius",
+        [0xa0 >> 1] = "eeprom",
+        [0xc0 >> 1] = "tuner",
+        [0xc2 >> 1] = "tuner",
+};
+
+/*
+ * cx231xx_do_i2c_scan()
+ * check i2c address range for devices
+ */
+void cx231xx_do_i2c_scan(struct cx231xx *dev, struct i2c_client *c)
+{
+        unsigned char buf;
+        int i, rc;
+
+        cx231xx_info(": Checking for I2C devices ..\n");
+        for (i = 0; i < 128; i++) {
+                c->addr = i;
+                rc = i2c_master_recv(c, &buf, 0);
+                if (rc < 0)
+                        continue;
+                cx231xx_info("%s: i2c scan: found device @ 0x%x  [%s]\n",
+                             dev->name, i << 1,
+                             i2c_devs[i] ? i2c_devs[i] : "???");
+        }
+        cx231xx_info(": Completed Checking for I2C devices.\n");
+}
+
+/*
+ * cx231xx_i2c_register()
+ * register i2c bus
+ */
+int cx231xx_i2c_register(struct cx231xx_i2c *bus)
+{
+        struct cx231xx *dev = bus->dev;
+
+        BUG_ON(!dev->cx231xx_send_usb_command);
+
+        bus->i2c_adap = cx231xx_adap_template;
+        bus->i2c_client = cx231xx_client_template;
+        bus->i2c_adap.dev.parent = &dev->udev->dev;
+
+        strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name));
+
+        bus->i2c_adap.algo_data = bus;
+        i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev);
+        i2c_add_adapter(&bus->i2c_adap);
+
+        bus->i2c_client.adapter = &bus->i2c_adap;
+
+        if (0 == bus->i2c_rc) {
+                if (i2c_scan)
+                        cx231xx_do_i2c_scan(dev, &bus->i2c_client);
+        } else
+                cx231xx_warn("%s: i2c bus %d register FAILED\n",
+                             dev->name, bus->nr);
+
+        return bus->i2c_rc;
+}
+
+/*
+ * cx231xx_i2c_unregister()
+ * unregister i2c_bus
+ */
+int cx231xx_i2c_unregister(struct cx231xx_i2c *bus)
+{
+        i2c_del_adapter(&bus->i2c_adap);
+        return 0;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-input.c b/drivers/media/usb/cx231xx/cx231xx-input.c
new file mode 100644
index 000000000000..96176e9db5a2
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-input.c
@@ -0,0 +1,119 @@
+/*
+ *   cx231xx IR glue driver
+ *
+ *   Copyright (C) 2010 Mauro Carvalho Chehab <mchehab@redhat.com>
+ *
+ *   Polaris (cx231xx) has its support for IR's with a design close to MCE.
+ *   however, a few designs are using an external I2C chip for IR, instead
+ *   of using the one provided by the chip.
+ *   This driver provides support for those extra devices
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License as
+ *   published by the Free Software Foundation version 2.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *   General Public License for more details.
+ */
+
+#include "cx231xx.h"
+#include <linux/usb.h>
+#include <linux/slab.h>
+
+#define MODULE_NAME "cx231xx-input"
+
+static int get_key_isdbt(struct IR_i2c *ir, u32 *ir_key,
+                         u32 *ir_raw)
+{
+        int     rc;
+        u8      cmd, scancode;
+
+        dev_dbg(&ir->rc->input_dev->dev, "%s\n", __func__);
+
+                /* poll IR chip */
+        rc = i2c_master_recv(ir->c, &cmd, 1);
+        if (rc < 0)
+                return rc;
+        if (rc != 1)
+                return -EIO;
+
+        /* it seems that 0xFE indicates that a button is still hold
+           down, while 0xff indicates that no button is hold
+           down. 0xfe sequences are sometimes interrupted by 0xFF */
+
+        if (cmd == 0xff)
+                return 0;
+
+        scancode =
+                 ((cmd & 0x01) ? 0x80 : 0) |
+                 ((cmd & 0x02) ? 0x40 : 0) |
+                 ((cmd & 0x04) ? 0x20 : 0) |
+                 ((cmd & 0x08) ? 0x10 : 0) |
+                 ((cmd & 0x10) ? 0x08 : 0) |
+                 ((cmd & 0x20) ? 0x04 : 0) |
+                 ((cmd & 0x40) ? 0x02 : 0) |
+                 ((cmd & 0x80) ? 0x01 : 0);
+
+        dev_dbg(&ir->rc->input_dev->dev, "cmd %02x, scan = %02x\n",
+                cmd, scancode);
+
+        *ir_key = scancode;
+        *ir_raw = scancode;
+        return 1;
+}
+
+int cx231xx_ir_init(struct cx231xx *dev)
+{
+        struct i2c_board_info info;
+        u8 ir_i2c_bus;
+
+        dev_dbg(&dev->udev->dev, "%s\n", __func__);
+
+        /* Only initialize if a rc keycode map is defined */
+        if (!cx231xx_boards[dev->model].rc_map_name)
+                return -ENODEV;
+
+        request_module("ir-kbd-i2c");
+
+        memset(&info, 0, sizeof(struct i2c_board_info));
+        memset(&dev->init_data, 0, sizeof(dev->init_data));
+        dev->init_data.rc_dev = rc_allocate_device();
+        if (!dev->init_data.rc_dev)
+                return -ENOMEM;
+
+        dev->init_data.name = cx231xx_boards[dev->model].name;
+
+        strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+        info.platform_data = &dev->init_data;
+
+        /*
+         * Board-dependent values
+         *
+         * For now, there's just one type of hardware design using
+         * an i2c device.
+         */
+        dev->init_data.get_key = get_key_isdbt;
+        dev->init_data.ir_codes = cx231xx_boards[dev->model].rc_map_name;
+        /* The i2c micro-controller only outputs the cmd part of NEC protocol */
+        dev->init_data.rc_dev->scanmask = 0xff;
+        dev->init_data.rc_dev->driver_name = "cx231xx";
+        dev->init_data.type = RC_TYPE_NEC;
+        info.addr = 0x30;
+
+        /* Load and bind ir-kbd-i2c */
+        ir_i2c_bus = cx231xx_boards[dev->model].ir_i2c_master;
+        dev_dbg(&dev->udev->dev, "Trying to bind ir at bus %d, addr 0x%02x\n",
+                ir_i2c_bus, info.addr);
+        dev->ir_i2c_client = i2c_new_device(&dev->i2c_bus[ir_i2c_bus].i2c_adap, &info);
+
+        return 0;
+}
+
+void cx231xx_ir_exit(struct cx231xx *dev)
+{
+        if (dev->ir_i2c_client)
+                i2c_unregister_device(dev->ir_i2c_client);
+        dev->ir_i2c_client = NULL;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.c b/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.c
new file mode 100644
index 000000000000..7473c33e823e
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.c
@@ -0,0 +1,795 @@
+/*
+   cx231xx-pcb-config.c - driver for Conexant
+                Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "cx231xx.h"
+#include "cx231xx-conf-reg.h"
+
+static unsigned int pcb_debug;
+module_param(pcb_debug, int, 0644);
+MODULE_PARM_DESC(pcb_debug, "enable pcb config debug messages [video]");
+
+/******************************************************************************/
+
+struct pcb_config cx231xx_Scenario[] = {
+        {
+         INDEX_SELFPOWER_DIGITAL_ONLY,  /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         MOD_DIGITAL,           /* mode */
+         SOURCE_TS_BDA,         /* ts1_source, digital tv only */
+         NOT_SUPPORTED,         /* ts2_source  */
+         NOT_SUPPORTED,         /* analog source */
+
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index   */
+         0,                     /* external_index */
+
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           ,
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed config */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_SELFPOWER_DUAL_DIGITAL,  /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         MOD_DIGITAL,           /* mode */
+         SOURCE_TS_BDA,         /* ts1_source, digital tv only */
+         0,                     /* ts2_source,need update from register */
+         NOT_SUPPORTED,         /* analog source */
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            2,                  /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            2,                  /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_SELFPOWER_ANALOG_ONLY,   /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         MOD_ANALOG | MOD_DIF | MOD_EXTERNAL,   /* mode ,analog tv only */
+         NOT_SUPPORTED,         /* ts1_source, NOT SUPPORT */
+         NOT_SUPPORTED,         /* ts2_source,NOT SUPPORT */
+         0,                     /* analog source, need update */
+
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            1,                  /* AUDIO */
+            2,                  /* VIDEO */
+            3,                  /* VANC */
+            4,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            1,                  /* AUDIO */
+            2,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_SELFPOWER_DUAL,  /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         /* mode ,analog tv and digital path */
+         MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
+         0,                     /* ts1_source,will update in register */
+         NOT_SUPPORTED,         /* ts2_source,NOT SUPPORT */
+         0,                     /* analog source need update */
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            4,                  /* VANC */
+            5,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_SELFPOWER_TRIPLE,        /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         /* mode ,analog tv and digital path */
+         MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
+         0,                     /* ts1_source, update in register */
+         0,                     /* ts2_source,update in register */
+         0,                     /* analog source, need update */
+
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            2,                  /* TS2 index */
+            3,                  /* AUDIO */
+            4,                  /* VIDEO */
+            5,                  /* VANC */
+            6,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            2,                  /* TS2 index */
+            3,                  /* AUDIO */
+            4,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_SELFPOWER_COMPRESSOR,    /* index */
+         USB_SELF_POWER,        /* power_type */
+         0,                     /* speed , not decide yet */
+         /* mode ,analog tv AND DIGITAL path */
+         MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
+         NOT_SUPPORTED,         /* ts1_source, disable */
+         SOURCE_TS_BDA,         /* ts2_source */
+         0,                     /* analog source,need update */
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            1,                  /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            4,                  /* VANC */
+            5,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed  */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            1,                  /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+        {
+         INDEX_BUSPOWER_DIGITAL_ONLY,   /* index */
+         USB_BUS_POWER,         /* power_type */
+         0,                     /* speed , not decide yet */
+         MOD_DIGITAL,           /* mode ,analog tv AND DIGITAL path */
+         SOURCE_TS_BDA,         /* ts1_source, disable */
+         NOT_SUPPORTED,         /* ts2_source */
+         NOT_SUPPORTED,         /* analog source */
+
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index  = 2 */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         /* full-speed */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index  = 2 */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            NOT_SUPPORTED,      /* AUDIO */
+            NOT_SUPPORTED,      /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+        {
+         INDEX_BUSPOWER_ANALOG_ONLY,    /* index */
+         USB_BUS_POWER,         /* power_type */
+         0,                     /* speed , not decide yet */
+         MOD_ANALOG,            /* mode ,analog tv AND DIGITAL path */
+         NOT_SUPPORTED,         /* ts1_source, disable */
+         NOT_SUPPORTED,         /* ts2_source */
+         SOURCE_ANALOG,         /* analog source--analog */
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            1,                  /* AUDIO */
+            2,                  /* VIDEO */
+            3,                  /* VANC */
+            4,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         {                      /* full-speed */
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            NOT_SUPPORTED,      /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            1,                  /* AUDIO */
+            2,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+        {
+         INDEX_BUSPOWER_DIF_ONLY,       /* index */
+         USB_BUS_POWER,         /* power_type */
+         0,                     /* speed , not decide yet */
+         /* mode ,analog tv AND DIGITAL path */
+         MOD_DIF | MOD_ANALOG | MOD_DIGITAL | MOD_EXTERNAL,
+         SOURCE_TS_BDA,         /* ts1_source, disable */
+         NOT_SUPPORTED,         /* ts2_source */
+         SOURCE_DIF | SOURCE_ANALOG | SOURCE_EXTERNAL,  /* analog source, dif */
+         0,                     /* digital_index  */
+         0,                     /* analog index */
+         0,                     /* dif_index */
+         0,                     /* external_index */
+         1,                     /* only one configuration */
+         {
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            4,                  /* VANC */
+            5,                  /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         ,
+         {                      /* full speed */
+          {
+           0,                   /* config index */
+           {
+            0,                  /* interrupt ep index */
+            1,                  /* ts1 index */
+            NOT_SUPPORTED,      /* TS2 index */
+            2,                  /* AUDIO */
+            3,                  /* VIDEO */
+            NOT_SUPPORTED,      /* VANC */
+            NOT_SUPPORTED,      /* HANC */
+            NOT_SUPPORTED       /* ir_index */
+            }
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          ,
+          {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
+                           NOT_SUPPORTED}
+           }
+          }
+         }
+        ,
+
+};
+
+/*****************************************************************/
+
+u32 initialize_cx231xx(struct cx231xx *dev)
+{
+        u32 config_info = 0;
+        struct pcb_config *p_pcb_info;
+        u8 usb_speed = 1;       /* from register,1--HS, 0--FS  */
+        u8 data[4] = { 0, 0, 0, 0 };
+        u32 ts1_source = 0;
+        u32 ts2_source = 0;
+        u32 analog_source = 0;
+        u8 _current_scenario_idx = 0xff;
+
+        ts1_source = SOURCE_TS_BDA;
+        ts2_source = SOURCE_TS_BDA;
+
+        /* read board config register to find out which
+        pcb config it is related to */
+        cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, data, 4);
+
+        config_info = *((u32 *) data);
+        usb_speed = (u8) (config_info & 0x1);
+
+        /* Verify this device belongs to Bus power or Self power device */
+        if (config_info & BUS_POWER) {  /* bus-power */
+                switch (config_info & BUSPOWER_MASK) {
+                case TS1_PORT | BUS_POWER:
+                        cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY].speed =
+                            usb_speed;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY];
+                        _current_scenario_idx = INDEX_BUSPOWER_DIGITAL_ONLY;
+                        break;
+                case AVDEC_ENABLE | BUS_POWER:
+                        cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY].speed =
+                            usb_speed;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY];
+                        _current_scenario_idx = INDEX_BUSPOWER_ANALOG_ONLY;
+                        break;
+                case AVDEC_ENABLE | BUS_POWER | TS1_PORT:
+                        cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY].speed =
+                            usb_speed;
+                        p_pcb_info = &cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY];
+                        _current_scenario_idx = INDEX_BUSPOWER_DIF_ONLY;
+                        break;
+                default:
+                        cx231xx_info("bad config in buspower!!!!\n");
+                        cx231xx_info("config_info=%x\n",
+                                     (config_info & BUSPOWER_MASK));
+                        return 1;
+                }
+        } else {                /* self-power */
+
+                switch (config_info & SELFPOWER_MASK) {
+                case TS1_PORT | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY].speed =
+                            usb_speed;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY];
+                        _current_scenario_idx = INDEX_SELFPOWER_DIGITAL_ONLY;
+                        break;
+                case TS1_TS2_PORT | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].speed =
+                            usb_speed;
+                        cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].
+                            ts2_source = ts2_source;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL];
+                        _current_scenario_idx = INDEX_SELFPOWER_DUAL_DIGITAL;
+                        break;
+                case AVDEC_ENABLE | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].speed =
+                            usb_speed;
+                        cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].
+                            analog_source = analog_source;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY];
+                        _current_scenario_idx = INDEX_SELFPOWER_ANALOG_ONLY;
+                        break;
+                case AVDEC_ENABLE | TS1_PORT | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_DUAL].speed =
+                            usb_speed;
+                        cx231xx_Scenario[INDEX_SELFPOWER_DUAL].ts1_source =
+                            ts1_source;
+                        cx231xx_Scenario[INDEX_SELFPOWER_DUAL].analog_source =
+                            analog_source;
+                        p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_DUAL];
+                        _current_scenario_idx = INDEX_SELFPOWER_DUAL;
+                        break;
+                case AVDEC_ENABLE | TS1_TS2_PORT | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].speed =
+                            usb_speed;
+                        cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts1_source =
+                            ts1_source;
+                        cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts2_source =
+                            ts2_source;
+                        cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].analog_source =
+                            analog_source;
+                        p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE];
+                        _current_scenario_idx = INDEX_SELFPOWER_TRIPLE;
+                        break;
+                case AVDEC_ENABLE | TS1VIP_TS2_PORT | SELF_POWER:
+                        cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].speed =
+                            usb_speed;
+                        cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].
+                            analog_source = analog_source;
+                        p_pcb_info =
+                            &cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR];
+                        _current_scenario_idx = INDEX_SELFPOWER_COMPRESSOR;
+                        break;
+                default:
+                        cx231xx_info("bad senario!!!!!\n");
+                        cx231xx_info("config_info=%x\n",
+                                     (config_info & SELFPOWER_MASK));
+                        return 1;
+                }
+        }
+
+        dev->current_scenario_idx = _current_scenario_idx;
+
+        memcpy(&dev->current_pcb_config, p_pcb_info,
+                   sizeof(struct pcb_config));
+
+        if (pcb_debug) {
+                cx231xx_info("SC(0x00) register = 0x%x\n", config_info);
+                cx231xx_info("scenario %d\n",
+                            (dev->current_pcb_config.index) + 1);
+                cx231xx_info("type=%x\n", dev->current_pcb_config.type);
+                cx231xx_info("mode=%x\n", dev->current_pcb_config.mode);
+                cx231xx_info("speed=%x\n", dev->current_pcb_config.speed);
+                cx231xx_info("ts1_source=%x\n",
+                             dev->current_pcb_config.ts1_source);
+                cx231xx_info("ts2_source=%x\n",
+                             dev->current_pcb_config.ts2_source);
+                cx231xx_info("analog_source=%x\n",
+                             dev->current_pcb_config.analog_source);
+        }
+
+        return 0;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.h b/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.h
new file mode 100644
index 000000000000..f5e46e89f3ab
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-pcb-cfg.h
@@ -0,0 +1,231 @@
+/*
+   cx231xx-pcb-cfg.h - driver for Conexant
+                Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PCB_CONFIG_H_
+#define _PCB_CONFIG_H_
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+/***************************************************************************
+                                * Class Information *
+***************************************************************************/
+#define CLASS_DEFAULT       0xFF
+
+enum VENDOR_REQUEST_TYPE {
+        /* Set/Get I2C */
+        VRT_SET_I2C0 = 0x0,
+        VRT_SET_I2C1 = 0x1,
+        VRT_SET_I2C2 = 0x2,
+        VRT_GET_I2C0 = 0x4,
+        VRT_GET_I2C1 = 0x5,
+        VRT_GET_I2C2 = 0x6,
+
+        /* Set/Get GPIO */
+        VRT_SET_GPIO = 0x8,
+        VRT_GET_GPIO = 0x9,
+
+        /* Set/Get GPIE */
+        VRT_SET_GPIE = 0xA,
+        VRT_GET_GPIE = 0xB,
+
+        /* Set/Get Register Control/Status */
+        VRT_SET_REGISTER = 0xC,
+        VRT_GET_REGISTER = 0xD,
+
+        /* Get Extended Compat ID Descriptor */
+        VRT_GET_EXTCID_DESC = 0xFF,
+};
+
+enum BYTE_ENABLE_MASK {
+        ENABLE_ONE_BYTE = 0x1,
+        ENABLE_TWE_BYTE = 0x3,
+        ENABLE_THREE_BYTE = 0x7,
+        ENABLE_FOUR_BYTE = 0xF,
+};
+
+#define SPEED_MASK      0x1
+enum USB_SPEED{
+        FULL_SPEED = 0x0,       /* 0: full speed */
+        HIGH_SPEED = 0x1        /* 1: high speed */
+};
+
+enum _true_false{
+        FALSE = 0,
+        TRUE = 1
+};
+
+#define TS_MASK         0x6
+enum TS_PORT{
+        NO_TS_PORT = 0x0,       /* 2'b00: Neither port used. PCB not a Hybrid,
+                                   only offers Analog TV or Video */
+        TS1_PORT = 0x4,         /* 2'b10: TS1 Input (Hybrid mode :
+                                Digital or External Analog/Compressed source) */
+        TS1_TS2_PORT = 0x6,     /* 2'b11: TS1 & TS2 Inputs
+                                (Dual inputs from Digital and/or
+                                External Analog/Compressed sources) */
+        TS1_EXT_CLOCK = 0x6,    /* 2'b11: TS1 & TS2 as selector
+                                                to external clock */
+        TS1VIP_TS2_PORT = 0x2   /* 2'b01: TS1 used as 656/VIP Output,
+                                   TS2 Input (from Compressor) */
+};
+
+#define EAVP_MASK       0x8
+enum EAV_PRESENT{
+        NO_EXTERNAL_AV = 0x0,   /* 0: No External A/V inputs
+                                                (no need for i2s blcok),
+                                                Analog Tuner must be present */
+        EXTERNAL_AV = 0x8       /* 1: External A/V inputs
+                                                present (requires i2s blk) */
+};
+
+#define ATM_MASK        0x30
+enum AT_MODE{
+        DIF_TUNER = 0x30,       /* 2'b11: IF Tuner (requires use of DIF) */
+        BASEBAND_SOUND = 0x20,  /* 2'b10: Baseband Composite &
+                                                Sound-IF Signals present */
+        NO_TUNER = 0x10         /* 2'b0x: No Analog Tuner present */
+};
+
+#define PWR_SEL_MASK    0x40
+enum POWE_TYPE{
+        SELF_POWER = 0x0,       /* 0: self power */
+        BUS_POWER = 0x40        /* 1: bus power */
+};
+
+enum USB_POWE_TYPE{
+        USB_SELF_POWER = 0,
+        USB_BUS_POWER
+};
+
+#define BO_0_MASK       0x80
+enum AVDEC_STATUS{
+        AVDEC_DISABLE = 0x0,    /* 0: A/V Decoder Disabled */
+        AVDEC_ENABLE = 0x80     /* 1: A/V Decoder Enabled */
+};
+
+#define BO_1_MASK       0x100
+
+#define BUSPOWER_MASK   0xC4    /* for Polaris spec 0.8 */
+#define SELFPOWER_MASK  0x86
+
+/***************************************************************************/
+#define NOT_DECIDE_YET  0xFE
+#define NOT_SUPPORTED   0xFF
+
+/***************************************************************************
+                                * for mod field use *
+***************************************************************************/
+#define MOD_DIGITAL     0x1
+#define MOD_ANALOG      0x2
+#define MOD_DIF         0x4
+#define MOD_EXTERNAL    0x8
+#define CAP_ALL_MOD     0x0f
+
+/***************************************************************************
+                                * source define *
+***************************************************************************/
+#define SOURCE_DIGITAL          0x1
+#define SOURCE_ANALOG           0x2
+#define SOURCE_DIF              0x4
+#define SOURCE_EXTERNAL         0x8
+#define SOURCE_TS_BDA                   0x10
+#define SOURCE_TS_ENCODE                0x20
+#define SOURCE_TS_EXTERNAL      0x40
+
+/***************************************************************************
+                                * interface information define *
+***************************************************************************/
+struct INTERFACE_INFO {
+        u8 interrupt_index;
+        u8 ts1_index;
+        u8 ts2_index;
+        u8 audio_index;
+        u8 video_index;
+        u8 vanc_index;          /* VBI */
+        u8 hanc_index;          /* Sliced CC */
+        u8 ir_index;
+};
+
+enum INDEX_INTERFACE_INFO{
+        INDEX_INTERRUPT = 0x0,
+        INDEX_TS1,
+        INDEX_TS2,
+        INDEX_AUDIO,
+        INDEX_VIDEO,
+        INDEX_VANC,
+        INDEX_HANC,
+        INDEX_IR,
+};
+
+/***************************************************************************
+                                * configuration information define *
+***************************************************************************/
+struct CONFIG_INFO {
+        u8 config_index;
+        struct INTERFACE_INFO interface_info;
+};
+
+struct pcb_config {
+        u8 index;
+        u8 type;                /* bus power or self power,
+                                           self power--0, bus_power--1 */
+        u8 speed;               /* usb speed, 2.0--1, 1.1--0 */
+        u8 mode;                /* digital , anlog, dif or external A/V */
+        u32 ts1_source;         /* three source -- BDA,External,encode */
+        u32 ts2_source;
+        u32 analog_source;
+        u8 digital_index;       /* bus-power used */
+        u8 analog_index;        /* bus-power used */
+        u8 dif_index;           /* bus-power used */
+        u8 external_index;      /* bus-power used */
+        u8 config_num;          /* current config num, 0,1,2,
+                                                   for self-power, always 0 */
+        struct CONFIG_INFO hs_config_info[3];
+        struct CONFIG_INFO fs_config_info[3];
+};
+
+enum INDEX_PCB_CONFIG{
+        INDEX_SELFPOWER_DIGITAL_ONLY = 0x0,
+        INDEX_SELFPOWER_DUAL_DIGITAL,
+        INDEX_SELFPOWER_ANALOG_ONLY,
+        INDEX_SELFPOWER_DUAL,
+        INDEX_SELFPOWER_TRIPLE,
+        INDEX_SELFPOWER_COMPRESSOR,
+        INDEX_BUSPOWER_DIGITAL_ONLY,
+        INDEX_BUSPOWER_ANALOG_ONLY,
+        INDEX_BUSPOWER_DIF_ONLY,
+        INDEX_BUSPOWER_EXTERNAL_ONLY,
+        INDEX_BUSPOWER_EXTERNAL_ANALOG,
+        INDEX_BUSPOWER_EXTERNAL_DIF,
+        INDEX_BUSPOWER_EXTERNAL_DIGITAL,
+        INDEX_BUSPOWER_DIGITAL_ANALOG,
+        INDEX_BUSPOWER_DIGITAL_DIF,
+        INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL,
+        INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL,
+};
+
+/***************************************************************************/
+struct cx231xx;
+
+u32 initialize_cx231xx(struct cx231xx *p_dev);
+
+#endif
diff --git a/drivers/media/usb/cx231xx/cx231xx-reg.h b/drivers/media/usb/cx231xx/cx231xx-reg.h
new file mode 100644
index 000000000000..750c5d37d569
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-reg.h
@@ -0,0 +1,1564 @@
+/*
+   cx231xx-reg.h - driver for Conexant Cx23100/101/102
+               USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _CX231XX_REG_H
+#define _CX231XX_REG_H
+
+/*****************************************************************************
+                                * VBI codes *
+*****************************************************************************/
+
+#define SAV_ACTIVE_VIDEO_FIELD1         0x80
+#define EAV_ACTIVE_VIDEO_FIELD1         0x90
+
+#define SAV_ACTIVE_VIDEO_FIELD2         0xc0
+#define EAV_ACTIVE_VIDEO_FIELD2         0xd0
+
+#define SAV_VBLANK_FIELD1               0xa0
+#define EAV_VBLANK_FIELD1               0xb0
+
+#define SAV_VBLANK_FIELD2               0xe0
+#define EAV_VBLANK_FIELD2               0xf0
+
+#define SAV_VBI_FIELD1                  0x20
+#define EAV_VBI_FIELD1                  0x30
+
+#define SAV_VBI_FIELD2                  0x60
+#define EAV_VBI_FIELD2                  0x70
+
+/*****************************************************************************/
+/* Audio ADC Registers */
+#define CH_PWR_CTRL1                    0x0000000e
+#define CH_PWR_CTRL2                    0x0000000f
+/*****************************************************************************/
+
+#define      HOST_REG1                0x000
+#define      FLD_FORCE_CHIP_SEL       0x80
+#define      FLD_AUTO_INC_DIS         0x20
+#define      FLD_PREFETCH_EN          0x10
+/* Reserved [2:3] */
+#define      FLD_DIGITAL_PWR_DN       0x02
+#define      FLD_SLEEP                0x01
+
+/*****************************************************************************/
+#define      HOST_REG2                0x001
+
+/*****************************************************************************/
+#define      HOST_REG3                0x002
+
+/*****************************************************************************/
+/* added for polaris */
+#define      GPIO_PIN_CTL0            0x3
+#define      GPIO_PIN_CTL1            0x4
+#define      GPIO_PIN_CTL2            0x5
+#define      GPIO_PIN_CTL3            0x6
+#define      TS1_PIN_CTL0             0x7
+#define      TS1_PIN_CTL1             0x8
+/*****************************************************************************/
+
+#define      FLD_CLK_IN_EN            0x80
+#define      FLD_XTAL_CTRL            0x70
+#define      FLD_BB_CLK_MODE          0x0C
+#define      FLD_REF_DIV_PLL          0x02
+#define      FLD_REF_SEL_PLL1         0x01
+
+/*****************************************************************************/
+#define      CHIP_CTRL                0x100
+/* Reserved [27] */
+/* Reserved [31:21] */
+#define      FLD_CHIP_ACFG_DIS        0x00100000
+/* Reserved [19] */
+#define      FLD_DUAL_MODE_ADC2       0x00040000
+#define      FLD_SIF_EN               0x00020000
+#define      FLD_SOFT_RST             0x00010000
+#define      FLD_DEVICE_ID            0x0000ffff
+
+/*****************************************************************************/
+#define      AFE_CTRL                 0x104
+#define      AFE_CTRL_C2HH_SRC_CTRL   0x104
+#define      FLD_DIF_OUT_SEL          0xc0000000
+#define      FLD_AUX_PLL_CLK_ALT_SEL  0x3c000000
+#define      FLD_UV_ORDER_MODE        0x02000000
+#define      FLD_FUNC_MODE            0x01800000
+#define      FLD_ROT1_PHASE_CTL       0x007f8000
+#define      FLD_AUD_IN_SEL           0x00004000
+#define      FLD_LUMA_IN_SEL          0x00002000
+#define      FLD_CHROMA_IN_SEL        0x00001000
+/* reserve [11:10] */
+#define      FLD_INV_SPEC_DIS         0x00000200
+#define      FLD_VGA_SEL_CH3          0x00000100
+#define      FLD_VGA_SEL_CH2          0x00000080
+#define      FLD_VGA_SEL_CH1          0x00000040
+#define      FLD_DCR_BYP_CH1          0x00000020
+#define      FLD_DCR_BYP_CH2          0x00000010
+#define      FLD_DCR_BYP_CH3          0x00000008
+#define      FLD_EN_12DB_CH3          0x00000004
+#define      FLD_EN_12DB_CH2          0x00000002
+#define      FLD_EN_12DB_CH1          0x00000001
+
+/* redefine in Cx231xx */
+/*****************************************************************************/
+#define      DC_CTRL1                 0x108
+/* reserve [31:30] */
+#define      FLD_CLAMP_LVL_CH1        0x3fff8000
+#define      FLD_CLAMP_LVL_CH2        0x00007fff
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      DC_CTRL2                 0x10c
+/* reserve [31:28] */
+#define      FLD_CLAMP_LVL_CH3        0x00fffe00
+#define      FLD_CLAMP_WIND_LENTH     0x000001e0
+#define      FLD_C2HH_SAT_MIN         0x0000001e
+#define      FLD_FLT_BYP_SEL          0x00000001
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      DC_CTRL3                 0x110
+/* reserve [31:16] */
+#define      FLD_ERR_GAIN_CTL         0x00070000
+#define      FLD_LPF_MIN              0x0000ffff
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      DC_CTRL4                 0x114
+/* reserve [31:31] */
+#define      FLD_INTG_CH1             0x7fffffff
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      DC_CTRL5                 0x118
+/* reserve [31:31] */
+#define      FLD_INTG_CH2             0x7fffffff
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      DC_CTRL6                 0x11c
+/* reserve [31:31] */
+#define      FLD_INTG_CH3             0x7fffffff
+/*****************************************************************************/
+
+/*****************************************************************************/
+#define      PIN_CTRL                 0x120
+#define      FLD_OEF_AGC_RF           0x00000001
+#define      FLD_OEF_AGC_IFVGA        0x00000002
+#define      FLD_OEF_AGC_IF           0x00000004
+#define      FLD_REG_BO_PUD           0x80000000
+#define      FLD_IR_IRQ_STAT          0x40000000
+#define      FLD_AUD_IRQ_STAT         0x20000000
+#define      FLD_VID_IRQ_STAT         0x10000000
+/* Reserved [27:26] */
+#define      FLD_IRQ_N_OUT_EN         0x02000000
+#define      FLD_IRQ_N_POLAR          0x01000000
+/* Reserved [23:6] */
+#define      FLD_OE_AUX_PLL_CLK       0x00000020
+#define      FLD_OE_I2S_BCLK          0x00000010
+#define      FLD_OE_I2S_WCLK          0x00000008
+#define      FLD_OE_AGC_IF            0x00000004
+#define      FLD_OE_AGC_IFVGA         0x00000002
+#define      FLD_OE_AGC_RF            0x00000001
+
+/*****************************************************************************/
+#define      AUD_IO_CTRL              0x124
+/* Reserved [31:8] */
+#define      FLD_I2S_PORT_DIR         0x00000080
+#define      FLD_I2S_OUT_SRC          0x00000040
+#define      FLD_AUD_CHAN3_SRC        0x00000030
+#define      FLD_AUD_CHAN2_SRC        0x0000000c
+#define      FLD_AUD_CHAN1_SRC        0x00000003
+
+/*****************************************************************************/
+#define      AUD_LOCK1                0x128
+#define      FLD_AUD_LOCK_KI_SHIFT    0xc0000000
+#define      FLD_AUD_LOCK_KD_SHIFT    0x30000000
+/* Reserved [27:25] */
+#define      FLD_EN_AV_LOCK           0x01000000
+#define      FLD_VID_COUNT            0x00ffffff
+
+/*****************************************************************************/
+#define      AUD_LOCK2                0x12c
+#define      FLD_AUD_LOCK_KI_MULT     0xf0000000
+#define      FLD_AUD_LOCK_KD_MULT     0x0F000000
+/* Reserved [23:22] */
+#define      FLD_AUD_LOCK_FREQ_SHIFT  0x00300000
+#define      FLD_AUD_COUNT            0x000fffff
+
+/*****************************************************************************/
+#define      AFE_DIAG_CTRL1           0x134
+/* Reserved [31:16] */
+#define      FLD_CUV_DLY_LENGTH       0x0000ff00
+#define      FLD_YC_DLY_LENGTH        0x000000ff
+
+/*****************************************************************************/
+/* Poalris redefine */
+#define      AFE_DIAG_CTRL3           0x138
+/* Reserved [31:26] */
+#define      FLD_AUD_DUAL_FLAG_POL    0x02000000
+#define      FLD_VID_DUAL_FLAG_POL    0x01000000
+/* Reserved [23:23] */
+#define      FLD_COL_CLAMP_DIS_CH1    0x00400000
+#define      FLD_COL_CLAMP_DIS_CH2    0x00200000
+#define      FLD_COL_CLAMP_DIS_CH3    0x00100000
+
+#define      TEST_CTRL1               0x144
+/* Reserved [31:29] */
+#define      FLD_LBIST_EN             0x10000000
+/* Reserved [27:10] */
+#define      FLD_FI_BIST_INTR_R       0x0000200
+#define      FLD_FI_BIST_INTR_L       0x0000100
+#define      FLD_BIST_FAIL_AUD_PLL    0x0000080
+#define      FLD_BIST_INTR_AUD_PLL    0x0000040
+#define      FLD_BIST_FAIL_VID_PLL    0x0000020
+#define      FLD_BIST_INTR_VID_PLL    0x0000010
+/* Reserved [3:1] */
+#define      FLD_CIR_TEST_DIS         0x00000001
+
+/*****************************************************************************/
+#define      TEST_CTRL2               0x148
+#define      FLD_TSXCLK_POL_CTL       0x80000000
+#define      FLD_ISO_CTL_SEL          0x40000000
+#define      FLD_ISO_CTL_EN           0x20000000
+#define      FLD_BIST_DEBUGZ          0x10000000
+#define      FLD_AUD_BIST_TEST_H      0x0f000000
+/* Reserved [23:22] */
+#define      FLD_FLTRN_BIST_TEST_H    0x00020000
+#define      FLD_VID_BIST_TEST_H      0x00010000
+/* Reserved [19:17] */
+#define      FLD_BIST_TEST_H          0x00010000
+/* Reserved [15:13] */
+#define      FLD_TAB_EN               0x00001000
+/* Reserved [11:0] */
+
+/*****************************************************************************/
+#define      BIST_STAT                0x14c
+#define      FLD_AUD_BIST_FAIL_H      0xfff00000
+#define      FLD_FLTRN_BIST_FAIL_H    0x00180000
+#define      FLD_VID_BIST_FAIL_H      0x00070000
+#define      FLD_AUD_BIST_TST_DONE    0x0000fff0
+#define      FLD_FLTRN_BIST_TST_DONE  0x00000008
+#define      FLD_VID_BIST_TST_DONE    0x00000007
+
+/*****************************************************************************/
+/* DirectIF registers definition have been moved to DIF_reg.h                */
+/*****************************************************************************/
+#define      MODE_CTRL                0x400
+#define      FLD_AFD_PAL60_DIS        0x20000000
+#define      FLD_AFD_FORCE_SECAM      0x10000000
+#define      FLD_AFD_FORCE_PALNC      0x08000000
+#define      FLD_AFD_FORCE_PAL        0x04000000
+#define      FLD_AFD_PALM_SEL         0x03000000
+#define      FLD_CKILL_MODE           0x00300000
+#define      FLD_COMB_NOTCH_MODE      0x00c00000       /* bit[19:18] */
+#define      FLD_CLR_LOCK_STAT        0x00020000
+#define      FLD_FAST_LOCK_MD         0x00010000
+#define      FLD_WCEN                 0x00008000
+#define      FLD_CAGCEN               0x00004000
+#define      FLD_CKILLEN              0x00002000
+#define      FLD_AUTO_SC_LOCK         0x00001000
+#define      FLD_MAN_SC_FAST_LOCK     0x00000800
+#define      FLD_INPUT_MODE           0x00000600
+#define      FLD_AFD_ACQUIRE          0x00000100
+#define      FLD_AFD_NTSC_SEL         0x00000080
+#define      FLD_AFD_PAL_SEL          0x00000040
+#define      FLD_ACFG_DIS             0x00000020
+#define      FLD_SQ_PIXEL             0x00000010
+#define      FLD_VID_FMT_SEL          0x0000000f
+
+/*****************************************************************************/
+#define      OUT_CTRL1                0x404
+#define      FLD_POLAR                0x7f000000
+/* Reserved [23] */
+#define      FLD_RND_MODE             0x00600000
+#define      FLD_VIPCLAMP_EN          0x00100000
+#define      FLD_VIPBLANK_EN          0x00080000
+#define      FLD_VIP_OPT_AL           0x00040000
+#define      FLD_IDID0_SOURCE         0x00020000
+#define      FLD_DCMODE               0x00010000
+#define      FLD_CLK_GATING           0x0000c000
+#define      FLD_CLK_INVERT           0x00002000
+#define      FLD_HSFMT                0x00001000
+#define      FLD_VALIDFMT             0x00000800
+#define      FLD_ACTFMT               0x00000400
+#define      FLD_SWAPRAW              0x00000200
+#define      FLD_CLAMPRAW_EN          0x00000100
+#define      FLD_BLUE_FIELD_EN        0x00000080
+#define      FLD_BLUE_FIELD_ACT       0x00000040
+#define      FLD_TASKBIT_VAL          0x00000020
+#define      FLD_ANC_DATA_EN          0x00000010
+#define      FLD_VBIHACTRAW_EN        0x00000008
+#define      FLD_MODE10B              0x00000004
+#define      FLD_OUT_MODE             0x00000003
+
+/*****************************************************************************/
+#define      OUT_CTRL2                0x408
+#define      FLD_AUD_GRP              0xc0000000
+#define      FLD_SAMPLE_RATE          0x30000000
+#define      FLD_AUD_ANC_EN           0x08000000
+#define      FLD_EN_C                 0x04000000
+#define      FLD_EN_B                 0x02000000
+#define      FLD_EN_A                 0x01000000
+/* Reserved [23:20] */
+#define      FLD_IDID1_LSB            0x000c0000
+#define      FLD_IDID0_LSB            0x00030000
+#define      FLD_IDID1_MSB            0x0000ff00
+#define      FLD_IDID0_MSB            0x000000ff
+
+/*****************************************************************************/
+#define      GEN_STAT                 0x40c
+#define      FLD_VCR_DETECT           0x00800000
+#define      FLD_SPECIAL_PLAY_N       0x00400000
+#define      FLD_VPRES                0x00200000
+#define      FLD_AGC_LOCK             0x00100000
+#define      FLD_CSC_LOCK             0x00080000
+#define      FLD_VLOCK                0x00040000
+#define      FLD_SRC_LOCK             0x00020000
+#define      FLD_HLOCK                0x00010000
+#define      FLD_VSYNC_N              0x00008000
+#define      FLD_SRC_FIFO_UFLOW       0x00004000
+#define      FLD_SRC_FIFO_OFLOW       0x00002000
+#define      FLD_FIELD                0x00001000
+#define      FLD_AFD_FMT_STAT         0x00000f00
+#define      FLD_MV_TYPE2_PAIR        0x00000080
+#define      FLD_MV_T3CS              0x00000040
+#define      FLD_MV_CS                0x00000020
+#define      FLD_MV_PSP               0x00000010
+/* Reserved [3] */
+#define      FLD_MV_CDAT              0x00000003
+
+/*****************************************************************************/
+#define      INT_STAT_MASK            0x410
+#define      FLD_COMB_3D_FIFO_MSK     0x80000000
+#define      FLD_WSS_DAT_AVAIL_MSK    0x40000000
+#define      FLD_GS2_DAT_AVAIL_MSK    0x20000000
+#define      FLD_GS1_DAT_AVAIL_MSK    0x10000000
+#define      FLD_CC_DAT_AVAIL_MSK     0x08000000
+#define      FLD_VPRES_CHANGE_MSK     0x04000000
+#define      FLD_MV_CHANGE_MSK        0x02000000
+#define      FLD_END_VBI_EVEN_MSK     0x01000000
+#define      FLD_END_VBI_ODD_MSK      0x00800000
+#define      FLD_FMT_CHANGE_MSK       0x00400000
+#define      FLD_VSYNC_TRAIL_MSK      0x00200000
+#define      FLD_HLOCK_CHANGE_MSK     0x00100000
+#define      FLD_VLOCK_CHANGE_MSK     0x00080000
+#define      FLD_CSC_LOCK_CHANGE_MSK  0x00040000
+#define      FLD_SRC_FIFO_UFLOW_MSK   0x00020000
+#define      FLD_SRC_FIFO_OFLOW_MSK   0x00010000
+#define      FLD_COMB_3D_FIFO_STAT    0x00008000
+#define      FLD_WSS_DAT_AVAIL_STAT   0x00004000
+#define      FLD_GS2_DAT_AVAIL_STAT   0x00002000
+#define      FLD_GS1_DAT_AVAIL_STAT   0x00001000
+#define      FLD_CC_DAT_AVAIL_STAT    0x00000800
+#define      FLD_VPRES_CHANGE_STAT    0x00000400
+#define      FLD_MV_CHANGE_STAT       0x00000200
+#define      FLD_END_VBI_EVEN_STAT    0x00000100
+#define      FLD_END_VBI_ODD_STAT     0x00000080
+#define      FLD_FMT_CHANGE_STAT      0x00000040
+#define      FLD_VSYNC_TRAIL_STAT     0x00000020
+#define      FLD_HLOCK_CHANGE_STAT    0x00000010
+#define      FLD_VLOCK_CHANGE_STAT    0x00000008
+#define      FLD_CSC_LOCK_CHANGE_STAT 0x00000004
+#define      FLD_SRC_FIFO_UFLOW_STAT  0x00000002
+#define      FLD_SRC_FIFO_OFLOW_STAT  0x00000001
+
+/*****************************************************************************/
+#define      LUMA_CTRL                0x414
+#define      BRIGHTNESS_CTRL_BYTE     0x414
+#define      CONTRAST_CTRL_BYTE       0x415
+#define      LUMA_CTRL_BYTE_3         0x416
+#define      FLD_LUMA_CORE_SEL        0x00c00000
+#define      FLD_RANGE                0x00300000
+/* Reserved [19] */
+#define      FLD_PEAK_EN              0x00040000
+#define      FLD_PEAK_SEL             0x00030000
+#define      FLD_CNTRST               0x0000ff00
+#define      FLD_BRITE                0x000000ff
+
+/*****************************************************************************/
+#define      HSCALE_CTRL              0x418
+#define      FLD_HFILT                0x03000000
+#define      FLD_HSCALE               0x00ffffff
+
+/*****************************************************************************/
+#define      VSCALE_CTRL              0x41c
+#define      FLD_LINE_AVG_DIS         0x01000000
+/* Reserved [23:20] */
+#define      FLD_VS_INTRLACE          0x00080000
+#define      FLD_VFILT                0x00070000
+/* Reserved [15:13] */
+#define      FLD_VSCALE               0x00001fff
+
+/*****************************************************************************/
+#define      CHROMA_CTRL              0x420
+#define      USAT_CTRL_BYTE           0x420
+#define      VSAT_CTRL_BYTE           0x421
+#define      HUE_CTRL_BYTE            0x422
+#define      FLD_C_LPF_EN             0x20000000
+#define      FLD_CHR_DELAY            0x1c000000
+#define      FLD_C_CORE_SEL           0x03000000
+#define      FLD_HUE                  0x00ff0000
+#define      FLD_VSAT                 0x0000ff00
+#define      FLD_USAT                 0x000000ff
+
+/*****************************************************************************/
+#define      VBI_LINE_CTRL1           0x424
+#define      FLD_VBI_MD_LINE4         0xff000000
+#define      FLD_VBI_MD_LINE3         0x00ff0000
+#define      FLD_VBI_MD_LINE2         0x0000ff00
+#define      FLD_VBI_MD_LINE1         0x000000ff
+
+/*****************************************************************************/
+#define      VBI_LINE_CTRL2           0x428
+#define      FLD_VBI_MD_LINE8         0xff000000
+#define      FLD_VBI_MD_LINE7         0x00ff0000
+#define      FLD_VBI_MD_LINE6         0x0000ff00
+#define      FLD_VBI_MD_LINE5         0x000000ff
+
+/*****************************************************************************/
+#define      VBI_LINE_CTRL3           0x42c
+#define      FLD_VBI_MD_LINE12        0xff000000
+#define      FLD_VBI_MD_LINE11        0x00ff0000
+#define      FLD_VBI_MD_LINE10        0x0000ff00
+#define      FLD_VBI_MD_LINE9         0x000000ff
+
+/*****************************************************************************/
+#define      VBI_LINE_CTRL4           0x430
+#define      FLD_VBI_MD_LINE16        0xff000000
+#define      FLD_VBI_MD_LINE15        0x00ff0000
+#define      FLD_VBI_MD_LINE14        0x0000ff00
+#define      FLD_VBI_MD_LINE13        0x000000ff
+
+/*****************************************************************************/
+#define      VBI_LINE_CTRL5           0x434
+#define      FLD_VBI_MD_LINE17        0x000000ff
+
+/*****************************************************************************/
+#define      VBI_FC_CFG               0x438
+#define      FLD_FC_ALT2              0xff000000
+#define      FLD_FC_ALT1              0x00ff0000
+#define      FLD_FC_ALT2_TYPE         0x0000f000
+#define      FLD_FC_ALT1_TYPE         0x00000f00
+/* Reserved [7:1] */
+#define      FLD_FC_SEARCH_MODE       0x00000001
+
+/*****************************************************************************/
+#define      VBI_MISC_CFG1            0x43c
+#define      FLD_TTX_PKTADRU          0xfff00000
+#define      FLD_TTX_PKTADRL          0x000fff00
+/* Reserved [7:6] */
+#define      FLD_MOJI_PACK_DIS        0x00000020
+#define      FLD_VPS_DEC_DIS          0x00000010
+#define      FLD_CRI_MARG_SCALE       0x0000000c
+#define      FLD_EDGE_RESYNC_EN       0x00000002
+#define      FLD_ADAPT_SLICE_DIS      0x00000001
+
+/*****************************************************************************/
+#define      VBI_MISC_CFG2            0x440
+#define      FLD_HAMMING_TYPE         0x0f000000
+/* Reserved [23:20] */
+#define      FLD_WSS_FIFO_RST         0x00080000
+#define      FLD_GS2_FIFO_RST         0x00040000
+#define      FLD_GS1_FIFO_RST         0x00020000
+#define      FLD_CC_FIFO_RST          0x00010000
+/* Reserved [15:12] */
+#define      FLD_VBI3_SDID            0x00000f00
+#define      FLD_VBI2_SDID            0x000000f0
+#define      FLD_VBI1_SDID            0x0000000f
+
+/*****************************************************************************/
+#define      VBI_PAY1                 0x444
+#define      FLD_GS1_FIFO_DAT         0xFF000000
+#define      FLD_GS1_STAT             0x00FF0000
+#define      FLD_CC_FIFO_DAT          0x0000FF00
+#define      FLD_CC_STAT              0x000000FF
+
+/*****************************************************************************/
+#define      VBI_PAY2                 0x448
+#define      FLD_WSS_FIFO_DAT         0xff000000
+#define      FLD_WSS_STAT             0x00ff0000
+#define      FLD_GS2_FIFO_DAT         0x0000ff00
+#define      FLD_GS2_STAT             0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST1_CFG1           0x44c
+/* Reserved [31] */
+#define      FLD_VBI1_CRIWIN          0x7f000000
+#define      FLD_VBI1_SLICE_DIST      0x00f00000
+#define      FLD_VBI1_BITINC          0x000fff00
+#define      FLD_VBI1_HDELAY          0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST1_CFG2           0x450
+#define      FLD_VBI1_FC_LENGTH       0x1f000000
+#define      FLD_VBI1_FRAME_CODE      0x00ffffff
+
+/*****************************************************************************/
+#define      VBI_CUST1_CFG3           0x454
+#define      FLD_VBI1_HAM_EN          0x80000000
+#define      FLD_VBI1_FIFO_MODE       0x70000000
+#define      FLD_VBI1_FORMAT_TYPE     0x0f000000
+#define      FLD_VBI1_PAYLD_LENGTH    0x00ff0000
+#define      FLD_VBI1_CRI_LENGTH      0x0000f000
+#define      FLD_VBI1_CRI_MARGIN      0x00000f00
+#define      FLD_VBI1_CRI_TIME        0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST2_CFG1           0x458
+/* Reserved [31] */
+#define      FLD_VBI2_CRIWIN          0x7f000000
+#define      FLD_VBI2_SLICE_DIST      0x00f00000
+#define      FLD_VBI2_BITINC          0x000fff00
+#define      FLD_VBI2_HDELAY          0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST2_CFG2           0x45c
+#define      FLD_VBI2_FC_LENGTH       0x1f000000
+#define      FLD_VBI2_FRAME_CODE      0x00ffffff
+
+/*****************************************************************************/
+#define      VBI_CUST2_CFG3           0x460
+#define      FLD_VBI2_HAM_EN          0x80000000
+#define      FLD_VBI2_FIFO_MODE       0x70000000
+#define      FLD_VBI2_FORMAT_TYPE     0x0f000000
+#define      FLD_VBI2_PAYLD_LENGTH    0x00ff0000
+#define      FLD_VBI2_CRI_LENGTH      0x0000f000
+#define      FLD_VBI2_CRI_MARGIN      0x00000f00
+#define      FLD_VBI2_CRI_TIME        0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST3_CFG1           0x464
+/* Reserved [31] */
+#define      FLD_VBI3_CRIWIN          0x7f000000
+#define      FLD_VBI3_SLICE_DIST      0x00f00000
+#define      FLD_VBI3_BITINC          0x000fff00
+#define      FLD_VBI3_HDELAY          0x000000ff
+
+/*****************************************************************************/
+#define      VBI_CUST3_CFG2           0x468
+#define      FLD_VBI3_FC_LENGTH       0x1f000000
+#define      FLD_VBI3_FRAME_CODE      0x00ffffff
+
+/*****************************************************************************/
+#define      VBI_CUST3_CFG3           0x46c
+#define      FLD_VBI3_HAM_EN          0x80000000
+#define      FLD_VBI3_FIFO_MODE       0x70000000
+#define      FLD_VBI3_FORMAT_TYPE     0x0f000000
+#define      FLD_VBI3_PAYLD_LENGTH    0x00ff0000
+#define      FLD_VBI3_CRI_LENGTH      0x0000f000
+#define      FLD_VBI3_CRI_MARGIN      0x00000f00
+#define      FLD_VBI3_CRI_TIME        0x000000ff
+
+/*****************************************************************************/
+#define      HORIZ_TIM_CTRL           0x470
+#define      FLD_BGDEL_CNT            0xff000000
+/* Reserved [23:22] */
+#define      FLD_HACTIVE_CNT          0x003ff000
+/* Reserved [11:10] */
+#define      FLD_HBLANK_CNT           0x000003ff
+
+/*****************************************************************************/
+#define      VERT_TIM_CTRL            0x474
+#define      FLD_V656BLANK_CNT        0xff000000
+/* Reserved [23:22] */
+#define      FLD_VACTIVE_CNT          0x003ff000
+/* Reserved [11:10] */
+#define      FLD_VBLANK_CNT           0x000003ff
+
+/*****************************************************************************/
+#define      SRC_COMB_CFG             0x478
+#define      FLD_CCOMB_2LN_CHECK      0x80000000
+#define      FLD_CCOMB_3LN_EN         0x40000000
+#define      FLD_CCOMB_2LN_EN         0x20000000
+#define      FLD_CCOMB_3D_EN          0x10000000
+/* Reserved [27] */
+#define      FLD_LCOMB_3LN_EN         0x04000000
+#define      FLD_LCOMB_2LN_EN         0x02000000
+#define      FLD_LCOMB_3D_EN          0x01000000
+#define      FLD_LUMA_LPF_SEL         0x00c00000
+#define      FLD_UV_LPF_SEL           0x00300000
+#define      FLD_BLEND_SLOPE          0x000f0000
+#define      FLD_CCOMB_REDUCE_EN      0x00008000
+/* Reserved [14:10] */
+#define      FLD_SRC_DECIM_RATIO      0x000003ff
+
+/*****************************************************************************/
+#define      CHROMA_VBIOFF_CFG        0x47c
+#define      FLD_VBI_VOFFSET          0x1f000000
+/* Reserved [23:20] */
+#define      FLD_SC_STEP              0x000fffff
+
+/*****************************************************************************/
+#define      FIELD_COUNT              0x480
+#define      FLD_FIELD_COUNT_FLD      0x000003ff
+
+/*****************************************************************************/
+#define      MISC_TIM_CTRL            0x484
+#define      FLD_DEBOUNCE_COUNT       0xc0000000
+#define      FLD_VT_LINE_CNT_HYST     0x30000000
+/* Reserved [27] */
+#define      FLD_AFD_STAT             0x07ff0000
+#define      FLD_VPRES_VERT_EN        0x00008000
+/* Reserved [14:12] */
+#define      FLD_HR32                 0x00000800
+#define      FLD_TDALGN               0x00000400
+#define      FLD_TDFIELD              0x00000200
+/* Reserved [8:6] */
+#define      FLD_TEMPDEC              0x0000003f
+
+/*****************************************************************************/
+#define      DFE_CTRL1                0x488
+#define      FLD_CLAMP_AUTO_EN        0x80000000
+#define      FLD_AGC_AUTO_EN          0x40000000
+#define      FLD_VGA_CRUSH_EN         0x20000000
+#define      FLD_VGA_AUTO_EN          0x10000000
+#define      FLD_VBI_GATE_EN          0x08000000
+#define      FLD_CLAMP_LEVEL          0x07000000
+/* Reserved [23:22] */
+#define      FLD_CLAMP_SKIP_CNT       0x00300000
+#define      FLD_AGC_GAIN             0x000fff00
+/* Reserved [7:6] */
+#define      FLD_VGA_GAIN             0x0000003f
+
+/*****************************************************************************/
+#define      DFE_CTRL2                0x48c
+#define      FLD_VGA_ACQUIRE_RANGE    0x00ff0000
+#define      FLD_VGA_TRACK_RANGE      0x0000ff00
+#define      FLD_VGA_SYNC             0x000000ff
+
+/*****************************************************************************/
+#define      DFE_CTRL3                0x490
+#define      FLD_BP_PERCENT           0xff000000
+#define      FLD_DFT_THRESHOLD        0x00ff0000
+/* Reserved [15:12] */
+#define      FLD_SYNC_WIDTH_SEL       0x00000600
+#define      FLD_BP_LOOP_GAIN         0x00000300
+#define      FLD_SYNC_LOOP_GAIN       0x000000c0
+/* Reserved [5:4] */
+#define      FLD_AGC_LOOP_GAIN        0x0000000c
+#define      FLD_DCC_LOOP_GAIN        0x00000003
+
+/*****************************************************************************/
+#define      PLL_CTRL                 0x494
+#define      FLD_PLL_KD               0xff000000
+#define      FLD_PLL_KI               0x00ff0000
+#define      FLD_PLL_MAX_OFFSET       0x0000ffff
+
+/*****************************************************************************/
+#define      HTL_CTRL                 0x498
+/* Reserved [31:24] */
+#define      FLD_AUTO_LOCK_SPD        0x00080000
+#define      FLD_MAN_FAST_LOCK        0x00040000
+#define      FLD_HTL_15K_EN           0x00020000
+#define      FLD_HTL_500K_EN          0x00010000
+#define      FLD_HTL_KD               0x0000ff00
+#define      FLD_HTL_KI               0x000000ff
+
+/*****************************************************************************/
+#define      COMB_CTRL                0x49c
+#define      FLD_COMB_PHASE_LIMIT     0xff000000
+#define      FLD_CCOMB_ERR_LIMIT      0x00ff0000
+#define      FLD_LUMA_THRESHOLD       0x0000ff00
+#define      FLD_LCOMB_ERR_LIMIT      0x000000ff
+
+/*****************************************************************************/
+#define      CRUSH_CTRL               0x4a0
+#define      FLD_WTW_EN               0x00400000
+#define      FLD_CRUSH_FREQ           0x00200000
+#define      FLD_MAJ_SEL_EN           0x00100000
+#define      FLD_MAJ_SEL              0x000c0000
+/* Reserved [17:15] */
+#define      FLD_SYNC_TIP_REDUCE      0x00007e00
+/* Reserved [8:6] */
+#define      FLD_SYNC_TIP_INC         0x0000003f
+
+/*****************************************************************************/
+#define      SOFT_RST_CTRL            0x4a4
+#define      FLD_VD_SOFT_RST          0x00008000
+/* Reserved [14:12] */
+#define      FLD_REG_RST_MSK          0x00000800
+#define      FLD_VOF_RST_MSK          0x00000400
+#define      FLD_MVDET_RST_MSK        0x00000200
+#define      FLD_VBI_RST_MSK          0x00000100
+#define      FLD_SCALE_RST_MSK        0x00000080
+#define      FLD_CHROMA_RST_MSK       0x00000040
+#define      FLD_LUMA_RST_MSK         0x00000020
+#define      FLD_VTG_RST_MSK          0x00000010
+#define      FLD_YCSEP_RST_MSK        0x00000008
+#define      FLD_SRC_RST_MSK          0x00000004
+#define      FLD_DFE_RST_MSK          0x00000002
+/* Reserved [0] */
+
+/*****************************************************************************/
+#define      MV_DT_CTRL1              0x4a8
+/* Reserved [31:29] */
+#define      FLD_PSP_STOP_LINE        0x1f000000
+/* Reserved [23:21] */
+#define      FLD_PSP_STRT_LINE        0x001f0000
+/* Reserved [15] */
+#define      FLD_PSP_LLIMW            0x00007f00
+/* Reserved [7] */
+#define      FLD_PSP_ULIMW            0x0000007f
+
+/*****************************************************************************/
+#define      MV_DT_CTRL2              0x4aC
+#define      FLD_CS_STOPWIN           0xff000000
+#define      FLD_CS_STRTWIN           0x00ff0000
+#define      FLD_CS_WIDTH             0x0000ff00
+#define      FLD_PSP_SPEC_VAL         0x000000ff
+
+/*****************************************************************************/
+#define      MV_DT_CTRL3              0x4B0
+#define      FLD_AUTO_RATE_DIS        0x80000000
+#define      FLD_HLOCK_DIS            0x40000000
+#define      FLD_SEL_FIELD_CNT        0x20000000
+#define      FLD_CS_TYPE2_SEL         0x10000000
+#define      FLD_CS_LINE_THRSH_SEL    0x08000000
+#define      FLD_CS_ATHRESH_SEL       0x04000000
+#define      FLD_PSP_SPEC_SEL         0x02000000
+#define      FLD_PSP_LINES_SEL        0x01000000
+#define      FLD_FIELD_CNT            0x00f00000
+#define      FLD_CS_TYPE2_CNT         0x000fc000
+#define      FLD_CS_LINE_CNT          0x00003f00
+#define      FLD_CS_ATHRESH_LEV       0x000000ff
+
+/*****************************************************************************/
+#define      CHIP_VERSION             0x4b4
+/* Cx231xx redefine  */
+#define      VERSION                  0x4b4
+#define      FLD_REV_ID               0x000000ff
+
+/*****************************************************************************/
+#define      MISC_DIAG_CTRL           0x4b8
+/* Reserved [31:24] */
+#define      FLD_SC_CONVERGE_THRESH   0x00ff0000
+#define      FLD_CCOMB_ERR_LIMIT_3D   0x0000ff00
+#define      FLD_LCOMB_ERR_LIMIT_3D   0x000000ff
+
+/*****************************************************************************/
+#define      VBI_PASS_CTRL            0x4bc
+#define      FLD_VBI_PASS_MD          0x00200000
+#define      FLD_VBI_SETUP_DIS        0x00100000
+#define      FLD_PASS_LINE_CTRL       0x000fffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      VCR_DET_CTRL             0x4c0
+#define      FLD_EN_FIELD_PHASE_DET   0x80000000
+#define      FLD_EN_HEAD_SW_DET       0x40000000
+#define      FLD_FIELD_PHASE_LENGTH   0x01ff0000
+/* Reserved [29:25] */
+#define      FLD_FIELD_PHASE_DELAY    0x0000ff00
+#define      FLD_FIELD_PHASE_LIMIT    0x000000f0
+#define      FLD_HEAD_SW_DET_LIMIT    0x0000000f
+
+/*****************************************************************************/
+#define      DL_CTL                   0x800
+#define      DL_CTL_ADDRESS_LOW       0x800    /* Byte 1 in DL_CTL */
+#define      DL_CTL_ADDRESS_HIGH      0x801    /* Byte 2 in DL_CTL */
+#define      DL_CTL_DATA              0x802    /* Byte 3 in DL_CTL */
+#define      DL_CTL_CONTROL           0x803    /* Byte 4 in DL_CTL */
+/* Reserved [31:5] */
+#define      FLD_START_8051           0x10000000
+#define      FLD_DL_ENABLE            0x08000000
+#define      FLD_DL_AUTO_INC          0x04000000
+#define      FLD_DL_MAP               0x03000000
+
+/*****************************************************************************/
+#define      STD_DET_STATUS           0x804
+#define      FLD_SPARE_STATUS1        0xff000000
+#define      FLD_SPARE_STATUS0        0x00ff0000
+#define      FLD_MOD_DET_STATUS1      0x0000ff00
+#define      FLD_MOD_DET_STATUS0      0x000000ff
+
+/*****************************************************************************/
+#define      AUD_BUILD_NUM            0x806
+#define      AUD_VER_NUM              0x807
+#define      STD_DET_CTL              0x808
+#define      STD_DET_CTL_AUD_CTL      0x808    /* Byte 1 in STD_DET_CTL */
+#define      STD_DET_CTL_PREF_MODE    0x809    /* Byte 2 in STD_DET_CTL */
+#define      FLD_SPARE_CTL0           0xff000000
+#define      FLD_DIS_DBX              0x00800000
+#define      FLD_DIS_BTSC             0x00400000
+#define      FLD_DIS_NICAM_A2         0x00200000
+#define      FLD_VIDEO_PRESENT        0x00100000
+#define      FLD_DW8051_VIDEO_FORMAT  0x000f0000
+#define      FLD_PREF_DEC_MODE        0x0000ff00
+#define      FLD_AUD_CONFIG           0x000000ff
+
+/*****************************************************************************/
+#define      DW8051_INT               0x80c
+#define      FLD_VIDEO_PRESENT_CHANGE 0x80000000
+#define      FLD_VIDEO_CHANGE         0x40000000
+#define      FLD_RDS_READY            0x20000000
+#define      FLD_AC97_INT             0x10000000
+#define      FLD_NICAM_BIT_ERROR_TOO_HIGH         0x08000000
+#define      FLD_NICAM_LOCK           0x04000000
+#define      FLD_NICAM_UNLOCK         0x02000000
+#define      FLD_DFT4_TH_CMP          0x01000000
+/* Reserved [23:22] */
+#define      FLD_LOCK_IND_INT         0x00200000
+#define      FLD_DFT3_TH_CMP          0x00100000
+#define      FLD_DFT2_TH_CMP          0x00080000
+#define      FLD_DFT1_TH_CMP          0x00040000
+#define      FLD_FM2_DFT_TH_CMP       0x00020000
+#define      FLD_FM1_DFT_TH_CMP       0x00010000
+#define      FLD_VIDEO_PRESENT_EN     0x00008000
+#define      FLD_VIDEO_CHANGE_EN      0x00004000
+#define      FLD_RDS_READY_EN         0x00002000
+#define      FLD_AC97_INT_EN          0x00001000
+#define      FLD_NICAM_BIT_ERROR_TOO_HIGH_EN      0x00000800
+#define      FLD_NICAM_LOCK_EN        0x00000400
+#define      FLD_NICAM_UNLOCK_EN      0x00000200
+#define      FLD_DFT4_TH_CMP_EN       0x00000100
+/* Reserved [7] */
+#define      FLD_DW8051_INT6_CTL1     0x00000040
+#define      FLD_DW8051_INT5_CTL1     0x00000020
+#define      FLD_DW8051_INT4_CTL1     0x00000010
+#define      FLD_DW8051_INT3_CTL1     0x00000008
+#define      FLD_DW8051_INT2_CTL1     0x00000004
+#define      FLD_DW8051_INT1_CTL1     0x00000002
+#define      FLD_DW8051_INT0_CTL1     0x00000001
+
+/*****************************************************************************/
+#define      GENERAL_CTL              0x810
+#define      FLD_RDS_INT              0x80000000
+#define      FLD_NBER_INT             0x40000000
+#define      FLD_NLL_INT              0x20000000
+#define      FLD_IFL_INT              0x10000000
+#define      FLD_FDL_INT              0x08000000
+#define      FLD_AFC_INT              0x04000000
+#define      FLD_AMC_INT              0x02000000
+#define      FLD_AC97_INT_CTL         0x01000000
+#define      FLD_RDS_INT_DIS          0x00800000
+#define      FLD_NBER_INT_DIS         0x00400000
+#define      FLD_NLL_INT_DIS          0x00200000
+#define      FLD_IFL_INT_DIS          0x00100000
+#define      FLD_FDL_INT_DIS          0x00080000
+#define      FLD_FC_INT_DIS           0x00040000
+#define      FLD_AMC_INT_DIS          0x00020000
+#define      FLD_AC97_INT_DIS         0x00010000
+#define      FLD_REV_NUM              0x0000ff00
+/* Reserved [7:5] */
+#define      FLD_DBX_SOFT_RESET_REG   0x00000010
+#define      FLD_AD_SOFT_RESET_REG    0x00000008
+#define      FLD_SRC_SOFT_RESET_REG   0x00000004
+#define      FLD_CDMOD_SOFT_RESET     0x00000002
+#define      FLD_8051_SOFT_RESET      0x00000001
+
+/*****************************************************************************/
+#define      AAGC_CTL                 0x814
+#define      FLD_AFE_12DB_EN          0x80000000
+#define      FLD_AAGC_DEFAULT_EN      0x40000000
+#define      FLD_AAGC_DEFAULT         0x3f000000
+/* Reserved [23] */
+#define      FLD_AAGC_GAIN            0x00600000
+#define      FLD_AAGC_TH              0x001f0000
+/* Reserved [15:14] */
+#define      FLD_AAGC_HYST2           0x00003f00
+/* Reserved [7:6] */
+#define      FLD_AAGC_HYST1           0x0000003f
+
+/*****************************************************************************/
+#define      IF_SRC_CTL               0x818
+#define      FLD_DBX_BYPASS           0x80000000
+/* Reserved [30:25] */
+#define      FLD_IF_SRC_MODE          0x01000000
+/* Reserved [23:18] */
+#define      FLD_IF_SRC_PHASE_INC     0x0001ffff
+
+/*****************************************************************************/
+#define      ANALOG_DEMOD_CTL         0x81c
+#define      FLD_ROT1_PHACC_PROG      0xffff0000
+/* Reserved [15] */
+#define      FLD_FM1_DELAY_FIX        0x00007000
+#define      FLD_PDF4_SHIFT           0x00000c00
+#define      FLD_PDF3_SHIFT           0x00000300
+#define      FLD_PDF2_SHIFT           0x000000c0
+#define      FLD_PDF1_SHIFT           0x00000030
+#define      FLD_FMBYPASS_MODE2       0x00000008
+#define      FLD_FMBYPASS_MODE1       0x00000004
+#define      FLD_NICAM_MODE           0x00000002
+#define      FLD_BTSC_FMRADIO_MODE    0x00000001
+
+/*****************************************************************************/
+#define      ROT_FREQ_CTL             0x820
+#define      FLD_ROT3_PHACC_PROG      0xffff0000
+#define      FLD_ROT2_PHACC_PROG      0x0000ffff
+
+/*****************************************************************************/
+#define      FM_CTL                   0x824
+#define      FLD_FM2_DC_FB_SHIFT      0xf0000000
+#define      FLD_FM2_DC_INT_SHIFT     0x0f000000
+#define      FLD_FM2_AFC_RESET        0x00800000
+#define      FLD_FM2_DC_PASS_IN       0x00400000
+#define      FLD_FM2_DAGC_SHIFT       0x00380000
+#define      FLD_FM2_CORDIC_SHIFT     0x00070000
+#define      FLD_FM1_DC_FB_SHIFT      0x0000f000
+#define      FLD_FM1_DC_INT_SHIFT     0x00000f00
+#define      FLD_FM1_AFC_RESET        0x00000080
+#define      FLD_FM1_DC_PASS_IN       0x00000040
+#define      FLD_FM1_DAGC_SHIFT       0x00000038
+#define      FLD_FM1_CORDIC_SHIFT     0x00000007
+
+/*****************************************************************************/
+#define      LPF_PDF_CTL              0x828
+/* Reserved [31:30] */
+#define      FLD_LPF32_SHIFT1         0x30000000
+#define      FLD_LPF32_SHIFT2         0x0c000000
+#define      FLD_LPF160_SHIFTA        0x03000000
+#define      FLD_LPF160_SHIFTB        0x00c00000
+#define      FLD_LPF160_SHIFTC        0x00300000
+#define      FLD_LPF32_COEF_SEL2      0x000c0000
+#define      FLD_LPF32_COEF_SEL1      0x00030000
+#define      FLD_LPF160_COEF_SELC     0x0000c000
+#define      FLD_LPF160_COEF_SELB     0x00003000
+#define      FLD_LPF160_COEF_SELA     0x00000c00
+#define      FLD_LPF160_IN_EN_REG     0x00000300
+#define      FLD_PDF4_PDF_SEL         0x000000c0
+#define      FLD_PDF3_PDF_SEL         0x00000030
+#define      FLD_PDF2_PDF_SEL         0x0000000c
+#define      FLD_PDF1_PDF_SEL         0x00000003
+
+/*****************************************************************************/
+#define      DFT1_CTL1                0x82c
+#define      FLD_DFT1_DWELL           0xffff0000
+#define      FLD_DFT1_FREQ            0x0000ffff
+
+/*****************************************************************************/
+#define      DFT1_CTL2                0x830
+#define      FLD_DFT1_THRESHOLD       0xffffff00
+#define      FLD_DFT1_CMP_CTL         0x00000080
+#define      FLD_DFT1_AVG             0x00000070
+/* Reserved [3:1] */
+#define      FLD_DFT1_START           0x00000001
+
+/*****************************************************************************/
+#define      DFT1_STATUS              0x834
+#define      FLD_DFT1_DONE            0x80000000
+#define      FLD_DFT1_TH_CMP_STAT     0x40000000
+#define      FLD_DFT1_RESULT          0x3fffffff
+
+/*****************************************************************************/
+#define      DFT2_CTL1                0x838
+#define      FLD_DFT2_DWELL           0xffff0000
+#define      FLD_DFT2_FREQ            0x0000ffff
+
+/*****************************************************************************/
+#define      DFT2_CTL2                0x83C
+#define      FLD_DFT2_THRESHOLD       0xffffff00
+#define      FLD_DFT2_CMP_CTL         0x00000080
+#define      FLD_DFT2_AVG             0x00000070
+/* Reserved [3:1] */
+#define      FLD_DFT2_START           0x00000001
+
+/*****************************************************************************/
+#define      DFT2_STATUS              0x840
+#define      FLD_DFT2_DONE            0x80000000
+#define      FLD_DFT2_TH_CMP_STAT     0x40000000
+#define      FLD_DFT2_RESULT          0x3fffffff
+
+/*****************************************************************************/
+#define      DFT3_CTL1                0x844
+#define      FLD_DFT3_DWELL           0xffff0000
+#define      FLD_DFT3_FREQ            0x0000ffff
+
+/*****************************************************************************/
+#define      DFT3_CTL2                0x848
+#define      FLD_DFT3_THRESHOLD       0xffffff00
+#define      FLD_DFT3_CMP_CTL         0x00000080
+#define      FLD_DFT3_AVG             0x00000070
+/* Reserved [3:1] */
+#define      FLD_DFT3_START           0x00000001
+
+/*****************************************************************************/
+#define      DFT3_STATUS              0x84c
+#define      FLD_DFT3_DONE            0x80000000
+#define      FLD_DFT3_TH_CMP_STAT     0x40000000
+#define      FLD_DFT3_RESULT          0x3fffffff
+
+/*****************************************************************************/
+#define      DFT4_CTL1                0x850
+#define      FLD_DFT4_DWELL           0xffff0000
+#define      FLD_DFT4_FREQ            0x0000ffff
+
+/*****************************************************************************/
+#define      DFT4_CTL2                0x854
+#define      FLD_DFT4_THRESHOLD       0xffffff00
+#define      FLD_DFT4_CMP_CTL         0x00000080
+#define      FLD_DFT4_AVG             0x00000070
+/* Reserved [3:1] */
+#define      FLD_DFT4_START           0x00000001
+
+/*****************************************************************************/
+#define      DFT4_STATUS              0x858
+#define      FLD_DFT4_DONE            0x80000000
+#define      FLD_DFT4_TH_CMP_STAT     0x40000000
+#define      FLD_DFT4_RESULT          0x3fffffff
+
+/*****************************************************************************/
+#define      AM_MTS_DET               0x85c
+#define      FLD_AM_MTS_MODE          0x80000000
+/* Reserved [30:26] */
+#define      FLD_AM_SUB               0x02000000
+#define      FLD_AM_GAIN_EN           0x01000000
+/* Reserved [23:16] */
+#define      FLD_AMMTS_GAIN_SCALE     0x0000e000
+#define      FLD_MTS_PDF_SHIFT        0x00001800
+#define      FLD_AM_REG_GAIN          0x00000700
+#define      FLD_AGC_REF              0x000000ff
+
+/*****************************************************************************/
+#define      ANALOG_MUX_CTL           0x860
+/* Reserved [31:29] */
+#define      FLD_MUX21_SEL            0x10000000
+#define      FLD_MUX20_SEL            0x08000000
+#define      FLD_MUX19_SEL            0x04000000
+#define      FLD_MUX18_SEL            0x02000000
+#define      FLD_MUX17_SEL            0x01000000
+#define      FLD_MUX16_SEL            0x00800000
+#define      FLD_MUX15_SEL            0x00400000
+#define      FLD_MUX14_SEL            0x00300000
+#define      FLD_MUX13_SEL            0x000C0000
+#define      FLD_MUX12_SEL            0x00020000
+#define      FLD_MUX11_SEL            0x00018000
+#define      FLD_MUX10_SEL            0x00004000
+#define      FLD_MUX9_SEL             0x00002000
+#define      FLD_MUX8_SEL             0x00001000
+#define      FLD_MUX7_SEL             0x00000800
+#define      FLD_MUX6_SEL             0x00000600
+#define      FLD_MUX5_SEL             0x00000100
+#define      FLD_MUX4_SEL             0x000000c0
+#define      FLD_MUX3_SEL             0x00000030
+#define      FLD_MUX2_SEL             0x0000000c
+#define      FLD_MUX1_SEL             0x00000003
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DPLL_CTRL1               0x864
+#define      DIG_PLL_CTL1             0x864
+
+#define      FLD_PLL_STATUS           0x07000000
+#define      FLD_BANDWIDTH_SELECT     0x00030000
+#define      FLD_PLL_SHIFT_REG        0x00007000
+#define      FLD_PHASE_SHIFT          0x000007ff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DPLL_CTRL2               0x868
+#define      DIG_PLL_CTL2             0x868
+#define      FLD_PLL_UNLOCK_THR       0xff000000
+#define      FLD_PLL_LOCK_THR         0x00ff0000
+/* Reserved [15:8] */
+#define      FLD_AM_PDF_SEL2          0x000000c0
+#define      FLD_AM_PDF_SEL1          0x00000030
+#define      FLD_DPLL_FSM_CTRL        0x0000000c
+/* Reserved [1] */
+#define      FLD_PLL_PILOT_DET        0x00000001
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DPLL_CTRL3               0x86c
+#define      DIG_PLL_CTL3             0x86c
+#define      FLD_DISABLE_LOOP         0x01000000
+#define      FLD_A1_DS1_SEL           0x000c0000
+#define      FLD_A1_DS2_SEL           0x00030000
+#define      FLD_A1_KI                0x0000ff00
+#define      FLD_A1_KD                0x000000ff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DPLL_CTRL4               0x870
+#define      DIG_PLL_CTL4             0x870
+#define      FLD_A2_DS1_SEL           0x000c0000
+#define      FLD_A2_DS2_SEL           0x00030000
+#define      FLD_A2_KI                0x0000ff00
+#define      FLD_A2_KD                0x000000ff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DPLL_CTRL5               0x874
+#define      DIG_PLL_CTL5             0x874
+#define      FLD_TRK_DS1_SEL          0x000c0000
+#define      FLD_TRK_DS2_SEL          0x00030000
+#define      FLD_TRK_KI               0x0000ff00
+#define      FLD_TRK_KD               0x000000ff
+
+/*****************************************************************************/
+#define      DEEMPH_GAIN_CTL          0x878
+#define      FLD_DEEMPH2_GAIN         0xFFFF0000
+#define      FLD_DEEMPH1_GAIN         0x0000FFFF
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_COEFF1            0x87c
+#define      DEEMPH_COEF1             0x87c
+#define      FLD_DEEMPH_B0            0xffff0000
+#define      FLD_DEEMPH_A0            0x0000ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_COEFF2            0x880
+#define      DEEMPH_COEF2             0x880
+#define      FLD_DEEMPH_B1            0xFFFF0000
+#define      FLD_DEEMPH_A1            0x0000FFFF
+
+/*****************************************************************************/
+#define      DBX1_CTL1                0x884
+#define      FLD_DBX1_WBE_GAIN        0xffff0000
+#define      FLD_DBX1_IN_GAIN         0x0000ffff
+
+/*****************************************************************************/
+#define      DBX1_CTL2                0x888
+#define      FLD_DBX1_SE_BYPASS       0xffff0000
+#define      FLD_DBX1_SE_GAIN         0x0000ffff
+
+/*****************************************************************************/
+#define      DBX1_RMS_SE              0x88C
+#define      FLD_DBX1_RMS_WBE         0xffff0000
+#define      FLD_DBX1_RMS_SE_FLD      0x0000ffff
+
+/*****************************************************************************/
+#define      DBX2_CTL1                0x890
+#define      FLD_DBX2_WBE_GAIN        0xffff0000
+#define      FLD_DBX2_IN_GAIN         0x0000ffff
+
+/*****************************************************************************/
+#define      DBX2_CTL2                0x894
+#define      FLD_DBX2_SE_BYPASS       0xffff0000
+#define      FLD_DBX2_SE_GAIN         0x0000ffff
+
+/*****************************************************************************/
+#define      DBX2_RMS_SE              0x898
+#define      FLD_DBX2_RMS_WBE         0xffff0000
+#define      FLD_DBX2_RMS_SE_FLD      0x0000ffff
+
+/*****************************************************************************/
+#define      AM_FM_DIFF               0x89c
+/* Reserved [31] */
+#define      FLD_FM_DIFF_OUT          0x7fff0000
+/* Reserved [15] */
+#define      FLD_AM_DIFF_OUT          0x00007fff
+
+/*****************************************************************************/
+#define      NICAM_FAW                0x8a0
+#define      FLD_FAWDETWINEND         0xFc000000
+#define      FLD_FAWDETWINSTR         0x03ff0000
+/* Reserved [15:12] */
+#define      FLD_FAWDETTHRSHLD3       0x00000f00
+#define      FLD_FAWDETTHRSHLD2       0x000000f0
+#define      FLD_FAWDETTHRSHLD1       0x0000000f
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_GAIN              0x8a4
+#define      NICAM_DEEMPHGAIN         0x8a4
+/* Reserved [31:18] */
+#define      FLD_DEEMPHGAIN           0x0003ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_NUMER1            0x8a8
+#define      NICAM_DEEMPHNUMER1       0x8a8
+/* Reserved [31:18] */
+#define      FLD_DEEMPHNUMER1         0x0003ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_NUMER2            0x8ac
+#define      NICAM_DEEMPHNUMER2       0x8ac
+/* Reserved [31:18] */
+#define      FLD_DEEMPHNUMER2         0x0003ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_DENOM1            0x8b0
+#define      NICAM_DEEMPHDENOM1       0x8b0
+/* Reserved [31:18] */
+#define      FLD_DEEMPHDENOM1         0x0003ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      DEEMPH_DENOM2            0x8b4
+#define      NICAM_DEEMPHDENOM2       0x8b4
+/* Reserved [31:18] */
+#define      FLD_DEEMPHDENOM2         0x0003ffff
+
+/*****************************************************************************/
+#define      NICAM_ERRLOG_CTL1        0x8B8
+/* Reserved [31:28] */
+#define      FLD_ERRINTRPTTHSHLD1     0x0fff0000
+/* Reserved [15:12] */
+#define      FLD_ERRLOGPERIOD         0x00000fff
+
+/*****************************************************************************/
+#define      NICAM_ERRLOG_CTL2        0x8bc
+/* Reserved [31:28] */
+#define      FLD_ERRINTRPTTHSHLD3     0x0fff0000
+/* Reserved [15:12] */
+#define      FLD_ERRINTRPTTHSHLD2     0x00000fff
+
+/*****************************************************************************/
+#define      NICAM_ERRLOG_STS1        0x8c0
+/* Reserved [31:28] */
+#define      FLD_ERRLOG2              0x0fff0000
+/* Reserved [15:12] */
+#define      FLD_ERRLOG1              0x00000fff
+
+/*****************************************************************************/
+#define      NICAM_ERRLOG_STS2        0x8c4
+/* Reserved [31:12] */
+#define      FLD_ERRLOG3              0x00000fff
+
+/*****************************************************************************/
+#define      NICAM_STATUS             0x8c8
+/* Reserved [31:20] */
+#define      FLD_NICAM_CIB            0x000c0000
+#define      FLD_NICAM_LOCK_STAT      0x00020000
+#define      FLD_NICAM_MUTE           0x00010000
+#define      FLD_NICAMADDIT_DATA      0x0000ffe0
+#define      FLD_NICAMCNTRL           0x0000001f
+
+/*****************************************************************************/
+#define      DEMATRIX_CTL             0x8cc
+#define      FLD_AC97_IN_SHIFT        0xf0000000
+#define      FLD_I2S_IN_SHIFT         0x0f000000
+#define      FLD_DEMATRIX_SEL_CTL     0x00ff0000
+/* Reserved [15:11] */
+#define      FLD_DMTRX_BYPASS         0x00000400
+#define      FLD_DEMATRIX_MODE        0x00000300
+/* Reserved [7:6] */
+#define      FLD_PH_DBX_SEL           0x00000020
+#define      FLD_PH_CH_SEL            0x00000010
+#define      FLD_PHASE_FIX            0x0000000f
+
+/*****************************************************************************/
+#define      PATH1_CTL1               0x8d0
+/* Reserved [31:29] */
+#define      FLD_PATH1_MUTE_CTL       0x1f000000
+/* Reserved [23:22] */
+#define      FLD_PATH1_AVC_CG         0x00300000
+#define      FLD_PATH1_AVC_RT         0x000f0000
+#define      FLD_PATH1_AVC_AT         0x0000f000
+#define      FLD_PATH1_AVC_STEREO     0x00000800
+#define      FLD_PATH1_AVC_CR         0x00000700
+#define      FLD_PATH1_AVC_RMS_CON    0x000000f0
+#define      FLD_PATH1_SEL_CTL        0x0000000f
+
+/*****************************************************************************/
+#define      PATH1_VOL_CTL            0x8d4
+#define      FLD_PATH1_AVC_THRESHOLD  0x7fff0000
+#define      FLD_PATH1_BAL_LEFT       0x00008000
+#define      FLD_PATH1_BAL_LEVEL      0x00007f00
+#define      FLD_PATH1_VOLUME         0x000000ff
+
+/*****************************************************************************/
+#define      PATH1_EQ_CTL             0x8d8
+/* Reserved [31:30] */
+#define      FLD_PATH1_EQ_TREBLE_VOL  0x3f000000
+/* Reserved [23:22] */
+#define      FLD_PATH1_EQ_MID_VOL     0x003f0000
+/* Reserved [15:14] */
+#define      FLD_PATH1_EQ_BASS_VOL    0x00003f00
+/* Reserved [7:1] */
+#define      FLD_PATH1_EQ_BAND_SEL    0x00000001
+
+/*****************************************************************************/
+#define      PATH1_SC_CTL             0x8dc
+#define      FLD_PATH1_SC_THRESHOLD   0x7fff0000
+#define      FLD_PATH1_SC_RT          0x0000f000
+#define      FLD_PATH1_SC_AT          0x00000f00
+#define      FLD_PATH1_SC_STEREO      0x00000080
+#define      FLD_PATH1_SC_CR          0x00000070
+#define      FLD_PATH1_SC_RMS_CON     0x0000000f
+
+/*****************************************************************************/
+#define      PATH2_CTL1               0x8e0
+/* Reserved [31:26] */
+#define      FLD_PATH2_MUTE_CTL       0x03000000
+/* Reserved [23:22] */
+#define      FLD_PATH2_AVC_CG         0x00300000
+#define      FLD_PATH2_AVC_RT         0x000f0000
+#define      FLD_PATH2_AVC_AT         0x0000f000
+#define      FLD_PATH2_AVC_STEREO     0x00000800
+#define      FLD_PATH2_AVC_CR         0x00000700
+#define      FLD_PATH2_AVC_RMS_CON    0x000000f0
+#define      FLD_PATH2_SEL_CTL        0x0000000f
+
+/*****************************************************************************/
+#define      PATH2_VOL_CTL            0x8e4
+#define      FLD_PATH2_AVC_THRESHOLD  0xffff0000
+#define      FLD_PATH2_BAL_LEFT       0x00008000
+#define      FLD_PATH2_BAL_LEVEL      0x00007f00
+#define      FLD_PATH2_VOLUME         0x000000ff
+
+/*****************************************************************************/
+#define      PATH2_EQ_CTL             0x8e8
+/* Reserved [31:30] */
+#define      FLD_PATH2_EQ_TREBLE_VOL  0x3f000000
+/* Reserved [23:22] */
+#define      FLD_PATH2_EQ_MID_VOL     0x003f0000
+/* Reserved [15:14] */
+#define      FLD_PATH2_EQ_BASS_VOL    0x00003f00
+/* Reserved [7:1] */
+#define      FLD_PATH2_EQ_BAND_SEL    0x00000001
+
+/*****************************************************************************/
+#define      PATH2_SC_CTL             0x8eC
+#define      FLD_PATH2_SC_THRESHOLD   0xffff0000
+#define      FLD_PATH2_SC_RT          0x0000f000
+#define      FLD_PATH2_SC_AT          0x00000f00
+#define      FLD_PATH2_SC_STEREO      0x00000080
+#define      FLD_PATH2_SC_CR          0x00000070
+#define      FLD_PATH2_SC_RMS_CON     0x0000000f
+
+/*****************************************************************************/
+#define      SRC_CTL                  0x8f0
+#define      FLD_SRC_STATUS           0xffffff00
+#define      FLD_FIFO_LF_EN           0x000000fc
+#define      FLD_BYPASS_LI            0x00000002
+#define      FLD_BYPASS_PF            0x00000001
+
+/*****************************************************************************/
+#define      SRC_LF_COEF              0x8f4
+#define      FLD_LOOP_FILTER_COEF2    0xffff0000
+#define      FLD_LOOP_FILTER_COEF1    0x0000ffff
+
+/*****************************************************************************/
+#define      SRC1_CTL                 0x8f8
+/* Reserved [31:28] */
+#define      FLD_SRC1_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC1_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      SRC2_CTL                 0x8fc
+/* Reserved [31:28] */
+#define      FLD_SRC2_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC2_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      SRC3_CTL                 0x900
+/* Reserved [31:28] */
+#define      FLD_SRC3_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC3_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      SRC4_CTL                 0x904
+/* Reserved [31:28] */
+#define      FLD_SRC4_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC4_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      SRC5_CTL                 0x908
+/* Reserved [31:28] */
+#define      FLD_SRC5_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC5_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      SRC6_CTL                 0x90c
+/* Reserved [31:28] */
+#define      FLD_SRC6_FIFO_RD_TH      0x0f000000
+/* Reserved [23:18] */
+#define      FLD_SRC6_PHASE_INC       0x0003ffff
+
+/*****************************************************************************/
+#define      BAND_OUT_SEL             0x910
+#define      FLD_SRC6_IN_SEL          0xc0000000
+#define      FLD_SRC6_CLK_SEL         0x30000000
+#define      FLD_SRC5_IN_SEL          0x0c000000
+#define      FLD_SRC5_CLK_SEL         0x03000000
+#define      FLD_SRC4_IN_SEL          0x00c00000
+#define      FLD_SRC4_CLK_SEL         0x00300000
+#define      FLD_SRC3_IN_SEL          0x000c0000
+#define      FLD_SRC3_CLK_SEL         0x00030000
+#define      FLD_BASEBAND_BYPASS_CTL  0x0000ff00
+#define      FLD_AC97_SRC_SEL         0x000000c0
+#define      FLD_I2S_SRC_SEL          0x00000030
+#define      FLD_PARALLEL2_SRC_SEL    0x0000000c
+#define      FLD_PARALLEL1_SRC_SEL    0x00000003
+
+/*****************************************************************************/
+#define      I2S_IN_CTL               0x914
+/* Reserved [31:11] */
+#define      FLD_I2S_UP2X_BW20K       0x00000400
+#define      FLD_I2S_UP2X_BYPASS      0x00000200
+#define      FLD_I2S_IN_MASTER_MODE   0x00000100
+#define      FLD_I2S_IN_SONY_MODE     0x00000080
+#define      FLD_I2S_IN_RIGHT_JUST    0x00000040
+#define      FLD_I2S_IN_WS_SEL        0x00000020
+#define      FLD_I2S_IN_BCN_DEL       0x0000001f
+
+/*****************************************************************************/
+#define      I2S_OUT_CTL              0x918
+/* Reserved [31:17] */
+#define      FLD_I2S_OUT_SOFT_RESET_EN  0x00010000
+/* Reserved [15:9] */
+#define      FLD_I2S_OUT_MASTER_MODE  0x00000100
+#define      FLD_I2S_OUT_SONY_MODE    0x00000080
+#define      FLD_I2S_OUT_RIGHT_JUST   0x00000040
+#define      FLD_I2S_OUT_WS_SEL       0x00000020
+#define      FLD_I2S_OUT_BCN_DEL      0x0000001f
+
+/*****************************************************************************/
+#define      AC97_CTL                 0x91c
+/* Reserved [31:26] */
+#define      FLD_AC97_UP2X_BW20K      0x02000000
+#define      FLD_AC97_UP2X_BYPASS     0x01000000
+/* Reserved [23:17] */
+#define      FLD_AC97_RST_ACL         0x00010000
+/* Reserved [15:9] */
+#define      FLD_AC97_WAKE_UP_SYNC    0x00000100
+/* Reserved [7:1] */
+#define      FLD_AC97_SHUTDOWN        0x00000001
+
+/* Cx231xx redefine */
+#define      QPSK_IAGC_CTL1             0x94c
+#define      QPSK_IAGC_CTL2             0x950
+#define      QPSK_FEPR_FREQ             0x954
+#define      QPSK_BTL_CTL1              0x958
+#define      QPSK_BTL_CTL2              0x95c
+#define      QPSK_CTL_CTL1              0x960
+#define      QPSK_CTL_CTL2              0x964
+#define      QPSK_MF_FAGC_CTL           0x968
+#define      QPSK_EQ_CTL                0x96c
+#define      QPSK_LOCK_CTL              0x970
+
+/*****************************************************************************/
+#define      FM1_DFT_CTL              0x9a8
+#define      FLD_FM1_DFT_THRESHOLD    0xffff0000
+/* Reserved [15:8] */
+#define      FLD_FM1_DFT_CMP_CTL      0x00000080
+#define      FLD_FM1_DFT_AVG          0x00000070
+/* Reserved [3:1] */
+#define      FLD_FM1_DFT_START        0x00000001
+
+/*****************************************************************************/
+#define      FM1_DFT_STATUS           0x9ac
+#define      FLD_FM1_DFT_DONE         0x80000000
+/* Reserved [30:19] */
+#define      FLD_FM_DFT_TH_CMP        0x00040000
+#define      FLD_FM1_DFT              0x0003ffff
+
+/*****************************************************************************/
+#define      FM2_DFT_CTL              0x9b0
+#define      FLD_FM2_DFT_THRESHOLD    0xffff0000
+/* Reserved [15:8] */
+#define      FLD_FM2_DFT_CMP_CTL      0x00000080
+#define      FLD_FM2_DFT_AVG          0x00000070
+/* Reserved [3:1] */
+#define      FLD_FM2_DFT_START        0x00000001
+
+/*****************************************************************************/
+#define      FM2_DFT_STATUS           0x9b4
+#define      FLD_FM2_DFT_DONE         0x80000000
+/* Reserved [30:19] */
+#define      FLD_FM2_DFT_TH_CMP_STAT  0x00040000
+#define      FLD_FM2_DFT              0x0003ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      AAGC_STATUS_REG          0x9b8
+#define      AAGC_STATUS              0x9b8
+/* Reserved [31:27] */
+#define      FLD_FM2_DAGC_OUT         0x07000000
+/* Reserved [23:19] */
+#define      FLD_FM1_DAGC_OUT         0x00070000
+/* Reserved [15:6] */
+#define      FLD_AFE_VGA_OUT          0x0000003f
+
+/*****************************************************************************/
+#define      MTS_GAIN_STATUS          0x9bc
+/* Reserved [31:14] */
+#define      FLD_MTS_GAIN             0x00003fff
+
+#define      RDS_OUT                  0x9c0
+#define      FLD_RDS_Q                0xffff0000
+#define      FLD_RDS_I                0x0000ffff
+
+/*****************************************************************************/
+#define      AUTOCONFIG_REG           0x9c4
+/* Reserved [31:4] */
+#define      FLD_AUTOCONFIG_MODE      0x0000000f
+
+#define      FM_AFC                   0x9c8
+#define      FLD_FM2_AFC              0xffff0000
+#define      FLD_FM1_AFC              0x0000ffff
+
+/*****************************************************************************/
+/* Cx231xx redefine */
+#define      NEW_SPARE                0x9cc
+#define      NEW_SPARE_REG            0x9cc
+
+/*****************************************************************************/
+#define      DBX_ADJ                  0x9d0
+/* Reserved [31:28] */
+#define      FLD_DBX2_ADJ             0x0fff0000
+/* Reserved [15:12] */
+#define      FLD_DBX1_ADJ             0x00000fff
+
+#define      VID_FMT_AUTO              0
+#define      VID_FMT_NTSC_M            1
+#define      VID_FMT_NTSC_J            2
+#define      VID_FMT_NTSC_443          3
+#define      VID_FMT_PAL_BDGHI         4
+#define      VID_FMT_PAL_M             5
+#define      VID_FMT_PAL_N             6
+#define      VID_FMT_PAL_NC            7
+#define      VID_FMT_PAL_60            8
+#define      VID_FMT_SECAM             12
+#define      VID_FMT_SECAM_60          13
+
+#define      INPUT_MODE_CVBS_0         0       /* INPUT_MODE_VALUE(0) */
+#define      INPUT_MODE_YC_1           1       /* INPUT_MODE_VALUE(1) */
+#define      INPUT_MODE_YC2_2          2       /* INPUT_MODE_VALUE(2) */
+#define      INPUT_MODE_YUV_3          3       /* INPUT_MODE_VALUE(3) */
+
+#define      LUMA_LPF_LOW_BANDPASS     0       /* 0.6Mhz LPF BW */
+#define      LUMA_LPF_MEDIUM_BANDPASS  1       /* 1.0Mhz LPF BW */
+#define      LUMA_LPF_HIGH_BANDPASS    2       /* 1.5Mhz LPF BW */
+
+#define      UV_LPF_LOW_BANDPASS       0       /* 0.6Mhz LPF BW */
+#define      UV_LPF_MEDIUM_BANDPASS    1       /* 1.0Mhz LPF BW */
+#define      UV_LPF_HIGH_BANDPASS      2       /* 1.5Mhz LPF BW */
+
+#define      TWO_TAP_FILT              0
+#define      THREE_TAP_FILT            1
+#define      FOUR_TAP_FILT             2
+#define      FIVE_TAP_FILT             3
+
+#define      AUD_CHAN_SRC_PARALLEL     0
+#define      AUD_CHAN_SRC_I2S_INPUT    1
+#define      AUD_CHAN_SRC_FLATIRON     2
+#define      AUD_CHAN_SRC_PARALLEL3    3
+
+#define      OUT_MODE_601              0
+#define      OUT_MODE_656              1
+#define      OUT_MODE_VIP11            2
+#define      OUT_MODE_VIP20            3
+
+#define      PHASE_INC_49MHZ          0x0df22
+#define      PHASE_INC_56MHZ          0x0fa5b
+#define      PHASE_INC_28MHZ          0x010000
+
+#endif
diff --git a/drivers/media/usb/cx231xx/cx231xx-vbi.c b/drivers/media/usb/cx231xx/cx231xx-vbi.c
new file mode 100644
index 000000000000..ac7db52f404f
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-vbi.c
@@ -0,0 +1,710 @@
+/*
+   cx231xx_vbi.c - driver for Conexant Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+        Based on cx88 driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/bitmap.h>
+#include <linux/usb.h>
+#include <linux/i2c.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/msp3400.h>
+#include <media/tuner.h>
+
+#include "cx231xx.h"
+#include "cx231xx-vbi.h"
+
+static inline void print_err_status(struct cx231xx *dev, int packet, int status)
+{
+        char *errmsg = "Unknown";
+
+        switch (status) {
+        case -ENOENT:
+                errmsg = "unlinked synchronuously";
+                break;
+        case -ECONNRESET:
+                errmsg = "unlinked asynchronuously";
+                break;
+        case -ENOSR:
+                errmsg = "Buffer error (overrun)";
+                break;
+        case -EPIPE:
+                errmsg = "Stalled (device not responding)";
+                break;
+        case -EOVERFLOW:
+                errmsg = "Babble (bad cable?)";
+                break;
+        case -EPROTO:
+                errmsg = "Bit-stuff error (bad cable?)";
+                break;
+        case -EILSEQ:
+                errmsg = "CRC/Timeout (could be anything)";
+                break;
+        case -ETIME:
+                errmsg = "Device does not respond";
+                break;
+        }
+        if (packet < 0) {
+                cx231xx_err(DRIVER_NAME "URB status %d [%s].\n", status,
+                            errmsg);
+        } else {
+                cx231xx_err(DRIVER_NAME "URB packet %d, status %d [%s].\n",
+                            packet, status, errmsg);
+        }
+}
+
+/*
+ * Controls the isoc copy of each urb packet
+ */
+static inline int cx231xx_isoc_vbi_copy(struct cx231xx *dev, struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        int rc = 1;
+        unsigned char *p_buffer;
+        u32 bytes_parsed = 0, buffer_size = 0;
+        u8 sav_eav = 0;
+
+        if (!dev)
+                return 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return 0;
+
+        if (urb->status < 0) {
+                print_err_status(dev, -1, urb->status);
+                if (urb->status == -ENOENT)
+                        return 0;
+        }
+
+        /* get buffer pointer and length */
+        p_buffer = urb->transfer_buffer;
+        buffer_size = urb->actual_length;
+
+        if (buffer_size > 0) {
+                bytes_parsed = 0;
+
+                if (dma_q->is_partial_line) {
+                        /* Handle the case where we were working on a partial
+                           line */
+                        sav_eav = dma_q->last_sav;
+                } else {
+                        /* Check for a SAV/EAV overlapping the
+                           buffer boundary */
+
+                        sav_eav = cx231xx_find_boundary_SAV_EAV(p_buffer,
+                                                          dma_q->partial_buf,
+                                                          &bytes_parsed);
+                }
+
+                sav_eav &= 0xF0;
+                /* Get the first line if we have some portion of an SAV/EAV from
+                   the last buffer or a partial line */
+                if (sav_eav) {
+                        bytes_parsed += cx231xx_get_vbi_line(dev, dma_q,
+                                sav_eav,                       /* SAV/EAV */
+                                p_buffer + bytes_parsed,       /* p_buffer */
+                                buffer_size - bytes_parsed);   /* buffer size */
+                }
+
+                /* Now parse data that is completely in this buffer */
+                dma_q->is_partial_line = 0;
+
+                while (bytes_parsed < buffer_size) {
+                        u32 bytes_used = 0;
+
+                        sav_eav = cx231xx_find_next_SAV_EAV(
+                                p_buffer + bytes_parsed,        /* p_buffer */
+                                buffer_size - bytes_parsed, /* buffer size */
+                                &bytes_used);   /* bytes used to get SAV/EAV */
+
+                        bytes_parsed += bytes_used;
+
+                        sav_eav &= 0xF0;
+                        if (sav_eav && (bytes_parsed < buffer_size)) {
+                                bytes_parsed += cx231xx_get_vbi_line(dev,
+                                        dma_q, sav_eav, /* SAV/EAV */
+                                        p_buffer+bytes_parsed, /* p_buffer */
+                                        buffer_size-bytes_parsed);/*buf size*/
+                        }
+                }
+
+                /* Save the last four bytes of the buffer so we can
+                check the buffer boundary condition next time */
+                memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
+                bytes_parsed = 0;
+        }
+
+        return rc;
+}
+
+/* ------------------------------------------------------------------
+        Vbi buf operations
+   ------------------------------------------------------------------*/
+
+static int
+vbi_buffer_setup(struct videobuf_queue *vq, unsigned int *count,
+                 unsigned int *size)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        u32 height = 0;
+
+        height = ((dev->norm & V4L2_STD_625_50) ?
+                  PAL_VBI_LINES : NTSC_VBI_LINES);
+
+        *size = (dev->width * height * 2 * 2);
+        if (0 == *count)
+                *count = CX231XX_DEF_VBI_BUF;
+
+        if (*count < CX231XX_MIN_BUF)
+                *count = CX231XX_MIN_BUF;
+
+        return 0;
+}
+
+/* This is called *without* dev->slock held; please keep it that way */
+static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        unsigned long flags = 0;
+        if (in_interrupt())
+                BUG();
+
+        /* We used to wait for the buffer to finish here, but this didn't work
+           because, as we were keeping the state as VIDEOBUF_QUEUED,
+           videobuf_queue_cancel marked it as finished for us.
+           (Also, it could wedge forever if the hardware was misconfigured.)
+
+           This should be safe; by the time we get here, the buffer isn't
+           queued anymore. If we ever start marking the buffers as
+           VIDEOBUF_ACTIVE, it won't be, though.
+         */
+        spin_lock_irqsave(&dev->vbi_mode.slock, flags);
+        if (dev->vbi_mode.bulk_ctl.buf == buf)
+                dev->vbi_mode.bulk_ctl.buf = NULL;
+        spin_unlock_irqrestore(&dev->vbi_mode.slock, flags);
+
+        videobuf_vmalloc_free(&buf->vb);
+        buf->vb.state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int
+vbi_buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
+                   enum v4l2_field field)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx *dev = fh->dev;
+        int rc = 0, urb_init = 0;
+        u32 height = 0;
+
+        height = ((dev->norm & V4L2_STD_625_50) ?
+                  PAL_VBI_LINES : NTSC_VBI_LINES);
+        buf->vb.size = ((dev->width << 1) * height * 2);
+
+        if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
+                return -EINVAL;
+
+        buf->vb.width = dev->width;
+        buf->vb.height = height;
+        buf->vb.field = field;
+        buf->vb.field = V4L2_FIELD_SEQ_TB;
+
+        if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
+                rc = videobuf_iolock(vq, &buf->vb, NULL);
+                if (rc < 0)
+                        goto fail;
+        }
+
+        if (!dev->vbi_mode.bulk_ctl.num_bufs)
+                urb_init = 1;
+
+        if (urb_init) {
+                rc = cx231xx_init_vbi_isoc(dev, CX231XX_NUM_VBI_PACKETS,
+                                           CX231XX_NUM_VBI_BUFS,
+                                           dev->vbi_mode.alt_max_pkt_size[0],
+                                           cx231xx_isoc_vbi_copy);
+                if (rc < 0)
+                        goto fail;
+        }
+
+        buf->vb.state = VIDEOBUF_PREPARED;
+        return 0;
+
+fail:
+        free_buffer(vq, buf);
+        return rc;
+}
+
+static void
+vbi_buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
+{
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        struct cx231xx_dmaqueue *vidq = &dev->vbi_mode.vidq;
+
+        buf->vb.state = VIDEOBUF_QUEUED;
+        list_add_tail(&buf->vb.queue, &vidq->active);
+
+}
+
+static void vbi_buffer_release(struct videobuf_queue *vq,
+                               struct videobuf_buffer *vb)
+{
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+
+
+        free_buffer(vq, buf);
+}
+
+struct videobuf_queue_ops cx231xx_vbi_qops = {
+        .buf_setup   = vbi_buffer_setup,
+        .buf_prepare = vbi_buffer_prepare,
+        .buf_queue   = vbi_buffer_queue,
+        .buf_release = vbi_buffer_release,
+};
+
+/* ------------------------------------------------------------------
+        URB control
+   ------------------------------------------------------------------*/
+
+/*
+ * IRQ callback, called by URB callback
+ */
+static void cx231xx_irq_vbi_callback(struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        struct cx231xx_video_mode *vmode =
+            container_of(dma_q, struct cx231xx_video_mode, vidq);
+        struct cx231xx *dev = container_of(vmode, struct cx231xx, vbi_mode);
+
+        switch (urb->status) {
+        case 0:         /* success */
+        case -ETIMEDOUT:        /* NAK */
+                break;
+        case -ECONNRESET:       /* kill */
+        case -ENOENT:
+        case -ESHUTDOWN:
+                return;
+        default:                /* error */
+                cx231xx_err(DRIVER_NAME "urb completition error %d.\n",
+                            urb->status);
+                break;
+        }
+
+        /* Copy data from URB */
+        spin_lock(&dev->vbi_mode.slock);
+        dev->vbi_mode.bulk_ctl.bulk_copy(dev, urb);
+        spin_unlock(&dev->vbi_mode.slock);
+
+        /* Reset status */
+        urb->status = 0;
+
+        urb->status = usb_submit_urb(urb, GFP_ATOMIC);
+        if (urb->status) {
+                cx231xx_err(DRIVER_NAME "urb resubmit failed (error=%i)\n",
+                            urb->status);
+        }
+}
+
+/*
+ * Stop and Deallocate URBs
+ */
+void cx231xx_uninit_vbi_isoc(struct cx231xx *dev)
+{
+        struct urb *urb;
+        int i;
+
+        cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_uninit_vbi_isoc\n");
+
+        dev->vbi_mode.bulk_ctl.nfields = -1;
+        for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
+                urb = dev->vbi_mode.bulk_ctl.urb[i];
+                if (urb) {
+                        if (!irqs_disabled())
+                                usb_kill_urb(urb);
+                        else
+                                usb_unlink_urb(urb);
+
+                        if (dev->vbi_mode.bulk_ctl.transfer_buffer[i]) {
+
+                                kfree(dev->vbi_mode.bulk_ctl.
+                                      transfer_buffer[i]);
+                                dev->vbi_mode.bulk_ctl.transfer_buffer[i] =
+                                    NULL;
+                        }
+                        usb_free_urb(urb);
+                        dev->vbi_mode.bulk_ctl.urb[i] = NULL;
+                }
+                dev->vbi_mode.bulk_ctl.transfer_buffer[i] = NULL;
+        }
+
+        kfree(dev->vbi_mode.bulk_ctl.urb);
+        kfree(dev->vbi_mode.bulk_ctl.transfer_buffer);
+
+        dev->vbi_mode.bulk_ctl.urb = NULL;
+        dev->vbi_mode.bulk_ctl.transfer_buffer = NULL;
+        dev->vbi_mode.bulk_ctl.num_bufs = 0;
+
+        cx231xx_capture_start(dev, 0, Vbi);
+}
+EXPORT_SYMBOL_GPL(cx231xx_uninit_vbi_isoc);
+
+/*
+ * Allocate URBs and start IRQ
+ */
+int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
+                          int num_bufs, int max_pkt_size,
+                          int (*bulk_copy) (struct cx231xx *dev,
+                                            struct urb *urb))
+{
+        struct cx231xx_dmaqueue *dma_q = &dev->vbi_mode.vidq;
+        int i;
+        int sb_size, pipe;
+        struct urb *urb;
+        int rc;
+
+        cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_prepare_isoc\n");
+
+        /* De-allocates all pending stuff */
+        cx231xx_uninit_vbi_isoc(dev);
+
+        /* clear if any halt */
+        usb_clear_halt(dev->udev,
+                       usb_rcvbulkpipe(dev->udev,
+                                       dev->vbi_mode.end_point_addr));
+
+        dev->vbi_mode.bulk_ctl.bulk_copy = bulk_copy;
+        dev->vbi_mode.bulk_ctl.num_bufs = num_bufs;
+        dma_q->pos = 0;
+        dma_q->is_partial_line = 0;
+        dma_q->last_sav = 0;
+        dma_q->current_field = -1;
+        dma_q->bytes_left_in_line = dev->width << 1;
+        dma_q->lines_per_field = ((dev->norm & V4L2_STD_625_50) ?
+                                  PAL_VBI_LINES : NTSC_VBI_LINES);
+        dma_q->lines_completed = 0;
+        for (i = 0; i < 8; i++)
+                dma_q->partial_buf[i] = 0;
+
+        dev->vbi_mode.bulk_ctl.urb = kzalloc(sizeof(void *) * num_bufs,
+                                             GFP_KERNEL);
+        if (!dev->vbi_mode.bulk_ctl.urb) {
+                cx231xx_errdev("cannot alloc memory for usb buffers\n");
+                return -ENOMEM;
+        }
+
+        dev->vbi_mode.bulk_ctl.transfer_buffer =
+            kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
+        if (!dev->vbi_mode.bulk_ctl.transfer_buffer) {
+                cx231xx_errdev("cannot allocate memory for usbtransfer\n");
+                kfree(dev->vbi_mode.bulk_ctl.urb);
+                return -ENOMEM;
+        }
+
+        dev->vbi_mode.bulk_ctl.max_pkt_size = max_pkt_size;
+        dev->vbi_mode.bulk_ctl.buf = NULL;
+
+        sb_size = max_packets * dev->vbi_mode.bulk_ctl.max_pkt_size;
+
+        /* allocate urbs and transfer buffers */
+        for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
+
+                urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (!urb) {
+                        cx231xx_err(DRIVER_NAME
+                                    ": cannot alloc bulk_ctl.urb %i\n", i);
+                        cx231xx_uninit_vbi_isoc(dev);
+                        return -ENOMEM;
+                }
+                dev->vbi_mode.bulk_ctl.urb[i] = urb;
+                urb->transfer_flags = 0;
+
+                dev->vbi_mode.bulk_ctl.transfer_buffer[i] =
+                    kzalloc(sb_size, GFP_KERNEL);
+                if (!dev->vbi_mode.bulk_ctl.transfer_buffer[i]) {
+                        cx231xx_err(DRIVER_NAME
+                                    ": unable to allocate %i bytes for transfer"
+                                    " buffer %i%s\n", sb_size, i,
+                                    in_interrupt() ? " while in int" : "");
+                        cx231xx_uninit_vbi_isoc(dev);
+                        return -ENOMEM;
+                }
+
+                pipe = usb_rcvbulkpipe(dev->udev, dev->vbi_mode.end_point_addr);
+                usb_fill_bulk_urb(urb, dev->udev, pipe,
+                                  dev->vbi_mode.bulk_ctl.transfer_buffer[i],
+                                  sb_size, cx231xx_irq_vbi_callback, dma_q);
+        }
+
+        init_waitqueue_head(&dma_q->wq);
+
+        /* submit urbs and enables IRQ */
+        for (i = 0; i < dev->vbi_mode.bulk_ctl.num_bufs; i++) {
+                rc = usb_submit_urb(dev->vbi_mode.bulk_ctl.urb[i], GFP_ATOMIC);
+                if (rc) {
+                        cx231xx_err(DRIVER_NAME
+                                    ": submit of urb %i failed (error=%i)\n", i,
+                                    rc);
+                        cx231xx_uninit_vbi_isoc(dev);
+                        return rc;
+                }
+        }
+
+        cx231xx_capture_start(dev, 1, Vbi);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(cx231xx_init_vbi_isoc);
+
+u32 cx231xx_get_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                         u8 sav_eav, u8 *p_buffer, u32 buffer_size)
+{
+        u32 bytes_copied = 0;
+        int current_field = -1;
+
+        switch (sav_eav) {
+
+        case SAV_VBI_FIELD1:
+                current_field = 1;
+                break;
+
+        case SAV_VBI_FIELD2:
+                current_field = 2;
+                break;
+        default:
+                break;
+        }
+
+        if (current_field < 0)
+                return bytes_copied;
+
+        dma_q->last_sav = sav_eav;
+
+        bytes_copied =
+            cx231xx_copy_vbi_line(dev, dma_q, p_buffer, buffer_size,
+                                  current_field);
+
+        return bytes_copied;
+}
+
+/*
+ * Announces that a buffer were filled and request the next
+ */
+static inline void vbi_buffer_filled(struct cx231xx *dev,
+                                     struct cx231xx_dmaqueue *dma_q,
+                                     struct cx231xx_buffer *buf)
+{
+        /* Advice that buffer was filled */
+        /* cx231xx_info(DRIVER_NAME "[%p/%d] wakeup\n", buf, buf->vb.i); */
+
+        buf->vb.state = VIDEOBUF_DONE;
+        buf->vb.field_count++;
+        do_gettimeofday(&buf->vb.ts);
+
+        dev->vbi_mode.bulk_ctl.buf = NULL;
+
+        list_del(&buf->vb.queue);
+        wake_up(&buf->vb.done);
+}
+
+u32 cx231xx_copy_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                          u8 *p_line, u32 length, int field_number)
+{
+        u32 bytes_to_copy;
+        struct cx231xx_buffer *buf;
+        u32 _line_size = dev->width * 2;
+
+        if (dma_q->current_field == -1) {
+                /* Just starting up */
+                cx231xx_reset_vbi_buffer(dev, dma_q);
+        }
+
+        if (dma_q->current_field != field_number)
+                dma_q->lines_completed = 0;
+
+        /* get the buffer pointer */
+        buf = dev->vbi_mode.bulk_ctl.buf;
+
+        /* Remember the field number for next time */
+        dma_q->current_field = field_number;
+
+        bytes_to_copy = dma_q->bytes_left_in_line;
+        if (bytes_to_copy > length)
+                bytes_to_copy = length;
+
+        if (dma_q->lines_completed >= dma_q->lines_per_field) {
+                dma_q->bytes_left_in_line -= bytes_to_copy;
+                dma_q->is_partial_line =
+                    (dma_q->bytes_left_in_line == 0) ? 0 : 1;
+                return 0;
+        }
+
+        dma_q->is_partial_line = 1;
+
+        /* If we don't have a buffer, just return the number of bytes we would
+           have copied if we had a buffer. */
+        if (!buf) {
+                dma_q->bytes_left_in_line -= bytes_to_copy;
+                dma_q->is_partial_line =
+                    (dma_q->bytes_left_in_line == 0) ? 0 : 1;
+                return bytes_to_copy;
+        }
+
+        /* copy the data to video buffer */
+        cx231xx_do_vbi_copy(dev, dma_q, p_line, bytes_to_copy);
+
+        dma_q->pos += bytes_to_copy;
+        dma_q->bytes_left_in_line -= bytes_to_copy;
+
+        if (dma_q->bytes_left_in_line == 0) {
+
+                dma_q->bytes_left_in_line = _line_size;
+                dma_q->lines_completed++;
+                dma_q->is_partial_line = 0;
+
+                if (cx231xx_is_vbi_buffer_done(dev, dma_q) && buf) {
+
+                        vbi_buffer_filled(dev, dma_q, buf);
+
+                        dma_q->pos = 0;
+                        dma_q->lines_completed = 0;
+                        cx231xx_reset_vbi_buffer(dev, dma_q);
+                }
+        }
+
+        return bytes_to_copy;
+}
+
+/*
+ * video-buf generic routine to get the next available buffer
+ */
+static inline void get_next_vbi_buf(struct cx231xx_dmaqueue *dma_q,
+                                    struct cx231xx_buffer **buf)
+{
+        struct cx231xx_video_mode *vmode =
+            container_of(dma_q, struct cx231xx_video_mode, vidq);
+        struct cx231xx *dev = container_of(vmode, struct cx231xx, vbi_mode);
+        char *outp;
+
+        if (list_empty(&dma_q->active)) {
+                cx231xx_err(DRIVER_NAME ": No active queue to serve\n");
+                dev->vbi_mode.bulk_ctl.buf = NULL;
+                *buf = NULL;
+                return;
+        }
+
+        /* Get the next buffer */
+        *buf = list_entry(dma_q->active.next, struct cx231xx_buffer, vb.queue);
+
+        /* Cleans up buffer - Useful for testing for frame/URB loss */
+        outp = videobuf_to_vmalloc(&(*buf)->vb);
+        memset(outp, 0, (*buf)->vb.size);
+
+        dev->vbi_mode.bulk_ctl.buf = *buf;
+
+        return;
+}
+
+void cx231xx_reset_vbi_buffer(struct cx231xx *dev,
+                              struct cx231xx_dmaqueue *dma_q)
+{
+        struct cx231xx_buffer *buf;
+
+        buf = dev->vbi_mode.bulk_ctl.buf;
+
+        if (buf == NULL) {
+                /* first try to get the buffer */
+                get_next_vbi_buf(dma_q, &buf);
+
+                dma_q->pos = 0;
+                dma_q->current_field = -1;
+        }
+
+        dma_q->bytes_left_in_line = dev->width << 1;
+        dma_q->lines_completed = 0;
+}
+
+int cx231xx_do_vbi_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                        u8 *p_buffer, u32 bytes_to_copy)
+{
+        u8 *p_out_buffer = NULL;
+        u32 current_line_bytes_copied = 0;
+        struct cx231xx_buffer *buf;
+        u32 _line_size = dev->width << 1;
+        void *startwrite;
+        int offset, lencopy;
+
+        buf = dev->vbi_mode.bulk_ctl.buf;
+
+        if (buf == NULL)
+                return -EINVAL;
+
+        p_out_buffer = videobuf_to_vmalloc(&buf->vb);
+
+        if (dma_q->bytes_left_in_line != _line_size) {
+                current_line_bytes_copied =
+                    _line_size - dma_q->bytes_left_in_line;
+        }
+
+        offset = (dma_q->lines_completed * _line_size) +
+                 current_line_bytes_copied;
+
+        if (dma_q->current_field == 2) {
+                /* Populate the second half of the frame */
+                offset += (dev->width * 2 * dma_q->lines_per_field);
+        }
+
+        /* prepare destination address */
+        startwrite = p_out_buffer + offset;
+
+        lencopy = dma_q->bytes_left_in_line > bytes_to_copy ?
+                  bytes_to_copy : dma_q->bytes_left_in_line;
+
+        memcpy(startwrite, p_buffer, lencopy);
+
+        return 0;
+}
+
+u8 cx231xx_is_vbi_buffer_done(struct cx231xx *dev,
+                              struct cx231xx_dmaqueue *dma_q)
+{
+        u32 height = 0;
+
+        height = ((dev->norm & V4L2_STD_625_50) ?
+                  PAL_VBI_LINES : NTSC_VBI_LINES);
+        if (dma_q->lines_completed == height && dma_q->current_field == 2)
+                return 1;
+        else
+                return 0;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx-vbi.h b/drivers/media/usb/cx231xx/cx231xx-vbi.h
new file mode 100644
index 000000000000..16c7d20a22a4
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-vbi.h
@@ -0,0 +1,65 @@
+/*
+   cx231xx_vbi.h - driver for Conexant Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+                Based on cx88 driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _CX231XX_VBI_H
+#define _CX231XX_VBI_H
+
+extern struct videobuf_queue_ops cx231xx_vbi_qops;
+
+#define   NTSC_VBI_START_LINE 10        /* line 10 - 21 */
+#define   NTSC_VBI_END_LINE   21
+#define   NTSC_VBI_LINES          (NTSC_VBI_END_LINE-NTSC_VBI_START_LINE+1)
+
+#define   PAL_VBI_START_LINE  6
+#define   PAL_VBI_END_LINE    23
+#define   PAL_VBI_LINES       (PAL_VBI_END_LINE-PAL_VBI_START_LINE+1)
+
+#define   VBI_STRIDE            1440
+#define   VBI_SAMPLES_PER_LINE  1440
+
+#define   CX231XX_NUM_VBI_PACKETS       4
+#define   CX231XX_NUM_VBI_BUFS          5
+
+/* stream functions */
+int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
+                          int num_bufs, int max_pkt_size,
+                          int (*bulk_copy) (struct cx231xx *dev,
+                                            struct urb *urb));
+
+void cx231xx_uninit_vbi_isoc(struct cx231xx *dev);
+
+/* vbi data copy functions */
+u32 cx231xx_get_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                         u8 sav_eav, u8 *p_buffer, u32 buffer_size);
+
+u32 cx231xx_copy_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                          u8 *p_line, u32 length, int field_number);
+
+void cx231xx_reset_vbi_buffer(struct cx231xx *dev,
+                              struct cx231xx_dmaqueue *dma_q);
+
+int cx231xx_do_vbi_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                        u8 *p_buffer, u32 bytes_to_copy);
+
+u8 cx231xx_is_vbi_buffer_done(struct cx231xx *dev,
+                              struct cx231xx_dmaqueue *dma_q);
+
+#endif
diff --git a/drivers/media/usb/cx231xx/cx231xx-video.c b/drivers/media/usb/cx231xx/cx231xx-video.c
new file mode 100644
index 000000000000..790b28d7f764
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx-video.c
@@ -0,0 +1,2670 @@
+/*
+   cx231xx-video.c - driver for Conexant Cx23100/101/102
+                     USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+        Based on em28xx driver
+        Based on cx23885 driver
+        Based on cx88 driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/bitmap.h>
+#include <linux/usb.h>
+#include <linux/i2c.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/msp3400.h>
+#include <media/tuner.h>
+
+#include "dvb_frontend.h"
+
+#include "cx231xx.h"
+#include "cx231xx-vbi.h"
+
+#define CX231XX_VERSION "0.0.2"
+
+#define DRIVER_AUTHOR   "Srinivasa Deevi <srinivasa.deevi@conexant.com>"
+#define DRIVER_DESC     "Conexant cx231xx based USB video device driver"
+
+#define cx231xx_videodbg(fmt, arg...) do {\
+        if (video_debug) \
+                printk(KERN_INFO "%s %s :"fmt, \
+                         dev->name, __func__ , ##arg); } while (0)
+
+static unsigned int isoc_debug;
+module_param(isoc_debug, int, 0644);
+MODULE_PARM_DESC(isoc_debug, "enable debug messages [isoc transfers]");
+
+#define cx231xx_isocdbg(fmt, arg...) \
+do {\
+        if (isoc_debug) { \
+                printk(KERN_INFO "%s %s :"fmt, \
+                         dev->name, __func__ , ##arg); \
+        } \
+  } while (0)
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+MODULE_VERSION(CX231XX_VERSION);
+
+static unsigned int card[]     = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
+static unsigned int video_nr[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
+static unsigned int vbi_nr[]   = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
+static unsigned int radio_nr[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
+
+module_param_array(card, int, NULL, 0444);
+module_param_array(video_nr, int, NULL, 0444);
+module_param_array(vbi_nr, int, NULL, 0444);
+module_param_array(radio_nr, int, NULL, 0444);
+
+MODULE_PARM_DESC(card, "card type");
+MODULE_PARM_DESC(video_nr, "video device numbers");
+MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
+MODULE_PARM_DESC(radio_nr, "radio device numbers");
+
+static unsigned int video_debug;
+module_param(video_debug, int, 0644);
+MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
+
+/* supported video standards */
+static struct cx231xx_fmt format[] = {
+        {
+         .name = "16bpp YUY2, 4:2:2, packed",
+         .fourcc = V4L2_PIX_FMT_YUYV,
+         .depth = 16,
+         .reg = 0,
+         },
+};
+
+/* supported controls */
+/* Common to all boards */
+
+/* ------------------------------------------------------------------- */
+
+static const struct v4l2_queryctrl no_ctl = {
+        .name = "42",
+        .flags = V4L2_CTRL_FLAG_DISABLED,
+};
+
+static struct cx231xx_ctrl cx231xx_ctls[] = {
+        /* --- video --- */
+        {
+                .v = {
+                        .id = V4L2_CID_BRIGHTNESS,
+                        .name = "Brightness",
+                        .minimum = 0x00,
+                        .maximum = 0xff,
+                        .step = 1,
+                        .default_value = 0x7f,
+                        .type = V4L2_CTRL_TYPE_INTEGER,
+                },
+                .off = 128,
+                .reg = LUMA_CTRL,
+                .mask = 0x00ff,
+                .shift = 0,
+        }, {
+                .v = {
+                        .id = V4L2_CID_CONTRAST,
+                        .name = "Contrast",
+                        .minimum = 0,
+                        .maximum = 0xff,
+                        .step = 1,
+                        .default_value = 0x3f,
+                        .type = V4L2_CTRL_TYPE_INTEGER,
+                },
+                .off = 0,
+                .reg = LUMA_CTRL,
+                .mask = 0xff00,
+                .shift = 8,
+        }, {
+                .v = {
+                        .id = V4L2_CID_HUE,
+                        .name = "Hue",
+                        .minimum = 0,
+                        .maximum = 0xff,
+                        .step = 1,
+                        .default_value = 0x7f,
+                        .type = V4L2_CTRL_TYPE_INTEGER,
+                },
+                .off = 128,
+                .reg = CHROMA_CTRL,
+                .mask = 0xff0000,
+                .shift = 16,
+        }, {
+        /* strictly, this only describes only U saturation.
+        * V saturation is handled specially through code.
+        */
+                .v = {
+                        .id = V4L2_CID_SATURATION,
+                        .name = "Saturation",
+                        .minimum = 0,
+                        .maximum = 0xff,
+                        .step = 1,
+                        .default_value = 0x7f,
+                        .type = V4L2_CTRL_TYPE_INTEGER,
+                },
+                .off = 0,
+                .reg = CHROMA_CTRL,
+                .mask = 0x00ff,
+                .shift = 0,
+        }, {
+                /* --- audio --- */
+                .v = {
+                        .id = V4L2_CID_AUDIO_MUTE,
+                        .name = "Mute",
+                        .minimum = 0,
+                        .maximum = 1,
+                        .default_value = 1,
+                        .type = V4L2_CTRL_TYPE_BOOLEAN,
+                },
+                .reg = PATH1_CTL1,
+                .mask = (0x1f << 24),
+                .shift = 24,
+        }, {
+                .v = {
+                        .id = V4L2_CID_AUDIO_VOLUME,
+                        .name = "Volume",
+                        .minimum = 0,
+                        .maximum = 0x3f,
+                        .step = 1,
+                        .default_value = 0x3f,
+                        .type = V4L2_CTRL_TYPE_INTEGER,
+                },
+                .reg = PATH1_VOL_CTL,
+                .mask = 0xff,
+                .shift = 0,
+        }
+};
+static const int CX231XX_CTLS = ARRAY_SIZE(cx231xx_ctls);
+
+static const u32 cx231xx_user_ctrls[] = {
+        V4L2_CID_USER_CLASS,
+        V4L2_CID_BRIGHTNESS,
+        V4L2_CID_CONTRAST,
+        V4L2_CID_SATURATION,
+        V4L2_CID_HUE,
+        V4L2_CID_AUDIO_VOLUME,
+#if 0
+        V4L2_CID_AUDIO_BALANCE,
+#endif
+        V4L2_CID_AUDIO_MUTE,
+        0
+};
+
+static const u32 *ctrl_classes[] = {
+        cx231xx_user_ctrls,
+        NULL
+};
+
+/* ------------------------------------------------------------------
+        Video buffer and parser functions
+   ------------------------------------------------------------------*/
+
+/*
+ * Announces that a buffer were filled and request the next
+ */
+static inline void buffer_filled(struct cx231xx *dev,
+                                 struct cx231xx_dmaqueue *dma_q,
+                                 struct cx231xx_buffer *buf)
+{
+        /* Advice that buffer was filled */
+        cx231xx_isocdbg("[%p/%d] wakeup\n", buf, buf->vb.i);
+        buf->vb.state = VIDEOBUF_DONE;
+        buf->vb.field_count++;
+        do_gettimeofday(&buf->vb.ts);
+
+        if (dev->USE_ISO)
+                dev->video_mode.isoc_ctl.buf = NULL;
+        else
+                dev->video_mode.bulk_ctl.buf = NULL;
+
+        list_del(&buf->vb.queue);
+        wake_up(&buf->vb.done);
+}
+
+static inline void print_err_status(struct cx231xx *dev, int packet, int status)
+{
+        char *errmsg = "Unknown";
+
+        switch (status) {
+        case -ENOENT:
+                errmsg = "unlinked synchronuously";
+                break;
+        case -ECONNRESET:
+                errmsg = "unlinked asynchronuously";
+                break;
+        case -ENOSR:
+                errmsg = "Buffer error (overrun)";
+                break;
+        case -EPIPE:
+                errmsg = "Stalled (device not responding)";
+                break;
+        case -EOVERFLOW:
+                errmsg = "Babble (bad cable?)";
+                break;
+        case -EPROTO:
+                errmsg = "Bit-stuff error (bad cable?)";
+                break;
+        case -EILSEQ:
+                errmsg = "CRC/Timeout (could be anything)";
+                break;
+        case -ETIME:
+                errmsg = "Device does not respond";
+                break;
+        }
+        if (packet < 0) {
+                cx231xx_isocdbg("URB status %d [%s].\n", status, errmsg);
+        } else {
+                cx231xx_isocdbg("URB packet %d, status %d [%s].\n",
+                                packet, status, errmsg);
+        }
+}
+
+/*
+ * video-buf generic routine to get the next available buffer
+ */
+static inline void get_next_buf(struct cx231xx_dmaqueue *dma_q,
+                                struct cx231xx_buffer **buf)
+{
+        struct cx231xx_video_mode *vmode =
+            container_of(dma_q, struct cx231xx_video_mode, vidq);
+        struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
+
+        char *outp;
+
+        if (list_empty(&dma_q->active)) {
+                cx231xx_isocdbg("No active queue to serve\n");
+                if (dev->USE_ISO)
+                        dev->video_mode.isoc_ctl.buf = NULL;
+                else
+                        dev->video_mode.bulk_ctl.buf = NULL;
+                *buf = NULL;
+                return;
+        }
+
+        /* Get the next buffer */
+        *buf = list_entry(dma_q->active.next, struct cx231xx_buffer, vb.queue);
+
+        /* Cleans up buffer - Useful for testing for frame/URB loss */
+        outp = videobuf_to_vmalloc(&(*buf)->vb);
+        memset(outp, 0, (*buf)->vb.size);
+
+        if (dev->USE_ISO)
+                dev->video_mode.isoc_ctl.buf = *buf;
+        else
+                dev->video_mode.bulk_ctl.buf = *buf;
+
+        return;
+}
+
+/*
+ * Controls the isoc copy of each urb packet
+ */
+static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        int i, rc = 1;
+        unsigned char *p_buffer;
+        u32 bytes_parsed = 0, buffer_size = 0;
+        u8 sav_eav = 0;
+
+        if (!dev)
+                return 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return 0;
+
+        if (urb->status < 0) {
+                print_err_status(dev, -1, urb->status);
+                if (urb->status == -ENOENT)
+                        return 0;
+        }
+
+        for (i = 0; i < urb->number_of_packets; i++) {
+                int status = urb->iso_frame_desc[i].status;
+
+                if (status < 0) {
+                        print_err_status(dev, i, status);
+                        if (urb->iso_frame_desc[i].status != -EPROTO)
+                                continue;
+                }
+
+                if (urb->iso_frame_desc[i].actual_length <= 0) {
+                        /* cx231xx_isocdbg("packet %d is empty",i); - spammy */
+                        continue;
+                }
+                if (urb->iso_frame_desc[i].actual_length >
+                    dev->video_mode.max_pkt_size) {
+                        cx231xx_isocdbg("packet bigger than packet size");
+                        continue;
+                }
+
+                /*  get buffer pointer and length */
+                p_buffer = urb->transfer_buffer + urb->iso_frame_desc[i].offset;
+                buffer_size = urb->iso_frame_desc[i].actual_length;
+                bytes_parsed = 0;
+
+                if (dma_q->is_partial_line) {
+                        /* Handle the case of a partial line */
+                        sav_eav = dma_q->last_sav;
+                } else {
+                        /* Check for a SAV/EAV overlapping
+                                the buffer boundary */
+                        sav_eav =
+                            cx231xx_find_boundary_SAV_EAV(p_buffer,
+                                                          dma_q->partial_buf,
+                                                          &bytes_parsed);
+                }
+
+                sav_eav &= 0xF0;
+                /* Get the first line if we have some portion of an SAV/EAV from
+                   the last buffer or a partial line  */
+                if (sav_eav) {
+                        bytes_parsed += cx231xx_get_video_line(dev, dma_q,
+                                sav_eav,        /* SAV/EAV */
+                                p_buffer + bytes_parsed,        /* p_buffer */
+                                buffer_size - bytes_parsed);/* buf size */
+                }
+
+                /* Now parse data that is completely in this buffer */
+                /* dma_q->is_partial_line = 0;  */
+
+                while (bytes_parsed < buffer_size) {
+                        u32 bytes_used = 0;
+
+                        sav_eav = cx231xx_find_next_SAV_EAV(
+                                p_buffer + bytes_parsed,        /* p_buffer */
+                                buffer_size - bytes_parsed,     /* buf size */
+                                &bytes_used);/* bytes used to get SAV/EAV */
+
+                        bytes_parsed += bytes_used;
+
+                        sav_eav &= 0xF0;
+                        if (sav_eav && (bytes_parsed < buffer_size)) {
+                                bytes_parsed += cx231xx_get_video_line(dev,
+                                        dma_q, sav_eav, /* SAV/EAV */
+                                        p_buffer + bytes_parsed,/* p_buffer */
+                                        buffer_size - bytes_parsed);/*buf size*/
+                        }
+                }
+
+                /* Save the last four bytes of the buffer so we can check the
+                   buffer boundary condition next time */
+                memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
+                bytes_parsed = 0;
+
+        }
+        return rc;
+}
+
+static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
+{
+        struct cx231xx_dmaqueue *dma_q = urb->context;
+        int rc = 1;
+        unsigned char *p_buffer;
+        u32 bytes_parsed = 0, buffer_size = 0;
+        u8 sav_eav = 0;
+
+        if (!dev)
+                return 0;
+
+        if (dev->state & DEV_DISCONNECTED)
+                return 0;
+
+        if (urb->status < 0) {
+                print_err_status(dev, -1, urb->status);
+                if (urb->status == -ENOENT)
+                        return 0;
+        }
+
+        if (1) {
+
+                /*  get buffer pointer and length */
+                p_buffer = urb->transfer_buffer;
+                buffer_size = urb->actual_length;
+                bytes_parsed = 0;
+
+                if (dma_q->is_partial_line) {
+                        /* Handle the case of a partial line */
+                        sav_eav = dma_q->last_sav;
+                } else {
+                        /* Check for a SAV/EAV overlapping
+                                the buffer boundary */
+                        sav_eav =
+                            cx231xx_find_boundary_SAV_EAV(p_buffer,
+                                                          dma_q->partial_buf,
+                                                          &bytes_parsed);
+                }
+
+                sav_eav &= 0xF0;
+                /* Get the first line if we have some portion of an SAV/EAV from
+                   the last buffer or a partial line  */
+                if (sav_eav) {
+                        bytes_parsed += cx231xx_get_video_line(dev, dma_q,
+                                sav_eav,        /* SAV/EAV */
+                                p_buffer + bytes_parsed,        /* p_buffer */
+                                buffer_size - bytes_parsed);/* buf size */
+                }
+
+                /* Now parse data that is completely in this buffer */
+                /* dma_q->is_partial_line = 0;  */
+
+                while (bytes_parsed < buffer_size) {
+                        u32 bytes_used = 0;
+
+                        sav_eav = cx231xx_find_next_SAV_EAV(
+                                p_buffer + bytes_parsed,        /* p_buffer */
+                                buffer_size - bytes_parsed,     /* buf size */
+                                &bytes_used);/* bytes used to get SAV/EAV */
+
+                        bytes_parsed += bytes_used;
+
+                        sav_eav &= 0xF0;
+                        if (sav_eav && (bytes_parsed < buffer_size)) {
+                                bytes_parsed += cx231xx_get_video_line(dev,
+                                        dma_q, sav_eav, /* SAV/EAV */
+                                        p_buffer + bytes_parsed,/* p_buffer */
+                                        buffer_size - bytes_parsed);/*buf size*/
+                        }
+                }
+
+                /* Save the last four bytes of the buffer so we can check the
+                   buffer boundary condition next time */
+                memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
+                bytes_parsed = 0;
+
+        }
+        return rc;
+}
+
+
+u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
+                                 u32 *p_bytes_used)
+{
+        u32 bytes_used;
+        u8 boundary_bytes[8];
+        u8 sav_eav = 0;
+
+        *p_bytes_used = 0;
+
+        /* Create an array of the last 4 bytes of the last buffer and the first
+           4 bytes of the current buffer. */
+
+        memcpy(boundary_bytes, partial_buf, 4);
+        memcpy(boundary_bytes + 4, p_buffer, 4);
+
+        /* Check for the SAV/EAV in the boundary buffer */
+        sav_eav = cx231xx_find_next_SAV_EAV((u8 *)&boundary_bytes, 8,
+                                            &bytes_used);
+
+        if (sav_eav) {
+                /* found a boundary SAV/EAV.  Updates the bytes used to reflect
+                   only those used in the new buffer */
+                *p_bytes_used = bytes_used - 4;
+        }
+
+        return sav_eav;
+}
+
+u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size, u32 *p_bytes_used)
+{
+        u32 i;
+        u8 sav_eav = 0;
+
+        /*
+         * Don't search if the buffer size is less than 4.  It causes a page
+         * fault since buffer_size - 4 evaluates to a large number in that
+         * case.
+         */
+        if (buffer_size < 4) {
+                *p_bytes_used = buffer_size;
+                return 0;
+        }
+
+        for (i = 0; i < (buffer_size - 3); i++) {
+
+                if ((p_buffer[i] == 0xFF) &&
+                    (p_buffer[i + 1] == 0x00) && (p_buffer[i + 2] == 0x00)) {
+
+                        *p_bytes_used = i + 4;
+                        sav_eav = p_buffer[i + 3];
+                        return sav_eav;
+                }
+        }
+
+        *p_bytes_used = buffer_size;
+        return 0;
+}
+
+u32 cx231xx_get_video_line(struct cx231xx *dev,
+                           struct cx231xx_dmaqueue *dma_q, u8 sav_eav,
+                           u8 *p_buffer, u32 buffer_size)
+{
+        u32 bytes_copied = 0;
+        int current_field = -1;
+
+        switch (sav_eav) {
+        case SAV_ACTIVE_VIDEO_FIELD1:
+                /* looking for skipped line which occurred in PAL 720x480 mode.
+                   In this case, there will be no active data contained
+                   between the SAV and EAV */
+                if ((buffer_size > 3) && (p_buffer[0] == 0xFF) &&
+                    (p_buffer[1] == 0x00) && (p_buffer[2] == 0x00) &&
+                    ((p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD1) ||
+                     (p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD2) ||
+                     (p_buffer[3] == EAV_VBLANK_FIELD1) ||
+                     (p_buffer[3] == EAV_VBLANK_FIELD2)))
+                        return bytes_copied;
+                current_field = 1;
+                break;
+
+        case SAV_ACTIVE_VIDEO_FIELD2:
+                /* looking for skipped line which occurred in PAL 720x480 mode.
+                   In this case, there will be no active data contained between
+                   the SAV and EAV */
+                if ((buffer_size > 3) && (p_buffer[0] == 0xFF) &&
+                    (p_buffer[1] == 0x00) && (p_buffer[2] == 0x00) &&
+                    ((p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD1) ||
+                     (p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD2) ||
+                     (p_buffer[3] == EAV_VBLANK_FIELD1)       ||
+                     (p_buffer[3] == EAV_VBLANK_FIELD2)))
+                        return bytes_copied;
+                current_field = 2;
+                break;
+        }
+
+        dma_q->last_sav = sav_eav;
+
+        bytes_copied = cx231xx_copy_video_line(dev, dma_q, p_buffer,
+                                               buffer_size, current_field);
+
+        return bytes_copied;
+}
+
+u32 cx231xx_copy_video_line(struct cx231xx *dev,
+                            struct cx231xx_dmaqueue *dma_q, u8 *p_line,
+                            u32 length, int field_number)
+{
+        u32 bytes_to_copy;
+        struct cx231xx_buffer *buf;
+        u32 _line_size = dev->width * 2;
+
+        if (dma_q->current_field != field_number)
+                cx231xx_reset_video_buffer(dev, dma_q);
+
+        /* get the buffer pointer */
+        if (dev->USE_ISO)
+                buf = dev->video_mode.isoc_ctl.buf;
+        else
+                buf = dev->video_mode.bulk_ctl.buf;
+
+        /* Remember the field number for next time */
+        dma_q->current_field = field_number;
+
+        bytes_to_copy = dma_q->bytes_left_in_line;
+        if (bytes_to_copy > length)
+                bytes_to_copy = length;
+
+        if (dma_q->lines_completed >= dma_q->lines_per_field) {
+                dma_q->bytes_left_in_line -= bytes_to_copy;
+                dma_q->is_partial_line = (dma_q->bytes_left_in_line == 0) ?
+                                          0 : 1;
+                return 0;
+        }
+
+        dma_q->is_partial_line = 1;
+
+        /* If we don't have a buffer, just return the number of bytes we would
+           have copied if we had a buffer. */
+        if (!buf) {
+                dma_q->bytes_left_in_line -= bytes_to_copy;
+                dma_q->is_partial_line = (dma_q->bytes_left_in_line == 0)
+                                         ? 0 : 1;
+                return bytes_to_copy;
+        }
+
+        /* copy the data to video buffer */
+        cx231xx_do_copy(dev, dma_q, p_line, bytes_to_copy);
+
+        dma_q->pos += bytes_to_copy;
+        dma_q->bytes_left_in_line -= bytes_to_copy;
+
+        if (dma_q->bytes_left_in_line == 0) {
+                dma_q->bytes_left_in_line = _line_size;
+                dma_q->lines_completed++;
+                dma_q->is_partial_line = 0;
+
+                if (cx231xx_is_buffer_done(dev, dma_q) && buf) {
+                        buffer_filled(dev, dma_q, buf);
+
+                        dma_q->pos = 0;
+                        buf = NULL;
+                        dma_q->lines_completed = 0;
+                }
+        }
+
+        return bytes_to_copy;
+}
+
+void cx231xx_reset_video_buffer(struct cx231xx *dev,
+                                struct cx231xx_dmaqueue *dma_q)
+{
+        struct cx231xx_buffer *buf;
+
+        /* handle the switch from field 1 to field 2 */
+        if (dma_q->current_field == 1) {
+                if (dma_q->lines_completed >= dma_q->lines_per_field)
+                        dma_q->field1_done = 1;
+                else
+                        dma_q->field1_done = 0;
+        }
+
+        if (dev->USE_ISO)
+                buf = dev->video_mode.isoc_ctl.buf;
+        else
+                buf = dev->video_mode.bulk_ctl.buf;
+
+        if (buf == NULL) {
+                /* first try to get the buffer */
+                get_next_buf(dma_q, &buf);
+
+                dma_q->pos = 0;
+                dma_q->field1_done = 0;
+                dma_q->current_field = -1;
+        }
+
+        /* reset the counters */
+        dma_q->bytes_left_in_line = dev->width << 1;
+        dma_q->lines_completed = 0;
+}
+
+int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                    u8 *p_buffer, u32 bytes_to_copy)
+{
+        u8 *p_out_buffer = NULL;
+        u32 current_line_bytes_copied = 0;
+        struct cx231xx_buffer *buf;
+        u32 _line_size = dev->width << 1;
+        void *startwrite;
+        int offset, lencopy;
+
+        if (dev->USE_ISO)
+                buf = dev->video_mode.isoc_ctl.buf;
+        else
+                buf = dev->video_mode.bulk_ctl.buf;
+
+        if (buf == NULL)
+                return -1;
+
+        p_out_buffer = videobuf_to_vmalloc(&buf->vb);
+
+        current_line_bytes_copied = _line_size - dma_q->bytes_left_in_line;
+
+        /* Offset field 2 one line from the top of the buffer */
+        offset = (dma_q->current_field == 1) ? 0 : _line_size;
+
+        /* Offset for field 2 */
+        startwrite = p_out_buffer + offset;
+
+        /* lines already completed in the current field */
+        startwrite += (dma_q->lines_completed * _line_size * 2);
+
+        /* bytes already completed in the current line */
+        startwrite += current_line_bytes_copied;
+
+        lencopy = dma_q->bytes_left_in_line > bytes_to_copy ?
+                  bytes_to_copy : dma_q->bytes_left_in_line;
+
+        if ((u8 *)(startwrite + lencopy) > (u8 *)(p_out_buffer + buf->vb.size))
+                return 0;
+
+        /* The below copies the UYVY data straight into video buffer */
+        cx231xx_swab((u16 *) p_buffer, (u16 *) startwrite, (u16) lencopy);
+
+        return 0;
+}
+
+void cx231xx_swab(u16 *from, u16 *to, u16 len)
+{
+        u16 i;
+
+        if (len <= 0)
+                return;
+
+        for (i = 0; i < len / 2; i++)
+                to[i] = (from[i] << 8) | (from[i] >> 8);
+}
+
+u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q)
+{
+        u8 buffer_complete = 0;
+
+        /* Dual field stream */
+        buffer_complete = ((dma_q->current_field == 2) &&
+                           (dma_q->lines_completed >= dma_q->lines_per_field) &&
+                            dma_q->field1_done);
+
+        return buffer_complete;
+}
+
+/* ------------------------------------------------------------------
+        Videobuf operations
+   ------------------------------------------------------------------*/
+
+static int
+buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+
+        *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7)>>3;
+        if (0 == *count)
+                *count = CX231XX_DEF_BUF;
+
+        if (*count < CX231XX_MIN_BUF)
+                *count = CX231XX_MIN_BUF;
+
+        return 0;
+}
+
+/* This is called *without* dev->slock held; please keep it that way */
+static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        unsigned long flags = 0;
+
+        if (in_interrupt())
+                BUG();
+
+        /* We used to wait for the buffer to finish here, but this didn't work
+           because, as we were keeping the state as VIDEOBUF_QUEUED,
+           videobuf_queue_cancel marked it as finished for us.
+           (Also, it could wedge forever if the hardware was misconfigured.)
+
+           This should be safe; by the time we get here, the buffer isn't
+           queued anymore. If we ever start marking the buffers as
+           VIDEOBUF_ACTIVE, it won't be, though.
+         */
+        spin_lock_irqsave(&dev->video_mode.slock, flags);
+        if (dev->USE_ISO) {
+                if (dev->video_mode.isoc_ctl.buf == buf)
+                        dev->video_mode.isoc_ctl.buf = NULL;
+        } else {
+                if (dev->video_mode.bulk_ctl.buf == buf)
+                        dev->video_mode.bulk_ctl.buf = NULL;
+        }
+        spin_unlock_irqrestore(&dev->video_mode.slock, flags);
+
+        videobuf_vmalloc_free(&buf->vb);
+        buf->vb.state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int
+buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
+               enum v4l2_field field)
+{
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx *dev = fh->dev;
+        int rc = 0, urb_init = 0;
+
+        /* The only currently supported format is 16 bits/pixel */
+        buf->vb.size = (fh->dev->width * fh->dev->height * dev->format->depth
+                        + 7) >> 3;
+        if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
+                return -EINVAL;
+
+        buf->vb.width = dev->width;
+        buf->vb.height = dev->height;
+        buf->vb.field = field;
+
+        if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
+                rc = videobuf_iolock(vq, &buf->vb, NULL);
+                if (rc < 0)
+                        goto fail;
+        }
+
+        if (dev->USE_ISO) {
+                if (!dev->video_mode.isoc_ctl.num_bufs)
+                        urb_init = 1;
+        } else {
+                if (!dev->video_mode.bulk_ctl.num_bufs)
+                        urb_init = 1;
+        }
+        /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
+                urb_init, dev->video_mode.max_pkt_size);*/
+        if (urb_init) {
+                dev->mode_tv = 0;
+                if (dev->USE_ISO)
+                        rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
+                                       CX231XX_NUM_BUFS,
+                                       dev->video_mode.max_pkt_size,
+                                       cx231xx_isoc_copy);
+                else
+                        rc = cx231xx_init_bulk(dev, CX231XX_NUM_PACKETS,
+                                       CX231XX_NUM_BUFS,
+                                       dev->video_mode.max_pkt_size,
+                                       cx231xx_bulk_copy);
+                if (rc < 0)
+                        goto fail;
+        }
+
+        buf->vb.state = VIDEOBUF_PREPARED;
+        return 0;
+
+fail:
+        free_buffer(vq, buf);
+        return rc;
+}
+
+static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
+{
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = fh->dev;
+        struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
+
+        buf->vb.state = VIDEOBUF_QUEUED;
+        list_add_tail(&buf->vb.queue, &vidq->active);
+
+}
+
+static void buffer_release(struct videobuf_queue *vq,
+                           struct videobuf_buffer *vb)
+{
+        struct cx231xx_buffer *buf =
+            container_of(vb, struct cx231xx_buffer, vb);
+        struct cx231xx_fh *fh = vq->priv_data;
+        struct cx231xx *dev = (struct cx231xx *)fh->dev;
+
+        cx231xx_isocdbg("cx231xx: called buffer_release\n");
+
+        free_buffer(vq, buf);
+}
+
+static struct videobuf_queue_ops cx231xx_video_qops = {
+        .buf_setup = buffer_setup,
+        .buf_prepare = buffer_prepare,
+        .buf_queue = buffer_queue,
+        .buf_release = buffer_release,
+};
+
+/*********************  v4l2 interface  **************************************/
+
+void video_mux(struct cx231xx *dev, int index)
+{
+        dev->video_input = index;
+        dev->ctl_ainput = INPUT(index)->amux;
+
+        cx231xx_set_video_input_mux(dev, index);
+
+        cx25840_call(dev, video, s_routing, INPUT(index)->vmux, 0, 0);
+
+        cx231xx_set_audio_input(dev, dev->ctl_ainput);
+
+        cx231xx_info("video_mux : %d\n", index);
+
+        /* do mode control overrides if required */
+        cx231xx_do_mode_ctrl_overrides(dev);
+}
+
+/* Usage lock check functions */
+static int res_get(struct cx231xx_fh *fh)
+{
+        struct cx231xx *dev = fh->dev;
+        int rc = 0;
+
+        /* This instance already has stream_on */
+        if (fh->stream_on)
+                return rc;
+
+        if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+                if (dev->stream_on)
+                        return -EBUSY;
+                dev->stream_on = 1;
+        } else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
+                if (dev->vbi_stream_on)
+                        return -EBUSY;
+                dev->vbi_stream_on = 1;
+        } else
+                return -EINVAL;
+
+        fh->stream_on = 1;
+
+        return rc;
+}
+
+static int res_check(struct cx231xx_fh *fh)
+{
+        return fh->stream_on;
+}
+
+static void res_free(struct cx231xx_fh *fh)
+{
+        struct cx231xx *dev = fh->dev;
+
+        fh->stream_on = 0;
+
+        if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+                dev->stream_on = 0;
+        if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE)
+                dev->vbi_stream_on = 0;
+}
+
+static int check_dev(struct cx231xx *dev)
+{
+        if (dev->state & DEV_DISCONNECTED) {
+                cx231xx_errdev("v4l2 ioctl: device not present\n");
+                return -ENODEV;
+        }
+        return 0;
+}
+
+/* ------------------------------------------------------------------
+        IOCTL vidioc handling
+   ------------------------------------------------------------------*/
+
+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        f->fmt.pix.width = dev->width;
+        f->fmt.pix.height = dev->height;
+        f->fmt.pix.pixelformat = dev->format->fourcc;
+        f->fmt.pix.bytesperline = (dev->width * dev->format->depth + 7) >> 3;
+        f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * dev->height;
+        f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
+
+        f->fmt.pix.field = V4L2_FIELD_INTERLACED;
+
+        return 0;
+}
+
+static struct cx231xx_fmt *format_by_fourcc(unsigned int fourcc)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(format); i++)
+                if (format[i].fourcc == fourcc)
+                        return &format[i];
+
+        return NULL;
+}
+
+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
+                                  struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        unsigned int width = f->fmt.pix.width;
+        unsigned int height = f->fmt.pix.height;
+        unsigned int maxw = norm_maxw(dev);
+        unsigned int maxh = norm_maxh(dev);
+        struct cx231xx_fmt *fmt;
+
+        fmt = format_by_fourcc(f->fmt.pix.pixelformat);
+        if (!fmt) {
+                cx231xx_videodbg("Fourcc format (%08x) invalid.\n",
+                                 f->fmt.pix.pixelformat);
+                return -EINVAL;
+        }
+
+        /* width must even because of the YUYV format
+           height must be even because of interlacing */
+        v4l_bound_align_image(&width, 48, maxw, 1, &height, 32, maxh, 1, 0);
+
+        f->fmt.pix.width = width;
+        f->fmt.pix.height = height;
+        f->fmt.pix.pixelformat = fmt->fourcc;
+        f->fmt.pix.bytesperline = (dev->width * fmt->depth + 7) >> 3;
+        f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * height;
+        f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
+        f->fmt.pix.field = V4L2_FIELD_INTERLACED;
+
+        return 0;
+}
+
+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+        struct cx231xx_fmt *fmt;
+        struct v4l2_mbus_framefmt mbus_fmt;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        vidioc_try_fmt_vid_cap(file, priv, f);
+
+        fmt = format_by_fourcc(f->fmt.pix.pixelformat);
+        if (!fmt)
+                return -EINVAL;
+
+        if (videobuf_queue_is_busy(&fh->vb_vidq)) {
+                cx231xx_errdev("%s queue busy\n", __func__);
+                return -EBUSY;
+        }
+
+        if (dev->stream_on && !fh->stream_on) {
+                cx231xx_errdev("%s device in use by another fh\n", __func__);
+                return -EBUSY;
+        }
+
+        /* set new image size */
+        dev->width = f->fmt.pix.width;
+        dev->height = f->fmt.pix.height;
+        dev->format = fmt;
+
+        v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, V4L2_MBUS_FMT_FIXED);
+        call_all(dev, video, s_mbus_fmt, &mbus_fmt);
+        v4l2_fill_pix_format(&f->fmt.pix, &mbus_fmt);
+
+        return rc;
+}
+
+static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        *id = dev->norm;
+        return 0;
+}
+
+static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *norm)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        struct v4l2_mbus_framefmt mbus_fmt;
+        struct v4l2_format f;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        cx231xx_info("vidioc_s_std : 0x%x\n", (unsigned int)*norm);
+
+        dev->norm = *norm;
+
+        /* Adjusts width/height, if needed */
+        f.fmt.pix.width = dev->width;
+        f.fmt.pix.height = dev->height;
+        vidioc_try_fmt_vid_cap(file, priv, &f);
+
+        call_all(dev, core, s_std, dev->norm);
+
+        /* We need to reset basic properties in the decoder related to
+           resolution (since a standard change effects things like the number
+           of lines in VACT, etc) */
+        v4l2_fill_mbus_format(&mbus_fmt, &f.fmt.pix, V4L2_MBUS_FMT_FIXED);
+        call_all(dev, video, s_mbus_fmt, &mbus_fmt);
+        v4l2_fill_pix_format(&f.fmt.pix, &mbus_fmt);
+
+        /* set new image size */
+        dev->width = f.fmt.pix.width;
+        dev->height = f.fmt.pix.height;
+
+        /* do mode control overrides */
+        cx231xx_do_mode_ctrl_overrides(dev);
+
+        return 0;
+}
+
+static const char *iname[] = {
+        [CX231XX_VMUX_COMPOSITE1] = "Composite1",
+        [CX231XX_VMUX_SVIDEO]     = "S-Video",
+        [CX231XX_VMUX_TELEVISION] = "Television",
+        [CX231XX_VMUX_CABLE]      = "Cable TV",
+        [CX231XX_VMUX_DVB]        = "DVB",
+        [CX231XX_VMUX_DEBUG]      = "for debug only",
+};
+
+static int vidioc_enum_input(struct file *file, void *priv,
+                             struct v4l2_input *i)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        u32 gen_stat;
+        unsigned int ret, n;
+
+        n = i->index;
+        if (n >= MAX_CX231XX_INPUT)
+                return -EINVAL;
+        if (0 == INPUT(n)->type)
+                return -EINVAL;
+
+        i->index = n;
+        i->type = V4L2_INPUT_TYPE_CAMERA;
+
+        strcpy(i->name, iname[INPUT(n)->type]);
+
+        if ((CX231XX_VMUX_TELEVISION == INPUT(n)->type) ||
+            (CX231XX_VMUX_CABLE == INPUT(n)->type))
+                i->type = V4L2_INPUT_TYPE_TUNER;
+
+        i->std = dev->vdev->tvnorms;
+
+        /* If they are asking about the active input, read signal status */
+        if (n == dev->video_input) {
+                ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                            GEN_STAT, 2, &gen_stat, 4);
+                if (ret > 0) {
+                        if ((gen_stat & FLD_VPRES) == 0x00)
+                                i->status |= V4L2_IN_ST_NO_SIGNAL;
+                        if ((gen_stat & FLD_HLOCK) == 0x00)
+                                i->status |= V4L2_IN_ST_NO_H_LOCK;
+                }
+        }
+
+        return 0;
+}
+
+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        *i = dev->video_input;
+
+        return 0;
+}
+
+static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        dev->mode_tv = 0;
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if (i >= MAX_CX231XX_INPUT)
+                return -EINVAL;
+        if (0 == INPUT(i)->type)
+                return -EINVAL;
+
+        video_mux(dev, i);
+
+        if (INPUT(i)->type == CX231XX_VMUX_TELEVISION ||
+            INPUT(i)->type == CX231XX_VMUX_CABLE) {
+                /* There's a tuner, so reset the standard and put it on the
+                   last known frequency (since it was probably powered down
+                   until now */
+                call_all(dev, core, s_std, dev->norm);
+        }
+
+        return 0;
+}
+
+static int vidioc_g_audio(struct file *file, void *priv, struct v4l2_audio *a)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        switch (a->index) {
+        case CX231XX_AMUX_VIDEO:
+                strcpy(a->name, "Television");
+                break;
+        case CX231XX_AMUX_LINE_IN:
+                strcpy(a->name, "Line In");
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        a->index = dev->ctl_ainput;
+        a->capability = V4L2_AUDCAP_STEREO;
+
+        return 0;
+}
+
+static int vidioc_s_audio(struct file *file, void *priv, struct v4l2_audio *a)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int status = 0;
+
+        /* Doesn't allow manual routing */
+        if (a->index != dev->ctl_ainput)
+                return -EINVAL;
+
+        dev->ctl_ainput = INPUT(a->index)->amux;
+        status = cx231xx_set_audio_input(dev, dev->ctl_ainput);
+
+        return status;
+}
+
+static int vidioc_queryctrl(struct file *file, void *priv,
+                            struct v4l2_queryctrl *qc)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int id = qc->id;
+        int i;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        qc->id = v4l2_ctrl_next(ctrl_classes, qc->id);
+        if (unlikely(qc->id == 0))
+                return -EINVAL;
+
+        memset(qc, 0, sizeof(*qc));
+
+        qc->id = id;
+
+        if (qc->id < V4L2_CID_BASE || qc->id >= V4L2_CID_LASTP1)
+                return -EINVAL;
+
+        for (i = 0; i < CX231XX_CTLS; i++)
+                if (cx231xx_ctls[i].v.id == qc->id)
+                        break;
+
+        if (i == CX231XX_CTLS) {
+                *qc = no_ctl;
+                return 0;
+        }
+        *qc = cx231xx_ctls[i].v;
+
+        call_all(dev, core, queryctrl, qc);
+
+        if (qc->type)
+                return 0;
+        else
+                return -EINVAL;
+}
+
+static int vidioc_g_ctrl(struct file *file, void *priv,
+                         struct v4l2_control *ctrl)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        call_all(dev, core, g_ctrl, ctrl);
+        return rc;
+}
+
+static int vidioc_s_ctrl(struct file *file, void *priv,
+                         struct v4l2_control *ctrl)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        call_all(dev, core, s_ctrl, ctrl);
+        return rc;
+}
+
+static int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if (0 != t->index)
+                return -EINVAL;
+
+        strcpy(t->name, "Tuner");
+
+        t->type = V4L2_TUNER_ANALOG_TV;
+        t->capability = V4L2_TUNER_CAP_NORM;
+        t->rangehigh = 0xffffffffUL;
+        t->signal = 0xffff;     /* LOCKED */
+
+        return 0;
+}
+
+static int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if (0 != t->index)
+                return -EINVAL;
+#if 0
+        call_all(dev, tuner, s_tuner, t);
+#endif
+        return 0;
+}
+
+static int vidioc_g_frequency(struct file *file, void *priv,
+                              struct v4l2_frequency *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        f->type = fh->radio ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
+        f->frequency = dev->ctl_freq;
+
+        call_all(dev, tuner, g_frequency, f);
+
+        return 0;
+}
+
+static int vidioc_s_frequency(struct file *file, void *priv,
+                              struct v4l2_frequency *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+        u32 if_frequency = 5400000;
+
+        cx231xx_info("Enter vidioc_s_frequency()f->frequency=%d;f->type=%d\n",
+                 f->frequency, f->type);
+        /*cx231xx_info("f->type:  1-radio 2-analogTV 3-digitalTV\n");*/
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if (0 != f->tuner)
+                return -EINVAL;
+
+        if (unlikely(0 == fh->radio && f->type != V4L2_TUNER_ANALOG_TV))
+                return -EINVAL;
+        if (unlikely(1 == fh->radio && f->type != V4L2_TUNER_RADIO))
+                return -EINVAL;
+
+        /* set pre channel change settings in DIF first */
+        rc = cx231xx_tuner_pre_channel_change(dev);
+
+        dev->ctl_freq = f->frequency;
+        call_all(dev, tuner, s_frequency, f);
+
+        /* set post channel change settings in DIF first */
+        rc = cx231xx_tuner_post_channel_change(dev);
+
+        if (dev->tuner_type == TUNER_NXP_TDA18271) {
+                if (dev->norm & (V4L2_STD_MN | V4L2_STD_NTSC_443))
+                        if_frequency = 5400000;  /*5.4MHz       */
+                else if (dev->norm & V4L2_STD_B)
+                        if_frequency = 6000000;  /*6.0MHz       */
+                else if (dev->norm & (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK))
+                        if_frequency = 6900000;  /*6.9MHz       */
+                else if (dev->norm & V4L2_STD_GH)
+                        if_frequency = 7100000;  /*7.1MHz       */
+                else if (dev->norm & V4L2_STD_PAL_I)
+                        if_frequency = 7250000;  /*7.25MHz      */
+                else if (dev->norm & V4L2_STD_SECAM_L)
+                        if_frequency = 6900000;  /*6.9MHz       */
+                else if (dev->norm & V4L2_STD_SECAM_LC)
+                        if_frequency = 1250000;  /*1.25MHz      */
+
+                cx231xx_info("if_frequency is set to %d\n", if_frequency);
+                cx231xx_set_Colibri_For_LowIF(dev, if_frequency, 1, 1);
+
+                update_HH_register_after_set_DIF(dev);
+        }
+
+        cx231xx_info("Set New FREQUENCY to %d\n", f->frequency);
+
+        return rc;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+
+/*
+  -R, --list-registers=type=<host/i2cdrv/i2caddr>,
+                                chip=<chip>[,min=<addr>,max=<addr>]
+                     dump registers from <min> to <max> [VIDIOC_DBG_G_REGISTER]
+  -r, --set-register=type=<host/i2cdrv/i2caddr>,
+                                chip=<chip>,reg=<addr>,val=<val>
+                     set the register [VIDIOC_DBG_S_REGISTER]
+
+  if type == host, then <chip> is the hosts chip ID (default 0)
+  if type == i2cdrv (default), then <chip> is the I2C driver name or ID
+  if type == i2caddr, then <chip> is the 7-bit I2C address
+*/
+
+static int vidioc_g_register(struct file *file, void *priv,
+                             struct v4l2_dbg_register *reg)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int ret = 0;
+        u8 value[4] = { 0, 0, 0, 0 };
+        u32 data = 0;
+
+        switch (reg->match.type) {
+        case V4L2_CHIP_MATCH_HOST:
+                switch (reg->match.addr) {
+                case 0: /* Cx231xx - internal registers */
+                        ret = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
+                                                  (u16)reg->reg, value, 4);
+                        reg->val = value[0] | value[1] << 8 |
+                                   value[2] << 16 | value[3] << 24;
+                        break;
+                case 1: /* AFE - read byte */
+                        ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
+                                                  (u16)reg->reg, 2, &data, 1);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 14: /* AFE - read dword */
+                        ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
+                                                  (u16)reg->reg, 2, &data, 4);
+                        reg->val = le32_to_cpu(data);
+                        break;
+                case 2: /* Video Block - read byte */
+                        ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                                  (u16)reg->reg, 2, &data, 1);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 24: /* Video Block - read dword */
+                        ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
+                                                  (u16)reg->reg, 2, &data, 4);
+                        reg->val = le32_to_cpu(data);
+                        break;
+                case 3: /* I2S block - read byte */
+                        ret = cx231xx_read_i2c_data(dev,
+                                                    I2S_BLK_DEVICE_ADDRESS,
+                                                    (u16)reg->reg, 1,
+                                                    &data, 1);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 34: /* I2S Block - read dword */
+                        ret =
+                            cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
+                                                  (u16)reg->reg, 1, &data, 4);
+                        reg->val = le32_to_cpu(data);
+                        break;
+                }
+                return ret < 0 ? ret : 0;
+
+        case V4L2_CHIP_MATCH_I2C_DRIVER:
+                call_all(dev, core, g_register, reg);
+                return 0;
+        case V4L2_CHIP_MATCH_I2C_ADDR:/*for register debug*/
+                switch (reg->match.addr) {
+                case 0: /* Cx231xx - internal registers */
+                        ret = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
+                                                  (u16)reg->reg, value, 4);
+                        reg->val = value[0] | value[1] << 8 |
+                                   value[2] << 16 | value[3] << 24;
+
+                        break;
+                case 0x600:/* AFE - read byte */
+                        ret = cx231xx_read_i2c_master(dev, AFE_DEVICE_ADDRESS,
+                                                 (u16)reg->reg, 2,
+                                                 &data, 1 , 0);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+
+                case 0x880:/* Video Block - read byte */
+                        if (reg->reg < 0x0b) {
+                                ret = cx231xx_read_i2c_master(dev,
+                                                VID_BLK_I2C_ADDRESS,
+                                                 (u16)reg->reg, 2,
+                                                 &data, 1 , 0);
+                                reg->val = le32_to_cpu(data & 0xff);
+                        } else {
+                                ret = cx231xx_read_i2c_master(dev,
+                                                VID_BLK_I2C_ADDRESS,
+                                                 (u16)reg->reg, 2,
+                                                 &data, 4 , 0);
+                                reg->val = le32_to_cpu(data);
+                        }
+                        break;
+                case 0x980:
+                        ret = cx231xx_read_i2c_master(dev,
+                                                I2S_BLK_DEVICE_ADDRESS,
+                                                (u16)reg->reg, 1,
+                                                &data, 1 , 0);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 0x400:
+                        ret =
+                            cx231xx_read_i2c_master(dev, 0x40,
+                                                  (u16)reg->reg, 1,
+                                                 &data, 1 , 0);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 0xc01:
+                        ret =
+                                cx231xx_read_i2c_master(dev, 0xc0,
+                                                (u16)reg->reg, 2,
+                                                 &data, 38, 1);
+                        reg->val = le32_to_cpu(data);
+                        break;
+                case 0x022:
+                        ret =
+                                cx231xx_read_i2c_master(dev, 0x02,
+                                                (u16)reg->reg, 1,
+                                                 &data, 1, 2);
+                        reg->val = le32_to_cpu(data & 0xff);
+                        break;
+                case 0x322:
+                        ret = cx231xx_read_i2c_master(dev,
+                                                0x32,
+                                                 (u16)reg->reg, 1,
+                                                 &data, 4 , 2);
+                                reg->val = le32_to_cpu(data);
+                        break;
+                case 0x342:
+                        ret = cx231xx_read_i2c_master(dev,
+                                                0x34,
+                                                 (u16)reg->reg, 1,
+                                                 &data, 4 , 2);
+                                reg->val = le32_to_cpu(data);
+                        break;
+
+                default:
+                        cx231xx_info("no match device address!!\n");
+                        break;
+                        }
+                return ret < 0 ? ret : 0;
+                /*return -EINVAL;*/
+        default:
+                if (!v4l2_chip_match_host(&reg->match))
+                        return -EINVAL;
+        }
+
+        call_all(dev, core, g_register, reg);
+
+        return ret;
+}
+
+static int vidioc_s_register(struct file *file, void *priv,
+                             struct v4l2_dbg_register *reg)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int ret = 0;
+        __le64 buf;
+        u32 value;
+        u8 data[4] = { 0, 0, 0, 0 };
+
+        buf = cpu_to_le64(reg->val);
+
+        switch (reg->match.type) {
+        case V4L2_CHIP_MATCH_HOST:
+                {
+                        value = (u32) buf & 0xffffffff;
+
+                        switch (reg->match.addr) {
+                        case 0: /* cx231xx internal registers */
+                                data[0] = (u8) value;
+                                data[1] = (u8) (value >> 8);
+                                data[2] = (u8) (value >> 16);
+                                data[3] = (u8) (value >> 24);
+                                ret = cx231xx_write_ctrl_reg(dev,
+                                                           VRT_SET_REGISTER,
+                                                           (u16)reg->reg, data,
+                                                           4);
+                                break;
+                        case 1: /* AFE - read byte */
+                                ret = cx231xx_write_i2c_data(dev,
+                                                        AFE_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 1);
+                                break;
+                        case 14: /* AFE - read dword */
+                                ret = cx231xx_write_i2c_data(dev,
+                                                        AFE_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 4);
+                                break;
+                        case 2: /* Video Block - read byte */
+                                ret =
+                                    cx231xx_write_i2c_data(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 1);
+                                break;
+                        case 24: /* Video Block - read dword */
+                                ret =
+                                    cx231xx_write_i2c_data(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 4);
+                                break;
+                        case 3: /* I2S block - read byte */
+                                ret =
+                                    cx231xx_write_i2c_data(dev,
+                                                        I2S_BLK_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 1,
+                                                        value, 1);
+                                break;
+                        case 34: /* I2S block - read dword */
+                                ret =
+                                    cx231xx_write_i2c_data(dev,
+                                                        I2S_BLK_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 1,
+                                                        value, 4);
+                                break;
+                        }
+                }
+                return ret < 0 ? ret : 0;
+        case V4L2_CHIP_MATCH_I2C_ADDR:
+                {
+                        value = (u32) buf & 0xffffffff;
+
+                        switch (reg->match.addr) {
+                        case 0:/*cx231xx internal registers*/
+                                        data[0] = (u8) value;
+                                        data[1] = (u8) (value >> 8);
+                                        data[2] = (u8) (value >> 16);
+                                        data[3] = (u8) (value >> 24);
+                                        ret = cx231xx_write_ctrl_reg(dev,
+                                                           VRT_SET_REGISTER,
+                                                           (u16)reg->reg, data,
+                                                           4);
+                                        break;
+                        case 0x600:/* AFE - read byte */
+                                        ret = cx231xx_write_i2c_master(dev,
+                                                        AFE_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 1 , 0);
+                                        break;
+
+                        case 0x880:/* Video Block - read byte */
+                                        if (reg->reg < 0x0b)
+                                                cx231xx_write_i2c_master(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 1, 0);
+                                        else
+                                                cx231xx_write_i2c_master(dev,
+                                                        VID_BLK_I2C_ADDRESS,
+                                                        (u16)reg->reg, 2,
+                                                        value, 4, 0);
+                                        break;
+                        case 0x980:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                        I2S_BLK_DEVICE_ADDRESS,
+                                                        (u16)reg->reg, 1,
+                                                        value, 1, 0);
+                                        break;
+                        case 0x400:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                        0x40,
+                                                        (u16)reg->reg, 1,
+                                                        value, 1, 0);
+                                        break;
+                        case 0xc01:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                         0xc0,
+                                                         (u16)reg->reg, 1,
+                                                         value, 1, 1);
+                                        break;
+
+                        case 0x022:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                        0x02,
+                                                        (u16)reg->reg, 1,
+                                                        value, 1, 2);
+                        case 0x322:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                        0x32,
+                                                        (u16)reg->reg, 1,
+                                                        value, 4, 2);
+                                        break;
+
+                        case 0x342:
+                                        ret =
+                                                cx231xx_write_i2c_master(dev,
+                                                        0x34,
+                                                        (u16)reg->reg, 1,
+                                                        value, 4, 2);
+                                        break;
+                        default:
+                                cx231xx_info("no match device address, "
+                                        "the value is %x\n", reg->match.addr);
+                                        break;
+
+                                        }
+
+                }
+        default:
+                break;
+        }
+
+        call_all(dev, core, s_register, reg);
+
+        return ret;
+}
+#endif
+
+static int vidioc_cropcap(struct file *file, void *priv,
+                          struct v4l2_cropcap *cc)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+                return -EINVAL;
+
+        cc->bounds.left = 0;
+        cc->bounds.top = 0;
+        cc->bounds.width = dev->width;
+        cc->bounds.height = dev->height;
+        cc->defrect = cc->bounds;
+        cc->pixelaspect.numerator = 54; /* 4:3 FIXME: remove magic numbers */
+        cc->pixelaspect.denominator = 59;
+
+        return 0;
+}
+
+static int vidioc_streamon(struct file *file, void *priv,
+                           enum v4l2_buf_type type)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        rc = res_get(fh);
+
+        if (likely(rc >= 0))
+                rc = videobuf_streamon(&fh->vb_vidq);
+
+        call_all(dev, video, s_stream, 1);
+
+        return rc;
+}
+
+static int vidioc_streamoff(struct file *file, void *priv,
+                            enum v4l2_buf_type type)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if ((fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+            (fh->type != V4L2_BUF_TYPE_VBI_CAPTURE))
+                return -EINVAL;
+        if (type != fh->type)
+                return -EINVAL;
+
+        cx25840_call(dev, video, s_stream, 0);
+
+        videobuf_streamoff(&fh->vb_vidq);
+        res_free(fh);
+
+        return 0;
+}
+
+static int vidioc_querycap(struct file *file, void *priv,
+                           struct v4l2_capability *cap)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        strlcpy(cap->driver, "cx231xx", sizeof(cap->driver));
+        strlcpy(cap->card, cx231xx_boards[dev->model].name, sizeof(cap->card));
+        usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info));
+
+        cap->capabilities = V4L2_CAP_VBI_CAPTURE |
+#if 0
+                V4L2_CAP_SLICED_VBI_CAPTURE |
+#endif
+                V4L2_CAP_VIDEO_CAPTURE  |
+                V4L2_CAP_AUDIO          |
+                V4L2_CAP_READWRITE      |
+                V4L2_CAP_STREAMING;
+
+        if (dev->tuner_type != TUNER_ABSENT)
+                cap->capabilities |= V4L2_CAP_TUNER;
+
+        return 0;
+}
+
+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
+                                   struct v4l2_fmtdesc *f)
+{
+        if (unlikely(f->index >= ARRAY_SIZE(format)))
+                return -EINVAL;
+
+        strlcpy(f->description, format[f->index].name, sizeof(f->description));
+        f->pixelformat = format[f->index].fourcc;
+
+        return 0;
+}
+
+/* Sliced VBI ioctls */
+static int vidioc_g_fmt_sliced_vbi_cap(struct file *file, void *priv,
+                                       struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        f->fmt.sliced.service_set = 0;
+
+        call_all(dev, vbi, g_sliced_fmt, &f->fmt.sliced);
+
+        if (f->fmt.sliced.service_set == 0)
+                rc = -EINVAL;
+
+        return rc;
+}
+
+static int vidioc_try_set_sliced_vbi_cap(struct file *file, void *priv,
+                                         struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        call_all(dev, vbi, g_sliced_fmt, &f->fmt.sliced);
+
+        if (f->fmt.sliced.service_set == 0)
+                return -EINVAL;
+
+        return 0;
+}
+
+/* RAW VBI ioctls */
+
+static int vidioc_g_fmt_vbi_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        f->fmt.vbi.sampling_rate = 6750000 * 4;
+        f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
+        f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
+        f->fmt.vbi.offset = 0;
+        f->fmt.vbi.start[0] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_START_LINE : NTSC_VBI_START_LINE;
+        f->fmt.vbi.count[0] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_LINES : NTSC_VBI_LINES;
+        f->fmt.vbi.start[1] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_START_LINE + 312 : NTSC_VBI_START_LINE + 263;
+        f->fmt.vbi.count[1] = f->fmt.vbi.count[0];
+
+        return 0;
+
+}
+
+static int vidioc_try_fmt_vbi_cap(struct file *file, void *priv,
+                                  struct v4l2_format *f)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+
+        if (dev->vbi_stream_on && !fh->stream_on) {
+                cx231xx_errdev("%s device in use by another fh\n", __func__);
+                return -EBUSY;
+        }
+
+        f->type = V4L2_BUF_TYPE_VBI_CAPTURE;
+        f->fmt.vbi.sampling_rate = 6750000 * 4;
+        f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
+        f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
+        f->fmt.vbi.offset = 0;
+        f->fmt.vbi.flags = 0;
+        f->fmt.vbi.start[0] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_START_LINE : NTSC_VBI_START_LINE;
+        f->fmt.vbi.count[0] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_LINES : NTSC_VBI_LINES;
+        f->fmt.vbi.start[1] = (dev->norm & V4L2_STD_625_50) ?
+            PAL_VBI_START_LINE + 312 : NTSC_VBI_START_LINE + 263;
+        f->fmt.vbi.count[1] = f->fmt.vbi.count[0];
+
+        return 0;
+
+}
+
+static int vidioc_reqbufs(struct file *file, void *priv,
+                          struct v4l2_requestbuffers *rb)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        return videobuf_reqbufs(&fh->vb_vidq, rb);
+}
+
+static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        return videobuf_querybuf(&fh->vb_vidq, b);
+}
+
+static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        return videobuf_qbuf(&fh->vb_vidq, b);
+}
+
+static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+        struct cx231xx_fh *fh = priv;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        return videobuf_dqbuf(&fh->vb_vidq, b, file->f_flags & O_NONBLOCK);
+}
+
+/* ----------------------------------------------------------- */
+/* RADIO ESPECIFIC IOCTLS                                      */
+/* ----------------------------------------------------------- */
+
+static int radio_querycap(struct file *file, void *priv,
+                          struct v4l2_capability *cap)
+{
+        struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
+
+        strlcpy(cap->driver, "cx231xx", sizeof(cap->driver));
+        strlcpy(cap->card, cx231xx_boards[dev->model].name, sizeof(cap->card));
+        usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info));
+
+        cap->capabilities = V4L2_CAP_TUNER;
+        return 0;
+}
+
+static int radio_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
+{
+        struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
+
+        if (unlikely(t->index > 0))
+                return -EINVAL;
+
+        strcpy(t->name, "Radio");
+        t->type = V4L2_TUNER_RADIO;
+
+        call_all(dev, tuner, s_tuner, t);
+
+        return 0;
+}
+
+static int radio_enum_input(struct file *file, void *priv, struct v4l2_input *i)
+{
+        if (i->index != 0)
+                return -EINVAL;
+        strcpy(i->name, "Radio");
+        i->type = V4L2_INPUT_TYPE_TUNER;
+
+        return 0;
+}
+
+static int radio_g_audio(struct file *file, void *priv, struct v4l2_audio *a)
+{
+        if (unlikely(a->index))
+                return -EINVAL;
+
+        strcpy(a->name, "Radio");
+        return 0;
+}
+
+static int radio_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
+{
+        struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
+
+        if (0 != t->index)
+                return -EINVAL;
+
+        call_all(dev, tuner, s_tuner, t);
+
+        return 0;
+}
+
+static int radio_s_audio(struct file *file, void *fh, struct v4l2_audio *a)
+{
+        return 0;
+}
+
+static int radio_s_input(struct file *file, void *fh, unsigned int i)
+{
+        return 0;
+}
+
+static int radio_queryctrl(struct file *file, void *priv,
+                           struct v4l2_queryctrl *c)
+{
+        int i;
+
+        if (c->id < V4L2_CID_BASE || c->id >= V4L2_CID_LASTP1)
+                return -EINVAL;
+        if (c->id == V4L2_CID_AUDIO_MUTE) {
+                for (i = 0; i < CX231XX_CTLS; i++) {
+                        if (cx231xx_ctls[i].v.id == c->id)
+                                break;
+                }
+                if (i == CX231XX_CTLS)
+                        return -EINVAL;
+                *c = cx231xx_ctls[i].v;
+        } else
+                *c = no_ctl;
+        return 0;
+}
+
+/*
+ * cx231xx_v4l2_open()
+ * inits the device and starts isoc transfer
+ */
+static int cx231xx_v4l2_open(struct file *filp)
+{
+        int errCode = 0, radio = 0;
+        struct video_device *vdev = video_devdata(filp);
+        struct cx231xx *dev = video_drvdata(filp);
+        struct cx231xx_fh *fh;
+        enum v4l2_buf_type fh_type = 0;
+
+        switch (vdev->vfl_type) {
+        case VFL_TYPE_GRABBER:
+                fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+                break;
+        case VFL_TYPE_VBI:
+                fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
+                break;
+        case VFL_TYPE_RADIO:
+                radio = 1;
+                break;
+        }
+
+        cx231xx_videodbg("open dev=%s type=%s users=%d\n",
+                         video_device_node_name(vdev), v4l2_type_names[fh_type],
+                         dev->users);
+
+#if 0
+        errCode = cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
+        if (errCode < 0) {
+                cx231xx_errdev
+                    ("Device locked on digital mode. Can't open analog\n");
+                return -EBUSY;
+        }
+#endif
+
+        fh = kzalloc(sizeof(struct cx231xx_fh), GFP_KERNEL);
+        if (!fh) {
+                cx231xx_errdev("cx231xx-video.c: Out of memory?!\n");
+                return -ENOMEM;
+        }
+        if (mutex_lock_interruptible(&dev->lock)) {
+                kfree(fh);
+                return -ERESTARTSYS;
+        }
+        fh->dev = dev;
+        fh->radio = radio;
+        fh->type = fh_type;
+        filp->private_data = fh;
+
+        if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE && dev->users == 0) {
+                dev->width = norm_maxw(dev);
+                dev->height = norm_maxh(dev);
+
+                /* Power up in Analog TV mode */
+                if (dev->board.external_av)
+                        cx231xx_set_power_mode(dev,
+                                 POLARIS_AVMODE_ENXTERNAL_AV);
+                else
+                        cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);
+
+#if 0
+                cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
+#endif
+
+                /* set video alternate setting */
+                cx231xx_set_video_alternate(dev);
+
+                /* Needed, since GPIO might have disabled power of
+                   some i2c device */
+                cx231xx_config_i2c(dev);
+
+                /* device needs to be initialized before isoc transfer */
+                dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
+
+        }
+        if (fh->radio) {
+                cx231xx_videodbg("video_open: setting radio device\n");
+
+                /* cx231xx_start_radio(dev); */
+
+                call_all(dev, tuner, s_radio);
+        }
+
+        dev->users++;
+
+        if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+                videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_video_qops,
+                                            NULL, &dev->video_mode.slock,
+                                            fh->type, V4L2_FIELD_INTERLACED,
+                                            sizeof(struct cx231xx_buffer),
+                                            fh, &dev->lock);
+        if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
+                /* Set the required alternate setting  VBI interface works in
+                   Bulk mode only */
+                cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
+
+                videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_vbi_qops,
+                                            NULL, &dev->vbi_mode.slock,
+                                            fh->type, V4L2_FIELD_SEQ_TB,
+                                            sizeof(struct cx231xx_buffer),
+                                            fh, &dev->lock);
+        }
+        mutex_unlock(&dev->lock);
+
+        return errCode;
+}
+
+/*
+ * cx231xx_realease_resources()
+ * unregisters the v4l2,i2c and usb devices
+ * called when the device gets disconected or at module unload
+*/
+void cx231xx_release_analog_resources(struct cx231xx *dev)
+{
+
+        /*FIXME: I2C IR should be disconnected */
+
+        if (dev->radio_dev) {
+                if (video_is_registered(dev->radio_dev))
+                        video_unregister_device(dev->radio_dev);
+                else
+                        video_device_release(dev->radio_dev);
+                dev->radio_dev = NULL;
+        }
+        if (dev->vbi_dev) {
+                cx231xx_info("V4L2 device %s deregistered\n",
+                             video_device_node_name(dev->vbi_dev));
+                if (video_is_registered(dev->vbi_dev))
+                        video_unregister_device(dev->vbi_dev);
+                else
+                        video_device_release(dev->vbi_dev);
+                dev->vbi_dev = NULL;
+        }
+        if (dev->vdev) {
+                cx231xx_info("V4L2 device %s deregistered\n",
+                             video_device_node_name(dev->vdev));
+
+                if (dev->board.has_417)
+                        cx231xx_417_unregister(dev);
+
+                if (video_is_registered(dev->vdev))
+                        video_unregister_device(dev->vdev);
+                else
+                        video_device_release(dev->vdev);
+                dev->vdev = NULL;
+        }
+}
+
+/*
+ * cx231xx_close()
+ * stops streaming and deallocates all resources allocated by the v4l2
+ * calls and ioctls
+ */
+static int cx231xx_close(struct file *filp)
+{
+        struct cx231xx_fh *fh = filp->private_data;
+        struct cx231xx *dev = fh->dev;
+
+        cx231xx_videodbg("users=%d\n", dev->users);
+
+        cx231xx_videodbg("users=%d\n", dev->users);
+        if (res_check(fh))
+                res_free(fh);
+
+        /*
+         * To workaround error number=-71 on EP0 for VideoGrabber,
+         *       need exclude following.
+         * FIXME: It is probably safe to remove most of these, as we're
+         * now avoiding the alternate setting for INDEX_VANC
+         */
+        if (!dev->board.no_alt_vanc)
+                if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
+                        videobuf_stop(&fh->vb_vidq);
+                        videobuf_mmap_free(&fh->vb_vidq);
+
+                        /* the device is already disconnect,
+                           free the remaining resources */
+                        if (dev->state & DEV_DISCONNECTED) {
+                                if (atomic_read(&dev->devlist_count) > 0) {
+                                        cx231xx_release_resources(dev);
+                                        fh->dev = NULL;
+                                        return 0;
+                                }
+                                return 0;
+                        }
+
+                        /* do this before setting alternate! */
+                        cx231xx_uninit_vbi_isoc(dev);
+
+                        /* set alternate 0 */
+                        if (!dev->vbi_or_sliced_cc_mode)
+                                cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
+                        else
+                                cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
+
+                        kfree(fh);
+                        dev->users--;
+                        wake_up_interruptible_nr(&dev->open, 1);
+                        return 0;
+                }
+
+        dev->users--;
+        if (!dev->users) {
+                videobuf_stop(&fh->vb_vidq);
+                videobuf_mmap_free(&fh->vb_vidq);
+
+                /* the device is already disconnect,
+                   free the remaining resources */
+                if (dev->state & DEV_DISCONNECTED) {
+                        cx231xx_release_resources(dev);
+                        fh->dev = NULL;
+                        return 0;
+                }
+
+                /* Save some power by putting tuner to sleep */
+                call_all(dev, core, s_power, 0);
+
+                /* do this before setting alternate! */
+                if (dev->USE_ISO)
+                        cx231xx_uninit_isoc(dev);
+                else
+                        cx231xx_uninit_bulk(dev);
+                cx231xx_set_mode(dev, CX231XX_SUSPEND);
+
+                /* set alternate 0 */
+                cx231xx_set_alt_setting(dev, INDEX_VIDEO, 0);
+        }
+        kfree(fh);
+        wake_up_interruptible_nr(&dev->open, 1);
+        return 0;
+}
+
+static int cx231xx_v4l2_close(struct file *filp)
+{
+        struct cx231xx_fh *fh = filp->private_data;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        mutex_lock(&dev->lock);
+        rc = cx231xx_close(filp);
+        mutex_unlock(&dev->lock);
+        return rc;
+}
+
+/*
+ * cx231xx_v4l2_read()
+ * will allocate buffers when called for the first time
+ */
+static ssize_t
+cx231xx_v4l2_read(struct file *filp, char __user *buf, size_t count,
+                  loff_t *pos)
+{
+        struct cx231xx_fh *fh = filp->private_data;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        if ((fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
+            (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE)) {
+                rc = res_get(fh);
+
+                if (unlikely(rc < 0))
+                        return rc;
+
+                if (mutex_lock_interruptible(&dev->lock))
+                        return -ERESTARTSYS;
+                rc = videobuf_read_stream(&fh->vb_vidq, buf, count, pos, 0,
+                                            filp->f_flags & O_NONBLOCK);
+                mutex_unlock(&dev->lock);
+                return rc;
+        }
+        return 0;
+}
+
+/*
+ * cx231xx_v4l2_poll()
+ * will allocate buffers when called for the first time
+ */
+static unsigned int cx231xx_v4l2_poll(struct file *filp, poll_table *wait)
+{
+        struct cx231xx_fh *fh = filp->private_data;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        rc = res_get(fh);
+
+        if (unlikely(rc < 0))
+                return POLLERR;
+
+        if ((V4L2_BUF_TYPE_VIDEO_CAPTURE == fh->type) ||
+            (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type)) {
+                unsigned int res;
+
+                mutex_lock(&dev->lock);
+                res = videobuf_poll_stream(filp, &fh->vb_vidq, wait);
+                mutex_unlock(&dev->lock);
+                return res;
+        }
+        return POLLERR;
+}
+
+/*
+ * cx231xx_v4l2_mmap()
+ */
+static int cx231xx_v4l2_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+        struct cx231xx_fh *fh = filp->private_data;
+        struct cx231xx *dev = fh->dev;
+        int rc;
+
+        rc = check_dev(dev);
+        if (rc < 0)
+                return rc;
+
+        rc = res_get(fh);
+
+        if (unlikely(rc < 0))
+                return rc;
+
+        if (mutex_lock_interruptible(&dev->lock))
+                return -ERESTARTSYS;
+        rc = videobuf_mmap_mapper(&fh->vb_vidq, vma);
+        mutex_unlock(&dev->lock);
+
+        cx231xx_videodbg("vma start=0x%08lx, size=%ld, ret=%d\n",
+                         (unsigned long)vma->vm_start,
+                         (unsigned long)vma->vm_end -
+                         (unsigned long)vma->vm_start, rc);
+
+        return rc;
+}
+
+static const struct v4l2_file_operations cx231xx_v4l_fops = {
+        .owner   = THIS_MODULE,
+        .open    = cx231xx_v4l2_open,
+        .release = cx231xx_v4l2_close,
+        .read    = cx231xx_v4l2_read,
+        .poll    = cx231xx_v4l2_poll,
+        .mmap    = cx231xx_v4l2_mmap,
+        .unlocked_ioctl   = video_ioctl2,
+};
+
+static const struct v4l2_ioctl_ops video_ioctl_ops = {
+        .vidioc_querycap               = vidioc_querycap,
+        .vidioc_enum_fmt_vid_cap       = vidioc_enum_fmt_vid_cap,
+        .vidioc_g_fmt_vid_cap          = vidioc_g_fmt_vid_cap,
+        .vidioc_try_fmt_vid_cap        = vidioc_try_fmt_vid_cap,
+        .vidioc_s_fmt_vid_cap          = vidioc_s_fmt_vid_cap,
+        .vidioc_g_fmt_vbi_cap          = vidioc_g_fmt_vbi_cap,
+        .vidioc_try_fmt_vbi_cap        = vidioc_try_fmt_vbi_cap,
+        .vidioc_s_fmt_vbi_cap          = vidioc_try_fmt_vbi_cap,
+        .vidioc_g_audio                =  vidioc_g_audio,
+        .vidioc_s_audio                = vidioc_s_audio,
+        .vidioc_cropcap                = vidioc_cropcap,
+        .vidioc_g_fmt_sliced_vbi_cap   = vidioc_g_fmt_sliced_vbi_cap,
+        .vidioc_try_fmt_sliced_vbi_cap = vidioc_try_set_sliced_vbi_cap,
+        .vidioc_reqbufs                = vidioc_reqbufs,
+        .vidioc_querybuf               = vidioc_querybuf,
+        .vidioc_qbuf                   = vidioc_qbuf,
+        .vidioc_dqbuf                  = vidioc_dqbuf,
+        .vidioc_s_std                  = vidioc_s_std,
+        .vidioc_g_std                  = vidioc_g_std,
+        .vidioc_enum_input             = vidioc_enum_input,
+        .vidioc_g_input                = vidioc_g_input,
+        .vidioc_s_input                = vidioc_s_input,
+        .vidioc_queryctrl              = vidioc_queryctrl,
+        .vidioc_g_ctrl                 = vidioc_g_ctrl,
+        .vidioc_s_ctrl                 = vidioc_s_ctrl,
+        .vidioc_streamon               = vidioc_streamon,
+        .vidioc_streamoff              = vidioc_streamoff,
+        .vidioc_g_tuner                = vidioc_g_tuner,
+        .vidioc_s_tuner                = vidioc_s_tuner,
+        .vidioc_g_frequency            = vidioc_g_frequency,
+        .vidioc_s_frequency            = vidioc_s_frequency,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+        .vidioc_g_register             = vidioc_g_register,
+        .vidioc_s_register             = vidioc_s_register,
+#endif
+};
+
+static struct video_device cx231xx_vbi_template;
+
+static const struct video_device cx231xx_video_template = {
+        .fops         = &cx231xx_v4l_fops,
+        .release      = video_device_release,
+        .ioctl_ops    = &video_ioctl_ops,
+        .tvnorms      = V4L2_STD_ALL,
+        .current_norm = V4L2_STD_PAL,
+};
+
+static const struct v4l2_file_operations radio_fops = {
+        .owner   = THIS_MODULE,
+        .open   = cx231xx_v4l2_open,
+        .release = cx231xx_v4l2_close,
+        .ioctl   = video_ioctl2,
+};
+
+static const struct v4l2_ioctl_ops radio_ioctl_ops = {
+        .vidioc_querycap    = radio_querycap,
+        .vidioc_g_tuner     = radio_g_tuner,
+        .vidioc_enum_input  = radio_enum_input,
+        .vidioc_g_audio     = radio_g_audio,
+        .vidioc_s_tuner     = radio_s_tuner,
+        .vidioc_s_audio     = radio_s_audio,
+        .vidioc_s_input     = radio_s_input,
+        .vidioc_queryctrl   = radio_queryctrl,
+        .vidioc_g_ctrl      = vidioc_g_ctrl,
+        .vidioc_s_ctrl      = vidioc_s_ctrl,
+        .vidioc_g_frequency = vidioc_g_frequency,
+        .vidioc_s_frequency = vidioc_s_frequency,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+        .vidioc_g_register  = vidioc_g_register,
+        .vidioc_s_register  = vidioc_s_register,
+#endif
+};
+
+static struct video_device cx231xx_radio_template = {
+        .name      = "cx231xx-radio",
+        .fops      = &radio_fops,
+        .ioctl_ops = &radio_ioctl_ops,
+};
+
+/******************************** usb interface ******************************/
+
+static struct video_device *cx231xx_vdev_init(struct cx231xx *dev,
+                const struct video_device
+                *template, const char *type_name)
+{
+        struct video_device *vfd;
+
+        vfd = video_device_alloc();
+        if (NULL == vfd)
+                return NULL;
+
+        *vfd = *template;
+        vfd->v4l2_dev = &dev->v4l2_dev;
+        vfd->release = video_device_release;
+        vfd->debug = video_debug;
+        vfd->lock = &dev->lock;
+
+        snprintf(vfd->name, sizeof(vfd->name), "%s %s", dev->name, type_name);
+
+        video_set_drvdata(vfd, dev);
+        return vfd;
+}
+
+int cx231xx_register_analog_devices(struct cx231xx *dev)
+{
+        int ret;
+
+        cx231xx_info("%s: v4l2 driver version %s\n",
+                     dev->name, CX231XX_VERSION);
+
+        /* set default norm */
+        /*dev->norm = cx231xx_video_template.current_norm; */
+        dev->width = norm_maxw(dev);
+        dev->height = norm_maxh(dev);
+        dev->interlaced = 0;
+
+        /* Analog specific initialization */
+        dev->format = &format[0];
+
+        /* Set the initial input */
+        video_mux(dev, dev->video_input);
+
+        /* Audio defaults */
+        dev->mute = 1;
+        dev->volume = 0x1f;
+
+        /* enable vbi capturing */
+        /* write code here...  */
+
+        /* allocate and fill video video_device struct */
+        dev->vdev = cx231xx_vdev_init(dev, &cx231xx_video_template, "video");
+        if (!dev->vdev) {
+                cx231xx_errdev("cannot allocate video_device.\n");
+                return -ENODEV;
+        }
+
+        /* register v4l2 video video_device */
+        ret = video_register_device(dev->vdev, VFL_TYPE_GRABBER,
+                                    video_nr[dev->devno]);
+        if (ret) {
+                cx231xx_errdev("unable to register video device (error=%i).\n",
+                               ret);
+                return ret;
+        }
+
+        cx231xx_info("%s/0: registered device %s [v4l2]\n",
+                     dev->name, video_device_node_name(dev->vdev));
+
+        /* Initialize VBI template */
+        memcpy(&cx231xx_vbi_template, &cx231xx_video_template,
+               sizeof(cx231xx_vbi_template));
+        strcpy(cx231xx_vbi_template.name, "cx231xx-vbi");
+
+        /* Allocate and fill vbi video_device struct */
+        dev->vbi_dev = cx231xx_vdev_init(dev, &cx231xx_vbi_template, "vbi");
+
+        /* register v4l2 vbi video_device */
+        ret = video_register_device(dev->vbi_dev, VFL_TYPE_VBI,
+                                    vbi_nr[dev->devno]);
+        if (ret < 0) {
+                cx231xx_errdev("unable to register vbi device\n");
+                return ret;
+        }
+
+        cx231xx_info("%s/0: registered device %s\n",
+                     dev->name, video_device_node_name(dev->vbi_dev));
+
+        if (cx231xx_boards[dev->model].radio.type == CX231XX_RADIO) {
+                dev->radio_dev = cx231xx_vdev_init(dev, &cx231xx_radio_template,
+                                                   "radio");
+                if (!dev->radio_dev) {
+                        cx231xx_errdev("cannot allocate video_device.\n");
+                        return -ENODEV;
+                }
+                ret = video_register_device(dev->radio_dev, VFL_TYPE_RADIO,
+                                            radio_nr[dev->devno]);
+                if (ret < 0) {
+                        cx231xx_errdev("can't register radio device\n");
+                        return ret;
+                }
+                cx231xx_info("Registered radio device as %s\n",
+                             video_device_node_name(dev->radio_dev));
+        }
+
+        cx231xx_info("V4L2 device registered as %s and %s\n",
+                     video_device_node_name(dev->vdev),
+                     video_device_node_name(dev->vbi_dev));
+
+        return 0;
+}
diff --git a/drivers/media/usb/cx231xx/cx231xx.h b/drivers/media/usb/cx231xx/cx231xx.h
new file mode 100644
index 000000000000..a89d020de948
--- /dev/null
+++ b/drivers/media/usb/cx231xx/cx231xx.h
@@ -0,0 +1,1012 @@
+/*
+   cx231xx.h - driver for Conexant Cx23100/101/102 USB video capture devices
+
+   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
+        Based on em28xx driver
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _CX231XX_H
+#define _CX231XX_H
+
+#include <linux/videodev2.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/i2c.h>
+#include <linux/workqueue.h>
+#include <linux/mutex.h>
+
+#include <media/cx2341x.h>
+
+#include <media/videobuf-vmalloc.h>
+#include <media/v4l2-device.h>
+#include <media/rc-core.h>
+#include <media/ir-kbd-i2c.h>
+#include <media/videobuf-dvb.h>
+
+#include "cx231xx-reg.h"
+#include "cx231xx-pcb-cfg.h"
+#include "cx231xx-conf-reg.h"
+
+#define DRIVER_NAME                     "cx231xx"
+#define PWR_SLEEP_INTERVAL              10
+
+/* I2C addresses for control block in Cx231xx */
+#define     AFE_DEVICE_ADDRESS          0x60
+#define     I2S_BLK_DEVICE_ADDRESS      0x98
+#define     VID_BLK_I2C_ADDRESS         0x88
+#define     VERVE_I2C_ADDRESS           0x40
+#define     DIF_USE_BASEBAND            0xFFFFFFFF
+
+/* Boards supported by driver */
+#define CX231XX_BOARD_UNKNOWN               0
+#define CX231XX_BOARD_CNXT_CARRAERA     1
+#define CX231XX_BOARD_CNXT_SHELBY       2
+#define CX231XX_BOARD_CNXT_RDE_253S     3
+#define CX231XX_BOARD_CNXT_RDU_253S     4
+#define CX231XX_BOARD_CNXT_VIDEO_GRABBER        5
+#define CX231XX_BOARD_CNXT_RDE_250      6
+#define CX231XX_BOARD_CNXT_RDU_250      7
+#define CX231XX_BOARD_HAUPPAUGE_EXETER  8
+#define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9
+#define CX231XX_BOARD_PV_PLAYTV_USB_HYBRID 10
+#define CX231XX_BOARD_PV_XCAPTURE_USB 11
+#define CX231XX_BOARD_KWORLD_UB430_USB_HYBRID 12
+#define CX231XX_BOARD_ICONBIT_U100 13
+#define CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL 14
+#define CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC 15
+
+/* Limits minimum and default number of buffers */
+#define CX231XX_MIN_BUF                 4
+#define CX231XX_DEF_BUF                 12
+#define CX231XX_DEF_VBI_BUF             6
+
+#define VBI_LINE_COUNT                  17
+#define VBI_LINE_LENGTH                 1440
+
+/*Limits the max URB message size */
+#define URB_MAX_CTRL_SIZE               80
+
+/* Params for validated field */
+#define CX231XX_BOARD_NOT_VALIDATED     1
+#define CX231XX_BOARD_VALIDATED         0
+
+/* maximum number of cx231xx boards */
+#define CX231XX_MAXBOARDS               8
+
+/* maximum number of frames that can be queued */
+#define CX231XX_NUM_FRAMES              5
+
+/* number of buffers for isoc transfers */
+#define CX231XX_NUM_BUFS                8
+
+/* number of packets for each buffer
+   windows requests only 40 packets .. so we better do the same
+   this is what I found out for all alternate numbers there!
+ */
+#define CX231XX_NUM_PACKETS             40
+
+/* default alternate; 0 means choose the best */
+#define CX231XX_PINOUT                  0
+
+#define CX231XX_INTERLACED_DEFAULT      1
+
+/* time to wait when stopping the isoc transfer */
+#define CX231XX_URB_TIMEOUT             \
+                msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS)
+
+#define CX231xx_NORMS (\
+        V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_443 | \
+        V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
+        V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_Nc   | \
+        V4L2_STD_PAL_60 |  V4L2_STD_SECAM_L   |  V4L2_STD_SECAM_DK)
+
+#define SLEEP_S5H1432    30
+#define CX23417_OSC_EN   8
+#define CX23417_RESET    9
+
+struct cx23417_fmt {
+        char  *name;
+        u32   fourcc;          /* v4l2 format id */
+        int   depth;
+        int   flags;
+        u32   cxformat;
+};
+enum cx231xx_mode {
+        CX231XX_SUSPEND,
+        CX231XX_ANALOG_MODE,
+        CX231XX_DIGITAL_MODE,
+};
+
+enum cx231xx_std_mode {
+        CX231XX_TV_AIR = 0,
+        CX231XX_TV_CABLE
+};
+
+enum cx231xx_stream_state {
+        STREAM_OFF,
+        STREAM_INTERRUPT,
+        STREAM_ON,
+};
+
+struct cx231xx;
+
+struct cx231xx_isoc_ctl {
+        /* max packet size of isoc transaction */
+        int max_pkt_size;
+
+        /* number of allocated urbs */
+        int num_bufs;
+
+        /* urb for isoc transfers */
+        struct urb **urb;
+
+        /* transfer buffers for isoc transfer */
+        char **transfer_buffer;
+
+        /* Last buffer command and region */
+        u8 cmd;
+        int pos, size, pktsize;
+
+        /* Last field: ODD or EVEN? */
+        int field;
+
+        /* Stores incomplete commands */
+        u32 tmp_buf;
+        int tmp_buf_len;
+
+        /* Stores already requested buffers */
+        struct cx231xx_buffer *buf;
+
+        /* Stores the number of received fields */
+        int nfields;
+
+        /* isoc urb callback */
+        int (*isoc_copy) (struct cx231xx *dev, struct urb *urb);
+};
+
+struct cx231xx_bulk_ctl {
+        /* max packet size of bulk transaction */
+        int max_pkt_size;
+
+        /* number of allocated urbs */
+        int num_bufs;
+
+        /* urb for bulk transfers */
+        struct urb **urb;
+
+        /* transfer buffers for bulk transfer */
+        char **transfer_buffer;
+
+        /* Last buffer command and region */
+        u8 cmd;
+        int pos, size, pktsize;
+
+        /* Last field: ODD or EVEN? */
+        int field;
+
+        /* Stores incomplete commands */
+        u32 tmp_buf;
+        int tmp_buf_len;
+
+        /* Stores already requested buffers */
+        struct cx231xx_buffer *buf;
+
+        /* Stores the number of received fields */
+        int nfields;
+
+        /* bulk urb callback */
+        int (*bulk_copy) (struct cx231xx *dev, struct urb *urb);
+};
+
+struct cx231xx_fmt {
+        char *name;
+        u32 fourcc;             /* v4l2 format id */
+        int depth;
+        int reg;
+};
+
+/* buffer for one video frame */
+struct cx231xx_buffer {
+        /* common v4l buffer stuff -- must be first */
+        struct videobuf_buffer vb;
+
+        struct list_head frame;
+        int top_field;
+        int receiving;
+};
+
+enum ps_package_head {
+        CX231XX_NEED_ADD_PS_PACKAGE_HEAD = 0,
+        CX231XX_NONEED_PS_PACKAGE_HEAD
+};
+
+struct cx231xx_dmaqueue {
+        struct list_head active;
+        struct list_head queued;
+
+        wait_queue_head_t wq;
+
+        /* Counters to control buffer fill */
+        int pos;
+        u8 is_partial_line;
+        u8 partial_buf[8];
+        u8 last_sav;
+        int current_field;
+        u32 bytes_left_in_line;
+        u32 lines_completed;
+        u8 field1_done;
+        u32 lines_per_field;
+
+        /*Mpeg2 control buffer*/
+        u8 *p_left_data;
+        u32 left_data_count;
+        u8 mpeg_buffer_done;
+        u32 mpeg_buffer_completed;
+        enum ps_package_head add_ps_package_head;
+        char ps_head[10];
+};
+
+/* inputs */
+
+#define MAX_CX231XX_INPUT               4
+
+enum cx231xx_itype {
+        CX231XX_VMUX_COMPOSITE1 = 1,
+        CX231XX_VMUX_SVIDEO,
+        CX231XX_VMUX_TELEVISION,
+        CX231XX_VMUX_CABLE,
+        CX231XX_RADIO,
+        CX231XX_VMUX_DVB,
+        CX231XX_VMUX_DEBUG
+};
+
+enum cx231xx_v_input {
+        CX231XX_VIN_1_1 = 0x1,
+        CX231XX_VIN_2_1,
+        CX231XX_VIN_3_1,
+        CX231XX_VIN_4_1,
+        CX231XX_VIN_1_2 = 0x01,
+        CX231XX_VIN_2_2,
+        CX231XX_VIN_3_2,
+        CX231XX_VIN_1_3 = 0x1,
+        CX231XX_VIN_2_3,
+        CX231XX_VIN_3_3,
+};
+
+/* cx231xx has two audio inputs: tuner and line in */
+enum cx231xx_amux {
+        /* This is the only entry for cx231xx tuner input */
+        CX231XX_AMUX_VIDEO,     /* cx231xx tuner */
+        CX231XX_AMUX_LINE_IN,   /* Line In */
+};
+
+struct cx231xx_reg_seq {
+        unsigned char bit;
+        unsigned char val;
+        int sleep;
+};
+
+struct cx231xx_input {
+        enum cx231xx_itype type;
+        unsigned int vmux;
+        enum cx231xx_amux amux;
+        struct cx231xx_reg_seq *gpio;
+};
+
+#define INPUT(nr) (&cx231xx_boards[dev->model].input[nr])
+
+enum cx231xx_decoder {
+        CX231XX_NODECODER,
+        CX231XX_AVDECODER
+};
+
+enum CX231XX_I2C_MASTER_PORT {
+        I2C_0 = 0,
+        I2C_1 = 1,
+        I2C_2 = 2,
+        I2C_3 = 3
+};
+
+struct cx231xx_board {
+        char *name;
+        int vchannels;
+        int tuner_type;
+        int tuner_addr;
+        v4l2_std_id norm;       /* tv norm */
+
+        /* demod related */
+        int demod_addr;
+        u8 demod_xfer_mode;     /* 0 - Serial; 1 - parallel */
+
+        /* GPIO Pins */
+        struct cx231xx_reg_seq *dvb_gpio;
+        struct cx231xx_reg_seq *suspend_gpio;
+        struct cx231xx_reg_seq *tuner_gpio;
+                /* Negative means don't use it */
+        s8 tuner_sif_gpio;
+        s8 tuner_scl_gpio;
+        s8 tuner_sda_gpio;
+
+        /* PIN ctrl */
+        u32 ctl_pin_status_mask;
+        u8 agc_analog_digital_select_gpio;
+        u32 gpio_pin_status_mask;
+
+        /* i2c masters */
+        u8 tuner_i2c_master;
+        u8 demod_i2c_master;
+        u8 ir_i2c_master;
+
+        /* for devices with I2C chips for IR */
+        char *rc_map_name;
+
+        unsigned int max_range_640_480:1;
+        unsigned int has_dvb:1;
+        unsigned int has_417:1;
+        unsigned int valid:1;
+        unsigned int no_alt_vanc:1;
+        unsigned int external_av:1;
+        unsigned int dont_use_port_3:1;
+
+        unsigned char xclk, i2c_speed;
+
+        enum cx231xx_decoder decoder;
+        int output_mode;
+
+        struct cx231xx_input input[MAX_CX231XX_INPUT];
+        struct cx231xx_input radio;
+        struct rc_map *ir_codes;
+};
+
+/* device states */
+enum cx231xx_dev_state {
+        DEV_INITIALIZED = 0x01,
+        DEV_DISCONNECTED = 0x02,
+};
+
+enum AFE_MODE {
+        AFE_MODE_LOW_IF,
+        AFE_MODE_BASEBAND,
+        AFE_MODE_EU_HI_IF,
+        AFE_MODE_US_HI_IF,
+        AFE_MODE_JAPAN_HI_IF
+};
+
+enum AUDIO_INPUT {
+        AUDIO_INPUT_MUTE,
+        AUDIO_INPUT_LINE,
+        AUDIO_INPUT_TUNER_TV,
+        AUDIO_INPUT_SPDIF,
+        AUDIO_INPUT_TUNER_FM
+};
+
+#define CX231XX_AUDIO_BUFS              5
+#define CX231XX_NUM_AUDIO_PACKETS       16
+#define CX231XX_ISO_NUM_AUDIO_PACKETS   64
+
+/* cx231xx extensions */
+#define CX231XX_AUDIO                   0x10
+#define CX231XX_DVB                     0x20
+
+struct cx231xx_audio {
+        char name[50];
+        char *transfer_buffer[CX231XX_AUDIO_BUFS];
+        struct urb *urb[CX231XX_AUDIO_BUFS];
+        struct usb_device *udev;
+        unsigned int capture_transfer_done;
+        struct snd_pcm_substream *capture_pcm_substream;
+
+        unsigned int hwptr_done_capture;
+        struct snd_card *sndcard;
+
+        int users, shutdown;
+        /* locks */
+        spinlock_t slock;
+
+        int alt;                /* alternate */
+        int max_pkt_size;       /* max packet size of isoc transaction */
+        int num_alt;            /* Number of alternative settings */
+        unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
+        u16 end_point_addr;
+};
+
+struct cx231xx;
+
+struct cx231xx_fh {
+        struct cx231xx *dev;
+        unsigned int stream_on:1;       /* Locks streams */
+        int radio;
+
+        struct videobuf_queue vb_vidq;
+
+        enum v4l2_buf_type type;
+
+
+
+/*following is copyed from cx23885.h*/
+        u32                        resources;
+
+        /* video overlay */
+        struct v4l2_window         win;
+        struct v4l2_clip           *clips;
+        unsigned int               nclips;
+
+        /* video capture */
+        struct cx23417_fmt         *fmt;
+        unsigned int               width, height;
+
+        /* vbi capture */
+        struct videobuf_queue      vidq;
+        struct videobuf_queue      vbiq;
+
+        /* MPEG Encoder specifics ONLY */
+
+        atomic_t                   v4l_reading;
+};
+
+/*****************************************************************/
+/* set/get i2c */
+/* 00--1Mb/s, 01-400kb/s, 10--100kb/s, 11--5Mb/s */
+#define I2C_SPEED_1M            0x0
+#define I2C_SPEED_400K          0x1
+#define I2C_SPEED_100K          0x2
+#define I2C_SPEED_5M            0x3
+
+/* 0-- STOP transaction */
+#define I2C_STOP                0x0
+/* 1-- do not transmit STOP at end of transaction */
+#define I2C_NOSTOP              0x1
+/* 1--allow slave to insert clock wait states */
+#define I2C_SYNC                0x1
+
+struct cx231xx_i2c {
+        struct cx231xx *dev;
+
+        int nr;
+
+        /* i2c i/o */
+        struct i2c_adapter i2c_adap;
+        struct i2c_client i2c_client;
+        u32 i2c_rc;
+
+        /* different settings for each bus */
+        u8 i2c_period;
+        u8 i2c_nostop;
+        u8 i2c_reserve;
+};
+
+struct cx231xx_i2c_xfer_data {
+        u8 dev_addr;
+        u8 direction;           /* 1 - IN, 0 - OUT */
+        u8 saddr_len;           /* sub address len */
+        u16 saddr_dat;          /* sub addr data */
+        u8 buf_size;            /* buffer size */
+        u8 *p_buffer;           /* pointer to the buffer */
+};
+
+struct VENDOR_REQUEST_IN {
+        u8 bRequest;
+        u16 wValue;
+        u16 wIndex;
+        u16 wLength;
+        u8 direction;
+        u8 bData;
+        u8 *pBuff;
+};
+
+struct cx231xx_tvnorm {
+        char            *name;
+        v4l2_std_id     id;
+        u32             cxiformat;
+        u32             cxoformat;
+};
+
+struct cx231xx_ctrl {
+        struct v4l2_queryctrl v;
+        u32 off;
+        u32 reg;
+        u32 mask;
+        u32 shift;
+};
+
+enum TRANSFER_TYPE {
+        Raw_Video = 0,
+        Audio,
+        Vbi,                    /* VANC */
+        Sliced_cc,              /* HANC */
+        TS1_serial_mode,
+        TS2,
+        TS1_parallel_mode
+} ;
+
+struct cx231xx_video_mode {
+        /* Isoc control struct */
+        struct cx231xx_dmaqueue vidq;
+        struct cx231xx_isoc_ctl isoc_ctl;
+        struct cx231xx_bulk_ctl bulk_ctl;
+        /* locks */
+        spinlock_t slock;
+
+        /* usb transfer */
+        int alt;                /* alternate */
+        int max_pkt_size;       /* max packet size of isoc transaction */
+        int num_alt;            /* Number of alternative settings */
+        unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
+        u16 end_point_addr;
+};
+/*
+struct cx23885_dmaqueue {
+        struct list_head       active;
+        struct list_head       queued;
+        struct timer_list      timeout;
+        struct btcx_riscmem    stopper;
+        u32                    count;
+};
+*/
+struct cx231xx_tsport {
+        struct cx231xx *dev;
+
+        int                        nr;
+        int                        sram_chno;
+
+        struct videobuf_dvb_frontends frontends;
+
+        /* dma queues */
+
+        u32                        ts_packet_size;
+        u32                        ts_packet_count;
+
+        int                        width;
+        int                        height;
+
+        /* locks */
+        spinlock_t                 slock;
+
+        /* registers */
+        u32                        reg_gpcnt;
+        u32                        reg_gpcnt_ctl;
+        u32                        reg_dma_ctl;
+        u32                        reg_lngth;
+        u32                        reg_hw_sop_ctrl;
+        u32                        reg_gen_ctrl;
+        u32                        reg_bd_pkt_status;
+        u32                        reg_sop_status;
+        u32                        reg_fifo_ovfl_stat;
+        u32                        reg_vld_misc;
+        u32                        reg_ts_clk_en;
+        u32                        reg_ts_int_msk;
+        u32                        reg_ts_int_stat;
+        u32                        reg_src_sel;
+
+        /* Default register vals */
+        int                        pci_irqmask;
+        u32                        dma_ctl_val;
+        u32                        ts_int_msk_val;
+        u32                        gen_ctrl_val;
+        u32                        ts_clk_en_val;
+        u32                        src_sel_val;
+        u32                        vld_misc_val;
+        u32                        hw_sop_ctrl_val;
+
+        /* Allow a single tsport to have multiple frontends */
+        u32                        num_frontends;
+        void                       *port_priv;
+};
+
+/* main device struct */
+struct cx231xx {
+        /* generic device properties */
+        char name[30];          /* name (including minor) of the device */
+        int model;              /* index in the device_data struct */
+        int devno;              /* marks the number of this device */
+
+        struct cx231xx_board board;
+
+        /* For I2C IR support */
+        struct IR_i2c_init_data    init_data;
+        struct i2c_client          *ir_i2c_client;
+
+        unsigned int stream_on:1;       /* Locks streams */
+        unsigned int vbi_stream_on:1;   /* Locks streams for VBI */
+        unsigned int has_audio_class:1;
+        unsigned int has_alsa_audio:1;
+
+        struct cx231xx_fmt *format;
+
+        struct v4l2_device v4l2_dev;
+        struct v4l2_subdev *sd_cx25840;
+        struct v4l2_subdev *sd_tuner;
+
+        struct work_struct wq_trigger;          /* Trigger to start/stop audio for alsa module */
+        atomic_t           stream_started;      /* stream should be running if true */
+
+        struct list_head devlist;
+
+        int tuner_type;         /* type of the tuner */
+        int tuner_addr;         /* tuner address */
+
+        /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
+        struct cx231xx_i2c i2c_bus[3];
+        unsigned int xc_fw_load_done:1;
+        /* locks */
+        struct mutex gpio_i2c_lock;
+        struct mutex i2c_lock;
+
+        /* video for linux */
+        int users;              /* user count for exclusive use */
+        struct video_device *vdev;      /* video for linux device struct */
+        v4l2_std_id norm;       /* selected tv norm */
+        int ctl_freq;           /* selected frequency */
+        unsigned int ctl_ainput;        /* selected audio input */
+        int mute;
+        int volume;
+
+        /* frame properties */
+        int width;              /* current frame width */
+        int height;             /* current frame height */
+        int interlaced;         /* 1=interlace fileds, 0=just top fileds */
+
+        struct cx231xx_audio adev;
+
+        /* states */
+        enum cx231xx_dev_state state;
+
+        struct work_struct request_module_wk;
+
+        /* locks */
+        struct mutex lock;
+        struct mutex ctrl_urb_lock;     /* protects urb_buf */
+        struct list_head inqueue, outqueue;
+        wait_queue_head_t open, wait_frame, wait_stream;
+        struct video_device *vbi_dev;
+        struct video_device *radio_dev;
+
+        unsigned char eedata[256];
+
+        struct cx231xx_video_mode video_mode;
+        struct cx231xx_video_mode vbi_mode;
+        struct cx231xx_video_mode sliced_cc_mode;
+        struct cx231xx_video_mode ts1_mode;
+
+        atomic_t devlist_count;
+
+        struct usb_device *udev;        /* the usb device */
+        char urb_buf[URB_MAX_CTRL_SIZE];        /* urb control msg buffer */
+
+        /* helper funcs that call usb_control_msg */
+        int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
+                                      char *buf, int len);
+        int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
+                                       char *buf, int len);
+        int (*cx231xx_send_usb_command) (struct cx231xx_i2c *i2c_bus,
+                                struct cx231xx_i2c_xfer_data *req_data);
+        int (*cx231xx_gpio_i2c_read) (struct cx231xx *dev, u8 dev_addr,
+                                      u8 *buf, u8 len);
+        int (*cx231xx_gpio_i2c_write) (struct cx231xx *dev, u8 dev_addr,
+                                       u8 *buf, u8 len);
+
+        int (*cx231xx_set_analog_freq) (struct cx231xx *dev, u32 freq);
+        int (*cx231xx_reset_analog_tuner) (struct cx231xx *dev);
+
+        enum cx231xx_mode mode;
+
+        struct cx231xx_dvb *dvb;
+
+        /* Cx231xx supported PCB config's */
+        struct pcb_config current_pcb_config;
+        u8 current_scenario_idx;
+        u8 interface_count;
+        u8 max_iad_interface_count;
+
+        /* GPIO related register direction and values */
+        u32 gpio_dir;
+        u32 gpio_val;
+
+        /* Power Modes */
+        int power_mode;
+
+        /* afe parameters */
+        enum AFE_MODE afe_mode;
+        u32 afe_ref_count;
+
+        /* video related parameters */
+        u32 video_input;
+        u32 active_mode;
+        u8 vbi_or_sliced_cc_mode;       /* 0 - vbi ; 1 - sliced cc mode */
+        enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */
+
+        /*mode: digital=1 or analog=0*/
+        u8 mode_tv;
+
+        u8 USE_ISO;
+        struct cx231xx_tvnorm      encodernorm;
+        struct cx231xx_tsport      ts1, ts2;
+        struct cx2341x_mpeg_params mpeg_params;
+        struct video_device        *v4l_device;
+        atomic_t                   v4l_reader_count;
+        u32                        freq;
+        unsigned int               input;
+        u32                        cx23417_mailbox;
+        u32                        __iomem *lmmio;
+        u8                         __iomem *bmmio;
+};
+
+extern struct list_head cx231xx_devlist;
+
+#define cx25840_call(cx231xx, o, f, args...) \
+        v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args)
+#define tuner_call(cx231xx, o, f, args...) \
+        v4l2_subdev_call(cx231xx->sd_tuner, o, f, ##args)
+#define call_all(dev, o, f, args...) \
+        v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args)
+
+struct cx231xx_ops {
+        struct list_head next;
+        char *name;
+        int id;
+        int (*init) (struct cx231xx *);
+        int (*fini) (struct cx231xx *);
+};
+
+/* call back functions in dvb module */
+int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq);
+int cx231xx_reset_analog_tuner(struct cx231xx *dev);
+
+/* Provided by cx231xx-i2c.c */
+void cx231xx_do_i2c_scan(struct cx231xx *dev, struct i2c_client *c);
+int cx231xx_i2c_register(struct cx231xx_i2c *bus);
+int cx231xx_i2c_unregister(struct cx231xx_i2c *bus);
+
+/* Internal block control functions */
+int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                 u8 saddr_len, u32 *data, u8 data_len, int master);
+int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
+                 u8 saddr_len, u32 data, u8 data_len, int master);
+int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr,
+                          u16 saddr, u8 saddr_len, u32 *data, u8 data_len);
+int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr,
+                           u16 saddr, u8 saddr_len, u32 data, u8 data_len);
+int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
+                           u16 register_address, u8 bit_start, u8 bit_end,
+                           u32 value);
+int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
+                                        u16 saddr, u32 mask, u32 value);
+u32 cx231xx_set_field(u32 field_mask, u32 data);
+
+/*verve r/w*/
+void initGPIO(struct cx231xx *dev);
+void uninitGPIO(struct cx231xx *dev);
+/* afe related functions */
+int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
+int cx231xx_afe_init_channels(struct cx231xx *dev);
+int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev);
+int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux);
+int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
+int cx231xx_afe_update_power_control(struct cx231xx *dev,
+                                        enum AV_MODE avmode);
+int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input);
+
+/* i2s block related functions */
+int cx231xx_i2s_blk_initialize(struct cx231xx *dev);
+int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
+                                        enum AV_MODE avmode);
+int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
+
+/* DIF related functions */
+int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
+                                          u32 function_mode, u32 standard);
+void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
+                                         u8 spectral_invert, u32 mode);
+u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd);
+void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
+                                         u8 spectral_invert, u32 mode);
+void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev);
+void reset_s5h1432_demod(struct cx231xx *dev);
+void cx231xx_dump_HH_reg(struct cx231xx *dev);
+void update_HH_register_after_set_DIF(struct cx231xx *dev);
+void cx231xx_dump_SC_reg(struct cx231xx *dev);
+
+
+
+int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard);
+int cx231xx_tuner_pre_channel_change(struct cx231xx *dev);
+int cx231xx_tuner_post_channel_change(struct cx231xx *dev);
+
+/* video parser functions */
+u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size,
+                             u32 *p_bytes_used);
+u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
+                                 u32 *p_bytes_used);
+int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                    u8 *p_buffer, u32 bytes_to_copy);
+void cx231xx_reset_video_buffer(struct cx231xx *dev,
+                                struct cx231xx_dmaqueue *dma_q);
+u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q);
+u32 cx231xx_copy_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                            u8 *p_line, u32 length, int field_number);
+u32 cx231xx_get_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
+                           u8 sav_eav, u8 *p_buffer, u32 buffer_size);
+void cx231xx_swab(u16 *from, u16 *to, u16 len);
+
+/* Provided by cx231xx-core.c */
+
+u32 cx231xx_request_buffers(struct cx231xx *dev, u32 count);
+void cx231xx_queue_unusedframes(struct cx231xx *dev);
+void cx231xx_release_buffers(struct cx231xx *dev);
+
+/* read from control pipe */
+int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
+                          char *buf, int len);
+
+/* write to control pipe */
+int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
+                           char *buf, int len);
+int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode);
+
+int cx231xx_send_vendor_cmd(struct cx231xx *dev,
+                                struct VENDOR_REQUEST_IN *ven_req);
+int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
+                                struct cx231xx_i2c_xfer_data *req_data);
+
+/* Gpio related functions */
+int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
+                          u8 len, u8 request, u8 direction);
+int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val);
+int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val);
+int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value);
+int cx231xx_set_gpio_direction(struct cx231xx *dev, int pin_number,
+                               int pin_value);
+
+int cx231xx_gpio_i2c_start(struct cx231xx *dev);
+int cx231xx_gpio_i2c_end(struct cx231xx *dev);
+int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data);
+int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf);
+int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev);
+int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev);
+int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev);
+
+int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
+int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
+
+/* audio related functions */
+int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
+                                    enum AUDIO_INPUT audio_input);
+
+int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type);
+int cx231xx_set_video_alternate(struct cx231xx *dev);
+int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt);
+int is_fw_load(struct cx231xx *dev);
+int cx231xx_check_fw(struct cx231xx *dev);
+int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
+                      int num_bufs, int max_pkt_size,
+                      int (*isoc_copy) (struct cx231xx *dev,
+                                        struct urb *urb));
+int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
+                      int num_bufs, int max_pkt_size,
+                      int (*bulk_copy) (struct cx231xx *dev,
+                                        struct urb *urb));
+void cx231xx_stop_TS1(struct cx231xx *dev);
+void cx231xx_start_TS1(struct cx231xx *dev);
+void cx231xx_uninit_isoc(struct cx231xx *dev);
+void cx231xx_uninit_bulk(struct cx231xx *dev);
+int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode);
+int cx231xx_unmute_audio(struct cx231xx *dev);
+int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size);
+void cx231xx_disable656(struct cx231xx *dev);
+void cx231xx_enable656(struct cx231xx *dev);
+int cx231xx_demod_reset(struct cx231xx *dev);
+int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio);
+
+/* Device list functions */
+void cx231xx_release_resources(struct cx231xx *dev);
+void cx231xx_release_analog_resources(struct cx231xx *dev);
+int cx231xx_register_analog_devices(struct cx231xx *dev);
+void cx231xx_remove_from_devlist(struct cx231xx *dev);
+void cx231xx_add_into_devlist(struct cx231xx *dev);
+void cx231xx_init_extension(struct cx231xx *dev);
+void cx231xx_close_extension(struct cx231xx *dev);
+
+/* hardware init functions */
+int cx231xx_dev_init(struct cx231xx *dev);
+void cx231xx_dev_uninit(struct cx231xx *dev);
+void cx231xx_config_i2c(struct cx231xx *dev);
+int cx231xx_config(struct cx231xx *dev);
+
+/* Stream control functions */
+int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask);
+int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
+
+int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
+
+/* Power control functions */
+int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
+int cx231xx_power_suspend(struct cx231xx *dev);
+
+/* chip specific control functions */
+int cx231xx_init_ctrl_pin_status(struct cx231xx *dev);
+int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
+                                              u8 analog_or_digital);
+int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3);
+
+/* video audio decoder related functions */
+void video_mux(struct cx231xx *dev, int index);
+int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input);
+int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input);
+int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev);
+int cx231xx_set_audio_input(struct cx231xx *dev, u8 input);
+
+/* Provided by cx231xx-video.c */
+int cx231xx_register_extension(struct cx231xx_ops *dev);
+void cx231xx_unregister_extension(struct cx231xx_ops *dev);
+void cx231xx_init_extension(struct cx231xx *dev);
+void cx231xx_close_extension(struct cx231xx *dev);
+
+/* Provided by cx231xx-cards.c */
+extern void cx231xx_pre_card_setup(struct cx231xx *dev);
+extern void cx231xx_card_setup(struct cx231xx *dev);
+extern struct cx231xx_board cx231xx_boards[];
+extern struct usb_device_id cx231xx_id_table[];
+extern const unsigned int cx231xx_bcount;
+int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
+
+/* cx23885-417.c                                               */
+extern int cx231xx_417_register(struct cx231xx *dev);
+extern void cx231xx_417_unregister(struct cx231xx *dev);
+
+/* cx23885-input.c                                             */
+
+#if defined(CONFIG_VIDEO_CX231XX_RC)
+int cx231xx_ir_init(struct cx231xx *dev);
+void cx231xx_ir_exit(struct cx231xx *dev);
+#else
+#define cx231xx_ir_init(dev)    (0)
+#define cx231xx_ir_exit(dev)    (0)
+#endif
+
+
+/* printk macros */
+
+#define cx231xx_err(fmt, arg...) do {\
+        printk(KERN_ERR fmt , ##arg); } while (0)
+
+#define cx231xx_errdev(fmt, arg...) do {\
+        printk(KERN_ERR "%s: "fmt,\
+                        dev->name , ##arg); } while (0)
+
+#define cx231xx_info(fmt, arg...) do {\
+        printk(KERN_INFO "%s: "fmt,\
+                        dev->name , ##arg); } while (0)
+#define cx231xx_warn(fmt, arg...) do {\
+        printk(KERN_WARNING "%s: "fmt,\
+                        dev->name , ##arg); } while (0)
+
+static inline unsigned int norm_maxw(struct cx231xx *dev)
+{
+        if (dev->board.max_range_640_480)
+                return 640;
+        else
+                return 720;
+}
+
+static inline unsigned int norm_maxh(struct cx231xx *dev)
+{
+        if (dev->board.max_range_640_480)
+                return 480;
+        else
+                return (dev->norm & V4L2_STD_625_50) ? 576 : 480;
+}
+#endif