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authorArun Kumar K <arun.kk@samsung.com>2012-10-03 21:19:09 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-10-05 21:57:25 -0400
commit8f532a7fec5ee872a65d2096f846f76afd9ede6f (patch)
treeb64b063936167cad2d7938aa4a6c72df933cb68b /drivers/media/platform/s5p-mfc
parent43a1ea1f90382a6a8fcf5ed94835b8518ebdefc8 (diff)
[media] s5p-mfc: Add MFC variant data to device context
MFC variant data replaces various macros used in the driver which will change in a different version of MFC hardware. Also does a cleanup of MFC context structure and common files. Signed-off-by: Jeongtae Park <jtp.park@samsung.com> Signed-off-by: Janghyuck Kim <janghyuck.kim@samsung.com> Signed-off-by: Jaeryul Oh <jaeryul.oh@samsung.com> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Acked-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform/s5p-mfc')
-rw-r--r--drivers/media/platform/s5p-mfc/regs-mfc.h20
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc.c78
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c4
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_common.h85
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c7
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_enc.c48
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c213
7 files changed, 268 insertions, 187 deletions
diff --git a/drivers/media/platform/s5p-mfc/regs-mfc.h b/drivers/media/platform/s5p-mfc/regs-mfc.h
index a19bece41ba9..f33c54d4df86 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc.h
@@ -12,6 +12,9 @@
12#ifndef _REGS_FIMV_H 12#ifndef _REGS_FIMV_H
13#define _REGS_FIMV_H 13#define _REGS_FIMV_H
14 14
15#include <linux/kernel.h>
16#include <linux/sizes.h>
17
15#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) 18#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4) 19#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
17 20
@@ -414,5 +417,22 @@
414#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078 417#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
415#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C 418#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
416#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0 419#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
420#define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT 2
421
422/* Offset used by the hardware to store addresses */
423#define MFC_OFFSET_SHIFT 11
424
425#define FIRMWARE_ALIGN (128 * SZ_1K) /* 128KB */
426#define MFC_H264_CTX_BUF_SIZE (600 * SZ_1K) /* 600KB per H264 instance */
427#define MFC_CTX_BUF_SIZE (10 * SZ_1K) /* 10KB per instance */
428#define DESC_BUF_SIZE (128 * SZ_1K) /* 128KB for DESC buffer */
429#define SHARED_BUF_SIZE (8 * SZ_1K) /* 8KB for shared buffer */
430
431#define DEF_CPB_SIZE (256 * SZ_1K) /* 256KB */
432#define MAX_CPB_SIZE (4 * SZ_1M) /* 4MB */
433#define MAX_FW_SIZE (384 * SZ_1K)
434
435#define MFC_VERSION 0x51
436#define MFC_NUM_PORTS 2
417 437
418#endif /* _REGS_FIMV_H */ 438#endif /* _REGS_FIMV_H */
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index d711b0f7420b..7feae81db00b 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -477,7 +477,6 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
477 unsigned int reason, unsigned int err) 477 unsigned int reason, unsigned int err)
478{ 478{
479 struct s5p_mfc_dev *dev; 479 struct s5p_mfc_dev *dev;
480 unsigned int guard_width, guard_height;
481 480
482 if (ctx == NULL) 481 if (ctx == NULL)
483 return; 482 return;
@@ -491,40 +490,8 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
491 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 490 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
492 dev); 491 dev);
493 492
494 ctx->buf_width = ALIGN(ctx->img_width, 493 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
495 S5P_FIMV_NV12MT_HALIGN); 494
496 ctx->buf_height = ALIGN(ctx->img_height,
497 S5P_FIMV_NV12MT_VALIGN);
498 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
499 "buffer dimensions: %dx%d\n", ctx->img_width,
500 ctx->img_height, ctx->buf_width,
501 ctx->buf_height);
502 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) {
503 ctx->luma_size = ALIGN(ctx->buf_width *
504 ctx->buf_height, S5P_FIMV_DEC_BUF_ALIGN);
505 ctx->chroma_size = ALIGN(ctx->buf_width *
506 ALIGN((ctx->img_height >> 1),
507 S5P_FIMV_NV12MT_VALIGN),
508 S5P_FIMV_DEC_BUF_ALIGN);
509 ctx->mv_size = ALIGN(ctx->buf_width *
510 ALIGN((ctx->buf_height >> 2),
511 S5P_FIMV_NV12MT_VALIGN),
512 S5P_FIMV_DEC_BUF_ALIGN);
513 } else {
514 guard_width = ALIGN(ctx->img_width + 24,
515 S5P_FIMV_NV12MT_HALIGN);
516 guard_height = ALIGN(ctx->img_height + 16,
517 S5P_FIMV_NV12MT_VALIGN);
518 ctx->luma_size = ALIGN(guard_width *
519 guard_height, S5P_FIMV_DEC_BUF_ALIGN);
520 guard_width = ALIGN(ctx->img_width + 16,
521 S5P_FIMV_NV12MT_HALIGN);
522 guard_height = ALIGN((ctx->img_height >> 1) + 4,
523 S5P_FIMV_NV12MT_VALIGN);
524 ctx->chroma_size = ALIGN(guard_width *
525 guard_height, S5P_FIMV_DEC_BUF_ALIGN);
526 ctx->mv_size = 0;
527 }
528 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 495 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
529 dev); 496 dev);
530 if (ctx->img_width == 0 || ctx->img_height == 0) 497 if (ctx->img_width == 0 || ctx->img_height == 0)
@@ -1066,6 +1033,9 @@ static int s5p_mfc_probe(struct platform_device *pdev)
1066 return -ENODEV; 1033 return -ENODEV;
1067 } 1034 }
1068 1035
1036 dev->variant = (struct s5p_mfc_variant *)
1037 platform_get_device_id(pdev)->driver_data;
1038
1069 ret = s5p_mfc_init_pm(dev); 1039 ret = s5p_mfc_init_pm(dev);
1070 if (ret < 0) { 1040 if (ret < 0) {
1071 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1041 dev_err(&pdev->dev, "failed to get mfc clock source\n");
@@ -1309,9 +1279,43 @@ static const struct dev_pm_ops s5p_mfc_pm_ops = {
1309 NULL) 1279 NULL)
1310}; 1280};
1311 1281
1282struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1283 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1284 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1285 .dsc = DESC_BUF_SIZE,
1286 .shm = SHARED_BUF_SIZE,
1287};
1288
1289struct s5p_mfc_buf_size buf_size_v5 = {
1290 .fw = MAX_FW_SIZE,
1291 .cpb = MAX_CPB_SIZE,
1292 .priv = &mfc_buf_size_v5,
1293};
1294
1295struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1296 .base = MFC_BASE_ALIGN_ORDER,
1297};
1298
1299static struct s5p_mfc_variant mfc_drvdata_v5 = {
1300 .version = MFC_VERSION,
1301 .port_num = MFC_NUM_PORTS,
1302 .buf_size = &buf_size_v5,
1303 .buf_align = &mfc_buf_align_v5,
1304};
1305
1306static struct platform_device_id mfc_driver_ids[] = {
1307 {
1308 .name = "s5p-mfc",
1309 .driver_data = (unsigned long)&mfc_drvdata_v5,
1310 },
1311 {},
1312};
1313MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1314
1312static struct platform_driver s5p_mfc_driver = { 1315static struct platform_driver s5p_mfc_driver = {
1313 .probe = s5p_mfc_probe, 1316 .probe = s5p_mfc_probe,
1314 .remove = __devexit_p(s5p_mfc_remove), 1317 .remove = __devexit_p(s5p_mfc_remove),
1318 .id_table = mfc_driver_ids,
1315 .driver = { 1319 .driver = {
1316 .name = S5P_MFC_NAME, 1320 .name = S5P_MFC_NAME,
1317 .owner = THIS_MODULE, 1321 .owner = THIS_MODULE,
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
index e4eb9569ba15..138778083c63 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
@@ -113,8 +113,8 @@ int s5p_mfc_open_inst_cmd_v5(struct s5p_mfc_ctx *ctx)
113 h2r_args.arg[0] = S5P_FIMV_CODEC_NONE; 113 h2r_args.arg[0] = S5P_FIMV_CODEC_NONE;
114 }; 114 };
115 h2r_args.arg[1] = 0; /* no crc & no pixelcache */ 115 h2r_args.arg[1] = 0; /* no crc & no pixelcache */
116 h2r_args.arg[2] = ctx->ctx_ofs; 116 h2r_args.arg[2] = ctx->ctx.ofs;
117 h2r_args.arg[3] = ctx->ctx_size; 117 h2r_args.arg[3] = ctx->ctx.size;
118 ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE, 118 ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE,
119 &h2r_args); 119 &h2r_args);
120 if (ret) { 120 if (ret) {
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 82931d471d5e..e495b13b2710 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -30,17 +30,6 @@
30* while mmaping */ 30* while mmaping */
31#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) 31#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
32 32
33/* Offset used by the hardware to store addresses */
34#define MFC_OFFSET_SHIFT 11
35
36#define FIRMWARE_ALIGN 0x20000 /* 128KB */
37#define MFC_H264_CTX_BUF_SIZE 0x96000 /* 600KB per H264 instance */
38#define MFC_CTX_BUF_SIZE 0x2800 /* 10KB per instance */
39#define DESC_BUF_SIZE 0x20000 /* 128KB for DESC buffer */
40#define SHARED_BUF_SIZE 0x2000 /* 8KB for shared buffer */
41
42#define DEF_CPB_SIZE 0x40000 /* 512KB */
43
44#define MFC_BANK1_ALLOC_CTX 0 33#define MFC_BANK1_ALLOC_CTX 0
45#define MFC_BANK2_ALLOC_CTX 1 34#define MFC_BANK2_ALLOC_CTX 1
46 35
@@ -210,6 +199,48 @@ struct s5p_mfc_pm {
210 struct device *device; 199 struct device *device;
211}; 200};
212 201
202struct s5p_mfc_buf_size_v5 {
203 unsigned int h264_ctx;
204 unsigned int non_h264_ctx;
205 unsigned int dsc;
206 unsigned int shm;
207};
208
209struct s5p_mfc_buf_size {
210 unsigned int fw;
211 unsigned int cpb;
212 void *priv;
213};
214
215struct s5p_mfc_buf_align {
216 unsigned int base;
217};
218
219struct s5p_mfc_variant {
220 unsigned int version;
221 unsigned int port_num;
222 struct s5p_mfc_buf_size *buf_size;
223 struct s5p_mfc_buf_align *buf_align;
224};
225
226/**
227 * struct s5p_mfc_priv_buf - represents internal used buffer
228 * @alloc: allocation-specific context for each buffer
229 * (videobuf2 allocator)
230 * @ofs: offset of each buffer, will be used for MFC
231 * @virt: kernel virtual address, only valid when the
232 * buffer accessed by driver
233 * @dma: DMA address, only valid when kernel DMA API used
234 * @size: size of the buffer
235 */
236struct s5p_mfc_priv_buf {
237 void *alloc;
238 unsigned long ofs;
239 void *virt;
240 dma_addr_t dma;
241 size_t size;
242};
243
213/** 244/**
214 * struct s5p_mfc_dev - The struct containing driver internal parameters. 245 * struct s5p_mfc_dev - The struct containing driver internal parameters.
215 * 246 *
@@ -224,6 +255,7 @@ struct s5p_mfc_pm {
224 * @dec_ctrl_handler: control framework handler for decoding 255 * @dec_ctrl_handler: control framework handler for decoding
225 * @enc_ctrl_handler: control framework handler for encoding 256 * @enc_ctrl_handler: control framework handler for encoding
226 * @pm: power management control 257 * @pm: power management control
258 * @variant: MFC hardware variant information
227 * @num_inst: couter of active MFC instances 259 * @num_inst: couter of active MFC instances
228 * @irqlock: lock for operations on videobuf2 queues 260 * @irqlock: lock for operations on videobuf2 queues
229 * @condlock: lock for changing/checking if a context is ready to be 261 * @condlock: lock for changing/checking if a context is ready to be
@@ -262,6 +294,7 @@ struct s5p_mfc_dev {
262 struct v4l2_ctrl_handler dec_ctrl_handler; 294 struct v4l2_ctrl_handler dec_ctrl_handler;
263 struct v4l2_ctrl_handler enc_ctrl_handler; 295 struct v4l2_ctrl_handler enc_ctrl_handler;
264 struct s5p_mfc_pm pm; 296 struct s5p_mfc_pm pm;
297 struct s5p_mfc_variant *variant;
265 int num_inst; 298 int num_inst;
266 spinlock_t irqlock; /* lock when operating on videobuf2 queues */ 299 spinlock_t irqlock; /* lock when operating on videobuf2 queues */
267 spinlock_t condlock; /* lock when changing/checking if a context is 300 spinlock_t condlock; /* lock when changing/checking if a context is
@@ -302,7 +335,6 @@ struct s5p_mfc_h264_enc_params {
302 u8 max_ref_pic; 335 u8 max_ref_pic;
303 u8 num_ref_pic_4p; 336 u8 num_ref_pic_4p;
304 int _8x8_transform; 337 int _8x8_transform;
305 int rc_mb;
306 int rc_mb_dark; 338 int rc_mb_dark;
307 int rc_mb_smooth; 339 int rc_mb_smooth;
308 int rc_mb_static; 340 int rc_mb_static;
@@ -321,6 +353,7 @@ struct s5p_mfc_h264_enc_params {
321 enum v4l2_mpeg_video_h264_level level_v4l2; 353 enum v4l2_mpeg_video_h264_level level_v4l2;
322 int level; 354 int level;
323 u16 cpb_size; 355 u16 cpb_size;
356 int interlace;
324}; 357};
325 358
326/** 359/**
@@ -359,6 +392,7 @@ struct s5p_mfc_enc_params {
359 u8 pad_cb; 392 u8 pad_cb;
360 u8 pad_cr; 393 u8 pad_cr;
361 int rc_frame; 394 int rc_frame;
395 int rc_mb;
362 u32 rc_bitrate; 396 u32 rc_bitrate;
363 u16 rc_reaction_coeff; 397 u16 rc_reaction_coeff;
364 u16 vbv_size; 398 u16 vbv_size;
@@ -370,7 +404,6 @@ struct s5p_mfc_enc_params {
370 u8 num_b_frame; 404 u8 num_b_frame;
371 u32 rc_framerate_num; 405 u32 rc_framerate_num;
372 u32 rc_framerate_denom; 406 u32 rc_framerate_denom;
373 int interlace;
374 407
375 union { 408 union {
376 struct s5p_mfc_h264_enc_params h264; 409 struct s5p_mfc_h264_enc_params h264;
@@ -455,14 +488,9 @@ struct s5p_mfc_codec_ops {
455 * @dpb_count: count of the DPB buffers required by MFC hw 488 * @dpb_count: count of the DPB buffers required by MFC hw
456 * @total_dpb_count: count of DPB buffers with additional buffers 489 * @total_dpb_count: count of DPB buffers with additional buffers
457 * requested by the application 490 * requested by the application
458 * @ctx_buf: handle to the memory associated with this context 491 * @ctx: context buffer information
459 * @ctx_phys: address of the memory associated with this context 492 * @dsc: descriptor buffer information
460 * @ctx_size: size of the memory associated with this context 493 * @shm: shared memory buffer information
461 * @desc_buf: description buffer for decoding handle
462 * @desc_phys: description buffer for decoding address
463 * @shm_alloc: handle for the shared memory buffer
464 * @shm: virtual address for the shared memory buffer
465 * @shm_ofs: address offset for shared memory
466 * @enc_params: encoding parameters for MFC 494 * @enc_params: encoding parameters for MFC
467 * @enc_dst_buf_size: size of the buffers for encoder output 495 * @enc_dst_buf_size: size of the buffers for encoder output
468 * @frame_type: used to force the type of the next encoded frame 496 * @frame_type: used to force the type of the next encoded frame
@@ -547,18 +575,9 @@ struct s5p_mfc_ctx {
547 int total_dpb_count; 575 int total_dpb_count;
548 576
549 /* Buffers */ 577 /* Buffers */
550 void *ctx_buf; 578 struct s5p_mfc_priv_buf ctx;
551 size_t ctx_phys; 579 struct s5p_mfc_priv_buf dsc;
552 size_t ctx_ofs; 580 struct s5p_mfc_priv_buf shm;
553 size_t ctx_size;
554
555 void *desc_buf;
556 size_t desc_phys;
557
558
559 void *shm_alloc;
560 void *shm;
561 size_t shm_ofs;
562 581
563 struct s5p_mfc_enc_params enc_params; 582 struct s5p_mfc_enc_params enc_params;
564 583
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
index 7666e9445fba..311ec90be621 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
@@ -43,7 +43,12 @@ int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev)
43 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n"); 43 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
44 return -EINVAL; 44 return -EINVAL;
45 } 45 }
46 dev->fw_size = ALIGN(fw_blob->size, FIRMWARE_ALIGN); 46 dev->fw_size = dev->variant->buf_size->fw;
47 if (fw_blob->size > dev->fw_size) {
48 mfc_err("MFC firmware is too big to be loaded\n");
49 release_firmware(fw_blob);
50 return -ENOMEM;
51 }
47 if (s5p_mfc_bitproc_buf) { 52 if (s5p_mfc_bitproc_buf) {
48 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n"); 53 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
49 release_firmware(fw_blob); 54 release_firmware(fw_blob);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index 3b0e594004d4..b0879f912db3 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -977,45 +977,13 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
977 mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n", 977 mfc_debug(2, "fmt - w: %d, h: %d, ctx - w: %d, h: %d\n",
978 pix_fmt_mp->width, pix_fmt_mp->height, 978 pix_fmt_mp->width, pix_fmt_mp->height,
979 ctx->img_width, ctx->img_height); 979 ctx->img_width, ctx->img_height);
980 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 980
981 ctx->buf_width = ALIGN(ctx->img_width, 981 s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx);
982 S5P_FIMV_NV12M_HALIGN); 982 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
983 ctx->luma_size = ALIGN(ctx->img_width, 983 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
984 S5P_FIMV_NV12M_HALIGN) * ALIGN(ctx->img_height, 984 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
985 S5P_FIMV_NV12M_LVALIGN); 985 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
986 ctx->chroma_size = ALIGN(ctx->img_width, 986
987 S5P_FIMV_NV12M_HALIGN) * ALIGN((ctx->img_height
988 >> 1), S5P_FIMV_NV12M_CVALIGN);
989
990 ctx->luma_size = ALIGN(ctx->luma_size,
991 S5P_FIMV_NV12M_SALIGN);
992 ctx->chroma_size = ALIGN(ctx->chroma_size,
993 S5P_FIMV_NV12M_SALIGN);
994
995 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
996 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
997 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
998 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
999
1000 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
1001 ctx->buf_width = ALIGN(ctx->img_width,
1002 S5P_FIMV_NV12MT_HALIGN);
1003 ctx->luma_size = ALIGN(ctx->img_width,
1004 S5P_FIMV_NV12MT_HALIGN) * ALIGN(ctx->img_height,
1005 S5P_FIMV_NV12MT_VALIGN);
1006 ctx->chroma_size = ALIGN(ctx->img_width,
1007 S5P_FIMV_NV12MT_HALIGN) * ALIGN((ctx->img_height
1008 >> 1), S5P_FIMV_NV12MT_VALIGN);
1009 ctx->luma_size = ALIGN(ctx->luma_size,
1010 S5P_FIMV_NV12MT_SALIGN);
1011 ctx->chroma_size = ALIGN(ctx->chroma_size,
1012 S5P_FIMV_NV12MT_SALIGN);
1013
1014 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
1015 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
1016 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
1017 pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
1018 }
1019 ctx->src_bufs_cnt = 0; 987 ctx->src_bufs_cnt = 0;
1020 ctx->output_state = QUEUE_FREE; 988 ctx->output_state = QUEUE_FREE;
1021 } else { 989 } else {
@@ -1357,7 +1325,7 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
1357 p->codec.h264._8x8_transform = ctrl->val; 1325 p->codec.h264._8x8_transform = ctrl->val;
1358 break; 1326 break;
1359 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: 1327 case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:
1360 p->codec.h264.rc_mb = ctrl->val; 1328 p->rc_mb = ctrl->val;
1361 break; 1329 break;
1362 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 1330 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1363 p->codec.h264.rc_frame_qp = ctrl->val; 1331 p->codec.h264.rc_frame_qp = ctrl->val;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c
index 17928c82c7f4..bf7d010a4107 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c
@@ -36,28 +36,29 @@
36/* Allocate temporary buffers for decoding */ 36/* Allocate temporary buffers for decoding */
37int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx) 37int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx)
38{ 38{
39 void *desc_virt;
40 struct s5p_mfc_dev *dev = ctx->dev; 39 struct s5p_mfc_dev *dev = ctx->dev;
40 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
41 41
42 ctx->desc_buf = vb2_dma_contig_memops.alloc( 42 ctx->dsc.alloc = vb2_dma_contig_memops.alloc(
43 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], DESC_BUF_SIZE); 43 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX],
44 if (IS_ERR_VALUE((int)ctx->desc_buf)) { 44 buf_size->dsc);
45 ctx->desc_buf = NULL; 45 if (IS_ERR_VALUE((int)ctx->dsc.alloc)) {
46 ctx->dsc.alloc = NULL;
46 mfc_err("Allocating DESC buffer failed\n"); 47 mfc_err("Allocating DESC buffer failed\n");
47 return -ENOMEM; 48 return -ENOMEM;
48 } 49 }
49 ctx->desc_phys = s5p_mfc_mem_cookie( 50 ctx->dsc.dma = s5p_mfc_mem_cookie(
50 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->desc_buf); 51 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->dsc.alloc);
51 BUG_ON(ctx->desc_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 52 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
52 desc_virt = vb2_dma_contig_memops.vaddr(ctx->desc_buf); 53 ctx->dsc.virt = vb2_dma_contig_memops.vaddr(ctx->dsc.alloc);
53 if (desc_virt == NULL) { 54 if (ctx->dsc.virt == NULL) {
54 vb2_dma_contig_memops.put(ctx->desc_buf); 55 vb2_dma_contig_memops.put(ctx->dsc.alloc);
55 ctx->desc_phys = 0; 56 ctx->dsc.dma = 0;
56 ctx->desc_buf = NULL; 57 ctx->dsc.alloc = NULL;
57 mfc_err("Remapping DESC buffer failed\n"); 58 mfc_err("Remapping DESC buffer failed\n");
58 return -ENOMEM; 59 return -ENOMEM;
59 } 60 }
60 memset(desc_virt, 0, DESC_BUF_SIZE); 61 memset(ctx->dsc.virt, 0, buf_size->dsc);
61 wmb(); 62 wmb();
62 return 0; 63 return 0;
63} 64}
@@ -65,10 +66,10 @@ int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx)
65/* Release temporary buffers for decoding */ 66/* Release temporary buffers for decoding */
66void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx) 67void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx)
67{ 68{
68 if (ctx->desc_phys) { 69 if (ctx->dsc.dma) {
69 vb2_dma_contig_memops.put(ctx->desc_buf); 70 vb2_dma_contig_memops.put(ctx->dsc.alloc);
70 ctx->desc_phys = 0; 71 ctx->dsc.alloc = NULL;
71 ctx->desc_buf = NULL; 72 ctx->dsc.dma = 0;
72 } 73 }
73} 74}
74 75
@@ -230,60 +231,60 @@ void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx)
230/* Allocate memory for instance data buffer */ 231/* Allocate memory for instance data buffer */
231int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 232int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
232{ 233{
233 void *context_virt;
234 struct s5p_mfc_dev *dev = ctx->dev; 234 struct s5p_mfc_dev *dev = ctx->dev;
235 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
235 236
236 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || 237 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
237 ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) 238 ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
238 ctx->ctx_size = MFC_H264_CTX_BUF_SIZE; 239 ctx->ctx.size = buf_size->h264_ctx;
239 else 240 else
240 ctx->ctx_size = MFC_CTX_BUF_SIZE; 241 ctx->ctx.size = buf_size->non_h264_ctx;
241 ctx->ctx_buf = vb2_dma_contig_memops.alloc( 242 ctx->ctx.alloc = vb2_dma_contig_memops.alloc(
242 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_size); 243 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx.size);
243 if (IS_ERR(ctx->ctx_buf)) { 244 if (IS_ERR(ctx->ctx.alloc)) {
244 mfc_err("Allocating context buffer failed\n"); 245 mfc_err("Allocating context buffer failed\n");
245 ctx->ctx_phys = 0; 246 ctx->ctx.alloc = NULL;
246 ctx->ctx_buf = NULL;
247 return -ENOMEM; 247 return -ENOMEM;
248 } 248 }
249 ctx->ctx_phys = s5p_mfc_mem_cookie( 249 ctx->ctx.dma = s5p_mfc_mem_cookie(
250 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_buf); 250 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx.alloc);
251 BUG_ON(ctx->ctx_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 251 BUG_ON(ctx->ctx.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
252 ctx->ctx_ofs = OFFSETA(ctx->ctx_phys); 252 ctx->ctx.ofs = OFFSETA(ctx->ctx.dma);
253 context_virt = vb2_dma_contig_memops.vaddr(ctx->ctx_buf); 253 ctx->ctx.virt = vb2_dma_contig_memops.vaddr(ctx->ctx.alloc);
254 if (context_virt == NULL) { 254 if (!ctx->ctx.virt) {
255 mfc_err("Remapping instance buffer failed\n"); 255 mfc_err("Remapping instance buffer failed\n");
256 vb2_dma_contig_memops.put(ctx->ctx_buf); 256 vb2_dma_contig_memops.put(ctx->ctx.alloc);
257 ctx->ctx_phys = 0; 257 ctx->ctx.alloc = NULL;
258 ctx->ctx_buf = NULL; 258 ctx->ctx.ofs = 0;
259 ctx->ctx.dma = 0;
259 return -ENOMEM; 260 return -ENOMEM;
260 } 261 }
261 /* Zero content of the allocated memory */ 262 /* Zero content of the allocated memory */
262 memset(context_virt, 0, ctx->ctx_size); 263 memset(ctx->ctx.virt, 0, ctx->ctx.size);
263 wmb(); 264 wmb();
264 265
265 /* Initialize shared memory */ 266 /* Initialize shared memory */
266 ctx->shm_alloc = vb2_dma_contig_memops.alloc( 267 ctx->shm.alloc = vb2_dma_contig_memops.alloc(
267 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], SHARED_BUF_SIZE); 268 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], buf_size->shm);
268 if (IS_ERR(ctx->shm_alloc)) { 269 if (IS_ERR(ctx->shm.alloc)) {
269 mfc_err("failed to allocate shared memory\n"); 270 mfc_err("failed to allocate shared memory\n");
270 return PTR_ERR(ctx->shm_alloc); 271 return PTR_ERR(ctx->shm.alloc);
271 } 272 }
272 /* shared memory offset only keeps the offset from base (port a) */ 273 /* shared memory offset only keeps the offset from base (port a) */
273 ctx->shm_ofs = s5p_mfc_mem_cookie( 274 ctx->shm.ofs = s5p_mfc_mem_cookie(
274 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->shm_alloc) 275 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->shm.alloc)
275 - dev->bank1; 276 - dev->bank1;
276 BUG_ON(ctx->shm_ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 277 BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
277 278
278 ctx->shm = vb2_dma_contig_memops.vaddr(ctx->shm_alloc); 279 ctx->shm.virt = vb2_dma_contig_memops.vaddr(ctx->shm.alloc);
279 if (!ctx->shm) { 280 if (!ctx->shm.virt) {
280 vb2_dma_contig_memops.put(ctx->shm_alloc); 281 vb2_dma_contig_memops.put(ctx->shm.alloc);
281 ctx->shm_ofs = 0; 282 ctx->shm.alloc = NULL;
282 ctx->shm_alloc = NULL; 283 ctx->shm.ofs = 0;
283 mfc_err("failed to virt addr of shared memory\n"); 284 mfc_err("failed to virt addr of shared memory\n");
284 return -ENOMEM; 285 return -ENOMEM;
285 } 286 }
286 memset((void *)ctx->shm, 0, SHARED_BUF_SIZE); 287 memset((void *)ctx->shm.virt, 0, buf_size->shm);
287 wmb(); 288 wmb();
288 return 0; 289 return 0;
289} 290}
@@ -291,15 +292,18 @@ int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
291/* Release instance buffer */ 292/* Release instance buffer */
292void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 293void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
293{ 294{
294 if (ctx->ctx_buf) { 295 if (ctx->ctx.alloc) {
295 vb2_dma_contig_memops.put(ctx->ctx_buf); 296 vb2_dma_contig_memops.put(ctx->ctx.alloc);
296 ctx->ctx_phys = 0; 297 ctx->ctx.alloc = NULL;
297 ctx->ctx_buf = NULL; 298 ctx->ctx.ofs = 0;
299 ctx->ctx.virt = NULL;
300 ctx->ctx.dma = 0;
298 } 301 }
299 if (ctx->shm_alloc) { 302 if (ctx->shm.alloc) {
300 vb2_dma_contig_memops.put(ctx->shm_alloc); 303 vb2_dma_contig_memops.put(ctx->shm.alloc);
301 ctx->shm_alloc = NULL; 304 ctx->shm.alloc = NULL;
302 ctx->shm = NULL; 305 ctx->shm.ofs = 0;
306 ctx->shm.virt = NULL;
303 } 307 }
304} 308}
305 309
@@ -318,7 +322,7 @@ void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev)
318static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, 322static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data,
319 unsigned int ofs) 323 unsigned int ofs)
320{ 324{
321 writel(data, (ctx->shm + ofs)); 325 writel(data, (ctx->shm.virt + ofs));
322 wmb(); 326 wmb();
323} 327}
324 328
@@ -326,33 +330,94 @@ static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx,
326 unsigned int ofs) 330 unsigned int ofs)
327{ 331{
328 rmb(); 332 rmb();
329 return readl(ctx->shm + ofs); 333 return readl(ctx->shm.virt + ofs);
330} 334}
331 335
332void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) 336void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx)
333{ 337{
334 /* NOP */ 338 unsigned int guard_width, guard_height;
339
340 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
341 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
342 mfc_debug(2,
343 "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n",
344 ctx->img_width, ctx->img_height, ctx->buf_width,
345 ctx->buf_height);
346
347 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) {
348 ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height,
349 S5P_FIMV_DEC_BUF_ALIGN);
350 ctx->chroma_size = ALIGN(ctx->buf_width *
351 ALIGN((ctx->img_height >> 1),
352 S5P_FIMV_NV12MT_VALIGN),
353 S5P_FIMV_DEC_BUF_ALIGN);
354 ctx->mv_size = ALIGN(ctx->buf_width *
355 ALIGN((ctx->buf_height >> 2),
356 S5P_FIMV_NV12MT_VALIGN),
357 S5P_FIMV_DEC_BUF_ALIGN);
358 } else {
359 guard_width =
360 ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN);
361 guard_height =
362 ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN);
363 ctx->luma_size = ALIGN(guard_width * guard_height,
364 S5P_FIMV_DEC_BUF_ALIGN);
365
366 guard_width =
367 ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
368 guard_height =
369 ALIGN((ctx->img_height >> 1) + 4,
370 S5P_FIMV_NV12MT_VALIGN);
371 ctx->chroma_size = ALIGN(guard_width * guard_height,
372 S5P_FIMV_DEC_BUF_ALIGN);
373
374 ctx->mv_size = 0;
375 }
335} 376}
336 377
337void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx) 378void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx)
338{ 379{
339 /* NOP */ 380 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
381 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN);
382
383 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
384 * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN);
385 ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
386 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN);
387
388 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN);
389 ctx->chroma_size =
390 ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN);
391 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
392 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
393
394 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
395 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
396 ctx->chroma_size =
397 ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
398 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
399
400 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN);
401 ctx->chroma_size =
402 ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN);
403 }
340} 404}
341 405
342/* Set registers for decoding temporary buffers */ 406/* Set registers for decoding temporary buffers */
343static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) 407static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
344{ 408{
345 struct s5p_mfc_dev *dev = ctx->dev; 409 struct s5p_mfc_dev *dev = ctx->dev;
410 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
346 411
347 mfc_write(dev, OFFSETA(ctx->desc_phys), S5P_FIMV_SI_CH0_DESC_ADR); 412 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);
348 mfc_write(dev, DESC_BUF_SIZE, S5P_FIMV_SI_CH0_DESC_SIZE); 413 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);
349} 414}
350 415
351/* Set registers for shared buffer */ 416/* Set registers for shared buffer */
352static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) 417static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx)
353{ 418{
354 struct s5p_mfc_dev *dev = ctx->dev; 419 struct s5p_mfc_dev *dev = ctx->dev;
355 mfc_write(dev, ctx->shm_ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); 420 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
356} 421}
357 422
358/* Set registers for decoding stream buffer */ 423/* Set registers for decoding stream buffer */
@@ -776,9 +841,9 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
776 reg |= p_264->profile; 841 reg |= p_264->profile;
777 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); 842 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
778 /* interlace */ 843 /* interlace */
779 mfc_write(dev, p->interlace, S5P_FIMV_ENC_PIC_STRUCT); 844 mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT);
780 /* height */ 845 /* height */
781 if (p->interlace) 846 if (p_264->interlace)
782 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); 847 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
783 /* loopfilter ctrl */ 848 /* loopfilter ctrl */
784 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); 849 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL);
@@ -820,7 +885,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
820 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 885 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
821 /* macroblock level rate control */ 886 /* macroblock level rate control */
822 reg &= ~(0x1 << 8); 887 reg &= ~(0x1 << 8);
823 reg |= (p_264->rc_mb << 8); 888 reg |= (p->rc_mb << 8);
824 /* frame QP */ 889 /* frame QP */
825 reg &= ~(0x3F); 890 reg &= ~(0x3F);
826 reg |= p_264->rc_frame_qp; 891 reg |= p_264->rc_frame_qp;
@@ -841,7 +906,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
841 reg |= p_264->rc_min_qp; 906 reg |= p_264->rc_min_qp;
842 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 907 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
843 /* macroblock adaptive scaling features */ 908 /* macroblock adaptive scaling features */
844 if (p_264->rc_mb) { 909 if (p->rc_mb) {
845 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); 910 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL);
846 /* dark region */ 911 /* dark region */
847 reg &= ~(0x1 << 3); 912 reg &= ~(0x1 << 3);
@@ -857,8 +922,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
857 reg |= p_264->rc_mb_activity; 922 reg |= p_264->rc_mb_activity;
858 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); 923 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL);
859 } 924 }
860 if (!p->rc_frame && 925 if (!p->rc_frame && !p->rc_mb) {
861 !p_264->rc_mb) {
862 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 926 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
863 shm &= ~(0xFFF); 927 shm &= ~(0xFFF);
864 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); 928 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6);
@@ -1515,8 +1579,9 @@ int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev)
1515 1579
1516int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx) 1580int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx)
1517{ 1581{
1518 /* NOP */ 1582 return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >>
1519 return -1; 1583 S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) &
1584 S5P_FIMV_DECODE_FRAME_MASK;
1520} 1585}
1521 1586
1522int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev) 1587int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev)