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authorPhilipp Zabel <p.zabel@pengutronix.de>2012-07-02 08:03:55 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-09-26 15:29:37 -0400
commit1043667b1763feac06654c9bf7263b215df2c893 (patch)
tree6a23e1ce991d4a5953952bcf19d2c176446575a2 /drivers/media/platform/coda.c
parentdf1e74cc04dbc0d2fada237333b91e167b09dd30 (diff)
[media] media: coda: fix IRAM/AXI handling for i.MX53
This uses the ARCH_MXC specific iram_alloc API to allocate a work buffer in the SoC's on-chip SRAM and sets up the AXI_SRAM_USE register. In the future, the allocation will be converted to use the genalloc API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform/coda.c')
-rw-r--r--drivers/media/platform/coda.c52
1 files changed, 48 insertions, 4 deletions
diff --git a/drivers/media/platform/coda.c b/drivers/media/platform/coda.c
index a560c0da68ae..53816d045c84 100644
--- a/drivers/media/platform/coda.c
+++ b/drivers/media/platform/coda.c
@@ -24,6 +24,7 @@
24#include <linux/videodev2.h> 24#include <linux/videodev2.h>
25#include <linux/of.h> 25#include <linux/of.h>
26 26
27#include <mach/iram.h>
27#include <media/v4l2-ctrls.h> 28#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h> 29#include <media/v4l2-device.h>
29#include <media/v4l2-ioctl.h> 30#include <media/v4l2-ioctl.h>
@@ -42,6 +43,7 @@
42#define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024) 43#define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
43#define CODA_PARA_BUF_SIZE (10 * 1024) 44#define CODA_PARA_BUF_SIZE (10 * 1024)
44#define CODA_ISRAM_SIZE (2048 * 2) 45#define CODA_ISRAM_SIZE (2048 * 2)
46#define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
45 47
46#define CODA_OUTPUT_BUFS 4 48#define CODA_OUTPUT_BUFS 4
47#define CODA_CAPTURE_BUFS 2 49#define CODA_CAPTURE_BUFS 2
@@ -127,6 +129,7 @@ struct coda_dev {
127 129
128 struct coda_aux_buf codebuf; 130 struct coda_aux_buf codebuf;
129 struct coda_aux_buf workbuf; 131 struct coda_aux_buf workbuf;
132 long unsigned int iram_paddr;
130 133
131 spinlock_t irqlock; 134 spinlock_t irqlock;
132 struct mutex dev_mutex; 135 struct mutex dev_mutex;
@@ -715,6 +718,13 @@ static void coda_device_run(void *m2m_priv)
715 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START); 718 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
716 coda_write(dev, pic_stream_buffer_size / 1024, 719 coda_write(dev, pic_stream_buffer_size / 1024,
717 CODA_CMD_ENC_PIC_BB_SIZE); 720 CODA_CMD_ENC_PIC_BB_SIZE);
721
722 if (dev->devtype->product == CODA_7541) {
723 coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
724 CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
725 CODA7_REG_BIT_AXI_SRAM_USE);
726 }
727
718 coda_command_async(ctx, CODA_COMMAND_PIC_RUN); 728 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
719} 729}
720 730
@@ -946,8 +956,10 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
946 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL); 956 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
947 } 957 }
948 958
949 /* Configure the coda */ 959 if (dev->devtype->product == CODA_DX6) {
950 coda_write(dev, 0xffff4c00, CODA_REG_BIT_SEARCH_RAM_BASE_ADDR); 960 /* Configure the coda */
961 coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
962 }
951 963
952 /* Could set rotation here if needed */ 964 /* Could set rotation here if needed */
953 switch (dev->devtype->product) { 965 switch (dev->devtype->product) {
@@ -1022,7 +1034,12 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
1022 value = (FMO_SLICE_SAVE_BUF_SIZE << 7); 1034 value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
1023 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET; 1035 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
1024 value |= 0 & CODA_FMOPARAM_SLICENUM_MASK; 1036 value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
1025 coda_write(dev, value, CODA_CMD_ENC_SEQ_FMO); 1037 if (dev->devtype->product == CODA_DX6) {
1038 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1039 } else {
1040 coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1041 coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1042 }
1026 } 1043 }
1027 1044
1028 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) { 1045 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
@@ -1052,7 +1069,15 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
1052 } 1069 }
1053 1070
1054 coda_write(dev, src_vq->num_buffers, CODA_CMD_SET_FRAME_BUF_NUM); 1071 coda_write(dev, src_vq->num_buffers, CODA_CMD_SET_FRAME_BUF_NUM);
1055 coda_write(dev, q_data_src->width, CODA_CMD_SET_FRAME_BUF_STRIDE); 1072 coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
1073 if (dev->devtype->product != CODA_DX6) {
1074 coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1075 coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1076 coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1077 coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1078 coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1079 coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1080 }
1056 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) { 1081 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1057 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n"); 1082 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1058 return -ETIMEDOUT; 1083 return -ETIMEDOUT;
@@ -1583,6 +1608,10 @@ static int coda_hw_init(struct coda_dev *dev)
1583 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL); 1608 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1584 } 1609 }
1585 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL); 1610 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
1611
1612 if (dev->devtype->product != CODA_DX6)
1613 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
1614
1586 coda_write(dev, CODA_INT_INTERRUPT_ENABLE, 1615 coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
1587 CODA_REG_BIT_INT_ENABLE); 1616 CODA_REG_BIT_INT_ENABLE);
1588 1617
@@ -1852,6 +1881,19 @@ static int __devinit coda_probe(struct platform_device *pdev)
1852 return -ENOMEM; 1881 return -ENOMEM;
1853 } 1882 }
1854 1883
1884 if (dev->devtype->product == CODA_DX6) {
1885 dev->iram_paddr = 0xffff4c00;
1886 } else {
1887 void __iomem *iram_vaddr;
1888
1889 iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
1890 &dev->iram_paddr);
1891 if (!iram_vaddr) {
1892 dev_err(&pdev->dev, "unable to alloc iram\n");
1893 return -ENOMEM;
1894 }
1895 }
1896
1855 platform_set_drvdata(pdev, dev); 1897 platform_set_drvdata(pdev, dev);
1856 1898
1857 return coda_firmware_request(dev); 1899 return coda_firmware_request(dev);
@@ -1867,6 +1909,8 @@ static int coda_remove(struct platform_device *pdev)
1867 if (dev->alloc_ctx) 1909 if (dev->alloc_ctx)
1868 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx); 1910 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1869 v4l2_device_unregister(&dev->v4l2_dev); 1911 v4l2_device_unregister(&dev->v4l2_dev);
1912 if (dev->iram_paddr)
1913 iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
1870 if (dev->codebuf.vaddr) 1914 if (dev->codebuf.vaddr)
1871 dma_free_coherent(&pdev->dev, dev->codebuf.size, 1915 dma_free_coherent(&pdev->dev, dev->codebuf.size,
1872 &dev->codebuf.vaddr, dev->codebuf.paddr); 1916 &dev->codebuf.vaddr, dev->codebuf.paddr);