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authorHans Verkuil <hans.verkuil@cisco.com>2013-07-29 07:41:01 -0400
committerMauro Carvalho Chehab <m.chehab@samsung.com>2013-08-18 07:20:30 -0400
commit041649048149b3e4afa56428e6d1b081b9dd49f5 (patch)
treeceff2af394191a71851e644193858d21941f9ee2 /drivers/media/i2c/ad9389b.c
parente36552684e24f8b21569dec47381c36b50a7966b (diff)
[media] ths8200/ad9389b: use new dv_timings helpers
Simplify the code by using the new dv_timings helpers. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'drivers/media/i2c/ad9389b.c')
-rw-r--r--drivers/media/i2c/ad9389b.c108
1 files changed, 17 insertions, 91 deletions
diff --git a/drivers/media/i2c/ad9389b.c b/drivers/media/i2c/ad9389b.c
index 5295234deb51..7e68d8f9676f 100644
--- a/drivers/media/i2c/ad9389b.c
+++ b/drivers/media/i2c/ad9389b.c
@@ -635,95 +635,34 @@ static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
635 return 0; 635 return 0;
636} 636}
637 637
638static const struct v4l2_dv_timings ad9389b_timings[] = { 638static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
639 V4L2_DV_BT_CEA_720X480P59_94, 639 .type = V4L2_DV_BT_656_1120,
640 V4L2_DV_BT_CEA_720X576P50, 640 .bt = {
641 V4L2_DV_BT_CEA_1280X720P24, 641 .max_width = 1920,
642 V4L2_DV_BT_CEA_1280X720P25, 642 .max_height = 1200,
643 V4L2_DV_BT_CEA_1280X720P30, 643 .min_pixelclock = 27000000,
644 V4L2_DV_BT_CEA_1280X720P50, 644 .max_pixelclock = 170000000,
645 V4L2_DV_BT_CEA_1280X720P60, 645 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
646 V4L2_DV_BT_CEA_1920X1080P24, 646 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
647 V4L2_DV_BT_CEA_1920X1080P25, 647 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
648 V4L2_DV_BT_CEA_1920X1080P30, 648 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
649 V4L2_DV_BT_CEA_1920X1080P50, 649 },
650 V4L2_DV_BT_CEA_1920X1080P60,
651
652 V4L2_DV_BT_DMT_640X350P85,
653 V4L2_DV_BT_DMT_640X400P85,
654 V4L2_DV_BT_DMT_720X400P85,
655 V4L2_DV_BT_DMT_640X480P60,
656 V4L2_DV_BT_DMT_640X480P72,
657 V4L2_DV_BT_DMT_640X480P75,
658 V4L2_DV_BT_DMT_640X480P85,
659 V4L2_DV_BT_DMT_800X600P56,
660 V4L2_DV_BT_DMT_800X600P60,
661 V4L2_DV_BT_DMT_800X600P72,
662 V4L2_DV_BT_DMT_800X600P75,
663 V4L2_DV_BT_DMT_800X600P85,
664 V4L2_DV_BT_DMT_848X480P60,
665 V4L2_DV_BT_DMT_1024X768P60,
666 V4L2_DV_BT_DMT_1024X768P70,
667 V4L2_DV_BT_DMT_1024X768P75,
668 V4L2_DV_BT_DMT_1024X768P85,
669 V4L2_DV_BT_DMT_1152X864P75,
670 V4L2_DV_BT_DMT_1280X768P60_RB,
671 V4L2_DV_BT_DMT_1280X768P60,
672 V4L2_DV_BT_DMT_1280X768P75,
673 V4L2_DV_BT_DMT_1280X768P85,
674 V4L2_DV_BT_DMT_1280X800P60_RB,
675 V4L2_DV_BT_DMT_1280X800P60,
676 V4L2_DV_BT_DMT_1280X800P75,
677 V4L2_DV_BT_DMT_1280X800P85,
678 V4L2_DV_BT_DMT_1280X960P60,
679 V4L2_DV_BT_DMT_1280X960P85,
680 V4L2_DV_BT_DMT_1280X1024P60,
681 V4L2_DV_BT_DMT_1280X1024P75,
682 V4L2_DV_BT_DMT_1280X1024P85,
683 V4L2_DV_BT_DMT_1360X768P60,
684 V4L2_DV_BT_DMT_1400X1050P60_RB,
685 V4L2_DV_BT_DMT_1400X1050P60,
686 V4L2_DV_BT_DMT_1400X1050P75,
687 V4L2_DV_BT_DMT_1400X1050P85,
688 V4L2_DV_BT_DMT_1440X900P60_RB,
689 V4L2_DV_BT_DMT_1440X900P60,
690 V4L2_DV_BT_DMT_1600X1200P60,
691 V4L2_DV_BT_DMT_1680X1050P60_RB,
692 V4L2_DV_BT_DMT_1680X1050P60,
693 V4L2_DV_BT_DMT_1792X1344P60,
694 V4L2_DV_BT_DMT_1856X1392P60,
695 V4L2_DV_BT_DMT_1920X1200P60_RB,
696 V4L2_DV_BT_DMT_1366X768P60,
697 V4L2_DV_BT_DMT_1920X1080P60,
698 {},
699}; 650};
700 651
701static int ad9389b_s_dv_timings(struct v4l2_subdev *sd, 652static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
702 struct v4l2_dv_timings *timings) 653 struct v4l2_dv_timings *timings)
703{ 654{
704 struct ad9389b_state *state = get_ad9389b_state(sd); 655 struct ad9389b_state *state = get_ad9389b_state(sd);
705 int i;
706 656
707 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 657 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
708 658
709 /* quick sanity check */ 659 /* quick sanity check */
710 if (timings->type != V4L2_DV_BT_656_1120) 660 if (!v4l2_dv_valid_timings(timings, &ad9389b_timings_cap))
711 return -EINVAL;
712
713 if (timings->bt.interlaced)
714 return -EINVAL;
715 if (timings->bt.pixelclock < 27000000 ||
716 timings->bt.pixelclock > 170000000)
717 return -EINVAL; 661 return -EINVAL;
718 662
719 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 663 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
720 if the format is listed in ad9389b_timings[] */ 664 if the format is one of the CEA or DMT timings. */
721 for (i = 0; ad9389b_timings[i].bt.width; i++) { 665 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0);
722 if (v4l_match_dv_timings(timings, &ad9389b_timings[i], 0)) {
723 *timings = ad9389b_timings[i];
724 break;
725 }
726 }
727 666
728 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; 667 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
729 668
@@ -761,26 +700,13 @@ static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
761static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd, 700static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
762 struct v4l2_enum_dv_timings *timings) 701 struct v4l2_enum_dv_timings *timings)
763{ 702{
764 if (timings->index >= ARRAY_SIZE(ad9389b_timings)) 703 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap);
765 return -EINVAL;
766
767 memset(timings->reserved, 0, sizeof(timings->reserved));
768 timings->timings = ad9389b_timings[timings->index];
769 return 0;
770} 704}
771 705
772static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd, 706static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
773 struct v4l2_dv_timings_cap *cap) 707 struct v4l2_dv_timings_cap *cap)
774{ 708{
775 cap->type = V4L2_DV_BT_656_1120; 709 *cap = ad9389b_timings_cap;
776 cap->bt.max_width = 1920;
777 cap->bt.max_height = 1200;
778 cap->bt.min_pixelclock = 27000000;
779 cap->bt.max_pixelclock = 170000000;
780 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
781 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
782 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
783 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
784 return 0; 710 return 0;
785} 711}
786 712