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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-03-25 10:45:29 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-05-20 06:26:26 -0400
commit58d5eaec9f877a9bcfa9b6dca0ea51850975c49f (patch)
tree6c061a242bd99df311ee36a19d1cec10e073d316 /drivers/media/dvb
parent7fc7356f4eafa953197e1c4e2d236e199a51db28 (diff)
[media] drxd: Don't use a macro for CHK_ERROR with a break inside
The macro is defined as: #define CHK_ERROR(s) if( (status = s)<0 ) break This sucks, as makes harder to debug if something got wrong and there are more than one level of loops. Also, violates CodingStyle. Fixed by this simple perl script: while (<>) { $f.=$_; }; $f=~ s,\n\#define CHK_ERROR[^\n]+\n,\n,; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s,\n(\t+)CHK_ERROR\((.*)\)\;,\n\1status = \2;\n\1if (status < 0)\n\1\tbreak;,g; print $f; Plus a few manual adjustments Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/drxd_hard.c1075
1 files changed, 637 insertions, 438 deletions
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
index e4440af31cd2..df70e18fc9b6 100644
--- a/drivers/media/dvb/frontends/drxd_hard.c
+++ b/drivers/media/dvb/frontends/drxd_hard.c
@@ -38,7 +38,6 @@
38#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" 38#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
39#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" 39#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
40 40
41#define CHK_ERROR(s) if( (status = s)<0 ) break
42#define CHUNK_SIZE 48 41#define CHUNK_SIZE 48
43 42
44#define DRX_I2C_RMW 0x10 43#define DRX_I2C_RMW 0x10
@@ -376,24 +375,36 @@ static int InitCE(struct drxd_state *state)
376 enum app_env AppEnv = state->app_env_default; 375 enum app_env AppEnv = state->app_env_default;
377 376
378 do { 377 do {
379 CHK_ERROR(WriteTable(state, state->m_InitCE)); 378 status = WriteTable(state, state->m_InitCE);
379 if (status < 0)
380 break;
380 381
381 if (state->operation_mode == OM_DVBT_Diversity_Front || 382 if (state->operation_mode == OM_DVBT_Diversity_Front ||
382 state->operation_mode == OM_DVBT_Diversity_End) { 383 state->operation_mode == OM_DVBT_Diversity_End) {
383 AppEnv = state->app_env_diversity; 384 AppEnv = state->app_env_diversity;
384 } 385 }
385 if (AppEnv == APPENV_STATIC) { 386 if (AppEnv == APPENV_STATIC) {
386 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0000, 0)); 387 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
388 if (status < 0)
389 break;
387 } else if (AppEnv == APPENV_PORTABLE) { 390 } else if (AppEnv == APPENV_PORTABLE) {
388 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0001, 0)); 391 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
392 if (status < 0)
393 break;
389 } else if (AppEnv == APPENV_MOBILE && state->type_A) { 394 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
390 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0002, 0)); 395 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
396 if (status < 0)
397 break;
391 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { 398 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
392 CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0006, 0)); 399 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
400 if (status < 0)
401 break;
393 } 402 }
394 403
395 /* start ce */ 404 /* start ce */
396 CHK_ERROR(Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0)); 405 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
406 if (status < 0)
407 break;
397 } while (0); 408 } while (0);
398 return status; 409 return status;
399} 410}
@@ -408,46 +419,58 @@ static int StopOC(struct drxd_state *state)
408 419
409 do { 420 do {
410 /* Store output configuration */ 421 /* Store output configuration */
411 CHK_ERROR(Read16(state, EC_OC_REG_SNC_ISC_LVL__A, 422 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
412 &ocSyncLvl, 0));; 423 if (status < 0)
413 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, 424 break;;
414 &ocModeLop)); */ 425 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
415 state->m_EcOcRegSncSncLvl = ocSyncLvl; 426 state->m_EcOcRegSncSncLvl = ocSyncLvl;
416 /* m_EcOcRegOcModeLop = ocModeLop; */ 427 /* m_EcOcRegOcModeLop = ocModeLop; */
417 428
418 /* Flush FIFO (byte-boundary) at fixed rate */ 429 /* Flush FIFO (byte-boundary) at fixed rate */
419 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A, 430 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
420 &dtoIncLop, 0)); 431 if (status < 0)
421 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A, 432 break;
422 &dtoIncHip, 0)); 433 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
423 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A, 434 if (status < 0)
424 dtoIncLop, 0)); 435 break;
425 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A, 436 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
426 dtoIncHip, 0)); 437 if (status < 0)
438 break;
439 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
440 if (status < 0)
441 break;
427 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); 442 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
428 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; 443 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
429 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 444 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
430 ocModeLop, 0)); 445 if (status < 0)
431 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 446 break;
432 EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); 447 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
448 if (status < 0)
449 break;
433 450
434 msleep(1); 451 msleep(1);
435 /* Output pins to '0' */ 452 /* Output pins to '0' */
436 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, 453 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
437 EC_OC_REG_OCR_MPG_UOS__M, 0)); 454 if (status < 0)
455 break;
438 456
439 /* Force the OC out of sync */ 457 /* Force the OC out of sync */
440 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); 458 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
441 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, 459 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
442 ocSyncLvl, 0)); 460 if (status < 0)
461 break;
443 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); 462 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
444 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; 463 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
445 ocModeLop |= 0x2; /* Magically-out-of-sync */ 464 ocModeLop |= 0x2; /* Magically-out-of-sync */
446 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 465 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
447 ocModeLop, 0)); 466 if (status < 0)
448 CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0)); 467 break;
449 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 468 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
450 EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); 469 if (status < 0)
470 break;
471 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
472 if (status < 0)
473 break;
451 } while (0); 474 } while (0);
452 475
453 return status; 476 return status;
@@ -459,22 +482,27 @@ static int StartOC(struct drxd_state *state)
459 482
460 do { 483 do {
461 /* Stop OC */ 484 /* Stop OC */
462 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 485 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
463 EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); 486 if (status < 0)
487 break;
464 488
465 /* Restore output configuration */ 489 /* Restore output configuration */
466 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, 490 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
467 state->m_EcOcRegSncSncLvl, 0)); 491 if (status < 0)
468 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 492 break;
469 state->m_EcOcRegOcModeLop, 0)); 493 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
494 if (status < 0)
495 break;
470 496
471 /* Output pins active again */ 497 /* Output pins active again */
472 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, 498 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
473 EC_OC_REG_OCR_MPG_UOS_INIT, 0)); 499 if (status < 0)
500 break;
474 501
475 /* Start OC */ 502 /* Start OC */
476 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, 503 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
477 EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); 504 if (status < 0)
505 break;
478 } while (0); 506 } while (0);
479 return status; 507 return status;
480} 508}
@@ -551,17 +579,20 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
551 u16 FeAgRegPm1AgcWri; 579 u16 FeAgRegPm1AgcWri;
552 u16 FeAgRegAgModeLop; 580 u16 FeAgRegAgModeLop;
553 581
554 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, 582 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
555 &FeAgRegAgModeLop, 0)); 583 if (status < 0)
584 break;
556 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 585 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
557 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; 586 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
558 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, 587 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
559 FeAgRegAgModeLop, 0)); 588 if (status < 0)
589 break;
560 590
561 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & 591 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
562 FE_AG_REG_PM1_AGC_WRI__M); 592 FE_AG_REG_PM1_AGC_WRI__M);
563 CHK_ERROR(Write16(state, FE_AG_REG_PM1_AGC_WRI__A, 593 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
564 FeAgRegPm1AgcWri, 0)); 594 if (status < 0)
595 break;
565 } 596 }
566 while (0); 597 while (0);
567 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { 598 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
@@ -578,20 +609,23 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
578 609
579 /* == Mode == */ 610 /* == Mode == */
580 611
581 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, 612 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
582 &FeAgRegAgModeLop, 0)); 613 if (status < 0)
614 break;
583 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); 615 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
584 FeAgRegAgModeLop |= 616 FeAgRegAgModeLop |=
585 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; 617 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
586 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, 618 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
587 FeAgRegAgModeLop, 0)); 619 if (status < 0)
620 break;
588 621
589 /* == Settle level == */ 622 /* == Settle level == */
590 623
591 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & 624 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
592 FE_AG_REG_EGC_SET_LVL__M); 625 FE_AG_REG_EGC_SET_LVL__M);
593 CHK_ERROR(Write16(state, FE_AG_REG_EGC_SET_LVL__A, 626 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
594 FeAgRegEgcSetLvl, 0)); 627 if (status < 0)
628 break;
595 629
596 /* == Min/Max == */ 630 /* == Min/Max == */
597 631
@@ -600,10 +634,12 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
600 offset = (u16) ((cfg->maxOutputLevel + 634 offset = (u16) ((cfg->maxOutputLevel +
601 cfg->minOutputLevel) / 2 - 511); 635 cfg->minOutputLevel) / 2 - 511);
602 636
603 CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_RIC__A, 637 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
604 slope, 0)); 638 if (status < 0)
605 CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_OFF__A, 639 break;
606 offset, 0)); 640 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
641 if (status < 0)
642 break;
607 643
608 /* == Speed == */ 644 /* == Speed == */
609 { 645 {
@@ -649,21 +685,21 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
649 (fineSteps / 685 (fineSteps /
650 (3 + 1))]; 686 (3 + 1))];
651 687
652 CHK_ERROR(Write16(state, 688 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
653 FE_AG_REG_EGC_RUR_CNT__A, 689 if (status < 0)
654 rurCount, 0)); 690 break;
655 CHK_ERROR(Write16(state, 691 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
656 FE_AG_REG_EGC_FAS_INC__A, 692 if (status < 0)
657 fastIncrDec, 0)); 693 break;
658 CHK_ERROR(Write16(state, 694 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
659 FE_AG_REG_EGC_FAS_DEC__A, 695 if (status < 0)
660 fastIncrDec, 0)); 696 break;
661 CHK_ERROR(Write16(state, 697 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
662 FE_AG_REG_EGC_SLO_INC__A, 698 if (status < 0)
663 slowIncrDec, 0)); 699 break;
664 CHK_ERROR(Write16(state, 700 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
665 FE_AG_REG_EGC_SLO_DEC__A, 701 if (status < 0)
666 slowIncrDec, 0)); 702 break;
667 } 703 }
668 } 704 }
669 } while (0); 705 } while (0);
@@ -690,8 +726,9 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
690 if (level == DRXD_FE_CTRL_MAX) 726 if (level == DRXD_FE_CTRL_MAX)
691 level++; 727 level++;
692 728
693 CHK_ERROR(Write16(state, FE_AG_REG_PM2_AGC_WRI__A, 729 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
694 level, 0x0000)); 730 if (status < 0)
731 break;
695 732
696 /*==== Mode ====*/ 733 /*==== Mode ====*/
697 734
@@ -699,31 +736,34 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
699 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 736 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
700 state->m_FeAgRegAgPwd |= 737 state->m_FeAgRegAgPwd |=
701 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 738 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
702 CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, 739 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
703 state->m_FeAgRegAgPwd, 0x0000)); 740 if (status < 0)
741 break;
704 742
705 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, 743 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
706 &AgModeLop, 0x0000)); 744 if (status < 0)
745 break;
707 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 746 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
708 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 747 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
709 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 748 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
710 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 749 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
711 CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, 750 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
712 AgModeLop, 0x0000)); 751 if (status < 0)
752 break;
713 753
714 /* enable AGC2 pin */ 754 /* enable AGC2 pin */
715 { 755 {
716 u16 FeAgRegAgAgcSio = 0; 756 u16 FeAgRegAgAgcSio = 0;
717 CHK_ERROR(Read16(state, 757 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
718 FE_AG_REG_AG_AGC_SIO__A, 758 if (status < 0)
719 &FeAgRegAgAgcSio, 0x0000)); 759 break;
720 FeAgRegAgAgcSio &= 760 FeAgRegAgAgcSio &=
721 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 761 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
722 FeAgRegAgAgcSio |= 762 FeAgRegAgAgcSio |=
723 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 763 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
724 CHK_ERROR(Write16(state, 764 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
725 FE_AG_REG_AG_AGC_SIO__A, 765 if (status < 0)
726 FeAgRegAgAgcSio, 0x0000)); 766 break;
727 } 767 }
728 768
729 } while (0); 769 } while (0);
@@ -738,24 +778,26 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
738 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 778 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
739 (state->m_FeAgRegAgPwd) |= 779 (state->m_FeAgRegAgPwd) |=
740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; 780 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
741 CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, 781 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
742 (state->m_FeAgRegAgPwd), 0x0000)); 782 if (status < 0)
783 break;
743 784
744 CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, 785 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
745 &AgModeLop, 0x0000)); 786 if (status < 0)
787 break;
746 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 788 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
747 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 789 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
748 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 790 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
749 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); 791 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
750 CHK_ERROR(Write16(state, 792 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
751 FE_AG_REG_AG_MODE_LOP__A, 793 if (status < 0)
752 AgModeLop, 0x0000)); 794 break;
753 /* Settle level */ 795 /* Settle level */
754 level = (((cfg->settleLevel) >> 4) & 796 level = (((cfg->settleLevel) >> 4) &
755 FE_AG_REG_TGC_SET_LVL__M); 797 FE_AG_REG_TGC_SET_LVL__M);
756 CHK_ERROR(Write16(state, 798 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
757 FE_AG_REG_TGC_SET_LVL__A, 799 if (status < 0)
758 level, 0x0000)); 800 break;
759 801
760 /* Min/max: don't care */ 802 /* Min/max: don't care */
761 803
@@ -764,16 +806,16 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
764 /* enable AGC2 pin */ 806 /* enable AGC2 pin */
765 { 807 {
766 u16 FeAgRegAgAgcSio = 0; 808 u16 FeAgRegAgAgcSio = 0;
767 CHK_ERROR(Read16(state, 809 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
768 FE_AG_REG_AG_AGC_SIO__A, 810 if (status < 0)
769 &FeAgRegAgAgcSio, 0x0000)); 811 break;
770 FeAgRegAgAgcSio &= 812 FeAgRegAgAgcSio &=
771 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 813 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
772 FeAgRegAgAgcSio |= 814 FeAgRegAgAgcSio |=
773 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; 815 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
774 CHK_ERROR(Write16(state, 816 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
775 FE_AG_REG_AG_AGC_SIO__A, 817 if (status < 0)
776 FeAgRegAgAgcSio, 0x0000)); 818 break;
777 } 819 }
778 820
779 } while (0); 821 } while (0);
@@ -787,34 +829,34 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
787 ~(FE_AG_REG_AG_PWD_PWD_PD2__M); 829 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
788 (state->m_FeAgRegAgPwd) |= 830 (state->m_FeAgRegAgPwd) |=
789 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; 831 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
790 CHK_ERROR(Write16(state, 832 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
791 FE_AG_REG_AG_PWD__A, 833 if (status < 0)
792 (state->m_FeAgRegAgPwd), 0x0000)); 834 break;
793 835
794 CHK_ERROR(Read16(state, 836 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
795 FE_AG_REG_AG_MODE_LOP__A, 837 if (status < 0)
796 &AgModeLop, 0x0000)); 838 break;
797 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | 839 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
798 FE_AG_REG_AG_MODE_LOP_MODE_E__M)); 840 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
799 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | 841 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
800 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); 842 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
801 CHK_ERROR(Write16(state, 843 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
802 FE_AG_REG_AG_MODE_LOP__A, 844 if (status < 0)
803 AgModeLop, 0x0000)); 845 break;
804 846
805 /* set FeAgRegAgAgcSio AGC2 (RF) as input */ 847 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
806 { 848 {
807 u16 FeAgRegAgAgcSio = 0; 849 u16 FeAgRegAgAgcSio = 0;
808 CHK_ERROR(Read16(state, 850 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
809 FE_AG_REG_AG_AGC_SIO__A, 851 if (status < 0)
810 &FeAgRegAgAgcSio, 0x0000)); 852 break;
811 FeAgRegAgAgcSio &= 853 FeAgRegAgAgcSio &=
812 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); 854 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
813 FeAgRegAgAgcSio |= 855 FeAgRegAgAgcSio |=
814 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; 856 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
815 CHK_ERROR(Write16(state, 857 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
816 FE_AG_REG_AG_AGC_SIO__A, 858 if (status < 0)
817 FeAgRegAgAgcSio, 0x0000)); 859 break;
818 } 860 }
819 } while (0); 861 } while (0);
820 } 862 }
@@ -1025,18 +1067,25 @@ static int AtomicReadBlock(struct drxd_state *state,
1025 do { 1067 do {
1026 /* Instruct HI to read n bytes */ 1068 /* Instruct HI to read n bytes */
1027 /* TODO use proper names forthese egisters */ 1069 /* TODO use proper names forthese egisters */
1028 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, 1070 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1029 (HI_TR_FUNC_ADDR & 0xFFFF), 0)); 1071 if (status < 0)
1030 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, 1072 break;
1031 (u16) (Addr >> 16), 0)); 1073 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1032 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, 1074 if (status < 0)
1033 (u16) (Addr & 0xFFFF), 0)); 1075 break;
1034 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, 1076 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1035 (u16) ((DataSize / 2) - 1), 0)); 1077 if (status < 0)
1036 CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, 1078 break;
1037 HI_TR_READ, 0)); 1079 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1038 1080 if (status < 0)
1039 CHK_ERROR(HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0)); 1081 break;
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1083 if (status < 0)
1084 break;
1085
1086 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1087 if (status < 0)
1088 break;
1040 1089
1041 } while (0); 1090 } while (0);
1042 1091
@@ -1137,50 +1186,58 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1137 if (pgaSwitch) { 1186 if (pgaSwitch) {
1138 /* PGA on */ 1187 /* PGA on */
1139 /* fine gain */ 1188 /* fine gain */
1140 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1189 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1141 &AgModeLop, 0x0000)); 1190 if (status < 0)
1191 break;
1142 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1192 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1143 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; 1193 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1144 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1194 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1145 AgModeLop, 0x0000)); 1195 if (status < 0)
1196 break;
1146 1197
1147 /* coarse gain */ 1198 /* coarse gain */
1148 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1199 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1149 &AgModeHip, 0x0000)); 1200 if (status < 0)
1201 break;
1150 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1202 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1151 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; 1203 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1152 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1204 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1153 AgModeHip, 0x0000)); 1205 if (status < 0)
1206 break;
1154 1207
1155 /* enable fine and coarse gain, enable AAF, 1208 /* enable fine and coarse gain, enable AAF,
1156 no ext resistor */ 1209 no ext resistor */
1157 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1210 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1158 B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 1211 if (status < 0)
1159 0x0000)); 1212 break;
1160 } else { 1213 } else {
1161 /* PGA off, bypass */ 1214 /* PGA off, bypass */
1162 1215
1163 /* fine gain */ 1216 /* fine gain */
1164 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1217 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1165 &AgModeLop, 0x0000)); 1218 if (status < 0)
1219 break;
1166 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); 1220 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1167 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; 1221 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1168 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, 1222 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1169 AgModeLop, 0x0000)); 1223 if (status < 0)
1224 break;
1170 1225
1171 /* coarse gain */ 1226 /* coarse gain */
1172 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1227 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1173 &AgModeHip, 0x0000)); 1228 if (status < 0)
1229 break;
1174 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); 1230 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1175 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; 1231 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1176 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, 1232 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1177 AgModeHip, 0x0000)); 1233 if (status < 0)
1234 break;
1178 1235
1179 /* disable fine and coarse gain, enable AAF, 1236 /* disable fine and coarse gain, enable AAF,
1180 no ext resistor */ 1237 no ext resistor */
1181 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, 1238 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1182 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 1239 if (status < 0)
1183 0x0000)); 1240 break;
1184 } 1241 }
1185 } 1242 }
1186 while (0); 1243 while (0);
@@ -1192,7 +1249,9 @@ static int InitFE(struct drxd_state *state)
1192 int status; 1249 int status;
1193 1250
1194 do { 1251 do {
1195 CHK_ERROR(WriteTable(state, state->m_InitFE_1)); 1252 status = WriteTable(state, state->m_InitFE_1);
1253 if (status < 0)
1254 break;
1196 1255
1197 if (state->type_A) { 1256 if (state->type_A) {
1198 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, 1257 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
@@ -1210,13 +1269,16 @@ static int InitFE(struct drxd_state *state)
1210 1269
1211 if (status < 0) 1270 if (status < 0)
1212 break; 1271 break;
1213 CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A, 1272 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1214 state->m_FeAgRegAgAgcSio, 0x0000)); 1273 if (status < 0)
1215 CHK_ERROR(Write16 1274 break;
1216 (state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 1275 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1217 0x0000)); 1276 if (status < 0)
1277 break;
1218 1278
1219 CHK_ERROR(WriteTable(state, state->m_InitFE_2)); 1279 status = WriteTable(state, state->m_InitFE_2);
1280 if (status < 0)
1281 break;
1220 1282
1221 } while (0); 1283 } while (0);
1222 1284
@@ -1294,12 +1356,22 @@ static int SC_SetPrefParamCommand(struct drxd_state *state,
1294 1356
1295 down(&state->mutex); 1357 down(&state->mutex);
1296 do { 1358 do {
1297 CHK_ERROR(SC_WaitForReady(state)); 1359 status = SC_WaitForReady(state);
1298 CHK_ERROR(Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0)); 1360 if (status < 0)
1299 CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0)); 1361 break;
1300 CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0)); 1362 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1363 if (status < 0)
1364 break;
1365 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1366 if (status < 0)
1367 break;
1368 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1369 if (status < 0)
1370 break;
1301 1371
1302 CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM)); 1372 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1373 if (status < 0)
1374 break;
1303 } while (0); 1375 } while (0);
1304 up(&state->mutex); 1376 up(&state->mutex);
1305 return status; 1377 return status;
@@ -1312,9 +1384,15 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1312 1384
1313 down(&state->mutex); 1385 down(&state->mutex);
1314 do { 1386 do {
1315 CHK_ERROR(SC_WaitForReady(state)); 1387 status = SC_WaitForReady(state);
1316 CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM)); 1388 if (status < 0)
1317 CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0)); 1389 break;
1390 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1391 if (status < 0)
1392 break;
1393 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1394 if (status < 0)
1395 break;
1318 } while (0); 1396 } while (0);
1319 up(&state->mutex); 1397 up(&state->mutex);
1320 return status; 1398 return status;
@@ -1331,8 +1409,7 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1331 u16 EcOcRegOcModeHip = 0; 1409 u16 EcOcRegOcModeHip = 0;
1332 u16 EcOcRegOcMpgSio = 0; 1410 u16 EcOcRegOcMpgSio = 0;
1333 1411
1334 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, 1412 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1335 &EcOcRegOcModeLop, 0)); */
1336 1413
1337 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1414 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1338 if (bEnableOutput) { 1415 if (bEnableOutput) {
@@ -1396,14 +1473,18 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1396 EcOcRegIprInvMpg &= (~(0x0800)); 1473 EcOcRegIprInvMpg &= (~(0x0800));
1397 1474
1398 /* EcOcRegOcModeLop =0x05; */ 1475 /* EcOcRegOcModeLop =0x05; */
1399 CHK_ERROR(Write16(state, EC_OC_REG_IPR_INV_MPG__A, 1476 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1400 EcOcRegIprInvMpg, 0)); 1477 if (status < 0)
1401 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, 1478 break;
1402 EcOcRegOcModeLop, 0)); 1479 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1403 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_HIP__A, 1480 if (status < 0)
1404 EcOcRegOcModeHip, 0x0000)); 1481 break;
1405 CHK_ERROR(Write16(state, EC_OC_REG_OC_MPG_SIO__A, 1482 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1406 EcOcRegOcMpgSio, 0)); 1483 if (status < 0)
1484 break;
1485 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1486 if (status < 0)
1487 break;
1407 } while (0); 1488 } while (0);
1408 return status; 1489 return status;
1409} 1490}
@@ -1414,9 +1495,13 @@ static int SetDeviceTypeId(struct drxd_state *state)
1414 u16 deviceId = 0; 1495 u16 deviceId = 0;
1415 1496
1416 do { 1497 do {
1417 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); 1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1499 if (status < 0)
1500 break;
1418 /* TODO: why twice? */ 1501 /* TODO: why twice? */
1419 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); 1502 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1503 if (status < 0)
1504 break;
1420 printk("drxd: deviceId = %04x\n", deviceId); 1505 printk("drxd: deviceId = %04x\n", deviceId);
1421 1506
1422 state->type_A = 0; 1507 state->type_A = 0;
@@ -1512,9 +1597,12 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
1512 1597
1513 /* These accesses should be AtomicReadReg32, but that 1598 /* These accesses should be AtomicReadReg32, but that
1514 causes trouble (at least for diversity */ 1599 causes trouble (at least for diversity */
1515 CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, 1600 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) & nomincr), 0);
1516 ((u32 *) & nomincr), 0)); 1601 if (status < 0)
1517 CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0)); 1602 break;
1603 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0);
1604 if (status < 0)
1605 break;
1518 1606
1519 if (state->type_A) { 1607 if (state->type_A) {
1520 if ((nomincr - incr < -500) || (nomincr - incr > 500)) 1608 if ((nomincr - incr < -500) || (nomincr - incr > 500))
@@ -1571,13 +1659,14 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
1571 } 1659 }
1572 } 1660 }
1573 /* switch OFF SRMM scan in SC */ 1661 /* switch OFF SRMM scan in SC */
1574 CHK_ERROR(Write16(state, 1662 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1575 SC_RA_RAM_SAMPLE_RATE_COUNT__A, 1663 if (status < 0)
1576 DRXD_OSCDEV_DONT_SCAN, 0)); 1664 break;
1577 /* overrule FE_IF internal value for 1665 /* overrule FE_IF internal value for
1578 proper re-locking */ 1666 proper re-locking */
1579 CHK_ERROR(Write16(state, SC_RA_RAM_IF_SAVE__AX, 1667 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1580 state->current_fe_if_incr, 0)); 1668 if (status < 0)
1669 break;
1581 state->cscd_state = CSCD_SAVED; 1670 state->cscd_state = CSCD_SAVED;
1582 } 1671 }
1583 } while (0); 1672 } while (0);
@@ -1595,46 +1684,56 @@ static int DRX_Stop(struct drxd_state *state)
1595 do { 1684 do {
1596 if (state->cscd_state != CSCD_SAVED) { 1685 if (state->cscd_state != CSCD_SAVED) {
1597 u32 lock; 1686 u32 lock;
1598 CHK_ERROR(DRX_GetLockStatus(state, &lock)); 1687 status = DRX_GetLockStatus(state, &lock);
1688 if (status < 0)
1689 break;
1599 } 1690 }
1600 1691
1601 CHK_ERROR(StopOC(state)); 1692 status = StopOC(state);
1693 if (status < 0)
1694 break;
1602 1695
1603 state->drxd_state = DRXD_STOPPED; 1696 state->drxd_state = DRXD_STOPPED;
1604 1697
1605 CHK_ERROR(ConfigureMPEGOutput(state, 0)); 1698 status = ConfigureMPEGOutput(state, 0);
1699 if (status < 0)
1700 break;
1606 1701
1607 if (state->type_A) { 1702 if (state->type_A) {
1608 /* Stop relevant processors off the device */ 1703 /* Stop relevant processors off the device */
1609 CHK_ERROR(Write16(state, EC_OD_REG_COMM_EXEC__A, 1704 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1610 0x0000, 0x0000)); 1705 if (status < 0)
1706 break;
1611 1707
1612 CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 1708 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1613 SC_COMM_EXEC_CTL_STOP, 0)); 1709 if (status < 0)
1614 CHK_ERROR(Write16(state, LC_COMM_EXEC__A, 1710 break;
1615 SC_COMM_EXEC_CTL_STOP, 0)); 1711 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1712 if (status < 0)
1713 break;
1616 } else { 1714 } else {
1617 /* Stop all processors except HI & CC & FE */ 1715 /* Stop all processors except HI & CC & FE */
1618 CHK_ERROR(Write16(state, 1716 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1619 B_SC_COMM_EXEC__A, 1717 if (status < 0)
1620 SC_COMM_EXEC_CTL_STOP, 0)); 1718 break;
1621 CHK_ERROR(Write16(state, 1719 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1622 B_LC_COMM_EXEC__A, 1720 if (status < 0)
1623 SC_COMM_EXEC_CTL_STOP, 0)); 1721 break;
1624 CHK_ERROR(Write16(state, 1722 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1625 B_FT_COMM_EXEC__A, 1723 if (status < 0)
1626 SC_COMM_EXEC_CTL_STOP, 0)); 1724 break;
1627 CHK_ERROR(Write16(state, 1725 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1628 B_CP_COMM_EXEC__A, 1726 if (status < 0)
1629 SC_COMM_EXEC_CTL_STOP, 0)); 1727 break;
1630 CHK_ERROR(Write16(state, 1728 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1631 B_CE_COMM_EXEC__A, 1729 if (status < 0)
1632 SC_COMM_EXEC_CTL_STOP, 0)); 1730 break;
1633 CHK_ERROR(Write16(state, 1731 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1634 B_EQ_COMM_EXEC__A, 1732 if (status < 0)
1635 SC_COMM_EXEC_CTL_STOP, 0)); 1733 break;
1636 CHK_ERROR(Write16(state, 1734 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1637 EC_OD_REG_COMM_EXEC__A, 0x0000, 0)); 1735 if (status < 0)
1736 break;
1638 } 1737 }
1639 1738
1640 } while (0); 1739 } while (0);
@@ -1689,33 +1788,35 @@ static int StartDiversity(struct drxd_state *state)
1689 1788
1690 do { 1789 do {
1691 if (state->operation_mode == OM_DVBT_Diversity_Front) { 1790 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1692 CHK_ERROR(WriteTable(state, 1791 status = WriteTable(state, state->m_StartDiversityFront);
1693 state->m_StartDiversityFront)); 1792 if (status < 0)
1793 break;
1694 } else if (state->operation_mode == OM_DVBT_Diversity_End) { 1794 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1695 CHK_ERROR(WriteTable(state, 1795 status = WriteTable(state, state->m_StartDiversityEnd);
1696 state->m_StartDiversityEnd)); 1796 if (status < 0)
1797 break;
1697 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { 1798 if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1698 CHK_ERROR(WriteTable(state, 1799 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1699 state-> 1800 if (status < 0)
1700 m_DiversityDelay8MHZ)); 1801 break;
1701 } else { 1802 } else {
1702 CHK_ERROR(WriteTable(state, 1803 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1703 state-> 1804 if (status < 0)
1704 m_DiversityDelay6MHZ)); 1805 break;
1705 } 1806 }
1706 1807
1707 CHK_ERROR(Read16(state, 1808 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1708 B_EQ_REG_RC_SEL_CAR__A, 1809 if (status < 0)
1709 &rcControl, 0)); 1810 break;
1710 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); 1811 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1711 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | 1812 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1712 /* combining enabled */ 1813 /* combining enabled */
1713 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | 1814 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1714 B_EQ_REG_RC_SEL_CAR_PASS_A_CC | 1815 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1715 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; 1816 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1716 CHK_ERROR(Write16(state, 1817 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1717 B_EQ_REG_RC_SEL_CAR__A, 1818 if (status < 0)
1718 rcControl, 0)); 1819 break;
1719 } 1820 }
1720 } while (0); 1821 } while (0);
1721 return status; 1822 return status;
@@ -1767,23 +1868,28 @@ static int SetCfgNoiseCalibration(struct drxd_state *state,
1767 int status = 0; 1868 int status = 0;
1768 1869
1769 do { 1870 do {
1770 CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0)); 1871 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1872 if (status < 0)
1873 break;
1771 if (noiseCal->cpOpt) { 1874 if (noiseCal->cpOpt) {
1772 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1875 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1773 } else { 1876 } else {
1774 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); 1877 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1775 CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, 1878 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1776 noiseCal->cpNexpOfs, 0)); 1879 if (status < 0)
1880 break;
1777 } 1881 }
1778 CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0)); 1882 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1883 if (status < 0)
1884 break;
1779 1885
1780 if (!state->type_A) { 1886 if (!state->type_A) {
1781 CHK_ERROR(Write16(state, 1887 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1782 B_SC_RA_RAM_CO_TD_CAL_2K__A, 1888 if (status < 0)
1783 noiseCal->tdCal2k, 0)); 1889 break;
1784 CHK_ERROR(Write16(state, 1890 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1785 B_SC_RA_RAM_CO_TD_CAL_8K__A, 1891 if (status < 0)
1786 noiseCal->tdCal8k, 0)); 1892 break;
1787 } 1893 }
1788 } while (0); 1894 } while (0);
1789 1895
@@ -1823,21 +1929,39 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1823 do { 1929 do {
1824 if (state->drxd_state != DRXD_STOPPED) 1930 if (state->drxd_state != DRXD_STOPPED)
1825 return -1; 1931 return -1;
1826 CHK_ERROR(ResetECOD(state)); 1932 status = ResetECOD(state);
1933 if (status < 0)
1934 break;
1827 if (state->type_A) { 1935 if (state->type_A) {
1828 CHK_ERROR(InitSC(state)); 1936 status = InitSC(state);
1937 if (status < 0)
1938 break;
1829 } else { 1939 } else {
1830 CHK_ERROR(InitFT(state)); 1940 status = InitFT(state);
1831 CHK_ERROR(InitCP(state)); 1941 if (status < 0)
1832 CHK_ERROR(InitCE(state)); 1942 break;
1833 CHK_ERROR(InitEQ(state)); 1943 status = InitCP(state);
1834 CHK_ERROR(InitSC(state)); 1944 if (status < 0)
1945 break;
1946 status = InitCE(state);
1947 if (status < 0)
1948 break;
1949 status = InitEQ(state);
1950 if (status < 0)
1951 break;
1952 status = InitSC(state);
1953 if (status < 0)
1954 break;
1835 } 1955 }
1836 1956
1837 /* Restore current IF & RF AGC settings */ 1957 /* Restore current IF & RF AGC settings */
1838 1958
1839 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); 1959 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1840 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); 1960 if (status < 0)
1961 break;
1962 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1963 if (status < 0)
1964 break;
1841 1965
1842 mirrorFreqSpect = (state->param.inversion == INVERSION_ON); 1966 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1843 1967
@@ -1848,10 +1972,9 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1848 case TRANSMISSION_MODE_8K: 1972 case TRANSMISSION_MODE_8K:
1849 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; 1973 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1850 if (state->type_A) { 1974 if (state->type_A) {
1851 CHK_ERROR(Write16(state, 1975 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1852 EC_SB_REG_TR_MODE__A, 1976 if (status < 0)
1853 EC_SB_REG_TR_MODE_8K, 1977 break;
1854 0x0000));
1855 qpskSnCeGain = 99; 1978 qpskSnCeGain = 99;
1856 qam16SnCeGain = 83; 1979 qam16SnCeGain = 83;
1857 qam64SnCeGain = 67; 1980 qam64SnCeGain = 67;
@@ -1860,10 +1983,9 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1860 case TRANSMISSION_MODE_2K: 1983 case TRANSMISSION_MODE_2K:
1861 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; 1984 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1862 if (state->type_A) { 1985 if (state->type_A) {
1863 CHK_ERROR(Write16(state, 1986 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1864 EC_SB_REG_TR_MODE__A, 1987 if (status < 0)
1865 EC_SB_REG_TR_MODE_2K, 1988 break;
1866 0x0000));
1867 qpskSnCeGain = 97; 1989 qpskSnCeGain = 97;
1868 qam16SnCeGain = 71; 1990 qam16SnCeGain = 71;
1869 qam64SnCeGain = 65; 1991 qam64SnCeGain = 65;
@@ -1895,10 +2017,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1895 case HIERARCHY_1: 2017 case HIERARCHY_1:
1896 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; 2018 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
1897 if (state->type_A) { 2019 if (state->type_A) {
1898 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, 2020 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
1899 0x0001, 0x0000)); 2021 if (status < 0)
1900 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, 2022 break;
1901 0x0001, 0x0000)); 2023 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2024 if (status < 0)
2025 break;
1902 2026
1903 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2027 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1904 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; 2028 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
@@ -1923,10 +2047,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1923 case HIERARCHY_2: 2047 case HIERARCHY_2:
1924 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; 2048 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
1925 if (state->type_A) { 2049 if (state->type_A) {
1926 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, 2050 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
1927 0x0002, 0x0000)); 2051 if (status < 0)
1928 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, 2052 break;
1929 0x0002, 0x0000)); 2053 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2054 if (status < 0)
2055 break;
1930 2056
1931 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2057 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1932 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; 2058 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
@@ -1950,10 +2076,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1950 case HIERARCHY_4: 2076 case HIERARCHY_4:
1951 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; 2077 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
1952 if (state->type_A) { 2078 if (state->type_A) {
1953 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, 2079 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
1954 0x0003, 0x0000)); 2080 if (status < 0)
1955 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, 2081 break;
1956 0x0003, 0x0000)); 2082 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2083 if (status < 0)
2084 break;
1957 2085
1958 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; 2086 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1959 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; 2087 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
@@ -1980,10 +2108,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
1980 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; 2108 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
1981 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; 2109 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
1982 if (state->type_A) { 2110 if (state->type_A) {
1983 CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, 2111 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
1984 0x0000, 0x0000)); 2112 if (status < 0)
1985 CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, 2113 break;
1986 0x0000, 0x0000)); 2114 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2115 if (status < 0)
2116 break;
1987 2117
1988 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; 2118 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
1989 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; 2119 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
@@ -2005,7 +2135,9 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2005 } 2135 }
2006 break; 2136 break;
2007 } 2137 }
2008 CHK_ERROR(status); 2138 status = status;
2139 if (status < 0)
2140 break;
2009 2141
2010 switch (p->constellation) { 2142 switch (p->constellation) {
2011 default: 2143 default:
@@ -2015,111 +2147,123 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2015 case QAM_64: 2147 case QAM_64:
2016 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; 2148 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2017 if (state->type_A) { 2149 if (state->type_A) {
2018 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2150 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2019 0x0002, 0x0000)); 2151 if (status < 0)
2020 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2152 break;
2021 EC_SB_REG_CONST_64QAM, 2153 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2022 0x0000)); 2154 if (status < 0)
2023 CHK_ERROR(Write16(state, 2155 break;
2024 EC_SB_REG_SCALE_MSB__A, 2156 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2025 0x0020, 0x0000)); 2157 if (status < 0)
2026 CHK_ERROR(Write16(state, 2158 break;
2027 EC_SB_REG_SCALE_BIT2__A, 2159 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2028 0x0008, 0x0000)); 2160 if (status < 0)
2029 CHK_ERROR(Write16(state, 2161 break;
2030 EC_SB_REG_SCALE_LSB__A, 2162 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2031 0x0002, 0x0000)); 2163 if (status < 0)
2032 2164 break;
2033 CHK_ERROR(Write16(state, 2165
2034 EQ_REG_TD_TPS_PWR_OFS__A, 2166 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2035 qam64TdTpsPwr, 0x0000)); 2167 if (status < 0)
2036 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, 2168 break;
2037 qam64SnCeGain, 0x0000)); 2169 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2038 CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_MAN__A, 2170 if (status < 0)
2039 qam64IsGainMan, 0x0000)); 2171 break;
2040 CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_EXP__A, 2172 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2041 qam64IsGainExp, 0x0000)); 2173 if (status < 0)
2174 break;
2175 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2176 if (status < 0)
2177 break;
2042 } 2178 }
2043 break; 2179 break;
2044 case QPSK: 2180 case QPSK:
2045 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; 2181 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2046 if (state->type_A) { 2182 if (state->type_A) {
2047 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2183 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2048 0x0000, 0x0000)); 2184 if (status < 0)
2049 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2185 break;
2050 EC_SB_REG_CONST_QPSK, 2186 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2051 0x0000)); 2187 if (status < 0)
2052 CHK_ERROR(Write16(state, 2188 break;
2053 EC_SB_REG_SCALE_MSB__A, 2189 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2054 0x0010, 0x0000)); 2190 if (status < 0)
2055 CHK_ERROR(Write16(state, 2191 break;
2056 EC_SB_REG_SCALE_BIT2__A, 2192 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2057 0x0000, 0x0000)); 2193 if (status < 0)
2058 CHK_ERROR(Write16(state, 2194 break;
2059 EC_SB_REG_SCALE_LSB__A, 2195 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2060 0x0000, 0x0000)); 2196 if (status < 0)
2061 2197 break;
2062 CHK_ERROR(Write16(state, 2198
2063 EQ_REG_TD_TPS_PWR_OFS__A, 2199 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2064 qpskTdTpsPwr, 0x0000)); 2200 if (status < 0)
2065 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, 2201 break;
2066 qpskSnCeGain, 0x0000)); 2202 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2067 CHK_ERROR(Write16(state, 2203 if (status < 0)
2068 EQ_REG_IS_GAIN_MAN__A, 2204 break;
2069 qpskIsGainMan, 0x0000)); 2205 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2070 CHK_ERROR(Write16(state, 2206 if (status < 0)
2071 EQ_REG_IS_GAIN_EXP__A, 2207 break;
2072 qpskIsGainExp, 0x0000)); 2208 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2209 if (status < 0)
2210 break;
2073 } 2211 }
2074 break; 2212 break;
2075 2213
2076 case QAM_16: 2214 case QAM_16:
2077 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; 2215 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2078 if (state->type_A) { 2216 if (state->type_A) {
2079 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, 2217 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2080 0x0001, 0x0000)); 2218 if (status < 0)
2081 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, 2219 break;
2082 EC_SB_REG_CONST_16QAM, 2220 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2083 0x0000)); 2221 if (status < 0)
2084 CHK_ERROR(Write16(state, 2222 break;
2085 EC_SB_REG_SCALE_MSB__A, 2223 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2086 0x0010, 0x0000)); 2224 if (status < 0)
2087 CHK_ERROR(Write16(state, 2225 break;
2088 EC_SB_REG_SCALE_BIT2__A, 2226 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2089 0x0004, 0x0000)); 2227 if (status < 0)
2090 CHK_ERROR(Write16(state, 2228 break;
2091 EC_SB_REG_SCALE_LSB__A, 2229 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2092 0x0000, 0x0000)); 2230 if (status < 0)
2093 2231 break;
2094 CHK_ERROR(Write16(state, 2232
2095 EQ_REG_TD_TPS_PWR_OFS__A, 2233 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2096 qam16TdTpsPwr, 0x0000)); 2234 if (status < 0)
2097 CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, 2235 break;
2098 qam16SnCeGain, 0x0000)); 2236 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2099 CHK_ERROR(Write16(state, 2237 if (status < 0)
2100 EQ_REG_IS_GAIN_MAN__A, 2238 break;
2101 qam16IsGainMan, 0x0000)); 2239 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2102 CHK_ERROR(Write16(state, 2240 if (status < 0)
2103 EQ_REG_IS_GAIN_EXP__A, 2241 break;
2104 qam16IsGainExp, 0x0000)); 2242 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2243 if (status < 0)
2244 break;
2105 } 2245 }
2106 break; 2246 break;
2107 2247
2108 } 2248 }
2109 CHK_ERROR(status); 2249 status = status;
2250 if (status < 0)
2251 break;
2110 2252
2111 switch (DRX_CHANNEL_HIGH) { 2253 switch (DRX_CHANNEL_HIGH) {
2112 default: 2254 default:
2113 case DRX_CHANNEL_AUTO: 2255 case DRX_CHANNEL_AUTO:
2114 case DRX_CHANNEL_LOW: 2256 case DRX_CHANNEL_LOW:
2115 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; 2257 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2116 CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, 2258 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2117 EC_SB_REG_PRIOR_LO, 0x0000)); 2259 if (status < 0)
2260 break;
2118 break; 2261 break;
2119 case DRX_CHANNEL_HIGH: 2262 case DRX_CHANNEL_HIGH:
2120 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; 2263 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2121 CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, 2264 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2122 EC_SB_REG_PRIOR_HI, 0x0000)); 2265 if (status < 0)
2266 break;
2123 break; 2267 break;
2124 2268
2125 } 2269 }
@@ -2128,10 +2272,9 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2128 case FEC_1_2: 2272 case FEC_1_2:
2129 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; 2273 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2130 if (state->type_A) { 2274 if (state->type_A) {
2131 CHK_ERROR(Write16(state, 2275 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2132 EC_VD_REG_SET_CODERATE__A, 2276 if (status < 0)
2133 EC_VD_REG_SET_CODERATE_C1_2, 2277 break;
2134 0x0000));
2135 } 2278 }
2136 break; 2279 break;
2137 default: 2280 default:
@@ -2139,41 +2282,39 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2139 case FEC_2_3: 2282 case FEC_2_3:
2140 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; 2283 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2141 if (state->type_A) { 2284 if (state->type_A) {
2142 CHK_ERROR(Write16(state, 2285 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2143 EC_VD_REG_SET_CODERATE__A, 2286 if (status < 0)
2144 EC_VD_REG_SET_CODERATE_C2_3, 2287 break;
2145 0x0000));
2146 } 2288 }
2147 break; 2289 break;
2148 case FEC_3_4: 2290 case FEC_3_4:
2149 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; 2291 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2150 if (state->type_A) { 2292 if (state->type_A) {
2151 CHK_ERROR(Write16(state, 2293 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2152 EC_VD_REG_SET_CODERATE__A, 2294 if (status < 0)
2153 EC_VD_REG_SET_CODERATE_C3_4, 2295 break;
2154 0x0000));
2155 } 2296 }
2156 break; 2297 break;
2157 case FEC_5_6: 2298 case FEC_5_6:
2158 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; 2299 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2159 if (state->type_A) { 2300 if (state->type_A) {
2160 CHK_ERROR(Write16(state, 2301 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2161 EC_VD_REG_SET_CODERATE__A, 2302 if (status < 0)
2162 EC_VD_REG_SET_CODERATE_C5_6, 2303 break;
2163 0x0000));
2164 } 2304 }
2165 break; 2305 break;
2166 case FEC_7_8: 2306 case FEC_7_8:
2167 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; 2307 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2168 if (state->type_A) { 2308 if (state->type_A) {
2169 CHK_ERROR(Write16(state, 2309 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2170 EC_VD_REG_SET_CODERATE__A, 2310 if (status < 0)
2171 EC_VD_REG_SET_CODERATE_C7_8, 2311 break;
2172 0x0000));
2173 } 2312 }
2174 break; 2313 break;
2175 } 2314 }
2176 CHK_ERROR(status); 2315 status = status;
2316 if (status < 0)
2317 break;
2177 2318
2178 /* First determine real bandwidth (Hz) */ 2319 /* First determine real bandwidth (Hz) */
2179 /* Also set delay for impulse noise cruncher (only A2) */ 2320 /* Also set delay for impulse noise cruncher (only A2) */
@@ -2207,15 +2348,19 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2207 FE_AG_REG_IND_DEL__A, 71, 0x0000); 2348 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2208 break; 2349 break;
2209 } 2350 }
2210 CHK_ERROR(status); 2351 status = status;
2352 if (status < 0)
2353 break;
2211 2354
2212 CHK_ERROR(Write16(state, 2355 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2213 SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); 2356 if (status < 0)
2357 break;
2214 2358
2215 { 2359 {
2216 u16 sc_config; 2360 u16 sc_config;
2217 CHK_ERROR(Read16(state, 2361 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2218 SC_RA_RAM_CONFIG__A, &sc_config, 0)); 2362 if (status < 0)
2363 break;
2219 2364
2220 /* enable SLAVE mode in 2k 1/32 to 2365 /* enable SLAVE mode in 2k 1/32 to
2221 prevent timing change glitches */ 2366 prevent timing change glitches */
@@ -2227,19 +2372,21 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2227 /* disable slave */ 2372 /* disable slave */
2228 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; 2373 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2229 } 2374 }
2230 CHK_ERROR(Write16(state, 2375 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2231 SC_RA_RAM_CONFIG__A, sc_config, 0)); 2376 if (status < 0)
2377 break;
2232 } 2378 }
2233 2379
2234 CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal)); 2380 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2381 if (status < 0)
2382 break;
2235 2383
2236 if (state->cscd_state == CSCD_INIT) { 2384 if (state->cscd_state == CSCD_INIT) {
2237 /* switch on SRMM scan in SC */ 2385 /* switch on SRMM scan in SC */
2238 CHK_ERROR(Write16(state, 2386 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2239 SC_RA_RAM_SAMPLE_RATE_COUNT__A, 2387 if (status < 0)
2240 DRXD_OSCDEV_DO_SCAN, 0x0000)); 2388 break;
2241/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A, 2389/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2242 DRXD_OSCDEV_STEP , 0x0000 ));*/
2243 state->cscd_state = CSCD_SET; 2390 state->cscd_state = CSCD_SET;
2244 } 2391 }
2245 2392
@@ -2248,14 +2395,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2248 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ 2395 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2249 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, 2396 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2250 (1ULL << 21), bandwidth) - (1 << 23); 2397 (1ULL << 21), bandwidth) - (1 << 23);
2251 CHK_ERROR(Write16(state, 2398 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2252 FE_IF_REG_INCR0__A, 2399 if (status < 0)
2253 (u16) (feIfIncr & FE_IF_REG_INCR0__M), 2400 break;
2254 0x0000)); 2401 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2255 CHK_ERROR(Write16(state, 2402 if (status < 0)
2256 FE_IF_REG_INCR1__A, 2403 break;
2257 (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) &
2258 FE_IF_REG_INCR1__M), 0x0000));
2259 /* Bandwidth setting done */ 2404 /* Bandwidth setting done */
2260 2405
2261 /* Mirror & frequency offset */ 2406 /* Mirror & frequency offset */
@@ -2264,8 +2409,12 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2264 /* Start SC, write channel settings to SC */ 2409 /* Start SC, write channel settings to SC */
2265 2410
2266 /* Enable SC after setting all other parameters */ 2411 /* Enable SC after setting all other parameters */
2267 CHK_ERROR(Write16(state, SC_COMM_STATE__A, 0, 0x0000)); 2412 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2268 CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); 2413 if (status < 0)
2414 break;
2415 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2416 if (status < 0)
2417 break;
2269 2418
2270 /* Write SC parameter registers, operation mode */ 2419 /* Write SC parameter registers, operation mode */
2271#if 1 2420#if 1
@@ -2275,19 +2424,23 @@ static int DRX_Start(struct drxd_state *state, s32 off)
2275 SC_RA_RAM_OP_AUTO_HIER__M | 2424 SC_RA_RAM_OP_AUTO_HIER__M |
2276 SC_RA_RAM_OP_AUTO_RATE__M); 2425 SC_RA_RAM_OP_AUTO_RATE__M);
2277#endif 2426#endif
2278 CHK_ERROR(SC_SetPrefParamCommand(state, 0x0000, 2427 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2279 transmissionParams, 2428 if (status < 0)
2280 operationMode)); 2429 break;
2281 2430
2282 /* Start correct processes to get in lock */ 2431 /* Start correct processes to get in lock */
2283 CHK_ERROR(SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, 2432 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2284 SC_RA_RAM_SW_EVENT_RUN_NMASK__M, 2433 if (status < 0)
2285 SC_RA_RAM_LOCKTRACK_MIN)); 2434 break;
2286 2435
2287 CHK_ERROR(StartOC(state)); 2436 status = StartOC(state);
2437 if (status < 0)
2438 break;
2288 2439
2289 if (state->operation_mode != OM_Default) { 2440 if (state->operation_mode != OM_Default) {
2290 CHK_ERROR(StartDiversity(state)); 2441 status = StartDiversity(state);
2442 if (status < 0)
2443 break;
2291 } 2444 }
2292 2445
2293 state->drxd_state = DRXD_STARTED; 2446 state->drxd_state = DRXD_STARTED;
@@ -2463,22 +2616,34 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2463 do { 2616 do {
2464 state->operation_mode = OM_Default; 2617 state->operation_mode = OM_Default;
2465 2618
2466 CHK_ERROR(SetDeviceTypeId(state)); 2619 status = SetDeviceTypeId(state);
2620 if (status < 0)
2621 break;
2467 2622
2468 /* Apply I2c address patch to B1 */ 2623 /* Apply I2c address patch to B1 */
2469 if (!state->type_A && state->m_HiI2cPatch != NULL) 2624 if (!state->type_A && state->m_HiI2cPatch != NULL)
2470 CHK_ERROR(WriteTable(state, state->m_HiI2cPatch)); 2625 status = WriteTable(state, state->m_HiI2cPatch);
2626 if (status < 0)
2627 break;
2471 2628
2472 if (state->type_A) { 2629 if (state->type_A) {
2473 /* HI firmware patch for UIO readout, 2630 /* HI firmware patch for UIO readout,
2474 avoid clearing of result register */ 2631 avoid clearing of result register */
2475 CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0)); 2632 status = Write16(state, 0x43012D, 0x047f, 0);
2633 if (status < 0)
2634 break;
2476 } 2635 }
2477 2636
2478 CHK_ERROR(HI_ResetCommand(state)); 2637 status = HI_ResetCommand(state);
2638 if (status < 0)
2639 break;
2479 2640
2480 CHK_ERROR(StopAllProcessors(state)); 2641 status = StopAllProcessors(state);
2481 CHK_ERROR(InitCC(state)); 2642 if (status < 0)
2643 break;
2644 status = InitCC(state);
2645 if (status < 0)
2646 break;
2482 2647
2483 state->osc_clock_deviation = 0; 2648 state->osc_clock_deviation = 0;
2484 2649
@@ -2506,18 +2671,29 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2506 (u16) ((state->expected_sys_clock_freq) + 2671 (u16) ((state->expected_sys_clock_freq) +
2507 deviation); 2672 deviation);
2508 } 2673 }
2509 CHK_ERROR(InitHI(state)); 2674 status = InitHI(state);
2510 CHK_ERROR(InitAtomicRead(state)); 2675 if (status < 0)
2676 break;
2677 status = InitAtomicRead(state);
2678 if (status < 0)
2679 break;
2511 2680
2512 CHK_ERROR(EnableAndResetMB(state)); 2681 status = EnableAndResetMB(state);
2682 if (status < 0)
2683 break;
2513 if (state->type_A) 2684 if (state->type_A)
2514 CHK_ERROR(ResetCEFR(state)); 2685 status = ResetCEFR(state);
2686 if (status < 0)
2687 break;
2515 2688
2516 if (fw) { 2689 if (fw) {
2517 CHK_ERROR(DownloadMicrocode(state, fw, fw_size)); 2690 status = DownloadMicrocode(state, fw, fw_size);
2691 if (status < 0)
2692 break;
2518 } else { 2693 } else {
2519 CHK_ERROR(DownloadMicrocode(state, state->microcode, 2694 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2520 state->microcode_length)); 2695 if (status < 0)
2696 break;
2521 } 2697 }
2522 2698
2523 if (state->PGA) { 2699 if (state->PGA) {
@@ -2529,22 +2705,42 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2529 2705
2530 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; 2706 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2531 2707
2532 CHK_ERROR(InitFE(state)); 2708 status = InitFE(state);
2533 CHK_ERROR(InitFT(state)); 2709 if (status < 0)
2534 CHK_ERROR(InitCP(state)); 2710 break;
2535 CHK_ERROR(InitCE(state)); 2711 status = InitFT(state);
2536 CHK_ERROR(InitEQ(state)); 2712 if (status < 0)
2537 CHK_ERROR(InitEC(state)); 2713 break;
2538 CHK_ERROR(InitSC(state)); 2714 status = InitCP(state);
2715 if (status < 0)
2716 break;
2717 status = InitCE(state);
2718 if (status < 0)
2719 break;
2720 status = InitEQ(state);
2721 if (status < 0)
2722 break;
2723 status = InitEC(state);
2724 if (status < 0)
2725 break;
2726 status = InitSC(state);
2727 if (status < 0)
2728 break;
2539 2729
2540 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); 2730 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2541 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); 2731 if (status < 0)
2732 break;
2733 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2734 if (status < 0)
2735 break;
2542 2736
2543 state->cscd_state = CSCD_INIT; 2737 state->cscd_state = CSCD_INIT;
2544 CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 2738 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2545 SC_COMM_EXEC_CTL_STOP, 0)); 2739 if (status < 0)
2546 CHK_ERROR(Write16(state, LC_COMM_EXEC__A, 2740 break;
2547 SC_COMM_EXEC_CTL_STOP, 0)); 2741 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2742 if (status < 0)
2743 break;
2548 2744
2549 driverVersion = (((VERSION_MAJOR / 10) << 4) + 2745 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2550 (VERSION_MAJOR % 10)) << 24; 2746 (VERSION_MAJOR % 10)) << 24;
@@ -2554,10 +2750,13 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2554 ((VERSION_PATCH / 100) << 8) + 2750 ((VERSION_PATCH / 100) << 8) +
2555 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); 2751 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2556 2752
2557 CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, 2753 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2558 driverVersion, 0)); 2754 if (status < 0)
2755 break;
2559 2756
2560 CHK_ERROR(StopOC(state)); 2757 status = StopOC(state);
2758 if (status < 0)
2759 break;
2561 2760
2562 state->drxd_state = DRXD_STOPPED; 2761 state->drxd_state = DRXD_STOPPED;
2563 state->init_done = 1; 2762 state->init_done = 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 19:33:11 -0500