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authorIgor M. Liplianin <liplianin@netup.ru>2009-11-06 21:42:22 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-12-05 15:41:26 -0500
commit1e0c397d5ee261b4d855bf38c1e9987caf0e37ca (patch)
treef77a5dcb0b16f1a2240576cd37900df7394b628d /drivers/media/dvb/frontends
parentab7134f1bd26a547a51c36dd44c55b15b3e15a6f (diff)
V4L/DVB (13340): stv0900: big rework to support cut 3.0.
Patch 3 of 4. Also patch changes logic to prevent code repetitions and big indents. It makes checkpatch silent :) Signed-off-by: Igor M. Liplianin <liplianin@netup.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends')
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c1453
1 files changed, 633 insertions, 820 deletions
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 11dbe942aa41..e2062048f433 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -105,7 +105,8 @@ static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
105 while (new_node->next_inode != NULL) 105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode; 106 new_node = new_node->next_inode;
107 107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL); 108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
109 GFP_KERNEL);
109 if (new_node->next_inode != NULL) 110 if (new_node->next_inode != NULL)
110 new_node = new_node->next_inode; 111 new_node = new_node->next_inode;
111 else 112 else
@@ -128,13 +129,13 @@ s32 ge2comp(s32 a, s32 width)
128 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a; 129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
129} 130}
130 131
131void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr, 132void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
132 u8 reg_data) 133 u8 reg_data)
133{ 134{
134 u8 data[3]; 135 u8 data[3];
135 int ret; 136 int ret;
136 struct i2c_msg i2cmsg = { 137 struct i2c_msg i2cmsg = {
137 .addr = i_params->i2c_addr, 138 .addr = intp->i2c_addr,
138 .flags = 0, 139 .flags = 0,
139 .len = 3, 140 .len = 3,
140 .buf = data, 141 .buf = data,
@@ -144,31 +145,31 @@ void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
144 data[1] = LSB(reg_addr); 145 data[1] = LSB(reg_addr);
145 data[2] = reg_data; 146 data[2] = reg_data;
146 147
147 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1); 148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
148 if (ret != 1) 149 if (ret != 1)
149 dprintk("%s: i2c error %d\n", __func__, ret); 150 dprintk("%s: i2c error %d\n", __func__, ret);
150} 151}
151 152
152u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg) 153u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
153{ 154{
154 int ret; 155 int ret;
155 u8 b0[] = { MSB(reg), LSB(reg) }; 156 u8 b0[] = { MSB(reg), LSB(reg) };
156 u8 buf = 0; 157 u8 buf = 0;
157 struct i2c_msg msg[] = { 158 struct i2c_msg msg[] = {
158 { 159 {
159 .addr = i_params->i2c_addr, 160 .addr = intp->i2c_addr,
160 .flags = 0, 161 .flags = 0,
161 .buf = b0, 162 .buf = b0,
162 .len = 2, 163 .len = 2,
163 }, { 164 }, {
164 .addr = i_params->i2c_addr, 165 .addr = intp->i2c_addr,
165 .flags = I2C_M_RD, 166 .flags = I2C_M_RD,
166 .buf = &buf, 167 .buf = &buf,
167 .len = 1, 168 .len = 1,
168 }, 169 },
169 }; 170 };
170 171
171 ret = i2c_transfer(i_params->i2c_adap, msg, 2); 172 ret = i2c_transfer(intp->i2c_adap, msg, 2);
172 if (ret != 2) 173 if (ret != 2)
173 dprintk("%s: i2c error %d, reg[0x%02x]\n", 174 dprintk("%s: i2c error %d, reg[0x%02x]\n",
174 __func__, ret, reg); 175 __func__, ret, reg);
@@ -190,94 +191,103 @@ void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
190 (*pos) = (i - 1); 191 (*pos) = (i - 1);
191} 192}
192 193
193void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val) 194void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
194{ 195{
195 u8 reg, mask, pos; 196 u8 reg, mask, pos;
196 197
197 reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff); 198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
198 extract_mask_pos(label, &mask, &pos); 199 extract_mask_pos(label, &mask, &pos);
199 200
200 val = mask & (val << pos); 201 val = mask & (val << pos);
201 202
202 reg = (reg & (~mask)) | val; 203 reg = (reg & (~mask)) | val;
203 stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg); 204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
204 205
205} 206}
206 207
207u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label) 208u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
208{ 209{
209 u8 val = 0xff; 210 u8 val = 0xff;
210 u8 mask, pos; 211 u8 mask, pos;
211 212
212 extract_mask_pos(label, &mask, &pos); 213 extract_mask_pos(label, &mask, &pos);
213 214
214 val = stv0900_read_reg(i_params, label >> 16); 215 val = stv0900_read_reg(intp, label >> 16);
215 val = (val & mask) >> pos; 216 val = (val & mask) >> pos;
216 217
217 return val; 218 return val;
218} 219}
219 220
220enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params) 221enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
221{ 222{
222 s32 i; 223 s32 i;
223 enum fe_stv0900_error error;
224
225 if (i_params != NULL) {
226 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
227 if (i_params->errs == STV0900_NO_ERROR) {
228 /*Startup sequence*/
229 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
230 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
231 stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
232 stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
233 stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
234 stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
235 stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
236 msleep(3);
237 stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
238
239 switch (i_params->clkmode) {
240 case 0:
241 case 2:
242 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
243 | i_params->clkmode);
244 break;
245 default:
246 /* preserve SELOSCI bit */
247 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
248 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
249 break;
250 }
251 224
252 msleep(3); 225 if (intp == NULL)
253 for (i = 0; i < 182; i++) 226 return STV0900_INVALID_HANDLE;
254 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
255 227
256 if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) { 228 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
257 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
258 for (i = 0; i < 32; i++)
259 stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
260 }
261 229
262 stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c); 230 if (intp->errs != STV0900_NO_ERROR)
263 stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c); 231 return intp->errs;
264 stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
266 }
267 error = i_params->errs;
268 } else
269 error = STV0900_INVALID_HANDLE;
270 232
271 return error; 233 /*Startup sequence*/
234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
236 msleep(3);
237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
242 msleep(3);
243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
244
245 switch (intp->clkmode) {
246 case 0:
247 case 2:
248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
249 | intp->clkmode);
250 break;
251 default:
252 /* preserve SELOSCI bit */
253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
255 break;
256 }
257
258 msleep(3);
259 for (i = 0; i < 181; i++)
260 stv0900_write_reg(intp, STV0900_InitVal[i][0],
261 STV0900_InitVal[i][1]);
272 262
263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
265 for (i = 0; i < 32; i++)
266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
267 STV0900_Cut20_AddOnVal[i][1]);
268 }
269
270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
272
273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
275
276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
278
279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
281
282 return STV0900_NO_ERROR;
273} 283}
274 284
275u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk) 285u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
276{ 286{
277 u32 mclk = 90000000, div = 0, ad_div = 0; 287 u32 mclk = 90000000, div = 0, ad_div = 0;
278 288
279 div = stv0900_get_bits(i_params, F0900_M_DIV); 289 div = stv0900_get_bits(intp, F0900_M_DIV);
280 ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6); 290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
281 291
282 mclk = (div + 1) * ext_clk / ad_div; 292 mclk = (div + 1) * ext_clk / ad_div;
283 293
@@ -286,73 +296,60 @@ u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
286 return mclk; 296 return mclk;
287} 297}
288 298
289enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk) 299enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
290{ 300{
291 enum fe_stv0900_error error = STV0900_NO_ERROR;
292 u32 m_div, clk_sel; 301 u32 m_div, clk_sel;
293 302
294 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
295 i_params->quartz); 304 intp->quartz);
296 305
297 if (i_params == NULL) 306 if (intp == NULL)
298 error = STV0900_INVALID_HANDLE; 307 return STV0900_INVALID_HANDLE;
299 else {
300 if (i_params->errs)
301 error = STV0900_I2C_ERROR;
302 else {
303 clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
304 m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
305 stv0900_write_bits(i_params, F0900_M_DIV, m_div);
306 i_params->mclk = stv0900_get_mclk_freq(i_params,
307 i_params->quartz);
308
309 /*Set the DiseqC frequency to 22KHz */
310 /*
311 Formula:
312 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
313 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
314 */
315 m_div = i_params->mclk / 704000;
316 stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
317 stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
318
319 stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
320 stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
321
322 if ((i_params->errs))
323 error = STV0900_I2C_ERROR;
324 }
325 }
326 308
327 return error; 309 if (intp->errs)
310 return STV0900_I2C_ERROR;
311
312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
313 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
314 stv0900_write_bits(intp, F0900_M_DIV, m_div);
315 intp->mclk = stv0900_get_mclk_freq(intp,
316 intp->quartz);
317
318 /*Set the DiseqC frequency to 22KHz */
319 /*
320 Formula:
321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
323 */
324 m_div = intp->mclk / 704000;
325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
327
328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
330
331 if ((intp->errs))
332 return STV0900_I2C_ERROR;
333
334 return STV0900_NO_ERROR;
328} 335}
329 336
330u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr, 337u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
331 enum fe_stv0900_demod_num demod) 338 enum fe_stv0900_demod_num demod)
332{ 339{
333 u32 lsb, msb, hsb, err_val; 340 u32 lsb, msb, hsb, err_val;
334 s32 err1field_hsb, err1field_msb, err1field_lsb;
335 s32 err2field_hsb, err2field_msb, err2field_lsb;
336
337 dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
338 dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
339 dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
340
341 dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
342 dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
343 dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
344 341
345 switch (cntr) { 342 switch (cntr) {
346 case 0: 343 case 0:
347 default: 344 default:
348 hsb = stv0900_get_bits(i_params, err1field_hsb); 345 hsb = stv0900_get_bits(intp, ERR_CNT12);
349 msb = stv0900_get_bits(i_params, err1field_msb); 346 msb = stv0900_get_bits(intp, ERR_CNT11);
350 lsb = stv0900_get_bits(i_params, err1field_lsb); 347 lsb = stv0900_get_bits(intp, ERR_CNT10);
351 break; 348 break;
352 case 1: 349 case 1:
353 hsb = stv0900_get_bits(i_params, err2field_hsb); 350 hsb = stv0900_get_bits(intp, ERR_CNT22);
354 msb = stv0900_get_bits(i_params, err2field_msb); 351 msb = stv0900_get_bits(intp, ERR_CNT21);
355 lsb = stv0900_get_bits(i_params, err2field_lsb); 352 lsb = stv0900_get_bits(intp, ERR_CNT20);
356 break; 353 break;
357 } 354 }
358 355
@@ -364,26 +361,22 @@ u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
364static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 361static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
365{ 362{
366 struct stv0900_state *state = fe->demodulator_priv; 363 struct stv0900_state *state = fe->demodulator_priv;
367 struct stv0900_internal *i_params = state->internal; 364 struct stv0900_internal *intp = state->internal;
368 enum fe_stv0900_demod_num demod = state->demod; 365 enum fe_stv0900_demod_num demod = state->demod;
369 366
370 u32 fi2c; 367 stv0900_write_bits(intp, I2CT_ON, enable);
371
372 dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
373
374 stv0900_write_bits(i_params, fi2c, enable);
375 368
376 return 0; 369 return 0;
377} 370}
378 371
379static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params, 372static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
380 enum fe_stv0900_clock_type path1_ts, 373 enum fe_stv0900_clock_type path1_ts,
381 enum fe_stv0900_clock_type path2_ts) 374 enum fe_stv0900_clock_type path2_ts)
382{ 375{
383 376
384 dprintk("%s\n", __func__); 377 dprintk("%s\n", __func__);
385 378
386 if (i_params->chip_id >= 0x20) { 379 if (intp->chip_id >= 0x20) {
387 switch (path1_ts) { 380 switch (path1_ts) {
388 case STV0900_PARALLEL_PUNCT_CLOCK: 381 case STV0900_PARALLEL_PUNCT_CLOCK:
389 case STV0900_DVBCI_CLOCK: 382 case STV0900_DVBCI_CLOCK:
@@ -391,20 +384,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
391 case STV0900_SERIAL_PUNCT_CLOCK: 384 case STV0900_SERIAL_PUNCT_CLOCK:
392 case STV0900_SERIAL_CONT_CLOCK: 385 case STV0900_SERIAL_CONT_CLOCK:
393 default: 386 default:
394 stv0900_write_reg(i_params, R0900_TSGENERAL, 387 stv0900_write_reg(intp, R0900_TSGENERAL,
395 0x00); 388 0x00);
396 break; 389 break;
397 case STV0900_PARALLEL_PUNCT_CLOCK: 390 case STV0900_PARALLEL_PUNCT_CLOCK:
398 case STV0900_DVBCI_CLOCK: 391 case STV0900_DVBCI_CLOCK:
399 stv0900_write_reg(i_params, R0900_TSGENERAL, 392 stv0900_write_reg(intp, R0900_TSGENERAL,
400 0x06); 393 0x06);
401 stv0900_write_bits(i_params, 394 stv0900_write_bits(intp,
402 F0900_P1_TSFIFO_MANSPEED, 3); 395 F0900_P1_TSFIFO_MANSPEED, 3);
403 stv0900_write_bits(i_params, 396 stv0900_write_bits(intp,
404 F0900_P2_TSFIFO_MANSPEED, 0); 397 F0900_P2_TSFIFO_MANSPEED, 0);
405 stv0900_write_reg(i_params, 398 stv0900_write_reg(intp,
406 R0900_P1_TSSPEED, 0x14); 399 R0900_P1_TSSPEED, 0x14);
407 stv0900_write_reg(i_params, 400 stv0900_write_reg(intp,
408 R0900_P2_TSSPEED, 0x28); 401 R0900_P2_TSSPEED, 0x28);
409 break; 402 break;
410 } 403 }
@@ -416,12 +409,12 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
416 case STV0900_SERIAL_PUNCT_CLOCK: 409 case STV0900_SERIAL_PUNCT_CLOCK:
417 case STV0900_SERIAL_CONT_CLOCK: 410 case STV0900_SERIAL_CONT_CLOCK:
418 default: 411 default:
419 stv0900_write_reg(i_params, 412 stv0900_write_reg(intp,
420 R0900_TSGENERAL, 0x0C); 413 R0900_TSGENERAL, 0x0C);
421 break; 414 break;
422 case STV0900_PARALLEL_PUNCT_CLOCK: 415 case STV0900_PARALLEL_PUNCT_CLOCK:
423 case STV0900_DVBCI_CLOCK: 416 case STV0900_DVBCI_CLOCK:
424 stv0900_write_reg(i_params, 417 stv0900_write_reg(intp,
425 R0900_TSGENERAL, 0x0A); 418 R0900_TSGENERAL, 0x0A);
426 dprintk("%s: 0x0a\n", __func__); 419 dprintk("%s: 0x0a\n", __func__);
427 break; 420 break;
@@ -436,20 +429,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
436 case STV0900_SERIAL_PUNCT_CLOCK: 429 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK: 430 case STV0900_SERIAL_CONT_CLOCK:
438 default: 431 default:
439 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 432 stv0900_write_reg(intp, R0900_TSGENERAL1X,
440 0x10); 433 0x10);
441 break; 434 break;
442 case STV0900_PARALLEL_PUNCT_CLOCK: 435 case STV0900_PARALLEL_PUNCT_CLOCK:
443 case STV0900_DVBCI_CLOCK: 436 case STV0900_DVBCI_CLOCK:
444 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 437 stv0900_write_reg(intp, R0900_TSGENERAL1X,
445 0x16); 438 0x16);
446 stv0900_write_bits(i_params, 439 stv0900_write_bits(intp,
447 F0900_P1_TSFIFO_MANSPEED, 3); 440 F0900_P1_TSFIFO_MANSPEED, 3);
448 stv0900_write_bits(i_params, 441 stv0900_write_bits(intp,
449 F0900_P2_TSFIFO_MANSPEED, 0); 442 F0900_P2_TSFIFO_MANSPEED, 0);
450 stv0900_write_reg(i_params, R0900_P1_TSSPEED, 443 stv0900_write_reg(intp, R0900_P1_TSSPEED,
451 0x14); 444 0x14);
452 stv0900_write_reg(i_params, R0900_P2_TSSPEED, 445 stv0900_write_reg(intp, R0900_P2_TSSPEED,
453 0x28); 446 0x28);
454 break; 447 break;
455 } 448 }
@@ -462,12 +455,12 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
462 case STV0900_SERIAL_PUNCT_CLOCK: 455 case STV0900_SERIAL_PUNCT_CLOCK:
463 case STV0900_SERIAL_CONT_CLOCK: 456 case STV0900_SERIAL_CONT_CLOCK:
464 default: 457 default:
465 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 458 stv0900_write_reg(intp, R0900_TSGENERAL1X,
466 0x14); 459 0x14);
467 break; 460 break;
468 case STV0900_PARALLEL_PUNCT_CLOCK: 461 case STV0900_PARALLEL_PUNCT_CLOCK:
469 case STV0900_DVBCI_CLOCK: 462 case STV0900_DVBCI_CLOCK:
470 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 463 stv0900_write_reg(intp, R0900_TSGENERAL1X,
471 0x12); 464 0x12);
472 dprintk("%s: 0x12\n", __func__); 465 dprintk("%s: 0x12\n", __func__);
473 break; 466 break;
@@ -479,20 +472,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
479 472
480 switch (path1_ts) { 473 switch (path1_ts) {
481 case STV0900_PARALLEL_PUNCT_CLOCK: 474 case STV0900_PARALLEL_PUNCT_CLOCK:
482 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00); 475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
483 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00); 476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
484 break; 477 break;
485 case STV0900_DVBCI_CLOCK: 478 case STV0900_DVBCI_CLOCK:
486 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00); 479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
487 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01); 480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
488 break; 481 break;
489 case STV0900_SERIAL_PUNCT_CLOCK: 482 case STV0900_SERIAL_PUNCT_CLOCK:
490 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01); 483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
491 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00); 484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
492 break; 485 break;
493 case STV0900_SERIAL_CONT_CLOCK: 486 case STV0900_SERIAL_CONT_CLOCK:
494 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01); 487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
495 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01); 488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
496 break; 489 break;
497 default: 490 default:
498 break; 491 break;
@@ -500,29 +493,29 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
500 493
501 switch (path2_ts) { 494 switch (path2_ts) {
502 case STV0900_PARALLEL_PUNCT_CLOCK: 495 case STV0900_PARALLEL_PUNCT_CLOCK:
503 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00); 496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
504 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00); 497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
505 break; 498 break;
506 case STV0900_DVBCI_CLOCK: 499 case STV0900_DVBCI_CLOCK:
507 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00); 500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
508 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01); 501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
509 break; 502 break;
510 case STV0900_SERIAL_PUNCT_CLOCK: 503 case STV0900_SERIAL_PUNCT_CLOCK:
511 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01); 504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
512 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00); 505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
513 break; 506 break;
514 case STV0900_SERIAL_CONT_CLOCK: 507 case STV0900_SERIAL_CONT_CLOCK:
515 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01); 508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
516 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01); 509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
517 break; 510 break;
518 default: 511 default:
519 break; 512 break;
520 } 513 }
521 514
522 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1); 515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
523 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0); 516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
524 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1); 517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
525 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0); 518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
526} 519}
527 520
528void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency, 521void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
@@ -574,7 +567,7 @@ void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
574 } 567 }
575} 568}
576 569
577static s32 stv0900_get_rf_level(struct stv0900_internal *i_params, 570static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
578 const struct stv0900_table *lookup, 571 const struct stv0900_table *lookup,
579 enum fe_stv0900_demod_num demod) 572 enum fe_stv0900_demod_num demod)
580{ 573{
@@ -586,43 +579,37 @@ static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
586 579
587 dprintk("%s\n", __func__); 580 dprintk("%s\n", __func__);
588 581
589 if ((lookup != NULL) && lookup->size) { 582 if ((lookup == NULL) || (lookup->size <= 0))
590 switch (demod) { 583 return 0;
591 case STV0900_DEMOD_1:
592 default:
593 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
594 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
595 break;
596 case STV0900_DEMOD_2:
597 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
598 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
599 break;
600 }
601
602 dprintk("%s: AGC Gain = 0x%x\n", __func__, agc_gain);
603 584
604 imin = 0; 585 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
605 imax = lookup->size - 1; 586 stv0900_get_bits(intp, AGCIQ_VALUE0));
606 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
607 while ((imax - imin) > 1) {
608 i = (imax + imin) >> 1;
609 587
610 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval)) 588 imin = 0;
611 imax = i; 589 imax = lookup->size - 1;
612 else 590 if (INRANGE(lookup->table[imin].regval, agc_gain,
613 imin = i; 591 lookup->table[imax].regval)) {
614 } 592 while ((imax - imin) > 1) {
593 i = (imax + imin) >> 1;
615 594
616 rf_lvl = (((s32)agc_gain - lookup->table[imin].regval) 595 if (INRANGE(lookup->table[imin].regval,
617 * (lookup->table[imax].realval - lookup->table[imin].realval) 596 agc_gain,
618 / (lookup->table[imax].regval - lookup->table[imin].regval)) 597 lookup->table[i].regval))
619 + lookup->table[imin].realval; 598 imax = i;
620 } else if (agc_gain > lookup->table[0].regval) 599 else
621 rf_lvl = 5; 600 imin = i;
622 else if (agc_gain < lookup->table[lookup->size-1].regval) 601 }
623 rf_lvl = -100;
624 602
625 } 603 rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
604 rf_lvl *= (lookup->table[imax].realval -
605 lookup->table[imin].realval);
606 rf_lvl /= (lookup->table[imax].regval -
607 lookup->table[imin].regval);
608 rf_lvl += lookup->table[imin].realval;
609 } else if (agc_gain > lookup->table[0].regval)
610 rf_lvl = 5;
611 else if (agc_gain < lookup->table[lookup->size-1].regval)
612 rf_lvl = -100;
626 613
627 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl); 614 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
628 615
@@ -648,45 +635,39 @@ static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
648 return 0; 635 return 0;
649} 636}
650 637
651
652static s32 stv0900_carr_get_quality(struct dvb_frontend *fe, 638static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
653 const struct stv0900_table *lookup) 639 const struct stv0900_table *lookup)
654{ 640{
655 struct stv0900_state *state = fe->demodulator_priv; 641 struct stv0900_state *state = fe->demodulator_priv;
656 struct stv0900_internal *i_params = state->internal; 642 struct stv0900_internal *intp = state->internal;
657 enum fe_stv0900_demod_num demod = state->demod; 643 enum fe_stv0900_demod_num demod = state->demod;
658 644
659 s32 c_n = -100, 645 s32 c_n = -100,
660 regval, imin, imax, 646 regval,
647 imin,
648 imax,
661 i, 649 i,
662 lock_flag_field,
663 noise_field1, 650 noise_field1,
664 noise_field0; 651 noise_field0;
665 652
666 dprintk("%s\n", __func__); 653 dprintk("%s\n", __func__);
667 654
668 dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
669 F0900_P2_LOCK_DEFINITIF);
670 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 655 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
671 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1, 656 noise_field1 = NOSPLHT_NORMED1;
672 F0900_P2_NOSPLHT_NORMED1); 657 noise_field0 = NOSPLHT_NORMED0;
673 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
674 F0900_P2_NOSPLHT_NORMED0);
675 } else { 658 } else {
676 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1, 659 noise_field1 = NOSDATAT_NORMED1;
677 F0900_P2_NOSDATAT_NORMED1); 660 noise_field0 = NOSDATAT_NORMED0;
678 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
679 F0900_P2_NOSDATAT_NORMED0);
680 } 661 }
681 662
682 if (stv0900_get_bits(i_params, lock_flag_field)) { 663 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
683 if ((lookup != NULL) && lookup->size) { 664 if ((lookup != NULL) && lookup->size) {
684 regval = 0; 665 regval = 0;
685 msleep(5); 666 msleep(5);
686 for (i = 0; i < 16; i++) { 667 for (i = 0; i < 16; i++) {
687 regval += MAKEWORD(stv0900_get_bits(i_params, 668 regval += MAKEWORD(stv0900_get_bits(intp,
688 noise_field1), 669 noise_field1),
689 stv0900_get_bits(i_params, 670 stv0900_get_bits(intp,
690 noise_field0)); 671 noise_field0));
691 msleep(1); 672 msleep(1);
692 } 673 }
@@ -718,18 +699,15 @@ static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
718 } 699 }
719 } 700 }
720 701
721 dprintk("%s: Quality = %d\n", __func__, c_n);
722
723 return c_n; 702 return c_n;
724} 703}
725 704
726static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 705static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
727{ 706{
728 struct stv0900_state *state = fe->demodulator_priv; 707 struct stv0900_state *state = fe->demodulator_priv;
729 struct stv0900_internal *i_params = state->internal; 708 struct stv0900_internal *intp = state->internal;
730 enum fe_stv0900_demod_num demod = state->demod; 709 enum fe_stv0900_demod_num demod = state->demod;
731 u8 err_val1, err_val0; 710 u8 err_val1, err_val0;
732 s32 err_field1, err_field0;
733 u32 header_err_val = 0; 711 u32 header_err_val = 0;
734 712
735 *ucblocks = 0x0; 713 *ucblocks = 0x0;
@@ -737,24 +715,14 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
737 /* DVB-S2 delineator errors count */ 715 /* DVB-S2 delineator errors count */
738 716
739 /* retreiving number for errnous headers */ 717 /* retreiving number for errnous headers */
740 dmd_reg(err_field0, R0900_P1_BBFCRCKO0, 718 err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
741 R0900_P2_BBFCRCKO0); 719 err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
742 dmd_reg(err_field1, R0900_P1_BBFCRCKO1, 720 header_err_val = (err_val1 << 8) | err_val0;
743 R0900_P2_BBFCRCKO1);
744
745 err_val1 = stv0900_read_reg(i_params, err_field1);
746 err_val0 = stv0900_read_reg(i_params, err_field0);
747 header_err_val = (err_val1<<8) | err_val0;
748 721
749 /* retreiving number for errnous packets */ 722 /* retreiving number for errnous packets */
750 dmd_reg(err_field0, R0900_P1_UPCRCKO0, 723 err_val1 = stv0900_read_reg(intp, UPCRCKO1);
751 R0900_P2_UPCRCKO0); 724 err_val0 = stv0900_read_reg(intp, UPCRCKO0);
752 dmd_reg(err_field1, R0900_P1_UPCRCKO1, 725 *ucblocks = (err_val1 << 8) | err_val0;
753 R0900_P2_UPCRCKO1);
754
755 err_val1 = stv0900_read_reg(i_params, err_field1);
756 err_val0 = stv0900_read_reg(i_params, err_field0);
757 *ucblocks = (err_val1<<8) | err_val0;
758 *ucblocks += header_err_val; 726 *ucblocks += header_err_val;
759 } 727 }
760 728
@@ -777,25 +745,13 @@ static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
777 return 0; 745 return 0;
778} 746}
779 747
780static u32 stv0900_get_ber(struct stv0900_internal *i_params, 748static u32 stv0900_get_ber(struct stv0900_internal *intp,
781 enum fe_stv0900_demod_num demod) 749 enum fe_stv0900_demod_num demod)
782{ 750{
783 u32 ber = 10000000, i; 751 u32 ber = 10000000, i;
784 s32 dmd_state_reg;
785 s32 demod_state; 752 s32 demod_state;
786 s32 vstatus_reg;
787 s32 prvit_field;
788 s32 pdel_status_reg;
789 s32 pdel_lock_field;
790
791 dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
792 dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
793 dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
794 dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
795 dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
796 F0900_P2_PKTDELIN_LOCK);
797 753
798 demod_state = stv0900_get_bits(i_params, dmd_state_reg); 754 demod_state = stv0900_get_bits(intp, HEADER_MODE);
799 755
800 switch (demod_state) { 756 switch (demod_state) {
801 case STV0900_SEARCH: 757 case STV0900_SEARCH:
@@ -807,11 +763,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
807 ber = 0; 763 ber = 0;
808 for (i = 0; i < 5; i++) { 764 for (i = 0; i < 5; i++) {
809 msleep(5); 765 msleep(5);
810 ber += stv0900_get_err_count(i_params, 0, demod); 766 ber += stv0900_get_err_count(intp, 0, demod);
811 } 767 }
812 768
813 ber /= 5; 769 ber /= 5;
814 if (stv0900_get_bits(i_params, prvit_field)) { 770 if (stv0900_get_bits(intp, PRFVIT)) {
815 ber *= 9766; 771 ber *= 9766;
816 ber = ber >> 13; 772 ber = ber >> 13;
817 } 773 }
@@ -821,11 +777,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
821 ber = 0; 777 ber = 0;
822 for (i = 0; i < 5; i++) { 778 for (i = 0; i < 5; i++) {
823 msleep(5); 779 msleep(5);
824 ber += stv0900_get_err_count(i_params, 0, demod); 780 ber += stv0900_get_err_count(intp, 0, demod);
825 } 781 }
826 782
827 ber /= 5; 783 ber /= 5;
828 if (stv0900_get_bits(i_params, pdel_lock_field)) { 784 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
829 ber *= 9766; 785 ber *= 9766;
830 ber = ber >> 13; 786 ber = ber >> 13;
831 } 787 }
@@ -846,20 +802,16 @@ static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
846 return 0; 802 return 0;
847} 803}
848 804
849int stv0900_get_demod_lock(struct stv0900_internal *i_params, 805int stv0900_get_demod_lock(struct stv0900_internal *intp,
850 enum fe_stv0900_demod_num demod, s32 time_out) 806 enum fe_stv0900_demod_num demod, s32 time_out)
851{ 807{
852 s32 timer = 0, 808 s32 timer = 0,
853 lock = 0, 809 lock = 0;
854 header_field,
855 lock_field;
856 810
857 enum fe_stv0900_search_state dmd_state; 811 enum fe_stv0900_search_state dmd_state;
858 812
859 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
860 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
861 while ((timer < time_out) && (lock == 0)) { 813 while ((timer < time_out) && (lock == 0)) {
862 dmd_state = stv0900_get_bits(i_params, header_field); 814 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
863 dprintk("Demod State = %d\n", dmd_state); 815 dprintk("Demod State = %d\n", dmd_state);
864 switch (dmd_state) { 816 switch (dmd_state) {
865 case STV0900_SEARCH: 817 case STV0900_SEARCH:
@@ -869,7 +821,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
869 break; 821 break;
870 case STV0900_DVBS2_FOUND: 822 case STV0900_DVBS2_FOUND:
871 case STV0900_DVBS_FOUND: 823 case STV0900_DVBS_FOUND:
872 lock = stv0900_get_bits(i_params, lock_field); 824 lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
873 break; 825 break;
874 } 826 }
875 827
@@ -887,7 +839,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
887 return lock; 839 return lock;
888} 840}
889 841
890void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params, 842void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
891 enum fe_stv0900_demod_num demod) 843 enum fe_stv0900_demod_num demod)
892{ 844{
893 s32 regflist, 845 s32 regflist,
@@ -895,48 +847,32 @@ void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
895 847
896 dprintk("%s\n", __func__); 848 dprintk("%s\n", __func__);
897 849
898 dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0); 850 regflist = MODCODLST0;
899 851
900 for (i = 0; i < 16; i++) 852 for (i = 0; i < 16; i++)
901 stv0900_write_reg(i_params, regflist + i, 0xff); 853 stv0900_write_reg(intp, regflist + i, 0xff);
902} 854}
903 855
904void stv0900_activate_s2_modcode(struct stv0900_internal *i_params, 856void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
905 enum fe_stv0900_demod_num demod) 857 enum fe_stv0900_demod_num demod)
906{ 858{
907 u32 matype, 859 u32 matype,
908 mod_code, 860 mod_code,
909 fmod, 861 fmod,
910 reg_index, 862 reg_index,
911 field_index; 863 field_index;
912 864
913 dprintk("%s\n", __func__); 865 dprintk("%s\n", __func__);
914 866
915 if (i_params->chip_id <= 0x11) { 867 if (intp->chip_id <= 0x11) {
916 msleep(5); 868 msleep(5);
917 869
918 switch (demod) { 870 mod_code = stv0900_read_reg(intp, PLHMODCOD);
919 case STV0900_DEMOD_1: 871 matype = mod_code & 0x3;
920 default: 872 mod_code = (mod_code & 0x7f) >> 2;
921 mod_code = stv0900_read_reg(i_params,
922 R0900_P1_PLHMODCOD);
923 matype = mod_code & 0x3;
924 mod_code = (mod_code & 0x7f) >> 2;
925
926 reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
927 field_index = mod_code % 2;
928 break;
929 case STV0900_DEMOD_2:
930 mod_code = stv0900_read_reg(i_params,
931 R0900_P2_PLHMODCOD);
932 matype = mod_code & 0x3;
933 mod_code = (mod_code & 0x7f) >> 2;
934
935 reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
936 field_index = mod_code % 2;
937 break;
938 }
939 873
874 reg_index = MODCODLSTF - mod_code / 2;
875 field_index = mod_code % 2;
940 876
941 switch (matype) { 877 switch (matype) {
942 case 0: 878 case 0:
@@ -955,70 +891,41 @@ void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
955 } 891 }
956 892
957 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910)) 893 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
958 && (matype <= 1)) { 894 && (matype <= 1)) {
959 if (field_index == 0) 895 if (field_index == 0)
960 stv0900_write_reg(i_params, reg_index, 896 stv0900_write_reg(intp, reg_index,
961 0xf0 | fmod); 897 0xf0 | fmod);
962 else 898 else
963 stv0900_write_reg(i_params, reg_index, 899 stv0900_write_reg(intp, reg_index,
964 (fmod << 4) | 0xf); 900 (fmod << 4) | 0xf);
965 } 901 }
966 } else if (i_params->chip_id >= 0x12) {
967 switch (demod) {
968 case STV0900_DEMOD_1:
969 default:
970 for (reg_index = 0; reg_index < 7; reg_index++)
971 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
972
973 stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
974 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
975 for (reg_index = 0; reg_index < 8; reg_index++)
976 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
977 902
978 break; 903 } else if (intp->chip_id >= 0x12) {
979 case STV0900_DEMOD_2: 904 for (reg_index = 0; reg_index < 7; reg_index++)
980 for (reg_index = 0; reg_index < 7; reg_index++) 905 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
981 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
982 906
983 stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff); 907 stv0900_write_reg(intp, MODCODLSTE, 0xff);
984 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf); 908 stv0900_write_reg(intp, MODCODLSTF, 0xcf);
985 for (reg_index = 0; reg_index < 8; reg_index++) 909 for (reg_index = 0; reg_index < 8; reg_index++)
986 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc); 910 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
987 911
988 break;
989 }
990 912
991 } 913 }
992} 914}
993 915
994void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params, 916void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
995 enum fe_stv0900_demod_num demod) 917 enum fe_stv0900_demod_num demod)
996{ 918{
997 u32 reg_index; 919 u32 reg_index;
998 920
999 dprintk("%s\n", __func__); 921 dprintk("%s\n", __func__);
1000 922
1001 switch (demod) { 923 stv0900_write_reg(intp, MODCODLST0, 0xff);
1002 case STV0900_DEMOD_1: 924 stv0900_write_reg(intp, MODCODLST1, 0xf0);
1003 default: 925 stv0900_write_reg(intp, MODCODLSTF, 0x0f);
1004 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff); 926 for (reg_index = 0; reg_index < 13; reg_index++)
1005 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0); 927 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
1006 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
1007 for (reg_index = 0; reg_index < 13; reg_index++)
1008 stv0900_write_reg(i_params,
1009 R0900_P1_MODCODLST2 + reg_index, 0);
1010
1011 break;
1012 case STV0900_DEMOD_2:
1013 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
1014 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
1015 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
1016 for (reg_index = 0; reg_index < 13; reg_index++)
1017 stv0900_write_reg(i_params,
1018 R0900_P2_MODCODLST2 + reg_index, 0);
1019 928
1020 break;
1021 }
1022} 929}
1023 930
1024static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe) 931static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
@@ -1042,161 +949,118 @@ static int stb0900_get_property(struct dvb_frontend *fe,
1042 return 0; 949 return 0;
1043} 950}
1044 951
1045void stv0900_start_search(struct stv0900_internal *i_params, 952void stv0900_start_search(struct stv0900_internal *intp,
1046 enum fe_stv0900_demod_num demod) 953 enum fe_stv0900_demod_num demod)
1047{ 954{
1048 955 u32 freq;
1049 switch (demod) { 956 s16 freq_s16 ;
1050 case STV0900_DEMOD_1: 957
1051 default: 958 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1052 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f); 959 if (intp->chip_id == 0x10)
1053 960 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1054 if (i_params->chip_id == 0x10) 961
1055 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa); 962 if (intp->chip_id < 0x20)
1056 963 stv0900_write_reg(intp, CARHDR, 0x55);
1057 if (i_params->chip_id < 0x20) 964
1058 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55); 965 if (intp->chip_id <= 0x20) {
1059 966 if (intp->symbol_rate[0] <= 5000000) {
1060 if (i_params->dmd1_symbol_rate <= 5000000) { 967 stv0900_write_reg(intp, CARCFG, 0x44);
1061 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44); 968 stv0900_write_reg(intp, CFRUP1, 0x0f);
1062 stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f); 969 stv0900_write_reg(intp, CFRUP0, 0xff);
1063 stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff); 970 stv0900_write_reg(intp, CFRLOW1, 0xf0);
1064 stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0); 971 stv0900_write_reg(intp, CFRLOW0, 0x00);
1065 stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00); 972 stv0900_write_reg(intp, RTCS2, 0x68);
1066 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
1067 } else { 973 } else {
1068 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4); 974 stv0900_write_reg(intp, CARCFG, 0xc4);
1069 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44); 975 stv0900_write_reg(intp, RTCS2, 0x44);
1070 } 976 }
1071 977
1072 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0); 978 } else { /*cut 3.0 above*/
1073 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0); 979 if (intp->symbol_rate[demod] <= 5000000)
1074 980 stv0900_write_reg(intp, RTCS2, 0x68);
1075 if (i_params->chip_id >= 0x20) { 981 else
1076 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41); 982 stv0900_write_reg(intp, RTCS2, 0x44);
1077 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1078
1079 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1080 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1081 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1082 }
1083 }
1084
1085 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1086 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
1087 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
1088 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1089 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1090 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1091 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1092 if (i_params->chip_id >= 0x20) {
1093 if (i_params->dmd1_symbol_rate < 2000000) {
1094 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1095 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1096 }
1097
1098 if (i_params->dmd1_symbol_rate < 10000000) {
1099 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1100 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1101 } else {
1102 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1103 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1104 }
1105 983
984 stv0900_write_reg(intp, CARCFG, 0x46);
985 if (intp->srch_algo[demod] == STV0900_WARM_START) {
986 freq = 1000 << 16;
987 freq /= (intp->mclk / 1000);
988 freq_s16 = (s16)freq;
1106 } else { 989 } else {
1107 if (i_params->dmd1_symbol_rate < 10000000) 990 freq = (intp->srch_range[demod] / 2000);
1108 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef); 991 if (intp->symbol_rate[demod] <= 5000000)
992 freq += 80;
1109 else 993 else
1110 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed); 994 freq += 600;
1111 }
1112
1113 switch (i_params->dmd1_srch_algo) {
1114 case STV0900_WARM_START:
1115 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1116 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1117 break;
1118 case STV0900_COLD_START:
1119 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1120 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1121 break;
1122 default:
1123 break;
1124 }
1125 995
1126 break; 996 freq = freq << 16;
1127 case STV0900_DEMOD_2: 997 freq /= (intp->mclk / 1000);
1128 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f); 998 freq_s16 = (s16)freq;
1129 if (i_params->chip_id == 0x10)
1130 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1131
1132 if (i_params->chip_id < 0x20)
1133 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1134
1135 if (i_params->dmd2_symbol_rate <= 5000000) {
1136 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1137 stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1138 stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1139 stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1140 stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1141 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1142 } else {
1143 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1144 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1145 } 999 }
1146 1000
1147 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0); 1001 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1148 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0); 1002 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1003 freq_s16 *= (-1);
1004 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1005 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1006 }
1149 1007
1150 if (i_params->chip_id >= 0x20) { 1008 stv0900_write_reg(intp, CFRINIT1, 0);
1151 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41); 1009 stv0900_write_reg(intp, CFRINIT0, 0);
1152 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1153 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1154 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1155 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1156 }
1157 }
1158 1010
1159 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00); 1011 if (intp->chip_id >= 0x20) {
1160 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0); 1012 stv0900_write_reg(intp, EQUALCFG, 0x41);
1161 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0); 1013 stv0900_write_reg(intp, FFECFG, 0x41);
1162 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1163 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1164 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1165 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1166 if (i_params->chip_id >= 0x20) {
1167 if (i_params->dmd2_symbol_rate < 2000000) {
1168 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1169 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1170 }
1171 1014
1172 if (i_params->dmd2_symbol_rate < 10000000) { 1015 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1173 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c); 1016 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1174 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20); 1017 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1175 } else { 1018 stv0900_write_reg(intp, VITSCALE,
1176 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b); 1019 0x82);
1177 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20); 1020 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1178 } 1021 }
1022 }
1179 1023
1024 stv0900_write_reg(intp, SFRSTEP, 0x00);
1025 stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1026 stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1027 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1028 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1029 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1030 stv0900_write_reg(intp, RTC, 0x88);
1031 if (intp->chip_id >= 0x20) {
1032 if (intp->symbol_rate[demod] < 2000000) {
1033 if (intp->chip_id <= 0x20)
1034 stv0900_write_reg(intp, CARFREQ, 0x39);
1035 else /*cut 3.0*/
1036 stv0900_write_reg(intp, CARFREQ, 0x89);
1037
1038 stv0900_write_reg(intp, CARHDR, 0x40);
1039 } else if (intp->symbol_rate[demod] < 10000000) {
1040 stv0900_write_reg(intp, CARFREQ, 0x4c);
1041 stv0900_write_reg(intp, CARHDR, 0x20);
1180 } else { 1042 } else {
1181 if (i_params->dmd2_symbol_rate < 10000000) 1043 stv0900_write_reg(intp, CARFREQ, 0x4b);
1182 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef); 1044 stv0900_write_reg(intp, CARHDR, 0x20);
1183 else
1184 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1185 } 1045 }
1186 1046
1187 switch (i_params->dmd2_srch_algo) { 1047 } else {
1188 case STV0900_WARM_START: 1048 if (intp->symbol_rate[demod] < 10000000)
1189 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f); 1049 stv0900_write_reg(intp, CARFREQ, 0xef);
1190 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18); 1050 else
1191 break; 1051 stv0900_write_reg(intp, CARFREQ, 0xed);
1192 case STV0900_COLD_START: 1052 }
1193 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1194 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1195 break;
1196 default:
1197 break;
1198 }
1199 1053
1054 switch (intp->srch_algo[demod]) {
1055 case STV0900_WARM_START:
1056 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1057 stv0900_write_reg(intp, DMDISTATE, 0x18);
1058 break;
1059 case STV0900_COLD_START:
1060 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1061 stv0900_write_reg(intp, DMDISTATE, 0x15);
1062 break;
1063 default:
1200 break; 1064 break;
1201 } 1065 }
1202} 1066}
@@ -1205,33 +1069,40 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1205 s32 pilot, u8 chip_id) 1069 s32 pilot, u8 chip_id)
1206{ 1070{
1207 u8 aclc_value = 0x29; 1071 u8 aclc_value = 0x29;
1208 s32 i; 1072 s32 i;
1209 const struct stv0900_car_loop_optim *car_loop_s2; 1073 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1210 1074
1211 dprintk("%s\n", __func__); 1075 dprintk("%s\n", __func__);
1212 1076
1213 if (chip_id <= 0x12) 1077 if (chip_id <= 0x12) {
1214 car_loop_s2 = FE_STV0900_S2CarLoop; 1078 cls2 = FE_STV0900_S2CarLoop;
1215 else if (chip_id == 0x20) 1079 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1216 car_loop_s2 = FE_STV0900_S2CarLoopCut20; 1080 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1217 else 1081 } else if (chip_id == 0x20) {
1218 car_loop_s2 = FE_STV0900_S2CarLoop; 1082 cls2 = FE_STV0900_S2CarLoopCut20;
1083 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1084 cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1085 } else {
1086 cls2 = FE_STV0900_S2CarLoopCut30;
1087 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1088 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1089 }
1219 1090
1220 if (modcode < STV0900_QPSK_12) { 1091 if (modcode < STV0900_QPSK_12) {
1221 i = 0; 1092 i = 0;
1222 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode)) 1093 while ((i < 3) && (modcode != cllqs2[i].modcode))
1223 i++; 1094 i++;
1224 1095
1225 if (i >= 3) 1096 if (i >= 3)
1226 i = 2; 1097 i = 2;
1227 } else { 1098 } else {
1228 i = 0; 1099 i = 0;
1229 while ((i < 14) && (modcode != car_loop_s2[i].modcode)) 1100 while ((i < 14) && (modcode != cls2[i].modcode))
1230 i++; 1101 i++;
1231 1102
1232 if (i >= 14) { 1103 if (i >= 14) {
1233 i = 0; 1104 i = 0;
1234 while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode)) 1105 while ((i < 11) && (modcode != cllas2[i].modcode))
1235 i++; 1106 i++;
1236 1107
1237 if (i >= 11) 1108 if (i >= 11)
@@ -1242,77 +1113,83 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1242 if (modcode <= STV0900_QPSK_25) { 1113 if (modcode <= STV0900_QPSK_25) {
1243 if (pilot) { 1114 if (pilot) {
1244 if (srate <= 3000000) 1115 if (srate <= 3000000)
1245 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2; 1116 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1246 else if (srate <= 7000000) 1117 else if (srate <= 7000000)
1247 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5; 1118 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1248 else if (srate <= 15000000) 1119 else if (srate <= 15000000)
1249 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10; 1120 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1250 else if (srate <= 25000000) 1121 else if (srate <= 25000000)
1251 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20; 1122 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1252 else 1123 else
1253 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30; 1124 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1254 } else { 1125 } else {
1255 if (srate <= 3000000) 1126 if (srate <= 3000000)
1256 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2; 1127 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1257 else if (srate <= 7000000) 1128 else if (srate <= 7000000)
1258 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5; 1129 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1259 else if (srate <= 15000000) 1130 else if (srate <= 15000000)
1260 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10; 1131 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1261 else if (srate <= 25000000) 1132 else if (srate <= 25000000)
1262 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20; 1133 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1263 else 1134 else
1264 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30; 1135 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1265 } 1136 }
1266 1137
1267 } else if (modcode <= STV0900_8PSK_910) { 1138 } else if (modcode <= STV0900_8PSK_910) {
1268 if (pilot) { 1139 if (pilot) {
1269 if (srate <= 3000000) 1140 if (srate <= 3000000)
1270 aclc_value = car_loop_s2[i].car_loop_pilots_on_2; 1141 aclc_value = cls2[i].car_loop_pilots_on_2;
1271 else if (srate <= 7000000) 1142 else if (srate <= 7000000)
1272 aclc_value = car_loop_s2[i].car_loop_pilots_on_5; 1143 aclc_value = cls2[i].car_loop_pilots_on_5;
1273 else if (srate <= 15000000) 1144 else if (srate <= 15000000)
1274 aclc_value = car_loop_s2[i].car_loop_pilots_on_10; 1145 aclc_value = cls2[i].car_loop_pilots_on_10;
1275 else if (srate <= 25000000) 1146 else if (srate <= 25000000)
1276 aclc_value = car_loop_s2[i].car_loop_pilots_on_20; 1147 aclc_value = cls2[i].car_loop_pilots_on_20;
1277 else 1148 else
1278 aclc_value = car_loop_s2[i].car_loop_pilots_on_30; 1149 aclc_value = cls2[i].car_loop_pilots_on_30;
1279 } else { 1150 } else {
1280 if (srate <= 3000000) 1151 if (srate <= 3000000)
1281 aclc_value = car_loop_s2[i].car_loop_pilots_off_2; 1152 aclc_value = cls2[i].car_loop_pilots_off_2;
1282 else if (srate <= 7000000) 1153 else if (srate <= 7000000)
1283 aclc_value = car_loop_s2[i].car_loop_pilots_off_5; 1154 aclc_value = cls2[i].car_loop_pilots_off_5;
1284 else if (srate <= 15000000) 1155 else if (srate <= 15000000)
1285 aclc_value = car_loop_s2[i].car_loop_pilots_off_10; 1156 aclc_value = cls2[i].car_loop_pilots_off_10;
1286 else if (srate <= 25000000) 1157 else if (srate <= 25000000)
1287 aclc_value = car_loop_s2[i].car_loop_pilots_off_20; 1158 aclc_value = cls2[i].car_loop_pilots_off_20;
1288 else 1159 else
1289 aclc_value = car_loop_s2[i].car_loop_pilots_off_30; 1160 aclc_value = cls2[i].car_loop_pilots_off_30;
1290 } 1161 }
1291 1162
1292 } else { 1163 } else {
1293 if (srate <= 3000000) 1164 if (srate <= 3000000)
1294 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2; 1165 aclc_value = cllas2[i].car_loop_pilots_on_2;
1295 else if (srate <= 7000000) 1166 else if (srate <= 7000000)
1296 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5; 1167 aclc_value = cllas2[i].car_loop_pilots_on_5;
1297 else if (srate <= 15000000) 1168 else if (srate <= 15000000)
1298 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10; 1169 aclc_value = cllas2[i].car_loop_pilots_on_10;
1299 else if (srate <= 25000000) 1170 else if (srate <= 25000000)
1300 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20; 1171 aclc_value = cllas2[i].car_loop_pilots_on_20;
1301 else 1172 else
1302 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30; 1173 aclc_value = cllas2[i].car_loop_pilots_on_30;
1303 } 1174 }
1304 1175
1305 return aclc_value; 1176 return aclc_value;
1306} 1177}
1307 1178
1308u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id) 1179u8 stv0900_get_optim_short_carr_loop(s32 srate,
1180 enum fe_stv0900_modulation modulation,
1181 u8 chip_id)
1309{ 1182{
1183 const struct stv0900_short_frames_car_loop_optim *s2scl;
1184 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1310 s32 mod_index = 0; 1185 s32 mod_index = 0;
1311
1312 u8 aclc_value = 0x0b; 1186 u8 aclc_value = 0x0b;
1313 1187
1314 dprintk("%s\n", __func__); 1188 dprintk("%s\n", __func__);
1315 1189
1190 s2scl = FE_STV0900_S2ShortCarLoop;
1191 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1192
1316 switch (modulation) { 1193 switch (modulation) {
1317 case STV0900_QPSK: 1194 case STV0900_QPSK:
1318 default: 1195 default:
@@ -1329,75 +1206,116 @@ u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modul
1329 break; 1206 break;
1330 } 1207 }
1331 1208
1332 switch (chip_id) { 1209 if (chip_id >= 0x30) {
1333 case 0x20:
1334 if (srate <= 3000000) 1210 if (srate <= 3000000)
1335 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2; 1211 aclc_value = s2sclc30[mod_index].car_loop_2;
1336 else if (srate <= 7000000) 1212 else if (srate <= 7000000)
1337 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5; 1213 aclc_value = s2sclc30[mod_index].car_loop_5;
1338 else if (srate <= 15000000) 1214 else if (srate <= 15000000)
1339 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10; 1215 aclc_value = s2sclc30[mod_index].car_loop_10;
1340 else if (srate <= 25000000) 1216 else if (srate <= 25000000)
1341 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20; 1217 aclc_value = s2sclc30[mod_index].car_loop_20;
1342 else 1218 else
1343 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30; 1219 aclc_value = s2sclc30[mod_index].car_loop_30;
1344 1220
1345 break; 1221 } else if (chip_id >= 0x20) {
1346 case 0x12:
1347 default:
1348 if (srate <= 3000000) 1222 if (srate <= 3000000)
1349 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2; 1223 aclc_value = s2scl[mod_index].car_loop_cut20_2;
1350 else if (srate <= 7000000) 1224 else if (srate <= 7000000)
1351 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5; 1225 aclc_value = s2scl[mod_index].car_loop_cut20_5;
1352 else if (srate <= 15000000) 1226 else if (srate <= 15000000)
1353 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10; 1227 aclc_value = s2scl[mod_index].car_loop_cut20_10;
1354 else if (srate <= 25000000) 1228 else if (srate <= 25000000)
1355 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20; 1229 aclc_value = s2scl[mod_index].car_loop_cut20_20;
1356 else 1230 else
1357 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30; 1231 aclc_value = s2scl[mod_index].car_loop_cut20_30;
1232
1233 } else {
1234 if (srate <= 3000000)
1235 aclc_value = s2scl[mod_index].car_loop_cut12_2;
1236 else if (srate <= 7000000)
1237 aclc_value = s2scl[mod_index].car_loop_cut12_5;
1238 else if (srate <= 15000000)
1239 aclc_value = s2scl[mod_index].car_loop_cut12_10;
1240 else if (srate <= 25000000)
1241 aclc_value = s2scl[mod_index].car_loop_cut12_20;
1242 else
1243 aclc_value = s2scl[mod_index].car_loop_cut12_30;
1358 1244
1359 break;
1360 } 1245 }
1361 1246
1362 return aclc_value; 1247 return aclc_value;
1363} 1248}
1364 1249
1365static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params, 1250static
1251enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1366 enum fe_stv0900_demod_mode LDPC_Mode, 1252 enum fe_stv0900_demod_mode LDPC_Mode,
1367 enum fe_stv0900_demod_num demod) 1253 enum fe_stv0900_demod_num demod)
1368{ 1254{
1369 enum fe_stv0900_error error = STV0900_NO_ERROR; 1255 enum fe_stv0900_error error = STV0900_NO_ERROR;
1256 s32 reg_ind;
1370 1257
1371 dprintk("%s\n", __func__); 1258 dprintk("%s\n", __func__);
1372 1259
1373 switch (LDPC_Mode) { 1260 switch (LDPC_Mode) {
1374 case STV0900_DUAL: 1261 case STV0900_DUAL:
1375 default: 1262 default:
1376 if ((i_params->demod_mode != STV0900_DUAL) 1263 if ((intp->demod_mode != STV0900_DUAL)
1377 || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) { 1264 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1378 stv0900_write_reg(i_params, R0900_GENCFG, 0x1d); 1265 stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1379 1266
1380 i_params->demod_mode = STV0900_DUAL; 1267 intp->demod_mode = STV0900_DUAL;
1381 1268
1382 stv0900_write_bits(i_params, F0900_FRESFEC, 1); 1269 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1383 stv0900_write_bits(i_params, F0900_FRESFEC, 0); 1270 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1271
1272 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1273 stv0900_write_reg(intp,
1274 R0900_P1_MODCODLST0 + reg_ind,
1275 0xff);
1276 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1277 stv0900_write_reg(intp,
1278 R0900_P1_MODCODLST7 + reg_ind,
1279 0xcc);
1280
1281 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1282 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1283
1284 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1285 stv0900_write_reg(intp,
1286 R0900_P2_MODCODLST0 + reg_ind,
1287 0xff);
1288 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1289 stv0900_write_reg(intp,
1290 R0900_P2_MODCODLST7 + reg_ind,
1291 0xcc);
1292
1293 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1294 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1384 } 1295 }
1385 1296
1386 break; 1297 break;
1387 case STV0900_SINGLE: 1298 case STV0900_SINGLE:
1388 if (demod == STV0900_DEMOD_2) 1299 if (demod == STV0900_DEMOD_2) {
1389 stv0900_write_reg(i_params, R0900_GENCFG, 0x06); 1300 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1390 else 1301 stv0900_activate_s2_modcod_single(intp,
1391 stv0900_write_reg(i_params, R0900_GENCFG, 0x04); 1302 STV0900_DEMOD_2);
1303 stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1304 } else {
1305 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1306 stv0900_activate_s2_modcod_single(intp,
1307 STV0900_DEMOD_1);
1308 stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1309 }
1392 1310
1393 i_params->demod_mode = STV0900_SINGLE; 1311 intp->demod_mode = STV0900_SINGLE;
1394 1312
1395 stv0900_write_bits(i_params, F0900_FRESFEC, 1); 1313 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1396 stv0900_write_bits(i_params, F0900_FRESFEC, 0); 1314 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1397 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1); 1315 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1398 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0); 1316 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1399 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1); 1317 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1400 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0); 1318 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1401 break; 1319 break;
1402 } 1320 }
1403 1321
@@ -1410,6 +1328,8 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1410 struct stv0900_state *state = fe->demodulator_priv; 1328 struct stv0900_state *state = fe->demodulator_priv;
1411 enum fe_stv0900_error error = STV0900_NO_ERROR; 1329 enum fe_stv0900_error error = STV0900_NO_ERROR;
1412 enum fe_stv0900_error demodError = STV0900_NO_ERROR; 1330 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1331 struct stv0900_internal *intp = NULL;
1332
1413 int selosci, i; 1333 int selosci, i;
1414 1334
1415 struct stv0900_inode *temp_int = find_inode(state->i2c_adap, 1335 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
@@ -1423,7 +1343,8 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1423 dprintk("%s: Find Internal Structure!\n", __func__); 1343 dprintk("%s: Find Internal Structure!\n", __func__);
1424 return STV0900_NO_ERROR; 1344 return STV0900_NO_ERROR;
1425 } else { 1345 } else {
1426 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL); 1346 state->internal = kmalloc(sizeof(struct stv0900_internal),
1347 GFP_KERNEL);
1427 temp_int = append_internal(state->internal); 1348 temp_int = append_internal(state->internal);
1428 state->internal->dmds_used = 1; 1349 state->internal->dmds_used = 1;
1429 state->internal->i2c_adap = state->i2c_adap; 1350 state->internal->i2c_adap = state->i2c_adap;
@@ -1433,108 +1354,105 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1433 dprintk("%s: Create New Internal Structure!\n", __func__); 1354 dprintk("%s: Create New Internal Structure!\n", __func__);
1434 } 1355 }
1435 1356
1436 if (state->internal != NULL) { 1357 if (state->internal == NULL) {
1437 demodError = stv0900_initialize(state->internal); 1358 error = STV0900_INVALID_HANDLE;
1438 if (demodError == STV0900_NO_ERROR) { 1359 return error;
1439 error = STV0900_NO_ERROR; 1360 }
1440 } else {
1441 if (demodError == STV0900_INVALID_HANDLE)
1442 error = STV0900_INVALID_HANDLE;
1443 else
1444 error = STV0900_I2C_ERROR;
1445 }
1446 1361
1447 if (state->internal != NULL) { 1362 demodError = stv0900_initialize(state->internal);
1448 if (error == STV0900_NO_ERROR) { 1363 if (demodError == STV0900_NO_ERROR) {
1449 state->internal->demod_mode = p_init->demod_mode; 1364 error = STV0900_NO_ERROR;
1450 1365 } else {
1451 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1); 1366 if (demodError == STV0900_INVALID_HANDLE)
1452 1367 error = STV0900_INVALID_HANDLE;
1453 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID); 1368 else
1454 state->internal->rolloff = p_init->rolloff; 1369 error = STV0900_I2C_ERROR;
1455 state->internal->quartz = p_init->dmd_ref_clk;
1456
1457 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1458 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1459
1460 state->internal->ts_config = p_init->ts_config;
1461 if (state->internal->ts_config == NULL)
1462 stv0900_set_ts_parallel_serial(state->internal,
1463 p_init->path1_ts_clock,
1464 p_init->path2_ts_clock);
1465 else {
1466 for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
1467 stv0900_write_reg(state->internal,
1468 state->internal->ts_config[i].addr,
1469 state->internal->ts_config[i].val);
1470
1471 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
1472 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
1473 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
1474 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
1475 }
1476 1370
1477 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress); 1371 return error;
1478 switch (p_init->tuner1_adc) { 1372 }
1479 case 1:
1480 stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1481 break;
1482 default:
1483 break;
1484 }
1485 1373
1486 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress); 1374 if (state->internal == NULL) {
1487 switch (p_init->tuner2_adc) { 1375 error = STV0900_INVALID_HANDLE;
1488 case 1: 1376 return error;
1489 stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26); 1377 }
1490 break;
1491 default:
1492 break;
1493 }
1494 1378
1495 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion); 1379 intp = state->internal;
1496 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1497 stv0900_set_mclk(state->internal, 135000000);
1498 msleep(3);
1499
1500 switch (state->internal->clkmode) {
1501 case 0:
1502 case 2:
1503 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1504 break;
1505 default:
1506 selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1507 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1508 break;
1509 }
1510 msleep(3);
1511 1380
1512 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz); 1381 intp->demod_mode = p_init->demod_mode;
1513 if (state->internal->errs) 1382 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1514 error = STV0900_I2C_ERROR; 1383 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1515 } 1384 intp->rolloff = p_init->rolloff;
1516 } else { 1385 intp->quartz = p_init->dmd_ref_clk;
1517 error = STV0900_INVALID_HANDLE; 1386
1518 } 1387 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1388 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1389
1390 intp->ts_config = p_init->ts_config;
1391 if (intp->ts_config == NULL)
1392 stv0900_set_ts_parallel_serial(intp,
1393 p_init->path1_ts_clock,
1394 p_init->path2_ts_clock);
1395 else {
1396 for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1397 stv0900_write_reg(intp,
1398 intp->ts_config[i].addr,
1399 intp->ts_config[i].val);
1400
1401 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1402 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1403 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1404 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1405 }
1406
1407 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1408 switch (p_init->tuner1_adc) {
1409 case 1:
1410 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1411 break;
1412 default:
1413 break;
1414 }
1415
1416 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1417 switch (p_init->tuner2_adc) {
1418 case 1:
1419 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1420 break;
1421 default:
1422 break;
1519 } 1423 }
1520 1424
1425 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1426 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1427 stv0900_set_mclk(intp, 135000000);
1428 msleep(3);
1429
1430 switch (intp->clkmode) {
1431 case 0:
1432 case 2:
1433 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1434 break;
1435 default:
1436 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1437 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1438 break;
1439 }
1440 msleep(3);
1441
1442 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1443 if (intp->errs)
1444 error = STV0900_I2C_ERROR;
1445
1521 return error; 1446 return error;
1522} 1447}
1523 1448
1524static int stv0900_status(struct stv0900_internal *i_params, 1449static int stv0900_status(struct stv0900_internal *intp,
1525 enum fe_stv0900_demod_num demod) 1450 enum fe_stv0900_demod_num demod)
1526{ 1451{
1527 enum fe_stv0900_search_state demod_state; 1452 enum fe_stv0900_search_state demod_state;
1528 s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1529 int locked = FALSE; 1453 int locked = FALSE;
1530 1454
1531 dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1455 demod_state = stv0900_get_bits(intp, HEADER_MODE);
1532 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1533 dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1534 dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1535 dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1536
1537 demod_state = stv0900_get_bits(i_params, mode_field);
1538 switch (demod_state) { 1456 switch (demod_state) {
1539 case STV0900_SEARCH: 1457 case STV0900_SEARCH:
1540 case STV0900_PLH_DETECTED: 1458 case STV0900_PLH_DETECTED:
@@ -1542,17 +1460,19 @@ static int stv0900_status(struct stv0900_internal *i_params,
1542 locked = FALSE; 1460 locked = FALSE;
1543 break; 1461 break;
1544 case STV0900_DVBS2_FOUND: 1462 case STV0900_DVBS2_FOUND:
1545 locked = stv0900_get_bits(i_params, lock_field) && 1463 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1546 stv0900_get_bits(i_params, delin_field) && 1464 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1547 stv0900_get_bits(i_params, fifo_field); 1465 stv0900_get_bits(intp, TSFIFO_LINEOK);
1548 break; 1466 break;
1549 case STV0900_DVBS_FOUND: 1467 case STV0900_DVBS_FOUND:
1550 locked = stv0900_get_bits(i_params, lock_field) && 1468 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1551 stv0900_get_bits(i_params, lockedvit_field) && 1469 stv0900_get_bits(intp, LOCKEDVIT) &&
1552 stv0900_get_bits(i_params, fifo_field); 1470 stv0900_get_bits(intp, TSFIFO_LINEOK);
1553 break; 1471 break;
1554 } 1472 }
1555 1473
1474 dprintk("%s: locked = %d\n", __func__, locked);
1475
1556 return locked; 1476 return locked;
1557} 1477}
1558 1478
@@ -1560,7 +1480,8 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1560 struct dvb_frontend_parameters *params) 1480 struct dvb_frontend_parameters *params)
1561{ 1481{
1562 struct stv0900_state *state = fe->demodulator_priv; 1482 struct stv0900_state *state = fe->demodulator_priv;
1563 struct stv0900_internal *i_params = state->internal; 1483 struct stv0900_internal *intp = state->internal;
1484 enum fe_stv0900_demod_num demod = state->demod;
1564 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1485 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1565 1486
1566 struct stv0900_search_params p_search; 1487 struct stv0900_search_params p_search;
@@ -1570,8 +1491,11 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1570 1491
1571 dprintk("%s: ", __func__); 1492 dprintk("%s: ", __func__);
1572 1493
1494 if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1495 return DVBFE_ALGO_SEARCH_FAILED;
1496
1573 p_result.locked = FALSE; 1497 p_result.locked = FALSE;
1574 p_search.path = state->demod; 1498 p_search.path = demod;
1575 p_search.frequency = c->frequency; 1499 p_search.frequency = c->frequency;
1576 p_search.symbol_rate = c->symbol_rate; 1500 p_search.symbol_rate = c->symbol_rate;
1577 p_search.search_range = 10000000; 1501 p_search.search_range = 10000000;
@@ -1580,93 +1504,38 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1580 p_search.iq_inversion = STV0900_IQ_AUTO; 1504 p_search.iq_inversion = STV0900_IQ_AUTO;
1581 p_search.search_algo = STV0900_BLIND_SEARCH; 1505 p_search.search_algo = STV0900_BLIND_SEARCH;
1582 1506
1583 if ((INRANGE(100000, p_search.symbol_rate, 70000000)) && 1507 intp->srch_standard[demod] = p_search.standard;
1584 (INRANGE(100000, p_search.search_range, 50000000))) { 1508 intp->symbol_rate[demod] = p_search.symbol_rate;
1585 switch (p_search.path) { 1509 intp->srch_range[demod] = p_search.search_range;
1586 case STV0900_DEMOD_1: 1510 intp->freq[demod] = p_search.frequency;
1587 default: 1511 intp->srch_algo[demod] = p_search.search_algo;
1588 i_params->dmd1_srch_standard = p_search.standard; 1512 intp->srch_iq_inv[demod] = p_search.iq_inversion;
1589 i_params->dmd1_symbol_rate = p_search.symbol_rate; 1513 intp->fec[demod] = p_search.fec;
1590 i_params->dmd1_srch_range = p_search.search_range; 1514 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1591 i_params->tuner1_freq = p_search.frequency; 1515 (intp->errs == STV0900_NO_ERROR)) {
1592 i_params->dmd1_srch_algo = p_search.search_algo; 1516 p_result.locked = intp->result[demod].locked;
1593 i_params->dmd1_srch_iq_inv = p_search.iq_inversion; 1517 p_result.standard = intp->result[demod].standard;
1594 i_params->dmd1_fec = p_search.fec; 1518 p_result.frequency = intp->result[demod].frequency;
1519 p_result.symbol_rate = intp->result[demod].symbol_rate;
1520 p_result.fec = intp->result[demod].fec;
1521 p_result.modcode = intp->result[demod].modcode;
1522 p_result.pilot = intp->result[demod].pilot;
1523 p_result.frame_len = intp->result[demod].frame_len;
1524 p_result.spectrum = intp->result[demod].spectrum;
1525 p_result.rolloff = intp->result[demod].rolloff;
1526 p_result.modulation = intp->result[demod].modulation;
1527 } else {
1528 p_result.locked = FALSE;
1529 switch (intp->err[demod]) {
1530 case STV0900_I2C_ERROR:
1531 error = STV0900_I2C_ERROR;
1595 break; 1532 break;
1596 1533 case STV0900_NO_ERROR:
1597 case STV0900_DEMOD_2: 1534 default:
1598 i_params->dmd2_srch_stndrd = p_search.standard; 1535 error = STV0900_SEARCH_FAILED;
1599 i_params->dmd2_symbol_rate = p_search.symbol_rate;
1600 i_params->dmd2_srch_range = p_search.search_range;
1601 i_params->tuner2_freq = p_search.frequency;
1602 i_params->dmd2_srch_algo = p_search.search_algo;
1603 i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1604 i_params->dmd2_fec = p_search.fec;
1605 break; 1536 break;
1606 } 1537 }
1607 1538 }
1608 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1609 (i_params->errs == STV0900_NO_ERROR)) {
1610 switch (p_search.path) {
1611 case STV0900_DEMOD_1:
1612 default:
1613 p_result.locked = i_params->dmd1_rslts.locked;
1614 p_result.standard = i_params->dmd1_rslts.standard;
1615 p_result.frequency = i_params->dmd1_rslts.frequency;
1616 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1617 p_result.fec = i_params->dmd1_rslts.fec;
1618 p_result.modcode = i_params->dmd1_rslts.modcode;
1619 p_result.pilot = i_params->dmd1_rslts.pilot;
1620 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1621 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1622 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1623 p_result.modulation = i_params->dmd1_rslts.modulation;
1624 break;
1625 case STV0900_DEMOD_2:
1626 p_result.locked = i_params->dmd2_rslts.locked;
1627 p_result.standard = i_params->dmd2_rslts.standard;
1628 p_result.frequency = i_params->dmd2_rslts.frequency;
1629 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1630 p_result.fec = i_params->dmd2_rslts.fec;
1631 p_result.modcode = i_params->dmd2_rslts.modcode;
1632 p_result.pilot = i_params->dmd2_rslts.pilot;
1633 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1634 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1635 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1636 p_result.modulation = i_params->dmd2_rslts.modulation;
1637 break;
1638 }
1639
1640 } else {
1641 p_result.locked = FALSE;
1642 switch (p_search.path) {
1643 case STV0900_DEMOD_1:
1644 switch (i_params->dmd1_err) {
1645 case STV0900_I2C_ERROR:
1646 error = STV0900_I2C_ERROR;
1647 break;
1648 case STV0900_NO_ERROR:
1649 default:
1650 error = STV0900_SEARCH_FAILED;
1651 break;
1652 }
1653 break;
1654 case STV0900_DEMOD_2:
1655 switch (i_params->dmd2_err) {
1656 case STV0900_I2C_ERROR:
1657 error = STV0900_I2C_ERROR;
1658 break;
1659 case STV0900_NO_ERROR:
1660 default:
1661 error = STV0900_SEARCH_FAILED;
1662 break;
1663 }
1664 break;
1665 }
1666 }
1667
1668 } else
1669 error = STV0900_BAD_PARAMETER;
1670 1539
1671 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) { 1540 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1672 dprintk("Search Success\n"); 1541 dprintk("Search Success\n");
@@ -1676,7 +1545,6 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1676 return DVBFE_ALGO_SEARCH_FAILED; 1545 return DVBFE_ALGO_SEARCH_FAILED;
1677 } 1546 }
1678 1547
1679 return DVBFE_ALGO_SEARCH_ERROR;
1680} 1548}
1681 1549
1682static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status) 1550static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
@@ -1707,16 +1575,13 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1707{ 1575{
1708 1576
1709 struct stv0900_state *state = fe->demodulator_priv; 1577 struct stv0900_state *state = fe->demodulator_priv;
1710 struct stv0900_internal *i_params = state->internal; 1578 struct stv0900_internal *intp = state->internal;
1711 enum fe_stv0900_demod_num demod = state->demod; 1579 enum fe_stv0900_demod_num demod = state->demod;
1712 s32 rst_field;
1713
1714 dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1715 1580
1716 if (stop_ts == TRUE) 1581 if (stop_ts == TRUE)
1717 stv0900_write_bits(i_params, rst_field, 1); 1582 stv0900_write_bits(intp, RST_HWARE, 1);
1718 else 1583 else
1719 stv0900_write_bits(i_params, rst_field, 0); 1584 stv0900_write_bits(intp, RST_HWARE, 0);
1720 1585
1721 return 0; 1586 return 0;
1722} 1587}
@@ -1724,16 +1589,12 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1724static int stv0900_diseqc_init(struct dvb_frontend *fe) 1589static int stv0900_diseqc_init(struct dvb_frontend *fe)
1725{ 1590{
1726 struct stv0900_state *state = fe->demodulator_priv; 1591 struct stv0900_state *state = fe->demodulator_priv;
1727 struct stv0900_internal *i_params = state->internal; 1592 struct stv0900_internal *intp = state->internal;
1728 enum fe_stv0900_demod_num demod = state->demod; 1593 enum fe_stv0900_demod_num demod = state->demod;
1729 s32 mode_field, reset_field;
1730 1594
1731 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE); 1595 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1732 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET); 1596 stv0900_write_bits(intp, DISEQC_RESET, 1);
1733 1597 stv0900_write_bits(intp, DISEQC_RESET, 0);
1734 stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1735 stv0900_write_bits(i_params, reset_field, 1);
1736 stv0900_write_bits(i_params, reset_field, 0);
1737 1598
1738 return 0; 1599 return 0;
1739} 1600}
@@ -1748,47 +1609,24 @@ static int stv0900_init(struct dvb_frontend *fe)
1748 return 0; 1609 return 0;
1749} 1610}
1750 1611
1751static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data, 1612static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1752 u32 NbData, enum fe_stv0900_demod_num demod) 1613 u32 NbData, enum fe_stv0900_demod_num demod)
1753{ 1614{
1754 s32 i = 0; 1615 s32 i = 0;
1755 1616
1756 switch (demod) { 1617 stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1757 case STV0900_DEMOD_1: 1618 while (i < NbData) {
1758 default: 1619 while (stv0900_get_bits(intp, FIFO_FULL))
1759 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1); 1620 ;/* checkpatch complains */
1760 while (i < NbData) { 1621 stv0900_write_reg(intp, DISTXDATA, data[i]);
1761 while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL)) 1622 i++;
1762 ;/* checkpatch complains */ 1623 }
1763 stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1764 i++;
1765 }
1766
1767 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1768 i = 0;
1769 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1770 msleep(10);
1771 i++;
1772 }
1773
1774 break;
1775 case STV0900_DEMOD_2:
1776 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1777
1778 while (i < NbData) {
1779 while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1780 ;/* checkpatch complains */
1781 stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1782 i++;
1783 }
1784 1624
1785 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0); 1625 stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1786 i = 0; 1626 i = 0;
1787 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) { 1627 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1788 msleep(10); 1628 msleep(10);
1789 i++; 1629 i++;
1790 }
1791 break;
1792 } 1630 }
1793 1631
1794 return 0; 1632 return 0;
@@ -1808,23 +1646,21 @@ static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1808static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 1646static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1809{ 1647{
1810 struct stv0900_state *state = fe->demodulator_priv; 1648 struct stv0900_state *state = fe->demodulator_priv;
1811 struct stv0900_internal *i_params = state->internal; 1649 struct stv0900_internal *intp = state->internal;
1812 enum fe_stv0900_demod_num demod = state->demod; 1650 enum fe_stv0900_demod_num demod = state->demod;
1813 s32 mode_field;
1814 u8 data; 1651 u8 data;
1815 1652
1816 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1817 1653
1818 switch (burst) { 1654 switch (burst) {
1819 case SEC_MINI_A: 1655 case SEC_MINI_A:
1820 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */ 1656 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
1821 data = 0x00; 1657 data = 0x00;
1822 stv0900_diseqc_send(state->internal, &data, 1, state->demod); 1658 stv0900_diseqc_send(intp, &data, 1, state->demod);
1823 break; 1659 break;
1824 case SEC_MINI_B: 1660 case SEC_MINI_B:
1825 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */ 1661 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
1826 data = 0xff; 1662 data = 0xff;
1827 stv0900_diseqc_send(state->internal, &data, 1, state->demod); 1663 stv0900_diseqc_send(intp, &data, 1, state->demod);
1828 break; 1664 break;
1829 } 1665 }
1830 1666
@@ -1835,41 +1671,22 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1835 struct dvb_diseqc_slave_reply *reply) 1671 struct dvb_diseqc_slave_reply *reply)
1836{ 1672{
1837 struct stv0900_state *state = fe->demodulator_priv; 1673 struct stv0900_state *state = fe->demodulator_priv;
1838 struct stv0900_internal *i_params = state->internal; 1674 struct stv0900_internal *intp = state->internal;
1675 enum fe_stv0900_demod_num demod = state->demod;
1839 s32 i = 0; 1676 s32 i = 0;
1840 1677
1841 switch (state->demod) { 1678 reply->msg_len = 0;
1842 case STV0900_DEMOD_1:
1843 default:
1844 reply->msg_len = 0;
1845
1846 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1847 msleep(10);
1848 i++;
1849 }
1850
1851 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1852 reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1853 1679
1854 for (i = 0; i < reply->msg_len; i++) 1680 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1855 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA); 1681 msleep(10);
1856 } 1682 i++;
1857 break; 1683 }
1858 case STV0900_DEMOD_2:
1859 reply->msg_len = 0;
1860
1861 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
1862 msleep(10);
1863 i++;
1864 }
1865 1684
1866 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) { 1685 if (stv0900_get_bits(intp, RX_END)) {
1867 reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR); 1686 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1868 1687
1869 for (i = 0; i < reply->msg_len; i++) 1688 for (i = 0; i < reply->msg_len; i++)
1870 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA); 1689 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1871 }
1872 break;
1873 } 1690 }
1874 1691
1875 return 0; 1692 return 0;
@@ -1878,31 +1695,27 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1878static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff) 1695static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
1879{ 1696{
1880 struct stv0900_state *state = fe->demodulator_priv; 1697 struct stv0900_state *state = fe->demodulator_priv;
1881 struct stv0900_internal *i_params = state->internal; 1698 struct stv0900_internal *intp = state->internal;
1882 enum fe_stv0900_demod_num demod = state->demod; 1699 enum fe_stv0900_demod_num demod = state->demod;
1883 s32 mode_field, reset_field;
1884 1700
1885 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off")); 1701 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1886 1702
1887 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1888 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1889
1890 switch (toneoff) { 1703 switch (toneoff) {
1891 case SEC_TONE_ON: 1704 case SEC_TONE_ON:
1892 /*Set the DiseqC mode to 22Khz _continues_ tone*/ 1705 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1893 stv0900_write_bits(i_params, mode_field, 0); 1706 stv0900_write_bits(intp, DISTX_MODE, 0);
1894 stv0900_write_bits(i_params, reset_field, 1); 1707 stv0900_write_bits(intp, DISEQC_RESET, 1);
1895 /*release DiseqC reset to enable the 22KHz tone*/ 1708 /*release DiseqC reset to enable the 22KHz tone*/
1896 stv0900_write_bits(i_params, reset_field, 0); 1709 stv0900_write_bits(intp, DISEQC_RESET, 0);
1897 break; 1710 break;
1898 case SEC_TONE_OFF: 1711 case SEC_TONE_OFF:
1899 /*return diseqc mode to config->diseqc_mode. 1712 /*return diseqc mode to config->diseqc_mode.
1900 Usually it's without _continues_ tone */ 1713 Usually it's without _continues_ tone */
1901 stv0900_write_bits(i_params, mode_field, 1714 stv0900_write_bits(intp, DISTX_MODE,
1902 state->config->diseqc_mode); 1715 state->config->diseqc_mode);
1903 /*maintain the DiseqC reset to disable the 22KHz tone*/ 1716 /*maintain the DiseqC reset to disable the 22KHz tone*/
1904 stv0900_write_bits(i_params, reset_field, 1); 1717 stv0900_write_bits(intp, DISEQC_RESET, 1);
1905 stv0900_write_bits(i_params, reset_field, 0); 1718 stv0900_write_bits(intp, DISEQC_RESET, 0);
1906 break; 1719 break;
1907 default: 1720 default:
1908 return -EINVAL; 1721 return -EINVAL;
@@ -1993,13 +1806,13 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1993 init_params.rolloff = STV0900_35; 1806 init_params.rolloff = STV0900_35;
1994 init_params.path1_ts_clock = config->path1_mode; 1807 init_params.path1_ts_clock = config->path1_mode;
1995 init_params.tun1_maddress = config->tun1_maddress; 1808 init_params.tun1_maddress = config->tun1_maddress;
1996 init_params.tun1_iq_inversion = STV0900_IQ_NORMAL; 1809 init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
1997 init_params.tuner1_adc = config->tun1_adc; 1810 init_params.tuner1_adc = config->tun1_adc;
1998 init_params.path2_ts_clock = config->path2_mode; 1811 init_params.path2_ts_clock = config->path2_mode;
1999 init_params.ts_config = config->ts_config_regs; 1812 init_params.ts_config = config->ts_config_regs;
2000 init_params.tun2_maddress = config->tun2_maddress; 1813 init_params.tun2_maddress = config->tun2_maddress;
2001 init_params.tuner2_adc = config->tun2_adc; 1814 init_params.tuner2_adc = config->tun2_adc;
2002 init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED; 1815 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
2003 1816
2004 err_stv0900 = stv0900_init_internal(&state->frontend, 1817 err_stv0900 = stv0900_init_internal(&state->frontend,
2005 &init_params); 1818 &init_params);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 09:57:06 -0500