aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/media/dvb/frontends/ves1x93.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/media/dvb/frontends/ves1x93.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/media/dvb/frontends/ves1x93.c')
-rw-r--r--drivers/media/dvb/frontends/ves1x93.c545
1 files changed, 545 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/ves1x93.c b/drivers/media/dvb/frontends/ves1x93.c
new file mode 100644
index 000000000000..edcad283aa86
--- /dev/null
+++ b/drivers/media/dvb/frontends/ves1x93.c
@@ -0,0 +1,545 @@
1/*
2 Driver for VES1893 and VES1993 QPSK Demodulators
3
4 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
5 Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de>
6 Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de>
7 Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24*/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32
33#include "dvb_frontend.h"
34#include "ves1x93.h"
35
36
37struct ves1x93_state {
38 struct i2c_adapter* i2c;
39 struct dvb_frontend_ops ops;
40 /* configuration settings */
41 const struct ves1x93_config* config;
42 struct dvb_frontend frontend;
43
44 /* previous uncorrected block counter */
45 fe_spectral_inversion_t inversion;
46 u8 *init_1x93_tab;
47 u8 *init_1x93_wtab;
48 u8 tab_size;
49 u8 demod_type;
50};
51
52static int debug = 0;
53#define dprintk if (debug) printk
54
55#define DEMOD_VES1893 0
56#define DEMOD_VES1993 1
57
58static u8 init_1893_tab [] = {
59 0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
60 0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
61 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
62 0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
63 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
64 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
65 0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
66};
67
68static u8 init_1993_tab [] = {
69 0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
70 0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
71 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
73 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
76 0x00, 0x00, 0x0e, 0x80, 0x00
77};
78
79static u8 init_1893_wtab[] =
80{
81 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
82 0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
83 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
84 1,1,1,0,1,1
85};
86
87static u8 init_1993_wtab[] =
88{
89 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
90 0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
91 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
92 1,1,1,0,1,1,1,1, 1,1,1,1,1
93};
94
95static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
96{
97 u8 buf [] = { 0x00, reg, data };
98 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
99 int err;
100
101 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
102 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
103 return -EREMOTEIO;
104 }
105
106 return 0;
107}
108
109static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
110{
111 int ret;
112 u8 b0 [] = { 0x00, reg };
113 u8 b1 [] = { 0 };
114 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
115 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
116
117 ret = i2c_transfer (state->i2c, msg, 2);
118
119 if (ret != 2) return ret;
120
121 return b1[0];
122}
123
124static int ves1x93_clr_bit (struct ves1x93_state* state)
125{
126 msleep(10);
127 ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
128 ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
129 msleep(50);
130 return 0;
131}
132
133static int ves1x93_set_inversion (struct ves1x93_state* state, fe_spectral_inversion_t inversion)
134{
135 u8 val;
136
137 /*
138 * inversion on/off are interchanged because i and q seem to
139 * be swapped on the hardware
140 */
141
142 switch (inversion) {
143 case INVERSION_OFF:
144 val = 0xc0;
145 break;
146 case INVERSION_ON:
147 val = 0x80;
148 break;
149 case INVERSION_AUTO:
150 val = 0x00;
151 break;
152 default:
153 return -EINVAL;
154 }
155
156 return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
157}
158
159static int ves1x93_set_fec (struct ves1x93_state* state, fe_code_rate_t fec)
160{
161 if (fec == FEC_AUTO)
162 return ves1x93_writereg (state, 0x0d, 0x08);
163 else if (fec < FEC_1_2 || fec > FEC_8_9)
164 return -EINVAL;
165 else
166 return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
167}
168
169static fe_code_rate_t ves1x93_get_fec (struct ves1x93_state* state)
170{
171 return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
172}
173
174static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
175{
176 u32 BDR;
177 u32 ratio;
178 u8 ADCONF, FCONF, FNR, AGCR;
179 u32 BDRI;
180 u32 tmp;
181 u32 FIN;
182
183 dprintk("%s: srate == %d\n", __FUNCTION__, (unsigned int) srate);
184
185 if (srate > state->config->xin/2)
186 srate = state->config->xin/2;
187
188 if (srate < 500000)
189 srate = 500000;
190
191#define MUL (1UL<<26)
192
193 FIN = (state->config->xin + 6000) >> 4;
194
195 tmp = srate << 6;
196 ratio = tmp / FIN;
197
198 tmp = (tmp % FIN) << 8;
199 ratio = (ratio << 8) + tmp / FIN;
200
201 tmp = (tmp % FIN) << 8;
202 ratio = (ratio << 8) + tmp / FIN;
203
204 FNR = 0xff;
205
206 if (ratio < MUL/3) FNR = 0;
207 if (ratio < (MUL*11)/50) FNR = 1;
208 if (ratio < MUL/6) FNR = 2;
209 if (ratio < MUL/9) FNR = 3;
210 if (ratio < MUL/12) FNR = 4;
211 if (ratio < (MUL*11)/200) FNR = 5;
212 if (ratio < MUL/24) FNR = 6;
213 if (ratio < (MUL*27)/1000) FNR = 7;
214 if (ratio < MUL/48) FNR = 8;
215 if (ratio < (MUL*137)/10000) FNR = 9;
216
217 if (FNR == 0xff) {
218 ADCONF = 0x89;
219 FCONF = 0x80;
220 FNR = 0;
221 } else {
222 ADCONF = 0x81;
223 FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
224 /*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/
225 }
226
227 BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
228 BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
229
230 dprintk("FNR= %d\n", FNR);
231 dprintk("ratio= %08x\n", (unsigned int) ratio);
232 dprintk("BDR= %08x\n", (unsigned int) BDR);
233 dprintk("BDRI= %02x\n", (unsigned int) BDRI);
234
235 if (BDRI > 0xff)
236 BDRI = 0xff;
237
238 ves1x93_writereg (state, 0x06, 0xff & BDR);
239 ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
240 ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
241
242 ves1x93_writereg (state, 0x09, BDRI);
243 ves1x93_writereg (state, 0x20, ADCONF);
244 ves1x93_writereg (state, 0x21, FCONF);
245
246 AGCR = state->init_1x93_tab[0x05];
247 if (state->config->invert_pwm)
248 AGCR |= 0x20;
249
250 if (srate < 6000000)
251 AGCR |= 0x80;
252 else
253 AGCR &= ~0x80;
254
255 ves1x93_writereg (state, 0x05, AGCR);
256
257 /* ves1993 hates this, will lose lock */
258 if (state->demod_type != DEMOD_VES1993)
259 ves1x93_clr_bit (state);
260
261 return 0;
262}
263
264static int ves1x93_init (struct dvb_frontend* fe)
265{
266 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
267 int i;
268 int val;
269
270 dprintk("%s: init chip\n", __FUNCTION__);
271
272 for (i = 0; i < state->tab_size; i++) {
273 if (state->init_1x93_wtab[i]) {
274 val = state->init_1x93_tab[i];
275
276 if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */
277 ves1x93_writereg (state, i, val);
278 }
279 }
280
281 if (state->config->pll_init) {
282 ves1x93_writereg(state, 0x00, 0x11);
283 state->config->pll_init(fe);
284 ves1x93_writereg(state, 0x00, 0x01);
285 }
286
287 return 0;
288}
289
290static int ves1x93_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
291{
292 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
293
294 switch (voltage) {
295 case SEC_VOLTAGE_13:
296 return ves1x93_writereg (state, 0x1f, 0x20);
297 case SEC_VOLTAGE_18:
298 return ves1x93_writereg (state, 0x1f, 0x30);
299 case SEC_VOLTAGE_OFF:
300 return ves1x93_writereg (state, 0x1f, 0x00);
301 default:
302 return -EINVAL;
303 }
304}
305
306static int ves1x93_read_status(struct dvb_frontend* fe, fe_status_t* status)
307{
308 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
309
310 u8 sync = ves1x93_readreg (state, 0x0e);
311
312 /*
313 * The ves1893 sometimes returns sync values that make no sense,
314 * because, e.g., the SIGNAL bit is 0, while some of the higher
315 * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
316 * Tests showed that the the VITERBI and SYNC bits are returned
317 * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
318 * If such a case occurs, we read the value again, until we get a
319 * valid value.
320 */
321 int maxtry = 10; /* just for safety - let's not get stuck here */
322 while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
323 msleep(10);
324 sync = ves1x93_readreg (state, 0x0e);
325 }
326
327 *status = 0;
328
329 if (sync & 1)
330 *status |= FE_HAS_SIGNAL;
331
332 if (sync & 2)
333 *status |= FE_HAS_CARRIER;
334
335 if (sync & 4)
336 *status |= FE_HAS_VITERBI;
337
338 if (sync & 8)
339 *status |= FE_HAS_SYNC;
340
341 if ((sync & 0x1f) == 0x1f)
342 *status |= FE_HAS_LOCK;
343
344 return 0;
345}
346
347static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
348{
349 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
350
351 *ber = ves1x93_readreg (state, 0x15);
352 *ber |= (ves1x93_readreg (state, 0x16) << 8);
353 *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
354 *ber *= 10;
355
356 return 0;
357}
358
359static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
360{
361 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
362
363 u8 signal = ~ves1x93_readreg (state, 0x0b);
364 *strength = (signal << 8) | signal;
365
366 return 0;
367}
368
369static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
370{
371 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
372
373 u8 _snr = ~ves1x93_readreg (state, 0x1c);
374 *snr = (_snr << 8) | _snr;
375
376 return 0;
377}
378
379static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
380{
381 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
382
383 *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;
384
385 if (*ucblocks == 0x7f)
386 *ucblocks = 0xffffffff; /* counter overflow... */
387
388 ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
389 ves1x93_writereg (state, 0x18, 0x80); /* dto. */
390
391 return 0;
392}
393
394static int ves1x93_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
395{
396 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
397
398 ves1x93_writereg(state, 0x00, 0x11);
399 state->config->pll_set(fe, p);
400 ves1x93_writereg(state, 0x00, 0x01);
401 ves1x93_set_inversion (state, p->inversion);
402 ves1x93_set_fec (state, p->u.qpsk.fec_inner);
403 ves1x93_set_symbolrate (state, p->u.qpsk.symbol_rate);
404 state->inversion = p->inversion;
405
406 return 0;
407}
408
409static int ves1x93_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
410{
411 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
412 int afc;
413
414 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
415 afc = (afc * (int)(p->u.qpsk.symbol_rate/1000/8))/16;
416
417 p->frequency -= afc;
418
419 /*
420 * inversion indicator is only valid
421 * if auto inversion was used
422 */
423 if (state->inversion == INVERSION_AUTO)
424 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
425 INVERSION_OFF : INVERSION_ON;
426 p->u.qpsk.fec_inner = ves1x93_get_fec (state);
427 /* XXX FIXME: timing offset !! */
428
429 return 0;
430}
431
432static int ves1x93_sleep(struct dvb_frontend* fe)
433{
434 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
435
436 return ves1x93_writereg (state, 0x00, 0x08);
437}
438
439static void ves1x93_release(struct dvb_frontend* fe)
440{
441 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
442 kfree(state);
443}
444
445static struct dvb_frontend_ops ves1x93_ops;
446
447struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
448 struct i2c_adapter* i2c)
449{
450 struct ves1x93_state* state = NULL;
451 u8 identity;
452
453 /* allocate memory for the internal state */
454 state = (struct ves1x93_state*) kmalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
455 if (state == NULL) goto error;
456
457 /* setup the state */
458 state->config = config;
459 state->i2c = i2c;
460 memcpy(&state->ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
461 state->inversion = INVERSION_OFF;
462
463 /* check if the demod is there + identify it */
464 identity = ves1x93_readreg(state, 0x1e);
465 switch (identity) {
466 case 0xdc: /* VES1893A rev1 */
467 printk("ves1x93: Detected ves1893a rev1\n");
468 state->demod_type = DEMOD_VES1893;
469 state->init_1x93_tab = init_1893_tab;
470 state->init_1x93_wtab = init_1893_wtab;
471 state->tab_size = sizeof(init_1893_tab);
472 break;
473
474 case 0xdd: /* VES1893A rev2 */
475 printk("ves1x93: Detected ves1893a rev2\n");
476 state->demod_type = DEMOD_VES1893;
477 state->init_1x93_tab = init_1893_tab;
478 state->init_1x93_wtab = init_1893_wtab;
479 state->tab_size = sizeof(init_1893_tab);
480 break;
481
482 case 0xde: /* VES1993 */
483 printk("ves1x93: Detected ves1993\n");
484 state->demod_type = DEMOD_VES1993;
485 state->init_1x93_tab = init_1993_tab;
486 state->init_1x93_wtab = init_1993_wtab;
487 state->tab_size = sizeof(init_1993_tab);
488 break;
489
490 default:
491 goto error;
492 }
493
494 /* create dvb_frontend */
495 state->frontend.ops = &state->ops;
496 state->frontend.demodulator_priv = state;
497 return &state->frontend;
498
499error:
500 kfree(state);
501 return NULL;
502}
503
504static struct dvb_frontend_ops ves1x93_ops = {
505
506 .info = {
507 .name = "VLSI VES1x93 DVB-S",
508 .type = FE_QPSK,
509 .frequency_min = 950000,
510 .frequency_max = 2150000,
511 .frequency_stepsize = 125, /* kHz for QPSK frontends */
512 .frequency_tolerance = 29500,
513 .symbol_rate_min = 1000000,
514 .symbol_rate_max = 45000000,
515 /* .symbol_rate_tolerance = ???,*/
516 .caps = FE_CAN_INVERSION_AUTO |
517 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
518 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
519 FE_CAN_QPSK
520 },
521
522 .release = ves1x93_release,
523
524 .init = ves1x93_init,
525 .sleep = ves1x93_sleep,
526
527 .set_frontend = ves1x93_set_frontend,
528 .get_frontend = ves1x93_get_frontend,
529
530 .read_status = ves1x93_read_status,
531 .read_ber = ves1x93_read_ber,
532 .read_signal_strength = ves1x93_read_signal_strength,
533 .read_snr = ves1x93_read_snr,
534 .read_ucblocks = ves1x93_read_ucblocks,
535
536 .set_voltage = ves1x93_set_voltage,
537};
538
539module_param(debug, int, 0644);
540
541MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
542MODULE_AUTHOR("Ralph Metzler");
543MODULE_LICENSE("GPL");
544
545EXPORT_SYMBOL(ves1x93_attach);