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authorPatrick Boettcher <pb@linuxtv.org>2008-04-13 14:47:53 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-04-24 13:09:39 -0400
commitdbad108bdcb30629c850f5606949510da010a686 (patch)
tree9d1460aaec7ec5be9c1374a86b8a6bc7b8b0c42d /drivers/media/dvb/frontends/s5h1420.c
parent44dc733cd9edac53402d705cd2f720accd0b3e2c (diff)
V4L/DVB (7568): Support for DVB-S demod PN1010 (clone of S5H1420) added
This device is a clone of the PN1010 used by SkyStar2 rev2.7 . This patch adds support for the flexcop-device and makes the driver look a little bit nicer. It needs to be checked whether the driver is still ok for the budget-cards. Signed-off-by: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/s5h1420.c')
-rw-r--r--drivers/media/dvb/frontends/s5h1420.c521
1 files changed, 332 insertions, 189 deletions
diff --git a/drivers/media/dvb/frontends/s5h1420.c b/drivers/media/dvb/frontends/s5h1420.c
index 1e2d602d371a..281e1cb2edc6 100644
--- a/drivers/media/dvb/frontends/s5h1420.c
+++ b/drivers/media/dvb/frontends/s5h1420.c
@@ -1,24 +1,26 @@
1/* 1/*
2Driver for Samsung S5H1420 QPSK Demodulator 2 * Driver for
3 3 * Samsung S5H1420 and
4Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net> 4 * PnpNetwork PN1010 QPSK Demodulator
5 5 *
6This program is free software; you can redistribute it and/or modify 6 * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
7it under the terms of the GNU General Public License as published by 7 * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
8the Free Software Foundation; either version 2 of the License, or 8 *
9(at your option) any later version. 9 * This program is free software; you can redistribute it and/or modify
10 10 * it under the terms of the GNU General Public License as published by
11This program is distributed in the hope that it will be useful, 11 * the Free Software Foundation; either version 2 of the License, or
12but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * (at your option) any later version.
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 *
14 14 * This program is distributed in the hope that it will be useful,
15GNU General Public License for more details. 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17You should have received a copy of the GNU General Public License 17 *
18along with this program; if not, write to the Free Software 18 * GNU General Public License for more details.
19Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 *
20 20 * You should have received a copy of the GNU General Public License
21*/ 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
22 24
23#include <linux/kernel.h> 25#include <linux/kernel.h>
24#include <linux/module.h> 26#include <linux/module.h>
@@ -29,23 +31,35 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29#include <linux/jiffies.h> 31#include <linux/jiffies.h>
30#include <asm/div64.h> 32#include <asm/div64.h>
31 33
32#include "dvb_frontend.h" 34#include <linux/i2c.h>
33#include "s5h1420.h"
34 35
35 36
37#include "dvb_frontend.h"
38#include "s5h1420.h"
39#include "s5h1420_priv.h"
36 40
37#define TONE_FREQ 22000 41#define TONE_FREQ 22000
38 42
39struct s5h1420_state { 43struct s5h1420_state {
40 struct i2c_adapter* i2c; 44 struct i2c_adapter* i2c;
41 const struct s5h1420_config* config; 45 const struct s5h1420_config* config;
46
42 struct dvb_frontend frontend; 47 struct dvb_frontend frontend;
48 struct i2c_adapter tuner_i2c_adapter;
49
50 u8 CON_1_val;
43 51
44 u8 postlocked:1; 52 u8 postlocked:1;
45 u32 fclk; 53 u32 fclk;
46 u32 tunedfreq; 54 u32 tunedfreq;
47 fe_code_rate_t fec_inner; 55 fe_code_rate_t fec_inner;
48 u32 symbol_rate; 56 u32 symbol_rate;
57
58 /* FIXME: ugly workaround for flexcop's incapable i2c-controller
59 * it does not support repeated-start, workaround: write addr-1
60 * and then read
61 */
62 u8 shadow[255];
49}; 63};
50 64
51static u32 s5h1420_getsymbolrate(struct s5h1420_state* state); 65static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
@@ -54,43 +68,65 @@ static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
54 68
55 69
56static int debug; 70static int debug;
57#define dprintk if (debug) printk 71module_param(debug, int, 0644);
72MODULE_PARM_DESC(debug, "enable debugging");
73
74#define dprintk(x...) do { \
75 if (debug) \
76 printk(KERN_DEBUG "S5H1420: " x); \
77} while (0)
78
79static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
80{
81 int ret;
82 u8 b[2];
83 struct i2c_msg msg[] = {
84 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
85 { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
86 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
87 };
88
89 b[0] = (reg - 1) & 0xff;
90 b[1] = state->shadow[(reg - 1) & 0xff];
91
92 if (state->config->repeated_start_workaround) {
93 ret = i2c_transfer(state->i2c, msg, 3);
94 if (ret != 3)
95 return ret;
96 } else {
97 ret = i2c_transfer(state->i2c, &msg[1], 2);
98 if (ret != 2)
99 return ret;
100 }
101
102 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
103
104 return b[0];
105}
58 106
59static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) 107static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
60{ 108{
61 u8 buf [] = { reg, data }; 109 u8 buf[] = { reg, data };
62 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; 110 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
63 int err; 111 int err;
64 112
65 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { 113 /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
66 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); 114 err = i2c_transfer(state->i2c, &msg, 1);
115 if (err != 1) {
116 dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
67 return -EREMOTEIO; 117 return -EREMOTEIO;
68 } 118 }
119 state->shadow[reg] = data;
69 120
70 return 0; 121 return 0;
71} 122}
72 123
73static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
74{
75 int ret;
76 u8 b0 [] = { reg };
77 u8 b1 [] = { 0 };
78 struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
79 struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
80
81 if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
82 return ret;
83
84 if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
85 return ret;
86
87 return b1[0];
88}
89
90static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage) 124static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
91{ 125{
92 struct s5h1420_state* state = fe->demodulator_priv; 126 struct s5h1420_state* state = fe->demodulator_priv;
93 127
128 dprintk("enter %s\n", __func__);
129
94 switch(voltage) { 130 switch(voltage) {
95 case SEC_VOLTAGE_13: 131 case SEC_VOLTAGE_13:
96 s5h1420_writereg(state, 0x3c, 132 s5h1420_writereg(state, 0x3c,
@@ -106,6 +142,7 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
106 break; 142 break;
107 } 143 }
108 144
145 dprintk("leave %s\n", __func__);
109 return 0; 146 return 0;
110} 147}
111 148
@@ -113,6 +150,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
113{ 150{
114 struct s5h1420_state* state = fe->demodulator_priv; 151 struct s5h1420_state* state = fe->demodulator_priv;
115 152
153 dprintk("enter %s\n", __func__);
116 switch(tone) { 154 switch(tone) {
117 case SEC_TONE_ON: 155 case SEC_TONE_ON:
118 s5h1420_writereg(state, 0x3b, 156 s5h1420_writereg(state, 0x3b,
@@ -124,6 +162,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
124 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); 162 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
125 break; 163 break;
126 } 164 }
165 dprintk("leave %s\n", __func__);
127 166
128 return 0; 167 return 0;
129} 168}
@@ -137,6 +176,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
137 unsigned long timeout; 176 unsigned long timeout;
138 int result = 0; 177 int result = 0;
139 178
179 dprintk("enter %s\n", __func__);
140 if (cmd->msg_len > 8) 180 if (cmd->msg_len > 8)
141 return -EINVAL; 181 return -EINVAL;
142 182
@@ -168,6 +208,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
168 /* restore original settings */ 208 /* restore original settings */
169 s5h1420_writereg(state, 0x3b, val); 209 s5h1420_writereg(state, 0x3b, val);
170 msleep(15); 210 msleep(15);
211 dprintk("leave %s\n", __func__);
171 return result; 212 return result;
172} 213}
173 214
@@ -289,6 +330,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
289 struct s5h1420_state* state = fe->demodulator_priv; 330 struct s5h1420_state* state = fe->demodulator_priv;
290 u8 val; 331 u8 val;
291 332
333 dprintk("enter %s\n", __func__);
334
292 if (status == NULL) 335 if (status == NULL)
293 return -EINVAL; 336 return -EINVAL;
294 337
@@ -297,13 +340,13 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
297 340
298 /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert 341 /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
299 the inversion, wait a bit and check again */ 342 the inversion, wait a bit and check again */
300 if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) { 343 if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
301 val = s5h1420_readreg(state, 0x32); 344 val = s5h1420_readreg(state, Vit10);
302 if ((val & 0x07) == 0x03) { 345 if ((val & 0x07) == 0x03) {
303 if (val & 0x08) 346 if (val & 0x08)
304 s5h1420_writereg(state, 0x31, 0x13); 347 s5h1420_writereg(state, Vit09, 0x13);
305 else 348 else
306 s5h1420_writereg(state, 0x31, 0x1b); 349 s5h1420_writereg(state, Vit09, 0x1b);
307 350
308 /* wait a bit then update lock status */ 351 /* wait a bit then update lock status */
309 mdelay(200); 352 mdelay(200);
@@ -312,68 +355,73 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
312 } 355 }
313 356
314 /* perform post lock setup */ 357 /* perform post lock setup */
315 if ((*status & FE_HAS_LOCK) && (!state->postlocked)) { 358 if ((*status & FE_HAS_LOCK) && !state->postlocked) {
316 359
317 /* calculate the data rate */ 360 /* calculate the data rate */
318 u32 tmp = s5h1420_getsymbolrate(state); 361 u32 tmp = s5h1420_getsymbolrate(state);
319 switch(s5h1420_readreg(state, 0x32) & 0x07) { 362 switch (s5h1420_readreg(state, Vit10) & 0x07) {
320 case 0: 363 case 0: tmp = (tmp * 2 * 1) / 2; break;
321 tmp = (tmp * 2 * 1) / 2; 364 case 1: tmp = (tmp * 2 * 2) / 3; break;
322 break; 365 case 2: tmp = (tmp * 2 * 3) / 4; break;
323 366 case 3: tmp = (tmp * 2 * 5) / 6; break;
324 case 1: 367 case 4: tmp = (tmp * 2 * 6) / 7; break;
325 tmp = (tmp * 2 * 2) / 3; 368 case 5: tmp = (tmp * 2 * 7) / 8; break;
326 break;
327
328 case 2:
329 tmp = (tmp * 2 * 3) / 4;
330 break;
331
332 case 3:
333 tmp = (tmp * 2 * 5) / 6;
334 break;
335
336 case 4:
337 tmp = (tmp * 2 * 6) / 7;
338 break;
339
340 case 5:
341 tmp = (tmp * 2 * 7) / 8;
342 break;
343 } 369 }
370
344 if (tmp == 0) { 371 if (tmp == 0) {
345 printk("s5h1420: avoided division by 0\n"); 372 printk(KERN_ERR "s5h1420: avoided division by 0\n");
346 tmp = 1; 373 tmp = 1;
347 } 374 }
348 tmp = state->fclk / tmp; 375 tmp = state->fclk / tmp;
349 376
377
350 /* set the MPEG_CLK_INTL for the calculated data rate */ 378 /* set the MPEG_CLK_INTL for the calculated data rate */
351 if (tmp < 4) 379 if (tmp < 2)
352 val = 0x00; 380 val = 0x00;
353 else if (tmp < 8) 381 else if (tmp < 5)
354 val = 0x01; 382 val = 0x01;
355 else if (tmp < 12) 383 else if (tmp < 9)
356 val = 0x02; 384 val = 0x02;
357 else if (tmp < 16) 385 else if (tmp < 13)
358 val = 0x03; 386 val = 0x03;
359 else if (tmp < 24) 387 else if (tmp < 17)
360 val = 0x04; 388 val = 0x04;
361 else if (tmp < 32) 389 else if (tmp < 25)
362 val = 0x05; 390 val = 0x05;
363 else 391 else if (tmp < 33)
364 val = 0x06; 392 val = 0x06;
365 s5h1420_writereg(state, 0x22, val); 393 else
394 val = 0x07;
395 dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
396
397 s5h1420_writereg(state, FEC01, 0x18);
398 s5h1420_writereg(state, FEC01, 0x10);
399 s5h1420_writereg(state, FEC01, val);
400
401 /* Enable "MPEG_Out" */
402 val = s5h1420_readreg(state, Mpeg02);
403 s5h1420_writereg(state, Mpeg02, val | (1 << 6));
366 404
367 /* DC freeze */ 405 /* kicker disable */
368 s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01); 406 val = s5h1420_readreg(state, QPSK01) & 0x7f;
407 s5h1420_writereg(state, QPSK01, val);
369 408
370 /* kicker disable + remove DC offset */ 409 /* DC freeze TODO it was never activated by default or it can stay activated */
371 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f); 410
411 if (s5h1420_getsymbolrate(state) >= 20000000) {
412 s5h1420_writereg(state, Loop04, 0x8a);
413 s5h1420_writereg(state, Loop05, 0x6a);
414 } else {
415 s5h1420_writereg(state, Loop04, 0x58);
416 s5h1420_writereg(state, Loop05, 0x27);
417 }
372 418
373 /* post-lock processing has been done! */ 419 /* post-lock processing has been done! */
374 state->postlocked = 1; 420 state->postlocked = 1;
375 } 421 }
376 422
423 dprintk("leave %s\n", __func__);
424
377 return 0; 425 return 0;
378} 426}
379 427
@@ -414,6 +462,7 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
414 462
415static void s5h1420_reset(struct s5h1420_state* state) 463static void s5h1420_reset(struct s5h1420_state* state)
416{ 464{
465 dprintk("%s\n", __func__);
417 s5h1420_writereg (state, 0x01, 0x08); 466 s5h1420_writereg (state, 0x01, 0x08);
418 s5h1420_writereg (state, 0x01, 0x00); 467 s5h1420_writereg (state, 0x01, 0x00);
419 udelay(10); 468 udelay(10);
@@ -422,54 +471,52 @@ static void s5h1420_reset(struct s5h1420_state* state)
422static void s5h1420_setsymbolrate(struct s5h1420_state* state, 471static void s5h1420_setsymbolrate(struct s5h1420_state* state,
423 struct dvb_frontend_parameters *p) 472 struct dvb_frontend_parameters *p)
424{ 473{
474 u8 v;
425 u64 val; 475 u64 val;
426 476
477 dprintk("enter %s\n", __func__);
478
427 val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24); 479 val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
428 if (p->u.qpsk.symbol_rate <= 21000000) { 480 if (p->u.qpsk.symbol_rate < 29000000)
429 val *= 2; 481 val *= 2;
430 }
431 do_div(val, (state->fclk / 1000)); 482 do_div(val, (state->fclk / 1000));
432 483
433 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f); 484 dprintk("symbol rate register: %06llx\n", val);
434 s5h1420_writereg(state, 0x11, val >> 16); 485
435 s5h1420_writereg(state, 0x12, val >> 8); 486 v = s5h1420_readreg(state, Loop01);
436 s5h1420_writereg(state, 0x13, val & 0xff); 487 s5h1420_writereg(state, Loop01, v & 0x7f);
437 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80); 488 s5h1420_writereg(state, Tnco01, val >> 16);
489 s5h1420_writereg(state, Tnco02, val >> 8);
490 s5h1420_writereg(state, Tnco03, val & 0xff);
491 s5h1420_writereg(state, Loop01, v | 0x80);
492 dprintk("leave %s\n", __func__);
438} 493}
439 494
440static u32 s5h1420_getsymbolrate(struct s5h1420_state* state) 495static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
441{ 496{
442 u64 val = 0; 497 return state->symbol_rate;
443 int sampling = 2;
444
445 if (s5h1420_readreg(state, 0x05) & 0x2)
446 sampling = 1;
447
448 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
449 val = s5h1420_readreg(state, 0x11) << 16;
450 val |= s5h1420_readreg(state, 0x12) << 8;
451 val |= s5h1420_readreg(state, 0x13);
452 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
453
454 val *= (state->fclk / 1000ULL);
455 do_div(val, ((1<<24) * sampling));
456
457 return (u32) (val * 1000ULL);
458} 498}
459 499
460static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset) 500static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
461{ 501{
462 int val; 502 int val;
503 u8 v;
504
505 dprintk("enter %s\n", __func__);
463 506
464 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so 507 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
465 * divide fclk by 1000000 to get the correct value. */ 508 * divide fclk by 1000000 to get the correct value. */
466 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); 509 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
467 510
468 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf); 511 dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
469 s5h1420_writereg(state, 0x0e, val >> 16); 512
470 s5h1420_writereg(state, 0x0f, val >> 8); 513 v = s5h1420_readreg(state, Loop01);
471 s5h1420_writereg(state, 0x10, val & 0xff); 514 s5h1420_writereg(state, Loop01, v & 0xbf);
472 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40); 515 s5h1420_writereg(state, Pnco01, val >> 16);
516 s5h1420_writereg(state, Pnco02, val >> 8);
517 s5h1420_writereg(state, Pnco03, val & 0xff);
518 s5h1420_writereg(state, Loop01, v | 0x40);
519 dprintk("leave %s\n", __func__);
473} 520}
474 521
475static int s5h1420_getfreqoffset(struct s5h1420_state* state) 522static int s5h1420_getfreqoffset(struct s5h1420_state* state)
@@ -496,52 +543,53 @@ static void s5h1420_setfec_inversion(struct s5h1420_state* state,
496 struct dvb_frontend_parameters *p) 543 struct dvb_frontend_parameters *p)
497{ 544{
498 u8 inversion = 0; 545 u8 inversion = 0;
546 u8 vit08, vit09;
547
548 dprintk("enter %s\n", __func__);
499 549
500 if (p->inversion == INVERSION_OFF) { 550 if (p->inversion == INVERSION_OFF)
501 inversion = state->config->invert ? 0x08 : 0; 551 inversion = state->config->invert ? 0x08 : 0;
502 } else if (p->inversion == INVERSION_ON) { 552 else if (p->inversion == INVERSION_ON)
503 inversion = state->config->invert ? 0 : 0x08; 553 inversion = state->config->invert ? 0 : 0x08;
504 }
505 554
506 if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) { 555 if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
507 s5h1420_writereg(state, 0x30, 0x3f); 556 vit08 = 0x3f;
508 s5h1420_writereg(state, 0x31, 0x00 | inversion); 557 vit09 = 0;
509 } else { 558 } else {
510 switch(p->u.qpsk.fec_inner) { 559 switch(p->u.qpsk.fec_inner) {
511 case FEC_1_2: 560 case FEC_1_2:
512 s5h1420_writereg(state, 0x30, 0x01); 561 vit08 = 0x01; vit09 = 0x10;
513 s5h1420_writereg(state, 0x31, 0x10 | inversion);
514 break; 562 break;
515 563
516 case FEC_2_3: 564 case FEC_2_3:
517 s5h1420_writereg(state, 0x30, 0x02); 565 vit08 = 0x02; vit09 = 0x11;
518 s5h1420_writereg(state, 0x31, 0x11 | inversion);
519 break; 566 break;
520 567
521 case FEC_3_4: 568 case FEC_3_4:
522 s5h1420_writereg(state, 0x30, 0x04); 569 vit08 = 0x04; vit09 = 0x12;
523 s5h1420_writereg(state, 0x31, 0x12 | inversion);
524 break; 570 break;
525 571
526 case FEC_5_6: 572 case FEC_5_6:
527 s5h1420_writereg(state, 0x30, 0x08); 573 vit08 = 0x08; vit09 = 0x13;
528 s5h1420_writereg(state, 0x31, 0x13 | inversion);
529 break; 574 break;
530 575
531 case FEC_6_7: 576 case FEC_6_7:
532 s5h1420_writereg(state, 0x30, 0x10); 577 vit08 = 0x10; vit09 = 0x14;
533 s5h1420_writereg(state, 0x31, 0x14 | inversion);
534 break; 578 break;
535 579
536 case FEC_7_8: 580 case FEC_7_8:
537 s5h1420_writereg(state, 0x30, 0x20); 581 vit08 = 0x20; vit09 = 0x15;
538 s5h1420_writereg(state, 0x31, 0x15 | inversion);
539 break; 582 break;
540 583
541 default: 584 default:
542 return; 585 return;
543 } 586 }
544 } 587 }
588 vit09 |= inversion;
589 dprintk("fec: %02x %02x\n", vit08, vit09);
590 s5h1420_writereg(state, Vit08, vit08);
591 s5h1420_writereg(state, Vit09, vit09);
592 dprintk("leave %s\n", __func__);
545} 593}
546 594
547static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state) 595static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
@@ -583,16 +631,19 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
583 struct s5h1420_state* state = fe->demodulator_priv; 631 struct s5h1420_state* state = fe->demodulator_priv;
584 int frequency_delta; 632 int frequency_delta;
585 struct dvb_frontend_tune_settings fesettings; 633 struct dvb_frontend_tune_settings fesettings;
634 uint8_t clock_settting;
635
636 dprintk("enter %s\n", __func__);
586 637
587 /* check if we should do a fast-tune */ 638 /* check if we should do a fast-tune */
588 memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters)); 639 memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
589 s5h1420_get_tune_settings(fe, &fesettings); 640 s5h1420_get_tune_settings(fe, &fesettings);
590 frequency_delta = p->frequency - state->tunedfreq; 641 frequency_delta = p->frequency - state->tunedfreq;
591 if ((frequency_delta > -fesettings.max_drift) && 642 if ((frequency_delta > -fesettings.max_drift) &&
592 (frequency_delta < fesettings.max_drift) && 643 (frequency_delta < fesettings.max_drift) &&
593 (frequency_delta != 0) && 644 (frequency_delta != 0) &&
594 (state->fec_inner == p->u.qpsk.fec_inner) && 645 (state->fec_inner == p->u.qpsk.fec_inner) &&
595 (state->symbol_rate == p->u.qpsk.symbol_rate)) { 646 (state->symbol_rate == p->u.qpsk.symbol_rate)) {
596 647
597 if (fe->ops.tuner_ops.set_params) { 648 if (fe->ops.tuner_ops.set_params) {
598 fe->ops.tuner_ops.set_params(fe, p); 649 fe->ops.tuner_ops.set_params(fe, p);
@@ -606,54 +657,93 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
606 } else { 657 } else {
607 s5h1420_setfreqoffset(state, 0); 658 s5h1420_setfreqoffset(state, 0);
608 } 659 }
660 dprintk("simple tune\n");
609 return 0; 661 return 0;
610 } 662 }
663 dprintk("tuning demod\n");
611 664
612 /* first of all, software reset */ 665 /* first of all, software reset */
613 s5h1420_reset(state); 666 s5h1420_reset(state);
614 667
615 /* set s5h1420 fclk PLL according to desired symbol rate */ 668 /* set s5h1420 fclk PLL according to desired symbol rate */
616 if (p->u.qpsk.symbol_rate > 28000000) { 669 if (p->u.qpsk.symbol_rate > 33000000)
617 state->fclk = 88000000; 670 state->fclk = 80000000;
618 s5h1420_writereg(state, 0x03, 0x50); 671 else if (p->u.qpsk.symbol_rate > 28500000)
619 s5h1420_writereg(state, 0x04, 0x40);
620 s5h1420_writereg(state, 0x05, 0xae);
621 } else if (p->u.qpsk.symbol_rate > 21000000) {
622 state->fclk = 59000000; 672 state->fclk = 59000000;
623 s5h1420_writereg(state, 0x03, 0x33); 673 else if (p->u.qpsk.symbol_rate > 25000000)
624 s5h1420_writereg(state, 0x04, 0x40); 674 state->fclk = 86000000;
625 s5h1420_writereg(state, 0x05, 0xae); 675 else if (p->u.qpsk.symbol_rate > 1900000)
626 } else {
627 state->fclk = 88000000; 676 state->fclk = 88000000;
628 s5h1420_writereg(state, 0x03, 0x50); 677 else
629 s5h1420_writereg(state, 0x04, 0x40); 678 state->fclk = 44000000;
630 s5h1420_writereg(state, 0x05, 0xac); 679
680 /* Clock */
681 switch (state->fclk) {
682 default:
683 case 88000000:
684 clock_settting = 80;
685 break;
686 case 86000000:
687 clock_settting = 78;
688 break;
689 case 80000000:
690 clock_settting = 72;
691 break;
692 case 59000000:
693 clock_settting = 51;
694 break;
695 case 44000000:
696 clock_settting = 36;
697 break;
631 } 698 }
699 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
700 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
701 s5h1420_writereg(state, PLL02, 0x40);
702 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
632 703
633 /* set misc registers */ 704 /* TODO DC offset removal, config parameter ? */
634 s5h1420_writereg(state, 0x02, 0x00); 705 if (p->u.qpsk.symbol_rate > 29000000)
635 s5h1420_writereg(state, 0x06, 0x00); 706 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
636 s5h1420_writereg(state, 0x07, 0xb0); 707 else
637 s5h1420_writereg(state, 0x0a, 0xe7); 708 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
638 s5h1420_writereg(state, 0x0b, 0x78);
639 s5h1420_writereg(state, 0x0c, 0x48);
640 s5h1420_writereg(state, 0x0d, 0x6b);
641 s5h1420_writereg(state, 0x2e, 0x8e);
642 s5h1420_writereg(state, 0x35, 0x33);
643 s5h1420_writereg(state, 0x38, 0x01);
644 s5h1420_writereg(state, 0x39, 0x7d);
645 s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
646 s5h1420_writereg(state, 0x3c, 0x00);
647 s5h1420_writereg(state, 0x45, 0x61);
648 s5h1420_writereg(state, 0x46, 0x1d);
649 709
650 /* start QPSK */ 710 /* set misc registers */
651 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1); 711 s5h1420_writereg(state, CON_1, 0x00);
712 s5h1420_writereg(state, QPSK02, 0x00);
713 s5h1420_writereg(state, Pre01, 0xb0);
714
715 s5h1420_writereg(state, Loop01, 0xF0);
716 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
717 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
718 if (p->u.qpsk.symbol_rate > 20000000)
719 s5h1420_writereg(state, Loop04, 0x79);
720 else
721 s5h1420_writereg(state, Loop04, 0x58);
722 s5h1420_writereg(state, Loop05, 0x6b);
723
724 if (p->u.qpsk.symbol_rate >= 8000000)
725 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
726 else if (p->u.qpsk.symbol_rate >= 4000000)
727 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
728 else
729 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
730
731 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
732
733 s5h1420_writereg(state, Sync01, 0x33);
734 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
735 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
736 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
737
738 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
739 s5h1420_writereg(state, DiS03, 0x00);
740 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
652 741
653 /* set tuner PLL */ 742 /* set tuner PLL */
654 if (fe->ops.tuner_ops.set_params) { 743 if (fe->ops.tuner_ops.set_params) {
655 fe->ops.tuner_ops.set_params(fe, p); 744 fe->ops.tuner_ops.set_params(fe, p);
656 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 745 if (fe->ops.i2c_gate_ctrl)
746 fe->ops.i2c_gate_ctrl(fe, 0);
657 s5h1420_setfreqoffset(state, 0); 747 s5h1420_setfreqoffset(state, 0);
658 } 748 }
659 749
@@ -661,10 +751,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
661 s5h1420_setsymbolrate(state, p); 751 s5h1420_setsymbolrate(state, p);
662 s5h1420_setfec_inversion(state, p); 752 s5h1420_setfec_inversion(state, p);
663 753
754 /* start QPSK */
755 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
756
664 state->fec_inner = p->u.qpsk.fec_inner; 757 state->fec_inner = p->u.qpsk.fec_inner;
665 state->symbol_rate = p->u.qpsk.symbol_rate; 758 state->symbol_rate = p->u.qpsk.symbol_rate;
666 state->postlocked = 0; 759 state->postlocked = 0;
667 state->tunedfreq = p->frequency; 760 state->tunedfreq = p->frequency;
761
762 dprintk("leave %s\n", __func__);
668 return 0; 763 return 0;
669} 764}
670 765
@@ -717,11 +812,10 @@ static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
717{ 812{
718 struct s5h1420_state* state = fe->demodulator_priv; 813 struct s5h1420_state* state = fe->demodulator_priv;
719 814
720 if (enable) { 815 if (enable)
721 return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1); 816 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
722 } else { 817 else
723 return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe); 818 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
724 }
725} 819}
726 820
727static int s5h1420_init (struct dvb_frontend* fe) 821static int s5h1420_init (struct dvb_frontend* fe)
@@ -729,7 +823,8 @@ static int s5h1420_init (struct dvb_frontend* fe)
729 struct s5h1420_state* state = fe->demodulator_priv; 823 struct s5h1420_state* state = fe->demodulator_priv;
730 824
731 /* disable power down and do reset */ 825 /* disable power down and do reset */
732 s5h1420_writereg(state, 0x02, 0x10); 826 state->CON_1_val = 0x10;
827 s5h1420_writereg(state, 0x02, state->CON_1_val);
733 msleep(10); 828 msleep(10);
734 s5h1420_reset(state); 829 s5h1420_reset(state);
735 830
@@ -739,26 +834,60 @@ static int s5h1420_init (struct dvb_frontend* fe)
739static int s5h1420_sleep(struct dvb_frontend* fe) 834static int s5h1420_sleep(struct dvb_frontend* fe)
740{ 835{
741 struct s5h1420_state* state = fe->demodulator_priv; 836 struct s5h1420_state* state = fe->demodulator_priv;
742 837 state->CON_1_val = 0x12;
743 return s5h1420_writereg(state, 0x02, 0x12); 838 return s5h1420_writereg(state, 0x02, state->CON_1_val);
744} 839}
745 840
746static void s5h1420_release(struct dvb_frontend* fe) 841static void s5h1420_release(struct dvb_frontend* fe)
747{ 842{
748 struct s5h1420_state* state = fe->demodulator_priv; 843 struct s5h1420_state* state = fe->demodulator_priv;
844 i2c_del_adapter(&state->tuner_i2c_adapter);
749 kfree(state); 845 kfree(state);
750} 846}
751 847
752static struct dvb_frontend_ops s5h1420_ops; 848static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
849{
850 return I2C_FUNC_I2C;
851}
852
853static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
854{
855 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
856 struct i2c_msg m[1 + num];
857 u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
858
859 memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
860
861 m[0].addr = state->config->demod_address;
862 m[0].buf = tx_open;
863 m[0].len = 2;
753 864
754struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config, 865 memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
755 struct i2c_adapter* i2c) 866
867 return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
868}
869
870static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
871 .master_xfer = s5h1420_tuner_i2c_tuner_xfer,
872 .functionality = s5h1420_tuner_i2c_func,
873};
874
875struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
756{ 876{
757 struct s5h1420_state* state = NULL; 877 struct s5h1420_state *state = fe->demodulator_priv;
758 u8 identity; 878 return &state->tuner_i2c_adapter;
879}
880EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
881
882static struct dvb_frontend_ops s5h1420_ops;
759 883
884struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
885 struct i2c_adapter *i2c)
886{
760 /* allocate memory for the internal state */ 887 /* allocate memory for the internal state */
761 state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL); 888 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
889 u8 i;
890
762 if (state == NULL) 891 if (state == NULL)
763 goto error; 892 goto error;
764 893
@@ -772,24 +901,42 @@ struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
772 state->symbol_rate = 0; 901 state->symbol_rate = 0;
773 902
774 /* check if the demod is there + identify it */ 903 /* check if the demod is there + identify it */
775 identity = s5h1420_readreg(state, 0x00); 904 i = s5h1420_readreg(state, ID01);
776 if (identity != 0x03) 905 if (i != 0x03)
777 goto error; 906 goto error;
778 907
908 memset(state->shadow, 0xff, sizeof(state->shadow));
909
910 for (i = 0; i < 0x50; i++)
911 state->shadow[i] = s5h1420_readreg(state, i);
912
779 /* create dvb_frontend */ 913 /* create dvb_frontend */
780 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops)); 914 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
781 state->frontend.demodulator_priv = state; 915 state->frontend.demodulator_priv = state;
916
917 /* create tuner i2c adapter */
918 strncpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", I2C_NAME_SIZE);
919 state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL,
920 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
921 state->tuner_i2c_adapter.algo_data = NULL;
922 i2c_set_adapdata(&state->tuner_i2c_adapter, state);
923 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
924 printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
925 goto error;
926 }
927
782 return &state->frontend; 928 return &state->frontend;
783 929
784error: 930error:
785 kfree(state); 931 kfree(state);
786 return NULL; 932 return NULL;
787} 933}
934EXPORT_SYMBOL(s5h1420_attach);
788 935
789static struct dvb_frontend_ops s5h1420_ops = { 936static struct dvb_frontend_ops s5h1420_ops = {
790 937
791 .info = { 938 .info = {
792 .name = "Samsung S5H1420 DVB-S", 939 .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
793 .type = FE_QPSK, 940 .type = FE_QPSK,
794 .frequency_min = 950000, 941 .frequency_min = 950000,
795 .frequency_max = 2150000, 942 .frequency_max = 2150000,
@@ -826,10 +973,6 @@ static struct dvb_frontend_ops s5h1420_ops = {
826 .set_voltage = s5h1420_set_voltage, 973 .set_voltage = s5h1420_set_voltage,
827}; 974};
828 975
829module_param(debug, int, 0644); 976MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
830 977MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
831MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
832MODULE_AUTHOR("Andrew de Quincey");
833MODULE_LICENSE("GPL"); 978MODULE_LICENSE("GPL");
834
835EXPORT_SYMBOL(s5h1420_attach);