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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-10 00:49:53 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-07-27 16:55:49 -0400
commitbe44eb283b97c29b06a125cb5527b299d84315f4 (patch)
tree73d92b59deafc66aca72d0208db0ab24baafa306 /drivers/media/dvb/frontends/drxk_hard.c
parentf1fe1b75d64046b693075045fe9fc5cafed9c981 (diff)
[media] drxk: Proper handle/propagate the error codes
This driver is very big and complex. An error happening in the middle of any initialization may cause the frontend to not work. So, it needs to properly propagate error codes internally and to userspace. Also, printing the error codes at the places it happened helps to discover were's a bug at the code. Before this change, a do { } while (0) loop and lots of breaks inside were used to propagate errors. While this works, if there are loops inside other loops, it could be easy to forget to add another break, causing the error to not abort the function. Also, as not all functions were reporting errors, it is hard to discover why something failed. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends/drxk_hard.c')
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c7109
1 files changed, 3545 insertions, 3564 deletions
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
index 523352670e73..74e986fd3283 100644
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -318,11 +318,13 @@ static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, 318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
319 .buf = val, .len = 1} 319 .buf = val, .len = 1}
320 }; 320 };
321 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; 321
322 return i2c_transfer(adapter, msgs, 1);
322} 323}
323 324
324static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) 325static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
325{ 326{
327 int status;
326 struct i2c_msg msg = { 328 struct i2c_msg msg = {
327 .addr = adr, .flags = 0, .buf = data, .len = len }; 329 .addr = adr, .flags = 0, .buf = data, .len = len };
328 330
@@ -333,16 +335,20 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
333 printk(KERN_CONT " %02x", data[i]); 335 printk(KERN_CONT " %02x", data[i]);
334 printk(KERN_CONT "\n"); 336 printk(KERN_CONT "\n");
335 } 337 }
336 if (i2c_transfer(adap, &msg, 1) != 1) { 338 status = i2c_transfer(adap, &msg, 1);
339 if (status >= 0 && status != 1)
340 status = -EIO;
341
342 if (status < 0)
337 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr); 343 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
338 return -1; 344
339 } 345 return status;
340 return 0;
341} 346}
342 347
343static int i2c_read(struct i2c_adapter *adap, 348static int i2c_read(struct i2c_adapter *adap,
344 u8 adr, u8 *msg, int len, u8 *answ, int alen) 349 u8 adr, u8 *msg, int len, u8 *answ, int alen)
345{ 350{
351 int status;
346 struct i2c_msg msgs[2] = { 352 struct i2c_msg msgs[2] = {
347 {.addr = adr, .flags = 0, 353 {.addr = adr, .flags = 0,
348 .buf = msg, .len = len}, 354 .buf = msg, .len = len},
@@ -356,12 +362,15 @@ static int i2c_read(struct i2c_adapter *adap,
356 printk(KERN_CONT " %02x", msg[i]); 362 printk(KERN_CONT " %02x", msg[i]);
357 printk(KERN_CONT "\n"); 363 printk(KERN_CONT "\n");
358 } 364 }
359 if (i2c_transfer(adap, msgs, 2) != 2) { 365 status = i2c_transfer(adap, msgs, 2);
366 if (status != 2) {
360 if (debug > 2) 367 if (debug > 2)
361 printk(KERN_CONT ": ERROR!\n"); 368 printk(KERN_CONT ": ERROR!\n");
369 if (status >= 0)
370 status = -EIO;
362 371
363 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr); 372 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
364 return -1; 373 return status;
365 } 374 }
366 if (debug > 2) { 375 if (debug > 2) {
367 int i; 376 int i;
@@ -375,6 +384,7 @@ static int i2c_read(struct i2c_adapter *adap,
375 384
376static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) 385static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
377{ 386{
387 int status;
378 u8 adr = state->demod_address, mm1[4], mm2[2], len; 388 u8 adr = state->demod_address, mm1[4], mm2[2], len;
379 389
380 if (state->single_master) 390 if (state->single_master)
@@ -392,8 +402,9 @@ static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
392 len = 2; 402 len = 2;
393 } 403 }
394 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 404 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
395 if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) 405 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
396 return -1; 406 if (status < 0)
407 return status;
397 if (data) 408 if (data)
398 *data = mm2[0] | (mm2[1] << 8); 409 *data = mm2[0] | (mm2[1] << 8);
399 410
@@ -407,6 +418,7 @@ static int read16(struct drxk_state *state, u32 reg, u16 *data)
407 418
408static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) 419static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
409{ 420{
421 int status;
410 u8 adr = state->demod_address, mm1[4], mm2[4], len; 422 u8 adr = state->demod_address, mm1[4], mm2[4], len;
411 423
412 if (state->single_master) 424 if (state->single_master)
@@ -424,8 +436,9 @@ static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
424 len = 2; 436 len = 2;
425 } 437 }
426 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 438 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
427 if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) 439 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
428 return -1; 440 if (status < 0)
441 return status;
429 if (data) 442 if (data)
430 *data = mm2[0] | (mm2[1] << 8) | 443 *data = mm2[0] | (mm2[1] << 8) |
431 (mm2[2] << 16) | (mm2[3] << 24); 444 (mm2[2] << 16) | (mm2[3] << 24);
@@ -459,9 +472,7 @@ static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
459 mm[len + 1] = (data >> 8) & 0xff; 472 mm[len + 1] = (data >> 8) & 0xff;
460 473
461 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); 474 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
462 if (i2c_write(state->i2c, adr, mm, len + 2) < 0) 475 return i2c_write(state->i2c, adr, mm, len + 2);
463 return -1;
464 return 0;
465} 476}
466 477
467static int write16(struct drxk_state *state, u32 reg, u16 data) 478static int write16(struct drxk_state *state, u32 reg, u16 data)
@@ -491,9 +502,8 @@ static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
491 mm[len + 2] = (data >> 16) & 0xff; 502 mm[len + 2] = (data >> 16) & 0xff;
492 mm[len + 3] = (data >> 24) & 0xff; 503 mm[len + 3] = (data >> 24) & 0xff;
493 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); 504 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
494 if (i2c_write(state->i2c, adr, mm, len + 4) < 0) 505
495 return -1; 506 return i2c_write(state->i2c, adr, mm, len + 4);
496 return 0;
497} 507}
498 508
499static int write32(struct drxk_state *state, u32 reg, u32 data) 509static int write32(struct drxk_state *state, u32 reg, u32 data)
@@ -567,33 +577,41 @@ int PowerUpDevice(struct drxk_state *state)
567 dprintk(1, "\n"); 577 dprintk(1, "\n");
568 578
569 status = i2c_read1(state->i2c, state->demod_address, &data); 579 status = i2c_read1(state->i2c, state->demod_address, &data);
570 if (status < 0) 580 if (status < 0) {
571 do { 581 do {
572 data = 0; 582 data = 0;
573 if (i2c_write(state->i2c, 583 status = i2c_write(state->i2c, state->demod_address,
574 state->demod_address, &data, 1) < 0) 584 &data, 1);
575 printk(KERN_ERR "drxk: powerup failed\n");
576 msleep(10); 585 msleep(10);
577 retryCount++; 586 retryCount++;
578 } while (i2c_read1(state->i2c, 587 if (status < 0)
579 state->demod_address, &data) < 0 && 588 continue;
589 status = i2c_read1(state->i2c, state->demod_address,
590 &data);
591 } while (status < 0 &&
580 (retryCount < DRXK_MAX_RETRIES_POWERUP)); 592 (retryCount < DRXK_MAX_RETRIES_POWERUP));
581 if (retryCount >= DRXK_MAX_RETRIES_POWERUP) 593 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
582 return -1; 594 goto error;
583 do { 595 }
584 /* Make sure all clk domains are active */ 596
585 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); 597 /* Make sure all clk domains are active */
586 if (status < 0) 598 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
587 break; 599 if (status < 0)
588 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 600 goto error;
589 if (status < 0) 601 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
590 break; 602 if (status < 0)
591 /* Enable pll lock tests */ 603 goto error;
592 status = write16(state, SIO_CC_PLL_LOCK__A, 1); 604 /* Enable pll lock tests */
593 if (status < 0) 605 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
594 break; 606 if (status < 0)
595 state->m_currentPowerMode = DRX_POWER_UP; 607 goto error;
596 } while (0); 608
609 state->m_currentPowerMode = DRX_POWER_UP;
610
611error:
612 if (status < 0)
613 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
614
597 return status; 615 return status;
598} 616}
599 617
@@ -863,28 +881,27 @@ static int DRXX_Open(struct drxk_state *state)
863 u16 key = 0; 881 u16 key = 0;
864 882
865 dprintk(1, "\n"); 883 dprintk(1, "\n");
866 do { 884 /* stop lock indicator process */
867 /* stop lock indicator process */ 885 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
868 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 886 if (status < 0)
869 if (status < 0) 887 goto error;
870 break; 888 /* Check device id */
871 /* Check device id */ 889 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
872 status = read16(state, SIO_TOP_COMM_KEY__A, &key); 890 if (status < 0)
873 if (status < 0) 891 goto error;
874 break; 892 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
875 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 893 if (status < 0)
876 if (status < 0) 894 goto error;
877 break; 895 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
878 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); 896 if (status < 0)
879 if (status < 0) 897 goto error;
880 break; 898 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
881 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); 899 if (status < 0)
882 if (status < 0) 900 goto error;
883 break; 901 status = write16(state, SIO_TOP_COMM_KEY__A, key);
884 status = write16(state, SIO_TOP_COMM_KEY__A, key); 902error:
885 if (status < 0) 903 if (status < 0)
886 break; 904 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
887 } while (0);
888 return status; 905 return status;
889} 906}
890 907
@@ -895,177 +912,183 @@ static int GetDeviceCapabilities(struct drxk_state *state)
895 int status; 912 int status;
896 913
897 dprintk(1, "\n"); 914 dprintk(1, "\n");
898 do {
899 /* driver 0.9.0 */
900 /* stop lock indicator process */
901 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
902 if (status < 0)
903 break;
904 915
905 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); 916 /* driver 0.9.0 */
906 if (status < 0) 917 /* stop lock indicator process */
907 break; 918 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
908 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); 919 if (status < 0)
909 if (status < 0) 920 goto error;
910 break; 921 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
911 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 922 if (status < 0)
912 if (status < 0) 923 goto error;
913 break; 924 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
925 if (status < 0)
926 goto error;
927 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
928 if (status < 0)
929 goto error;
914 930
915 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 931 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
916 case 0: 932 case 0:
917 /* ignore (bypass ?) */ 933 /* ignore (bypass ?) */
918 break; 934 break;
919 case 1: 935 case 1:
920 /* 27 MHz */ 936 /* 27 MHz */
921 state->m_oscClockFreq = 27000; 937 state->m_oscClockFreq = 27000;
922 break; 938 break;
923 case 2: 939 case 2:
924 /* 20.25 MHz */ 940 /* 20.25 MHz */
925 state->m_oscClockFreq = 20250; 941 state->m_oscClockFreq = 20250;
926 break; 942 break;
927 case 3: 943 case 3:
928 /* 4 MHz */ 944 /* 4 MHz */
929 state->m_oscClockFreq = 20250; 945 state->m_oscClockFreq = 20250;
930 break; 946 break;
931 default: 947 default:
932 return -1; 948 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
933 } 949 return -EINVAL;
934 /* 950 }
935 Determine device capabilities 951 /*
936 Based on pinning v14 952 Determine device capabilities
937 */ 953 Based on pinning v14
938 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); 954 */
939 if (status < 0) 955 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
940 break; 956 if (status < 0)
941 /* driver 0.9.0 */ 957 goto error;
942 switch ((sioTopJtagidLo >> 29) & 0xF) { 958 /* driver 0.9.0 */
943 case 0: 959 switch ((sioTopJtagidLo >> 29) & 0xF) {
944 state->m_deviceSpin = DRXK_SPIN_A1; 960 case 0:
945 break; 961 state->m_deviceSpin = DRXK_SPIN_A1;
946 case 2: 962 break;
947 state->m_deviceSpin = DRXK_SPIN_A2; 963 case 2:
948 break; 964 state->m_deviceSpin = DRXK_SPIN_A2;
949 case 3: 965 break;
950 state->m_deviceSpin = DRXK_SPIN_A3; 966 case 3:
951 break; 967 state->m_deviceSpin = DRXK_SPIN_A3;
952 default: 968 break;
953 state->m_deviceSpin = DRXK_SPIN_UNKNOWN; 969 default:
954 status = -1; 970 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
955 break; 971 status = -EINVAL;
956 } 972 printk(KERN_ERR "drxk: Spin unknown\n");
957 switch ((sioTopJtagidLo >> 12) & 0xFF) { 973 goto error2;
958 case 0x13: 974 }
959 /* typeId = DRX3913K_TYPE_ID */ 975 switch ((sioTopJtagidLo >> 12) & 0xFF) {
960 state->m_hasLNA = false; 976 case 0x13:
961 state->m_hasOOB = false; 977 /* typeId = DRX3913K_TYPE_ID */
962 state->m_hasATV = false; 978 state->m_hasLNA = false;
963 state->m_hasAudio = false; 979 state->m_hasOOB = false;
964 state->m_hasDVBT = true; 980 state->m_hasATV = false;
965 state->m_hasDVBC = true; 981 state->m_hasAudio = false;
966 state->m_hasSAWSW = true; 982 state->m_hasDVBT = true;
967 state->m_hasGPIO2 = false; 983 state->m_hasDVBC = true;
968 state->m_hasGPIO1 = false; 984 state->m_hasSAWSW = true;
969 state->m_hasIRQN = false; 985 state->m_hasGPIO2 = false;
970 break; 986 state->m_hasGPIO1 = false;
971 case 0x15: 987 state->m_hasIRQN = false;
972 /* typeId = DRX3915K_TYPE_ID */ 988 break;
973 state->m_hasLNA = false; 989 case 0x15:
974 state->m_hasOOB = false; 990 /* typeId = DRX3915K_TYPE_ID */
975 state->m_hasATV = true; 991 state->m_hasLNA = false;
976 state->m_hasAudio = false; 992 state->m_hasOOB = false;
977 state->m_hasDVBT = true; 993 state->m_hasATV = true;
978 state->m_hasDVBC = false; 994 state->m_hasAudio = false;
979 state->m_hasSAWSW = true; 995 state->m_hasDVBT = true;
980 state->m_hasGPIO2 = true; 996 state->m_hasDVBC = false;
981 state->m_hasGPIO1 = true; 997 state->m_hasSAWSW = true;
982 state->m_hasIRQN = false; 998 state->m_hasGPIO2 = true;
983 break; 999 state->m_hasGPIO1 = true;
984 case 0x16: 1000 state->m_hasIRQN = false;
985 /* typeId = DRX3916K_TYPE_ID */ 1001 break;
986 state->m_hasLNA = false; 1002 case 0x16:
987 state->m_hasOOB = false; 1003 /* typeId = DRX3916K_TYPE_ID */
988 state->m_hasATV = true; 1004 state->m_hasLNA = false;
989 state->m_hasAudio = false; 1005 state->m_hasOOB = false;
990 state->m_hasDVBT = true; 1006 state->m_hasATV = true;
991 state->m_hasDVBC = false; 1007 state->m_hasAudio = false;
992 state->m_hasSAWSW = true; 1008 state->m_hasDVBT = true;
993 state->m_hasGPIO2 = true; 1009 state->m_hasDVBC = false;
994 state->m_hasGPIO1 = true; 1010 state->m_hasSAWSW = true;
995 state->m_hasIRQN = false; 1011 state->m_hasGPIO2 = true;
996 break; 1012 state->m_hasGPIO1 = true;
997 case 0x18: 1013 state->m_hasIRQN = false;
998 /* typeId = DRX3918K_TYPE_ID */ 1014 break;
999 state->m_hasLNA = false; 1015 case 0x18:
1000 state->m_hasOOB = false; 1016 /* typeId = DRX3918K_TYPE_ID */
1001 state->m_hasATV = true; 1017 state->m_hasLNA = false;
1002 state->m_hasAudio = true; 1018 state->m_hasOOB = false;
1003 state->m_hasDVBT = true; 1019 state->m_hasATV = true;
1004 state->m_hasDVBC = false; 1020 state->m_hasAudio = true;
1005 state->m_hasSAWSW = true; 1021 state->m_hasDVBT = true;
1006 state->m_hasGPIO2 = true; 1022 state->m_hasDVBC = false;
1007 state->m_hasGPIO1 = true; 1023 state->m_hasSAWSW = true;
1008 state->m_hasIRQN = false; 1024 state->m_hasGPIO2 = true;
1009 break; 1025 state->m_hasGPIO1 = true;
1010 case 0x21: 1026 state->m_hasIRQN = false;
1011 /* typeId = DRX3921K_TYPE_ID */ 1027 break;
1012 state->m_hasLNA = false; 1028 case 0x21:
1013 state->m_hasOOB = false; 1029 /* typeId = DRX3921K_TYPE_ID */
1014 state->m_hasATV = true; 1030 state->m_hasLNA = false;
1015 state->m_hasAudio = true; 1031 state->m_hasOOB = false;
1016 state->m_hasDVBT = true; 1032 state->m_hasATV = true;
1017 state->m_hasDVBC = true; 1033 state->m_hasAudio = true;
1018 state->m_hasSAWSW = true; 1034 state->m_hasDVBT = true;
1019 state->m_hasGPIO2 = true; 1035 state->m_hasDVBC = true;
1020 state->m_hasGPIO1 = true; 1036 state->m_hasSAWSW = true;
1021 state->m_hasIRQN = false; 1037 state->m_hasGPIO2 = true;
1022 break; 1038 state->m_hasGPIO1 = true;
1023 case 0x23: 1039 state->m_hasIRQN = false;
1024 /* typeId = DRX3923K_TYPE_ID */ 1040 break;
1025 state->m_hasLNA = false; 1041 case 0x23:
1026 state->m_hasOOB = false; 1042 /* typeId = DRX3923K_TYPE_ID */
1027 state->m_hasATV = true; 1043 state->m_hasLNA = false;
1028 state->m_hasAudio = true; 1044 state->m_hasOOB = false;
1029 state->m_hasDVBT = true; 1045 state->m_hasATV = true;
1030 state->m_hasDVBC = true; 1046 state->m_hasAudio = true;
1031 state->m_hasSAWSW = true; 1047 state->m_hasDVBT = true;
1032 state->m_hasGPIO2 = true; 1048 state->m_hasDVBC = true;
1033 state->m_hasGPIO1 = true; 1049 state->m_hasSAWSW = true;
1034 state->m_hasIRQN = false; 1050 state->m_hasGPIO2 = true;
1035 break; 1051 state->m_hasGPIO1 = true;
1036 case 0x25: 1052 state->m_hasIRQN = false;
1037 /* typeId = DRX3925K_TYPE_ID */ 1053 break;
1038 state->m_hasLNA = false; 1054 case 0x25:
1039 state->m_hasOOB = false; 1055 /* typeId = DRX3925K_TYPE_ID */
1040 state->m_hasATV = true; 1056 state->m_hasLNA = false;
1041 state->m_hasAudio = true; 1057 state->m_hasOOB = false;
1042 state->m_hasDVBT = true; 1058 state->m_hasATV = true;
1043 state->m_hasDVBC = true; 1059 state->m_hasAudio = true;
1044 state->m_hasSAWSW = true; 1060 state->m_hasDVBT = true;
1045 state->m_hasGPIO2 = true; 1061 state->m_hasDVBC = true;
1046 state->m_hasGPIO1 = true; 1062 state->m_hasSAWSW = true;
1047 state->m_hasIRQN = false; 1063 state->m_hasGPIO2 = true;
1048 break; 1064 state->m_hasGPIO1 = true;
1049 case 0x26: 1065 state->m_hasIRQN = false;
1050 /* typeId = DRX3926K_TYPE_ID */ 1066 break;
1051 state->m_hasLNA = false; 1067 case 0x26:
1052 state->m_hasOOB = false; 1068 /* typeId = DRX3926K_TYPE_ID */
1053 state->m_hasATV = true; 1069 state->m_hasLNA = false;
1054 state->m_hasAudio = false; 1070 state->m_hasOOB = false;
1055 state->m_hasDVBT = true; 1071 state->m_hasATV = true;
1056 state->m_hasDVBC = true; 1072 state->m_hasAudio = false;
1057 state->m_hasSAWSW = true; 1073 state->m_hasDVBT = true;
1058 state->m_hasGPIO2 = true; 1074 state->m_hasDVBC = true;
1059 state->m_hasGPIO1 = true; 1075 state->m_hasSAWSW = true;
1060 state->m_hasIRQN = false; 1076 state->m_hasGPIO2 = true;
1061 break; 1077 state->m_hasGPIO1 = true;
1062 default: 1078 state->m_hasIRQN = false;
1063 printk(KERN_ERR "drxk: DeviceID not supported = %02x\n", 1079 break;
1064 ((sioTopJtagidLo >> 12) & 0xFF)); 1080 default:
1065 status = -1; 1081 printk(KERN_ERR "drxk: DeviceID not supported = %02x\n",
1066 break; 1082 ((sioTopJtagidLo >> 12) & 0xFF));
1067 } 1083 status = -EINVAL;
1068 } while (0); 1084 goto error2;
1085 }
1086
1087error:
1088 if (status < 0)
1089 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1090
1091error2:
1069 return status; 1092 return status;
1070} 1093}
1071 1094
@@ -1079,7 +1102,7 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1079 /* Write command */ 1102 /* Write command */
1080 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); 1103 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1081 if (status < 0) 1104 if (status < 0)
1082 return status; 1105 goto error;
1083 if (cmd == SIO_HI_RA_RAM_CMD_RESET) 1106 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1084 msleep(1); 1107 msleep(1);
1085 1108
@@ -1100,11 +1123,14 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1100 &waitCmd); 1123 &waitCmd);
1101 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) 1124 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1102 && (waitCmd != 0)); 1125 && (waitCmd != 0));
1103 1126 if (status < 0)
1104 if (status == 0) 1127 goto error;
1105 status = read16(state, SIO_HI_RA_RAM_RES__A, 1128 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1106 pResult);
1107 } 1129 }
1130error:
1131 if (status < 0)
1132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1133
1108 return status; 1134 return status;
1109} 1135}
1110 1136
@@ -1115,32 +1141,34 @@ static int HI_CfgCommand(struct drxk_state *state)
1115 dprintk(1, "\n"); 1141 dprintk(1, "\n");
1116 1142
1117 mutex_lock(&state->mutex); 1143 mutex_lock(&state->mutex);
1118 do {
1119 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1120 if (status < 0)
1121 break;
1122 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1123 if (status < 0)
1124 break;
1125 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1126 if (status < 0)
1127 break;
1128 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1129 if (status < 0)
1130 break;
1131 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1132 if (status < 0)
1133 break;
1134 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1135 if (status < 0)
1136 break;
1137 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1138 if (status < 0)
1139 break;
1140 1144
1141 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1145 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1142 } while (0); 1146 if (status < 0)
1147 goto error;
1148 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1149 if (status < 0)
1150 goto error;
1151 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1152 if (status < 0)
1153 goto error;
1154 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1155 if (status < 0)
1156 goto error;
1157 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1158 if (status < 0)
1159 goto error;
1160 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1161 if (status < 0)
1162 goto error;
1163 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1164 if (status < 0)
1165 goto error;
1166
1167 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1168error:
1143 mutex_unlock(&state->mutex); 1169 mutex_unlock(&state->mutex);
1170 if (status < 0)
1171 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1144 return status; 1172 return status;
1145} 1173}
1146 1174
@@ -1152,6 +1180,7 @@ static int InitHI(struct drxk_state *state)
1152 state->m_HICfgTimeout = 0x96FF; 1180 state->m_HICfgTimeout = 0x96FF;
1153 /* port/bridge/power down ctrl */ 1181 /* port/bridge/power down ctrl */
1154 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 1182 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1183
1155 return HI_CfgCommand(state); 1184 return HI_CfgCommand(state);
1156} 1185}
1157 1186
@@ -1162,139 +1191,139 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1162 u16 sioPdrMdxCfg = 0; 1191 u16 sioPdrMdxCfg = 0;
1163 1192
1164 dprintk(1, "\n"); 1193 dprintk(1, "\n");
1165 do {
1166 /* stop lock indicator process */
1167 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1168 if (status < 0)
1169 break;
1170 1194
1171 /* MPEG TS pad configuration */ 1195 /* stop lock indicator process */
1172 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); 1196 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1197 if (status < 0)
1198 goto error;
1199
1200 /* MPEG TS pad configuration */
1201 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1202 if (status < 0)
1203 goto error;
1204
1205 if (mpegEnable == false) {
1206 /* Set MPEG TS pads to inputmode */
1207 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1173 if (status < 0) 1208 if (status < 0)
1174 break; 1209 goto error;
1210 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1211 if (status < 0)
1212 goto error;
1213 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1214 if (status < 0)
1215 goto error;
1216 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1217 if (status < 0)
1218 goto error;
1219 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1220 if (status < 0)
1221 goto error;
1222 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1223 if (status < 0)
1224 goto error;
1225 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1226 if (status < 0)
1227 goto error;
1228 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1229 if (status < 0)
1230 goto error;
1231 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1232 if (status < 0)
1233 goto error;
1234 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1235 if (status < 0)
1236 goto error;
1237 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1238 if (status < 0)
1239 goto error;
1240 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1241 if (status < 0)
1242 goto error;
1243 } else {
1244 /* Enable MPEG output */
1245 sioPdrMdxCfg =
1246 ((state->m_TSDataStrength <<
1247 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1248 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1249 SIO_PDR_MCLK_CFG_DRIVE__B) |
1250 0x0003);
1175 1251
1176 if (mpegEnable == false) { 1252 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1177 /* Set MPEG TS pads to inputmode */ 1253 if (status < 0)
1178 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1254 goto error;
1255 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1256 if (status < 0)
1257 goto error;
1258 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1259 if (status < 0)
1260 goto error;
1261 if (state->m_enableParallel == true) {
1262 /* paralel -> enable MD1 to MD7 */
1263 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1179 if (status < 0) 1264 if (status < 0)
1180 break; 1265 goto error;
1181 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); 1266 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1182 if (status < 0) 1267 if (status < 0)
1183 break; 1268 goto error;
1184 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); 1269 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1185 if (status < 0) 1270 if (status < 0)
1186 break; 1271 goto error;
1187 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); 1272 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1188 if (status < 0) 1273 if (status < 0)
1189 break; 1274 goto error;
1190 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); 1275 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1191 if (status < 0) 1276 if (status < 0)
1192 break; 1277 goto error;
1278 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1279 if (status < 0)
1280 goto error;
1281 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1282 if (status < 0)
1283 goto error;
1284 } else {
1285 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1286 SIO_PDR_MD0_CFG_DRIVE__B)
1287 | 0x0003);
1288 /* serial -> disable MD1 to MD7 */
1193 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1289 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1194 if (status < 0) 1290 if (status < 0)
1195 break; 1291 goto error;
1196 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1292 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1197 if (status < 0) 1293 if (status < 0)
1198 break; 1294 goto error;
1199 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1295 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1200 if (status < 0) 1296 if (status < 0)
1201 break; 1297 goto error;
1202 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1298 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1203 if (status < 0) 1299 if (status < 0)
1204 break; 1300 goto error;
1205 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1301 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1206 if (status < 0) 1302 if (status < 0)
1207 break; 1303 goto error;
1208 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1304 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1209 if (status < 0) 1305 if (status < 0)
1210 break; 1306 goto error;
1211 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1307 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1212 if (status < 0) 1308 if (status < 0)
1213 break; 1309 goto error;
1214 } else {
1215 /* Enable MPEG output */
1216 sioPdrMdxCfg =
1217 ((state->m_TSDataStrength <<
1218 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1219 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1220 SIO_PDR_MCLK_CFG_DRIVE__B) |
1221 0x0003);
1222
1223 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1224 if (status < 0)
1225 break;
1226 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1227 if (status < 0)
1228 break;
1229 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1230 if (status < 0)
1231 break;
1232 if (state->m_enableParallel == true) {
1233 /* paralel -> enable MD1 to MD7 */
1234 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1235 if (status < 0)
1236 break;
1237 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1238 if (status < 0)
1239 break;
1240 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1241 if (status < 0)
1242 break;
1243 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1244 if (status < 0)
1245 break;
1246 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1247 if (status < 0)
1248 break;
1249 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1250 if (status < 0)
1251 break;
1252 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1253 if (status < 0)
1254 break;
1255 } else {
1256 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1257 SIO_PDR_MD0_CFG_DRIVE__B)
1258 | 0x0003);
1259 /* serial -> disable MD1 to MD7 */
1260 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1261 if (status < 0)
1262 break;
1263 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1264 if (status < 0)
1265 break;
1266 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1267 if (status < 0)
1268 break;
1269 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1270 if (status < 0)
1271 break;
1272 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1273 if (status < 0)
1274 break;
1275 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1276 if (status < 0)
1277 break;
1278 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1279 if (status < 0)
1280 break;
1281 }
1282 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1283 if (status < 0)
1284 break;
1285 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1286 if (status < 0)
1287 break;
1288 } 1310 }
1289 /* Enable MB output over MPEG pads and ctl input */ 1311 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1290 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1291 if (status < 0) 1312 if (status < 0)
1292 break; 1313 goto error;
1293 /* Write nomagic word to enable pdr reg write */ 1314 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1294 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1295 if (status < 0) 1315 if (status < 0)
1296 break; 1316 goto error;
1297 } while (0); 1317 }
1318 /* Enable MB output over MPEG pads and ctl input */
1319 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1320 if (status < 0)
1321 goto error;
1322 /* Write nomagic word to enable pdr reg write */
1323 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1324error:
1325 if (status < 0)
1326 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1298 return status; 1327 return status;
1299} 1328}
1300 1329
@@ -1313,36 +1342,38 @@ static int BLChainCmd(struct drxk_state *state,
1313 unsigned long end; 1342 unsigned long end;
1314 1343
1315 dprintk(1, "\n"); 1344 dprintk(1, "\n");
1316
1317 mutex_lock(&state->mutex); 1345 mutex_lock(&state->mutex);
1346 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1347 if (status < 0)
1348 goto error;
1349 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1350 if (status < 0)
1351 goto error;
1352 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1353 if (status < 0)
1354 goto error;
1355 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1356 if (status < 0)
1357 goto error;
1358
1359 end = jiffies + msecs_to_jiffies(timeOut);
1318 do { 1360 do {
1319 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1361 msleep(1);
1320 if (status < 0) 1362 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1321 break;
1322 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1323 if (status < 0)
1324 break;
1325 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1326 if (status < 0)
1327 break;
1328 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1329 if (status < 0) 1363 if (status < 0)
1330 break; 1364 goto error;
1331 end = jiffies + msecs_to_jiffies(timeOut); 1365 } while ((blStatus == 0x1) &&
1366 ((time_is_after_jiffies(end))));
1332 1367
1333 do { 1368 if (blStatus == 0x1) {
1334 msleep(1); 1369 printk(KERN_ERR "drxk: SIO not ready\n");
1335 status = read16(state, SIO_BL_STATUS__A, &blStatus); 1370 status = -EINVAL;
1336 if (status < 0) 1371 goto error2;
1337 break; 1372 }
1338 } while ((blStatus == 0x1) && 1373error:
1339 ((time_is_after_jiffies(end)))); 1374 if (status < 0)
1340 if (blStatus == 0x1) { 1375 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1341 printk(KERN_ERR "drxk: SIO not ready\n"); 1376error2:
1342 mutex_unlock(&state->mutex);
1343 return -1;
1344 }
1345 } while (0);
1346 mutex_unlock(&state->mutex); 1377 mutex_unlock(&state->mutex);
1347 return status; 1378 return status;
1348} 1379}
@@ -1421,25 +1452,24 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1421 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1452 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1422 } 1453 }
1423 1454
1424 status = (read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); 1455 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1425 1456 if (status >= 0 && data == desiredStatus) {
1426 if (data == desiredStatus) {
1427 /* tokenring already has correct status */ 1457 /* tokenring already has correct status */
1428 return status; 1458 return status;
1429 } 1459 }
1430 /* Disable/enable dvbt tokenring bridge */ 1460 /* Disable/enable dvbt tokenring bridge */
1431 status = 1461 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1432 write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1433 1462
1434 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1463 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1435 do { 1464 do {
1436 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1465 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1437 if (status < 0) 1466 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1438 break; 1467 break;
1439 } while ((data != desiredStatus) && ((time_is_after_jiffies(end)))); 1468 msleep(1);
1469 } while (1);
1440 if (data != desiredStatus) { 1470 if (data != desiredStatus) {
1441 printk(KERN_ERR "drxk: SIO not ready\n"); 1471 printk(KERN_ERR "drxk: SIO not ready\n");
1442 return -1; 1472 return -EINVAL;
1443 } 1473 }
1444 return status; 1474 return status;
1445} 1475}
@@ -1452,25 +1482,26 @@ static int MPEGTSStop(struct drxk_state *state)
1452 1482
1453 dprintk(1, "\n"); 1483 dprintk(1, "\n");
1454 1484
1455 do { 1485 /* Gracefull shutdown (byte boundaries) */
1456 /* Gracefull shutdown (byte boundaries) */ 1486 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1457 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1487 if (status < 0)
1458 if (status < 0) 1488 goto error;
1459 break; 1489 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1460 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1490 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1461 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1491 if (status < 0)
1462 if (status < 0) 1492 goto error;
1463 break; 1493
1494 /* Suppress MCLK during absence of data */
1495 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1496 if (status < 0)
1497 goto error;
1498 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1499 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1500
1501error:
1502 if (status < 0)
1503 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1464 1504
1465 /* Suppress MCLK during absence of data */
1466 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1467 if (status < 0)
1468 break;
1469 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1470 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1471 if (status < 0)
1472 break;
1473 } while (0);
1474 return status; 1505 return status;
1475} 1506}
1476 1507
@@ -1482,82 +1513,83 @@ static int scu_command(struct drxk_state *state,
1482#error DRXK register mapping no longer compatible with this routine! 1513#error DRXK register mapping no longer compatible with this routine!
1483#endif 1514#endif
1484 u16 curCmd = 0; 1515 u16 curCmd = 0;
1485 int status; 1516 int status = -EINVAL;
1486 unsigned long end; 1517 unsigned long end;
1518 u8 buffer[34];
1519 int cnt = 0, ii;
1487 1520
1488 dprintk(1, "\n"); 1521 dprintk(1, "\n");
1489 1522
1490 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || 1523 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1491 ((resultLen > 0) && (result == NULL))) 1524 ((resultLen > 0) && (result == NULL)))
1492 return -1; 1525 goto error;
1493 1526
1494 mutex_lock(&state->mutex); 1527 mutex_lock(&state->mutex);
1528
1529 /* assume that the command register is ready
1530 since it is checked afterwards */
1531 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1532 buffer[cnt++] = (parameter[ii] & 0xFF);
1533 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1534 }
1535 buffer[cnt++] = (cmd & 0xFF);
1536 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1537
1538 write_block(state, SCU_RAM_PARAM_0__A -
1539 (parameterLen - 1), cnt, buffer);
1540 /* Wait until SCU has processed command */
1541 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1495 do { 1542 do {
1496 /* assume that the command register is ready 1543 msleep(1);
1497 since it is checked afterwards */ 1544 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1498 u8 buffer[34]; 1545 if (status < 0)
1499 int cnt = 0, ii; 1546 goto error;
1500 1547 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1501 for (ii = parameterLen - 1; ii >= 0; ii -= 1) { 1548 if (curCmd != DRX_SCU_READY) {
1502 buffer[cnt++] = (parameter[ii] & 0xFF); 1549 printk(KERN_ERR "drxk: SCU not ready\n");
1503 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); 1550 status = -EIO;
1504 } 1551 goto error2;
1505 buffer[cnt++] = (cmd & 0xFF); 1552 }
1506 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1553 /* read results */
1554 if ((resultLen > 0) && (result != NULL)) {
1555 s16 err;
1556 int ii;
1507 1557
1508 write_block(state, SCU_RAM_PARAM_0__A - 1558 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1509 (parameterLen - 1), cnt, buffer); 1559 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1510 /* Wait until SCU has processed command */
1511 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1512 do {
1513 msleep(1);
1514 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1515 if (status < 0) 1560 if (status < 0)
1516 break; 1561 goto error;
1517 } while (!(curCmd == DRX_SCU_READY)
1518 && (time_is_after_jiffies(end)));
1519 if (curCmd != DRX_SCU_READY) {
1520 printk(KERN_ERR "drxk: SCU not ready\n");
1521 mutex_unlock(&state->mutex);
1522 return -1;
1523 } 1562 }
1524 /* read results */ 1563
1525 if ((resultLen > 0) && (result != NULL)) { 1564 /* Check if an error was reported by SCU */
1526 s16 err; 1565 err = (s16)result[0];
1527 int ii; 1566
1528 1567 /* check a few fixed error codes */
1529 for (ii = resultLen - 1; ii >= 0; ii -= 1) { 1568 if (err == SCU_RESULT_UNKSTD) {
1530 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); 1569 printk(KERN_ERR "drxk: SCU_RESULT_UNKSTD\n");
1531 if (status < 0) 1570 status = -EINVAL;
1532 break; 1571 goto error2;
1533 } 1572 } else if (err == SCU_RESULT_UNKCMD) {
1534 1573 printk(KERN_ERR "drxk: SCU_RESULT_UNKCMD\n");
1535 /* Check if an error was reported by SCU */ 1574 status = -EINVAL;
1536 err = (s16) result[0]; 1575 goto error2;
1537 1576 } else if (err < 0) {
1538 /* check a few fixed error codes */ 1577 /*
1539 if (err == SCU_RESULT_UNKSTD) { 1578 * here it is assumed that a nagative result means
1540 printk(KERN_ERR "drxk: SCU_RESULT_UNKSTD\n"); 1579 * error, and positive no error
1541 mutex_unlock(&state->mutex); 1580 */
1542 return -1; 1581 printk(KERN_ERR "drxk: %s ERROR: %d\n", __func__, err);
1543 } else if (err == SCU_RESULT_UNKCMD) { 1582 status = -EINVAL;
1544 printk(KERN_ERR "drxk: SCU_RESULT_UNKCMD\n"); 1583 goto error2;
1545 mutex_unlock(&state->mutex);
1546 return -1;
1547 }
1548 /* here it is assumed that negative means error,
1549 and positive no error */
1550 else if (err < 0) {
1551 printk(KERN_ERR "drxk: %s ERROR\n", __func__);
1552 mutex_unlock(&state->mutex);
1553 return -1;
1554 }
1555 } 1584 }
1556 } while (0); 1585 }
1557 mutex_unlock(&state->mutex); 1586
1587error:
1558 if (status < 0) 1588 if (status < 0)
1559 printk(KERN_ERR "drxk: %s: status = %d\n", __func__, status); 1589 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1560 1590
1591error2:
1592 mutex_unlock(&state->mutex);
1561 return status; 1593 return status;
1562} 1594}
1563 1595
@@ -1568,30 +1600,30 @@ static int SetIqmAf(struct drxk_state *state, bool active)
1568 1600
1569 dprintk(1, "\n"); 1601 dprintk(1, "\n");
1570 1602
1571 do { 1603 /* Configure IQM */
1572 /* Configure IQM */ 1604 status = read16(state, IQM_AF_STDBY__A, &data);
1573 status = read16(state, IQM_AF_STDBY__A, &data); 1605 if (status < 0)
1574 if (status < 0) 1606 goto error;
1575 break; 1607
1576 if (!active) { 1608 if (!active) {
1577 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY 1609 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1578 | IQM_AF_STDBY_STDBY_AMP_STANDBY 1610 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1579 | IQM_AF_STDBY_STDBY_PD_STANDBY 1611 | IQM_AF_STDBY_STDBY_PD_STANDBY
1580 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 1612 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1581 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); 1613 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1582 } else { /* active */ 1614 } else {
1583 1615 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1584 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) 1616 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1585 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) 1617 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1586 & (~IQM_AF_STDBY_STDBY_PD_STANDBY) 1618 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1587 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) 1619 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1588 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1620 );
1589 ); 1621 }
1590 } 1622 status = write16(state, IQM_AF_STDBY__A, data);
1591 status = write16(state, IQM_AF_STDBY__A, data); 1623
1592 if (status < 0) 1624error:
1593 break; 1625 if (status < 0)
1594 } while (0); 1626 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1595 return status; 1627 return status;
1596} 1628}
1597 1629
@@ -1604,7 +1636,7 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1604 1636
1605 /* Check arguments */ 1637 /* Check arguments */
1606 if (mode == NULL) 1638 if (mode == NULL)
1607 return -1; 1639 return -EINVAL;
1608 1640
1609 switch (*mode) { 1641 switch (*mode) {
1610 case DRX_POWER_UP: 1642 case DRX_POWER_UP:
@@ -1624,7 +1656,7 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1624 break; 1656 break;
1625 default: 1657 default:
1626 /* Unknow sleep mode */ 1658 /* Unknow sleep mode */
1627 return -1; 1659 return -EINVAL;
1628 break; 1660 break;
1629 } 1661 }
1630 1662
@@ -1634,14 +1666,12 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1634 1666
1635 /* For next steps make sure to start from DRX_POWER_UP mode */ 1667 /* For next steps make sure to start from DRX_POWER_UP mode */
1636 if (state->m_currentPowerMode != DRX_POWER_UP) { 1668 if (state->m_currentPowerMode != DRX_POWER_UP) {
1637 do { 1669 status = PowerUpDevice(state);
1638 status = PowerUpDevice(state); 1670 if (status < 0)
1639 if (status < 0) 1671 goto error;
1640 break; 1672 status = DVBTEnableOFDMTokenRing(state, true);
1641 status = DVBTEnableOFDMTokenRing(state, true); 1673 if (status < 0)
1642 if (status < 0) 1674 goto error;
1643 break;
1644 } while (0);
1645 } 1675 }
1646 1676
1647 if (*mode == DRX_POWER_UP) { 1677 if (*mode == DRX_POWER_UP) {
@@ -1656,48 +1686,51 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1656 /* Power down device */ 1686 /* Power down device */
1657 /* stop all comm_exec */ 1687 /* stop all comm_exec */
1658 /* Stop and power down previous standard */ 1688 /* Stop and power down previous standard */
1659 do { 1689 switch (state->m_OperationMode) {
1660 switch (state->m_OperationMode) { 1690 case OM_DVBT:
1661 case OM_DVBT: 1691 status = MPEGTSStop(state);
1662 status = MPEGTSStop(state);
1663 if (status < 0)
1664 break;
1665 status = PowerDownDVBT(state, false);
1666 if (status < 0)
1667 break;
1668 break;
1669 case OM_QAM_ITU_A:
1670 case OM_QAM_ITU_C:
1671 status = MPEGTSStop(state);
1672 if (status < 0)
1673 break;
1674 status = PowerDownQAM(state);
1675 if (status < 0)
1676 break;
1677 break;
1678 default:
1679 break;
1680 }
1681 status = DVBTEnableOFDMTokenRing(state, false);
1682 if (status < 0) 1692 if (status < 0)
1683 break; 1693 goto error;
1684 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); 1694 status = PowerDownDVBT(state, false);
1685 if (status < 0) 1695 if (status < 0)
1686 break; 1696 goto error;
1687 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1697 break;
1698 case OM_QAM_ITU_A:
1699 case OM_QAM_ITU_C:
1700 status = MPEGTSStop(state);
1688 if (status < 0) 1701 if (status < 0)
1689 break; 1702 goto error;
1703 status = PowerDownQAM(state);
1704 if (status < 0)
1705 goto error;
1706 break;
1707 default:
1708 break;
1709 }
1710 status = DVBTEnableOFDMTokenRing(state, false);
1711 if (status < 0)
1712 goto error;
1713 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1714 if (status < 0)
1715 goto error;
1716 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1717 if (status < 0)
1718 goto error;
1690 1719
1691 if (*mode != DRXK_POWER_DOWN_OFDM) { 1720 if (*mode != DRXK_POWER_DOWN_OFDM) {
1692 state->m_HICfgCtrl |= 1721 state->m_HICfgCtrl |=
1693 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1722 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1694 status = HI_CfgCommand(state); 1723 status = HI_CfgCommand(state);
1695 if (status < 0) 1724 if (status < 0)
1696 break; 1725 goto error;
1697 } 1726 }
1698 } while (0);
1699 } 1727 }
1700 state->m_currentPowerMode = *mode; 1728 state->m_currentPowerMode = *mode;
1729
1730error:
1731 if (status < 0)
1732 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1733
1701 return status; 1734 return status;
1702} 1735}
1703 1736
@@ -1710,44 +1743,45 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1710 1743
1711 dprintk(1, "\n"); 1744 dprintk(1, "\n");
1712 1745
1713 do { 1746 status = read16(state, SCU_COMM_EXEC__A, &data);
1714 status = read16(state, SCU_COMM_EXEC__A, &data); 1747 if (status < 0)
1715 if (status < 0) 1748 goto error;
1716 break; 1749 if (data == SCU_COMM_EXEC_ACTIVE) {
1717 if (data == SCU_COMM_EXEC_ACTIVE) { 1750 /* Send OFDM stop command */
1718 /* Send OFDM stop command */ 1751 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1719 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1720 if (status < 0)
1721 break;
1722 /* Send OFDM reset command */
1723 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1724 if (status < 0)
1725 break;
1726 }
1727
1728 /* Reset datapath for OFDM, processors first */
1729 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1730 if (status < 0)
1731 break;
1732 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1733 if (status < 0) 1752 if (status < 0)
1734 break; 1753 goto error;
1735 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 1754 /* Send OFDM reset command */
1755 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1736 if (status < 0) 1756 if (status < 0)
1737 break; 1757 goto error;
1758 }
1738 1759
1739 /* powerdown AFE */ 1760 /* Reset datapath for OFDM, processors first */
1740 status = SetIqmAf(state, false); 1761 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1741 if (status < 0) 1762 if (status < 0)
1742 break; 1763 goto error;
1764 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1765 if (status < 0)
1766 goto error;
1767 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1768 if (status < 0)
1769 goto error;
1743 1770
1744 /* powerdown to OFDM mode */ 1771 /* powerdown AFE */
1745 if (setPowerMode) { 1772 status = SetIqmAf(state, false);
1746 status = CtrlPowerMode(state, &powerMode); 1773 if (status < 0)
1747 if (status < 0) 1774 goto error;
1748 break; 1775
1749 } 1776 /* powerdown to OFDM mode */
1750 } while (0); 1777 if (setPowerMode) {
1778 status = CtrlPowerMode(state, &powerMode);
1779 if (status < 0)
1780 goto error;
1781 }
1782error:
1783 if (status < 0)
1784 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1751 return status; 1785 return status;
1752} 1786}
1753 1787
@@ -1762,127 +1796,118 @@ static int SetOperationMode(struct drxk_state *state,
1762 TODO investigate total power down instead of partial 1796 TODO investigate total power down instead of partial
1763 power down depending on "previous" standard. 1797 power down depending on "previous" standard.
1764 */ 1798 */
1765 do {
1766 /* disable HW lock indicator */
1767 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1768 if (status < 0)
1769 break;
1770 1799
1771 if (state->m_OperationMode != oMode) { 1800 /* disable HW lock indicator */
1772 switch (state->m_OperationMode) { 1801 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1773 /* OM_NONE was added for start up */ 1802 if (status < 0)
1774 case OM_NONE: 1803 goto error;
1775 break;
1776 case OM_DVBT:
1777 status = MPEGTSStop(state);
1778 if (status < 0)
1779 break;
1780 status = PowerDownDVBT(state, true);
1781 if (status < 0)
1782 break;
1783 state->m_OperationMode = OM_NONE;
1784 break;
1785 case OM_QAM_ITU_B:
1786 status = -1;
1787 break;
1788 case OM_QAM_ITU_A: /* fallthrough */
1789 case OM_QAM_ITU_C:
1790 status = MPEGTSStop(state);
1791 if (status < 0)
1792 break;
1793 status = PowerDownQAM(state);
1794 if (status < 0)
1795 break;
1796 state->m_OperationMode = OM_NONE;
1797 break;
1798 default:
1799 status = -1;
1800 }
1801 status = status;
1802 if (status < 0)
1803 break;
1804 1804
1805 /* 1805 if (state->m_OperationMode != oMode) {
1806 Power up new standard 1806 switch (state->m_OperationMode) {
1807 */ 1807 /* OM_NONE was added for start up */
1808 switch (oMode) { 1808 case OM_NONE:
1809 case OM_DVBT: 1809 break;
1810 state->m_OperationMode = oMode; 1810 case OM_DVBT:
1811 status = SetDVBTStandard(state, oMode); 1811 status = MPEGTSStop(state);
1812 if (status < 0) 1812 if (status < 0)
1813 break; 1813 goto error;
1814 break; 1814 status = PowerDownDVBT(state, true);
1815 case OM_QAM_ITU_B: 1815 if (status < 0)
1816 status = -1; 1816 goto error;
1817 break; 1817 state->m_OperationMode = OM_NONE;
1818 case OM_QAM_ITU_A: /* fallthrough */ 1818 break;
1819 case OM_QAM_ITU_C: 1819 case OM_QAM_ITU_A: /* fallthrough */
1820 state->m_OperationMode = oMode; 1820 case OM_QAM_ITU_C:
1821 status = SetQAMStandard(state, oMode); 1821 status = MPEGTSStop(state);
1822 if (status < 0) 1822 if (status < 0)
1823 break; 1823 goto error;
1824 break; 1824 status = PowerDownQAM(state);
1825 default: 1825 if (status < 0)
1826 status = -1; 1826 goto error;
1827 } 1827 state->m_OperationMode = OM_NONE;
1828 break;
1829 case OM_QAM_ITU_B:
1830 default:
1831 status = -EINVAL;
1832 goto error;
1828 } 1833 }
1829 status = status; 1834
1830 if (status < 0) 1835 /*
1836 Power up new standard
1837 */
1838 switch (oMode) {
1839 case OM_DVBT:
1840 status = SetDVBTStandard(state, oMode);
1841 if (status < 0)
1842 goto error;
1843 state->m_OperationMode = oMode;
1831 break; 1844 break;
1832 } while (0); 1845 case OM_QAM_ITU_A: /* fallthrough */
1833 return 0; 1846 case OM_QAM_ITU_C:
1847 status = SetQAMStandard(state, oMode);
1848 if (status < 0)
1849 goto error;
1850 state->m_OperationMode = oMode;
1851 break;
1852 case OM_QAM_ITU_B:
1853 default:
1854 status = -EINVAL;
1855 }
1856 }
1857error:
1858 if (status < 0)
1859 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1860 return status;
1834} 1861}
1835 1862
1836static int Start(struct drxk_state *state, s32 offsetFreq, 1863static int Start(struct drxk_state *state, s32 offsetFreq,
1837 s32 IntermediateFrequency) 1864 s32 IntermediateFrequency)
1838{ 1865{
1839 int status = 0; 1866 int status = -EINVAL;
1867
1868 u16 IFreqkHz;
1869 s32 OffsetkHz = offsetFreq / 1000;
1840 1870
1841 dprintk(1, "\n"); 1871 dprintk(1, "\n");
1842 do { 1872 if (state->m_DrxkState != DRXK_STOPPED &&
1843 u16 IFreqkHz; 1873 state->m_DrxkState != DRXK_DTV_STARTED)
1844 s32 OffsetkHz = offsetFreq / 1000; 1874 goto error;
1845 1875
1846 if (state->m_DrxkState != DRXK_STOPPED && 1876 state->m_bMirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1847 state->m_DrxkState != DRXK_DTV_STARTED) {
1848 status = -1;
1849 break;
1850 }
1851 state->m_bMirrorFreqSpect =
1852 (state->param.inversion == INVERSION_ON);
1853 1877
1854 if (IntermediateFrequency < 0) { 1878 if (IntermediateFrequency < 0) {
1855 state->m_bMirrorFreqSpect = 1879 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1856 !state->m_bMirrorFreqSpect; 1880 IntermediateFrequency = -IntermediateFrequency;
1857 IntermediateFrequency = -IntermediateFrequency; 1881 }
1858 }
1859 1882
1860 switch (state->m_OperationMode) { 1883 switch (state->m_OperationMode) {
1861 case OM_QAM_ITU_A: 1884 case OM_QAM_ITU_A:
1862 case OM_QAM_ITU_C: 1885 case OM_QAM_ITU_C:
1863 IFreqkHz = (IntermediateFrequency / 1000); 1886 IFreqkHz = (IntermediateFrequency / 1000);
1864 status = SetQAM(state, IFreqkHz, OffsetkHz); 1887 status = SetQAM(state, IFreqkHz, OffsetkHz);
1865 if (status < 0) 1888 if (status < 0)
1866 break; 1889 goto error;
1867 state->m_DrxkState = DRXK_DTV_STARTED; 1890 state->m_DrxkState = DRXK_DTV_STARTED;
1868 break; 1891 break;
1869 case OM_DVBT: 1892 case OM_DVBT:
1870 IFreqkHz = (IntermediateFrequency / 1000); 1893 IFreqkHz = (IntermediateFrequency / 1000);
1871 status = MPEGTSStop(state); 1894 status = MPEGTSStop(state);
1872 if (status < 0) 1895 if (status < 0)
1873 break; 1896 goto error;
1874 status = SetDVBT(state, IFreqkHz, OffsetkHz); 1897 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1875 if (status < 0) 1898 if (status < 0)
1876 break; 1899 goto error;
1877 status = DVBTStart(state); 1900 status = DVBTStart(state);
1878 if (status < 0) 1901 if (status < 0)
1879 break; 1902 goto error;
1880 state->m_DrxkState = DRXK_DTV_STARTED; 1903 state->m_DrxkState = DRXK_DTV_STARTED;
1881 break; 1904 break;
1882 default: 1905 default:
1883 break; 1906 break;
1884 } 1907 }
1885 } while (0); 1908error:
1909 if (status < 0)
1910 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1886 return status; 1911 return status;
1887} 1912}
1888 1913
@@ -1897,12 +1922,12 @@ static int ShutDown(struct drxk_state *state)
1897static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, 1922static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1898 u32 Time) 1923 u32 Time)
1899{ 1924{
1900 int status = 0; 1925 int status = -EINVAL;
1901 1926
1902 dprintk(1, "\n"); 1927 dprintk(1, "\n");
1903 1928
1904 if (pLockStatus == NULL) 1929 if (pLockStatus == NULL)
1905 return -1; 1930 goto error;
1906 1931
1907 *pLockStatus = NOT_LOCKED; 1932 *pLockStatus = NOT_LOCKED;
1908 1933
@@ -1919,82 +1944,84 @@ static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1919 default: 1944 default:
1920 break; 1945 break;
1921 } 1946 }
1947error:
1948 if (status < 0)
1949 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1922 return status; 1950 return status;
1923} 1951}
1924 1952
1925static int MPEGTSStart(struct drxk_state *state) 1953static int MPEGTSStart(struct drxk_state *state)
1926{ 1954{
1927 int status = 0; 1955 int status;
1928 1956
1929 u16 fecOcSncMode = 0; 1957 u16 fecOcSncMode = 0;
1930 1958
1931 do { 1959 /* Allow OC to sync again */
1932 /* Allow OC to sync again */ 1960 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1933 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1961 if (status < 0)
1934 if (status < 0) 1962 goto error;
1935 break; 1963 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1936 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1964 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1937 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1965 if (status < 0)
1938 if (status < 0) 1966 goto error;
1939 break; 1967 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1940 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); 1968error:
1941 if (status < 0) 1969 if (status < 0)
1942 break; 1970 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1943 } while (0);
1944 return status; 1971 return status;
1945} 1972}
1946 1973
1947static int MPEGTSDtoInit(struct drxk_state *state) 1974static int MPEGTSDtoInit(struct drxk_state *state)
1948{ 1975{
1949 int status = -1; 1976 int status;
1950 1977
1951 dprintk(1, "\n"); 1978 dprintk(1, "\n");
1952 1979
1953 do { 1980 /* Rate integration settings */
1954 /* Rate integration settings */ 1981 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1955 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); 1982 if (status < 0)
1956 if (status < 0) 1983 goto error;
1957 break; 1984 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1958 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); 1985 if (status < 0)
1959 if (status < 0) 1986 goto error;
1960 break; 1987 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1961 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); 1988 if (status < 0)
1962 if (status < 0) 1989 goto error;
1963 break; 1990 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1964 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); 1991 if (status < 0)
1965 if (status < 0) 1992 goto error;
1966 break; 1993 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1967 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); 1994 if (status < 0)
1968 if (status < 0) 1995 goto error;
1969 break; 1996 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1970 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); 1997 if (status < 0)
1971 if (status < 0) 1998 goto error;
1972 break; 1999 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1973 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); 2000 if (status < 0)
1974 if (status < 0) 2001 goto error;
1975 break; 2002 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1976 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); 2003 if (status < 0)
1977 if (status < 0) 2004 goto error;
1978 break; 2005
2006 /* Additional configuration */
2007 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2008 if (status < 0)
2009 goto error;
2010 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2011 if (status < 0)
2012 goto error;
2013 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2014error:
2015 if (status < 0)
2016 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1979 2017
1980 /* Additional configuration */
1981 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1982 if (status < 0)
1983 break;
1984 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1985 if (status < 0)
1986 break;
1987 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1988 if (status < 0)
1989 break;
1990 } while (0);
1991 return status; 2018 return status;
1992} 2019}
1993 2020
1994static int MPEGTSDtoSetup(struct drxk_state *state, 2021static int MPEGTSDtoSetup(struct drxk_state *state,
1995 enum OperationMode oMode) 2022 enum OperationMode oMode)
1996{ 2023{
1997 int status = -1; 2024 int status;
1998 2025
1999 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ 2026 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2000 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ 2027 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
@@ -2010,132 +2037,127 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
2010 2037
2011 dprintk(1, "\n"); 2038 dprintk(1, "\n");
2012 2039
2013 do { 2040 /* Check insertion of the Reed-Solomon parity bytes */
2014 /* Check insertion of the Reed-Solomon parity bytes */ 2041 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2015 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); 2042 if (status < 0)
2016 if (status < 0) 2043 goto error;
2017 break; 2044 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2018 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); 2045 if (status < 0)
2019 if (status < 0) 2046 goto error;
2020 break; 2047 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2021 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); 2048 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2022 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 2049 if (state->m_insertRSByte == true) {
2023 if (state->m_insertRSByte == true) { 2050 /* enable parity symbol forward */
2024 /* enable parity symbol forward */ 2051 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2025 fecOcRegMode |= FEC_OC_MODE_PARITY__M; 2052 /* MVAL disable during parity bytes */
2026 /* MVAL disable during parity bytes */ 2053 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2027 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 2054 /* TS burst length to 204 */
2028 /* TS burst length to 204 */ 2055 fecOcDtoBurstLen = 204;
2029 fecOcDtoBurstLen = 204; 2056 }
2030 }
2031 2057
2032 /* Check serial or parrallel output */ 2058 /* Check serial or parrallel output */
2033 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 2059 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2034 if (state->m_enableParallel == false) { 2060 if (state->m_enableParallel == false) {
2035 /* MPEG data output is serial -> set ipr_mode[0] */ 2061 /* MPEG data output is serial -> set ipr_mode[0] */
2036 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; 2062 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2037 } 2063 }
2038 2064
2039 switch (oMode) { 2065 switch (oMode) {
2040 case OM_DVBT: 2066 case OM_DVBT:
2041 maxBitRate = state->m_DVBTBitrate; 2067 maxBitRate = state->m_DVBTBitrate;
2042 fecOcTmdMode = 3; 2068 fecOcTmdMode = 3;
2043 fecOcRcnCtlRate = 0xC00000; 2069 fecOcRcnCtlRate = 0xC00000;
2044 staticCLK = state->m_DVBTStaticCLK; 2070 staticCLK = state->m_DVBTStaticCLK;
2045 break; 2071 break;
2046 case OM_QAM_ITU_A: /* fallthrough */ 2072 case OM_QAM_ITU_A: /* fallthrough */
2047 case OM_QAM_ITU_C: 2073 case OM_QAM_ITU_C:
2048 fecOcTmdMode = 0x0004; 2074 fecOcTmdMode = 0x0004;
2049 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ 2075 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2050 maxBitRate = state->m_DVBCBitrate; 2076 maxBitRate = state->m_DVBCBitrate;
2051 staticCLK = state->m_DVBCStaticCLK; 2077 staticCLK = state->m_DVBCStaticCLK;
2052 break; 2078 break;
2053 default: 2079 default:
2054 status = -1; 2080 status = -EINVAL;
2055 } /* switch (standard) */ 2081 } /* switch (standard) */
2056 status = status; 2082 if (status < 0)
2057 if (status < 0) 2083 goto error;
2058 break;
2059 2084
2060 /* Configure DTO's */ 2085 /* Configure DTO's */
2061 if (staticCLK) { 2086 if (staticCLK) {
2062 u32 bitRate = 0; 2087 u32 bitRate = 0;
2063 2088
2064 /* Rational DTO for MCLK source (static MCLK rate), 2089 /* Rational DTO for MCLK source (static MCLK rate),
2065 Dynamic DTO for optimal grouping 2090 Dynamic DTO for optimal grouping
2066 (avoid intra-packet gaps), 2091 (avoid intra-packet gaps),
2067 DTO offset enable to sync TS burst with MSTRT */ 2092 DTO offset enable to sync TS burst with MSTRT */
2068 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | 2093 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2069 FEC_OC_DTO_MODE_OFFSET_ENABLE__M); 2094 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2070 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | 2095 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2071 FEC_OC_FCT_MODE_VIRT_ENA__M); 2096 FEC_OC_FCT_MODE_VIRT_ENA__M);
2072 2097
2073 /* Check user defined bitrate */ 2098 /* Check user defined bitrate */
2074 bitRate = maxBitRate; 2099 bitRate = maxBitRate;
2075 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */ 2100 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2076 bitRate = 75900000UL; 2101 bitRate = 75900000UL;
2077 }
2078 /* Rational DTO period:
2079 dto_period = (Fsys / bitrate) - 2
2080
2081 Result should be floored,
2082 to make sure >= requested bitrate
2083 */
2084 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2085 * 1000) / bitRate);
2086 if (fecOcDtoPeriod <= 2)
2087 fecOcDtoPeriod = 0;
2088 else
2089 fecOcDtoPeriod -= 2;
2090 fecOcTmdIntUpdRate = 8;
2091 } else {
2092 /* (commonAttr->staticCLK == false) => dynamic mode */
2093 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2094 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2095 fecOcTmdIntUpdRate = 5;
2096 } 2102 }
2103 /* Rational DTO period:
2104 dto_period = (Fsys / bitrate) - 2
2105
2106 Result should be floored,
2107 to make sure >= requested bitrate
2108 */
2109 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2110 * 1000) / bitRate);
2111 if (fecOcDtoPeriod <= 2)
2112 fecOcDtoPeriod = 0;
2113 else
2114 fecOcDtoPeriod -= 2;
2115 fecOcTmdIntUpdRate = 8;
2116 } else {
2117 /* (commonAttr->staticCLK == false) => dynamic mode */
2118 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2119 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2120 fecOcTmdIntUpdRate = 5;
2121 }
2097 2122
2098 /* Write appropriate registers with requested configuration */ 2123 /* Write appropriate registers with requested configuration */
2099 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); 2124 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2100 if (status < 0) 2125 if (status < 0)
2101 break; 2126 goto error;
2102 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); 2127 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2103 if (status < 0) 2128 if (status < 0)
2104 break; 2129 goto error;
2105 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); 2130 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2106 if (status < 0) 2131 if (status < 0)
2107 break; 2132 goto error;
2108 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); 2133 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2109 if (status < 0) 2134 if (status < 0)
2110 break; 2135 goto error;
2111 status = write16(state, FEC_OC_MODE__A, fecOcRegMode); 2136 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2112 if (status < 0) 2137 if (status < 0)
2113 break; 2138 goto error;
2114 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); 2139 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2115 if (status < 0) 2140 if (status < 0)
2116 break; 2141 goto error;
2117 2142
2118 /* Rate integration settings */ 2143 /* Rate integration settings */
2119 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); 2144 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2120 if (status < 0) 2145 if (status < 0)
2121 break; 2146 goto error;
2122 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); 2147 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2123 if (status < 0) 2148 if (status < 0)
2124 break; 2149 goto error;
2125 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); 2150 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2126 if (status < 0) 2151error:
2127 break; 2152 if (status < 0)
2128 } while (0); 2153 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2129 return status; 2154 return status;
2130} 2155}
2131 2156
2132static int MPEGTSConfigurePolarity(struct drxk_state *state) 2157static int MPEGTSConfigurePolarity(struct drxk_state *state)
2133{ 2158{
2134 int status;
2135 u16 fecOcRegIprInvert = 0; 2159 u16 fecOcRegIprInvert = 0;
2136 2160
2137 dprintk(1, "\n");
2138
2139 /* Data mask for the output data byte */ 2161 /* Data mask for the output data byte */
2140 u16 InvertDataMask = 2162 u16 InvertDataMask =
2141 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2163 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
@@ -2143,6 +2165,8 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
2143 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2165 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2144 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; 2166 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2145 2167
2168 dprintk(1, "\n");
2169
2146 /* Control selective inversion of output bits */ 2170 /* Control selective inversion of output bits */
2147 fecOcRegIprInvert &= (~(InvertDataMask)); 2171 fecOcRegIprInvert &= (~(InvertDataMask));
2148 if (state->m_invertDATA == true) 2172 if (state->m_invertDATA == true)
@@ -2159,8 +2183,8 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
2159 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2183 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2160 if (state->m_invertCLK == true) 2184 if (state->m_invertCLK == true)
2161 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; 2185 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2162 status = write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); 2186
2163 return status; 2187 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2164} 2188}
2165 2189
2166#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 2190#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
@@ -2168,145 +2192,145 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
2168static int SetAgcRf(struct drxk_state *state, 2192static int SetAgcRf(struct drxk_state *state,
2169 struct SCfgAgc *pAgcCfg, bool isDTV) 2193 struct SCfgAgc *pAgcCfg, bool isDTV)
2170{ 2194{
2171 int status = 0; 2195 int status = -EINVAL;
2196 u16 data = 0;
2172 struct SCfgAgc *pIfAgcSettings; 2197 struct SCfgAgc *pIfAgcSettings;
2173 2198
2174 dprintk(1, "\n"); 2199 dprintk(1, "\n");
2175 2200
2176 if (pAgcCfg == NULL) 2201 if (pAgcCfg == NULL)
2177 return -1; 2202 goto error;
2178
2179 do {
2180 u16 data = 0;
2181 2203
2182 switch (pAgcCfg->ctrlMode) { 2204 switch (pAgcCfg->ctrlMode) {
2183 case DRXK_AGC_CTRL_AUTO: 2205 case DRXK_AGC_CTRL_AUTO:
2206 /* Enable RF AGC DAC */
2207 status = read16(state, IQM_AF_STDBY__A, &data);
2208 if (status < 0)
2209 goto error;
2210 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2211 status = write16(state, IQM_AF_STDBY__A, data);
2212 if (status < 0)
2213 goto error;
2214 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2215 if (status < 0)
2216 goto error;
2184 2217
2185 /* Enable RF AGC DAC */ 2218 /* Enable SCU RF AGC loop */
2186 status = read16(state, IQM_AF_STDBY__A, &data); 2219 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2187 if (status < 0)
2188 break;
2189 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2190 status = write16(state, IQM_AF_STDBY__A, data);
2191 if (status < 0)
2192 break;
2193 2220
2194 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2221 /* Polarity */
2195 if (status < 0) 2222 if (state->m_RfAgcPol)
2196 break; 2223 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2224 else
2225 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2226 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2227 if (status < 0)
2228 goto error;
2197 2229
2198 /* Enable SCU RF AGC loop */ 2230 /* Set speed (using complementary reduction value) */
2199 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2231 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2232 if (status < 0)
2233 goto error;
2200 2234
2201 /* Polarity */ 2235 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2202 if (state->m_RfAgcPol) 2236 data |= (~(pAgcCfg->speed <<
2203 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2237 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2204 else 2238 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2205 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2206 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2207 if (status < 0)
2208 break;
2209 2239
2210 /* Set speed (using complementary reduction value) */ 2240 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2211 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2241 if (status < 0)
2212 if (status < 0) 2242 goto error;
2213 break;
2214 2243
2215 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2244 if (IsDVBT(state))
2216 data |= (~(pAgcCfg->speed << 2245 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2217 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2246 else if (IsQAM(state))
2218 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2247 pIfAgcSettings = &state->m_qamIfAgcCfg;
2248 else
2249 pIfAgcSettings = &state->m_atvIfAgcCfg;
2250 if (pIfAgcSettings == NULL) {
2251 status = -EINVAL;
2252 goto error;
2253 }
2219 2254
2220 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2255 /* Set TOP, only if IF-AGC is in AUTO mode */
2256 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2257 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2221 if (status < 0) 2258 if (status < 0)
2222 break; 2259 goto error;
2223 2260
2224 if (IsDVBT(state)) 2261 /* Cut-Off current */
2225 pIfAgcSettings = &state->m_dvbtIfAgcCfg; 2262 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2226 else if (IsQAM(state)) 2263 if (status < 0)
2227 pIfAgcSettings = &state->m_qamIfAgcCfg; 2264 goto error;
2228 else
2229 pIfAgcSettings = &state->m_atvIfAgcCfg;
2230 if (pIfAgcSettings == NULL)
2231 return -1;
2232
2233 /* Set TOP, only if IF-AGC is in AUTO mode */
2234 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2235 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2236 if (status < 0)
2237 break;
2238
2239 /* Cut-Off current */
2240 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2241 if (status < 0)
2242 break;
2243 2265
2244 /* Max. output level */ 2266 /* Max. output level */
2245 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); 2267 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2246 if (status < 0) 2268 if (status < 0)
2247 break; 2269 goto error;
2248 2270
2249 break; 2271 break;
2250 2272
2251 case DRXK_AGC_CTRL_USER: 2273 case DRXK_AGC_CTRL_USER:
2252 /* Enable RF AGC DAC */ 2274 /* Enable RF AGC DAC */
2253 status = read16(state, IQM_AF_STDBY__A, &data); 2275 status = read16(state, IQM_AF_STDBY__A, &data);
2254 if (status < 0) 2276 if (status < 0)
2255 break; 2277 goto error;
2256 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2278 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2257 status = write16(state, IQM_AF_STDBY__A, data); 2279 status = write16(state, IQM_AF_STDBY__A, data);
2258 if (status < 0) 2280 if (status < 0)
2259 break; 2281 goto error;
2260 2282
2261 /* Disable SCU RF AGC loop */ 2283 /* Disable SCU RF AGC loop */
2262 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2284 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2263 if (status < 0) 2285 if (status < 0)
2264 break; 2286 goto error;
2265 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2287 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2266 if (state->m_RfAgcPol) 2288 if (state->m_RfAgcPol)
2267 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2289 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2268 else 2290 else
2269 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2291 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2270 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2292 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2271 if (status < 0) 2293 if (status < 0)
2272 break; 2294 goto error;
2273 2295
2274 /* SCU c.o.c. to 0, enabling full control range */ 2296 /* SCU c.o.c. to 0, enabling full control range */
2275 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); 2297 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2276 if (status < 0) 2298 if (status < 0)
2277 break; 2299 goto error;
2278 2300
2279 /* Write value to output pin */ 2301 /* Write value to output pin */
2280 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); 2302 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2281 if (status < 0) 2303 if (status < 0)
2282 break; 2304 goto error;
2283 break; 2305 break;
2284 2306
2285 case DRXK_AGC_CTRL_OFF: 2307 case DRXK_AGC_CTRL_OFF:
2286 /* Disable RF AGC DAC */ 2308 /* Disable RF AGC DAC */
2287 status = read16(state, IQM_AF_STDBY__A, &data); 2309 status = read16(state, IQM_AF_STDBY__A, &data);
2288 if (status < 0) 2310 if (status < 0)
2289 break; 2311 goto error;
2290 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2312 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2291 status = write16(state, IQM_AF_STDBY__A, data); 2313 status = write16(state, IQM_AF_STDBY__A, data);
2292 if (status < 0) 2314 if (status < 0)
2293 break; 2315 goto error;
2294 2316
2295 /* Disable SCU RF AGC loop */ 2317 /* Disable SCU RF AGC loop */
2296 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2318 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2297 if (status < 0) 2319 if (status < 0)
2298 break; 2320 goto error;
2299 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2321 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2300 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2322 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2301 if (status < 0) 2323 if (status < 0)
2302 break; 2324 goto error;
2303 break; 2325 break;
2304 2326
2305 default: 2327 default:
2306 return -1; 2328 status = -EINVAL;
2307 2329
2308 } /* switch (agcsettings->ctrlMode) */ 2330 }
2309 } while (0); 2331error:
2332 if (status < 0)
2333 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2310 return status; 2334 return status;
2311} 2335}
2312 2336
@@ -2321,144 +2345,146 @@ static int SetAgcIf(struct drxk_state *state,
2321 2345
2322 dprintk(1, "\n"); 2346 dprintk(1, "\n");
2323 2347
2324 do { 2348 switch (pAgcCfg->ctrlMode) {
2325 switch (pAgcCfg->ctrlMode) { 2349 case DRXK_AGC_CTRL_AUTO:
2326 case DRXK_AGC_CTRL_AUTO:
2327
2328 /* Enable IF AGC DAC */
2329 status = read16(state, IQM_AF_STDBY__A, &data);
2330 if (status < 0)
2331 break;
2332 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2333 status = write16(state, IQM_AF_STDBY__A, data);
2334 if (status < 0)
2335 break;
2336
2337 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2338 if (status < 0)
2339 break;
2340 2350
2341 /* Enable SCU IF AGC loop */ 2351 /* Enable IF AGC DAC */
2342 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2352 status = read16(state, IQM_AF_STDBY__A, &data);
2353 if (status < 0)
2354 goto error;
2355 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2356 status = write16(state, IQM_AF_STDBY__A, data);
2357 if (status < 0)
2358 goto error;
2343 2359
2344 /* Polarity */ 2360 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2345 if (state->m_IfAgcPol) 2361 if (status < 0)
2346 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2362 goto error;
2347 else
2348 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2349 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2350 if (status < 0)
2351 break;
2352 2363
2353 /* Set speed (using complementary reduction value) */ 2364 /* Enable SCU IF AGC loop */
2354 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2365 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2355 if (status < 0)
2356 break;
2357 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2358 data |= (~(pAgcCfg->speed <<
2359 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2360 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2361 2366
2362 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2367 /* Polarity */
2363 if (status < 0) 2368 if (state->m_IfAgcPol)
2364 break; 2369 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2370 else
2371 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2372 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2373 if (status < 0)
2374 goto error;
2365 2375
2366 if (IsQAM(state)) 2376 /* Set speed (using complementary reduction value) */
2367 pRfAgcSettings = &state->m_qamRfAgcCfg; 2377 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2368 else 2378 if (status < 0)
2369 pRfAgcSettings = &state->m_atvRfAgcCfg; 2379 goto error;
2370 if (pRfAgcSettings == NULL) 2380 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2371 return -1; 2381 data |= (~(pAgcCfg->speed <<
2372 /* Restore TOP */ 2382 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2373 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); 2383 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2374 if (status < 0)
2375 break;
2376 break;
2377 2384
2378 case DRXK_AGC_CTRL_USER: 2385 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2386 if (status < 0)
2387 goto error;
2379 2388
2380 /* Enable IF AGC DAC */ 2389 if (IsQAM(state))
2381 status = read16(state, IQM_AF_STDBY__A, &data); 2390 pRfAgcSettings = &state->m_qamRfAgcCfg;
2382 if (status < 0) 2391 else
2383 break; 2392 pRfAgcSettings = &state->m_atvRfAgcCfg;
2384 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2393 if (pRfAgcSettings == NULL)
2385 status = write16(state, IQM_AF_STDBY__A, data); 2394 return -1;
2386 if (status < 0) 2395 /* Restore TOP */
2387 break; 2396 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2397 if (status < 0)
2398 goto error;
2399 break;
2388 2400
2389 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2401 case DRXK_AGC_CTRL_USER:
2390 if (status < 0)
2391 break;
2392 2402
2393 /* Disable SCU IF AGC loop */ 2403 /* Enable IF AGC DAC */
2394 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2404 status = read16(state, IQM_AF_STDBY__A, &data);
2405 if (status < 0)
2406 goto error;
2407 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2408 status = write16(state, IQM_AF_STDBY__A, data);
2409 if (status < 0)
2410 goto error;
2395 2411
2396 /* Polarity */ 2412 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2397 if (state->m_IfAgcPol) 2413 if (status < 0)
2398 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2414 goto error;
2399 else
2400 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2401 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2402 if (status < 0)
2403 break;
2404 2415
2405 /* Write value to output pin */ 2416 /* Disable SCU IF AGC loop */
2406 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); 2417 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2407 if (status < 0)
2408 break;
2409 break;
2410 2418
2411 case DRXK_AGC_CTRL_OFF: 2419 /* Polarity */
2420 if (state->m_IfAgcPol)
2421 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2422 else
2423 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2424 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2425 if (status < 0)
2426 goto error;
2412 2427
2413 /* Disable If AGC DAC */ 2428 /* Write value to output pin */
2414 status = read16(state, IQM_AF_STDBY__A, &data); 2429 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2415 if (status < 0) 2430 if (status < 0)
2416 break; 2431 goto error;
2417 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2432 break;
2418 status = write16(state, IQM_AF_STDBY__A, data);
2419 if (status < 0)
2420 break;
2421 2433
2422 /* Disable SCU IF AGC loop */ 2434 case DRXK_AGC_CTRL_OFF:
2423 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2424 if (status < 0)
2425 break;
2426 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2427 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2428 if (status < 0)
2429 break;
2430 break;
2431 } /* switch (agcSettingsIf->ctrlMode) */
2432 2435
2433 /* always set the top to support 2436 /* Disable If AGC DAC */
2434 configurations without if-loop */ 2437 status = read16(state, IQM_AF_STDBY__A, &data);
2435 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2436 if (status < 0) 2438 if (status < 0)
2437 break; 2439 goto error;
2440 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2441 status = write16(state, IQM_AF_STDBY__A, data);
2442 if (status < 0)
2443 goto error;
2438 2444
2445 /* Disable SCU IF AGC loop */
2446 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2447 if (status < 0)
2448 goto error;
2449 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2450 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2451 if (status < 0)
2452 goto error;
2453 break;
2454 } /* switch (agcSettingsIf->ctrlMode) */
2439 2455
2440 } while (0); 2456 /* always set the top to support
2457 configurations without if-loop */
2458 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2459error:
2460 if (status < 0)
2461 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2441 return status; 2462 return status;
2442} 2463}
2443 2464
2444static int ReadIFAgc(struct drxk_state *state, u32 *pValue) 2465static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2445{ 2466{
2446 u16 agcDacLvl; 2467 u16 agcDacLvl;
2447 int status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl); 2468 int status;
2469 u16 Level = 0;
2448 2470
2449 dprintk(1, "\n"); 2471 dprintk(1, "\n");
2450 2472
2473 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2474 if (status < 0) {
2475 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2476 return status;
2477 }
2478
2451 *pValue = 0; 2479 *pValue = 0;
2452 2480
2453 if (status == 0) { 2481 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2454 u16 Level = 0; 2482 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2455 if (agcDacLvl > DRXK_AGC_DAC_OFFSET) 2483 if (Level < 14000)
2456 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; 2484 *pValue = (14000 - Level) / 4;
2457 if (Level < 14000) 2485 else
2458 *pValue = (14000 - Level) / 4; 2486 *pValue = 0;
2459 else 2487
2460 *pValue = 0;
2461 }
2462 return status; 2488 return status;
2463} 2489}
2464 2490
@@ -2466,55 +2492,55 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2466 s32 *pSignalToNoise) 2492 s32 *pSignalToNoise)
2467{ 2493{
2468 int status = 0; 2494 int status = 0;
2495 u16 qamSlErrPower = 0; /* accum. error between
2496 raw and sliced symbols */
2497 u32 qamSlSigPower = 0; /* used for MER, depends of
2498 QAM constellation */
2499 u32 qamSlMer = 0; /* QAM MER */
2469 2500
2470 dprintk(1, "\n"); 2501 dprintk(1, "\n");
2471 2502
2472 do { 2503 /* MER calculation */
2473 /* MER calculation */
2474 u16 qamSlErrPower = 0; /* accum. error between
2475 raw and sliced symbols */
2476 u32 qamSlSigPower = 0; /* used for MER, depends of
2477 QAM constellation */
2478 u32 qamSlMer = 0; /* QAM MER */
2479
2480 /* get the register value needed for MER */
2481 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2482 if (status < 0)
2483 break;
2484 2504
2485 switch (state->param.u.qam.modulation) { 2505 /* get the register value needed for MER */
2486 case QAM_16: 2506 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2487 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2507 if (status < 0) {
2488 break; 2508 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2489 case QAM_32: 2509 return -EINVAL;
2490 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; 2510 }
2491 break; 2511
2492 case QAM_64: 2512 switch (state->param.u.qam.modulation) {
2493 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; 2513 case QAM_16:
2494 break; 2514 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2495 case QAM_128: 2515 break;
2496 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; 2516 case QAM_32:
2497 break; 2517 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2498 default: 2518 break;
2499 case QAM_256: 2519 case QAM_64:
2500 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; 2520 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2501 break; 2521 break;
2502 } 2522 case QAM_128:
2523 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2524 break;
2525 default:
2526 case QAM_256:
2527 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2528 break;
2529 }
2530
2531 if (qamSlErrPower > 0) {
2532 qamSlMer = Log10Times100(qamSlSigPower) -
2533 Log10Times100((u32) qamSlErrPower);
2534 }
2535 *pSignalToNoise = qamSlMer;
2503 2536
2504 if (qamSlErrPower > 0) {
2505 qamSlMer = Log10Times100(qamSlSigPower) -
2506 Log10Times100((u32) qamSlErrPower);
2507 }
2508 *pSignalToNoise = qamSlMer;
2509 } while (0);
2510 return status; 2537 return status;
2511} 2538}
2512 2539
2513static int GetDVBTSignalToNoise(struct drxk_state *state, 2540static int GetDVBTSignalToNoise(struct drxk_state *state,
2514 s32 *pSignalToNoise) 2541 s32 *pSignalToNoise)
2515{ 2542{
2516 int status = 0; 2543 int status;
2517
2518 u16 regData = 0; 2544 u16 regData = 0;
2519 u32 EqRegTdSqrErrI = 0; 2545 u32 EqRegTdSqrErrI = 0;
2520 u32 EqRegTdSqrErrQ = 0; 2546 u32 EqRegTdSqrErrQ = 0;
@@ -2530,86 +2556,88 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,
2530 u16 transmissionParams = 0; 2556 u16 transmissionParams = 0;
2531 2557
2532 dprintk(1, "\n"); 2558 dprintk(1, "\n");
2533 do {
2534 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2535 if (status < 0)
2536 break;
2537 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2538 if (status < 0)
2539 break;
2540 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2541 if (status < 0)
2542 break;
2543 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2544 if (status < 0)
2545 break;
2546 /* Extend SQR_ERR_I operational range */
2547 EqRegTdSqrErrI = (u32) regData;
2548 if ((EqRegTdSqrErrExp > 11) &&
2549 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2550 EqRegTdSqrErrI += 0x00010000UL;
2551 }
2552 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2553 if (status < 0)
2554 break;
2555 /* Extend SQR_ERR_Q operational range */
2556 EqRegTdSqrErrQ = (u32) regData;
2557 if ((EqRegTdSqrErrExp > 11) &&
2558 (EqRegTdSqrErrQ < 0x00000FFFUL))
2559 EqRegTdSqrErrQ += 0x00010000UL;
2560 2559
2561 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); 2560 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2562 if (status < 0) 2561 if (status < 0)
2563 break; 2562 goto error;
2563 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2564 if (status < 0)
2565 goto error;
2566 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2567 if (status < 0)
2568 goto error;
2569 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2570 if (status < 0)
2571 goto error;
2572 /* Extend SQR_ERR_I operational range */
2573 EqRegTdSqrErrI = (u32) regData;
2574 if ((EqRegTdSqrErrExp > 11) &&
2575 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2576 EqRegTdSqrErrI += 0x00010000UL;
2577 }
2578 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2579 if (status < 0)
2580 goto error;
2581 /* Extend SQR_ERR_Q operational range */
2582 EqRegTdSqrErrQ = (u32) regData;
2583 if ((EqRegTdSqrErrExp > 11) &&
2584 (EqRegTdSqrErrQ < 0x00000FFFUL))
2585 EqRegTdSqrErrQ += 0x00010000UL;
2586
2587 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2588 if (status < 0)
2589 goto error;
2564 2590
2565 /* Check input data for MER */ 2591 /* Check input data for MER */
2566 2592
2567 /* MER calculation (in 0.1 dB) without math.h */ 2593 /* MER calculation (in 0.1 dB) without math.h */
2568 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) 2594 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2569 iMER = 0; 2595 iMER = 0;
2570 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { 2596 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2571 /* No error at all, this must be the HW reset value 2597 /* No error at all, this must be the HW reset value
2572 * Apparently no first measurement yet 2598 * Apparently no first measurement yet
2573 * Set MER to 0.0 */ 2599 * Set MER to 0.0 */
2600 iMER = 0;
2601 } else {
2602 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2603 EqRegTdSqrErrExp;
2604 if ((transmissionParams &
2605 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2606 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2607 tpsCnt = 17;
2608 else
2609 tpsCnt = 68;
2610
2611 /* IMER = 100 * log10 (x)
2612 where x = (EqRegTdTpsPwrOfs^2 *
2613 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2614
2615 => IMER = a + b -c
2616 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2617 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2618 c = 100 * log10 (SqrErrIQ)
2619 */
2620
2621 /* log(x) x = 9bits * 9bits->18 bits */
2622 a = Log10Times100(EqRegTdTpsPwrOfs *
2623 EqRegTdTpsPwrOfs);
2624 /* log(x) x = 16bits * 7bits->23 bits */
2625 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2626 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2627 c = Log10Times100(SqrErrIQ);
2628
2629 iMER = a + b;
2630 /* No negative MER, clip to zero */
2631 if (iMER > c)
2632 iMER -= c;
2633 else
2574 iMER = 0; 2634 iMER = 0;
2575 } else { 2635 }
2576 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << 2636 *pSignalToNoise = iMER;
2577 EqRegTdSqrErrExp;
2578 if ((transmissionParams &
2579 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2580 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2581 tpsCnt = 17;
2582 else
2583 tpsCnt = 68;
2584
2585 /* IMER = 100 * log10 (x)
2586 where x = (EqRegTdTpsPwrOfs^2 *
2587 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2588
2589 => IMER = a + b -c
2590 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2591 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2592 c = 100 * log10 (SqrErrIQ)
2593 */
2594
2595 /* log(x) x = 9bits * 9bits->18 bits */
2596 a = Log10Times100(EqRegTdTpsPwrOfs *
2597 EqRegTdTpsPwrOfs);
2598 /* log(x) x = 16bits * 7bits->23 bits */
2599 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2600 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2601 c = Log10Times100(SqrErrIQ);
2602
2603 iMER = a + b;
2604 /* No negative MER, clip to zero */
2605 if (iMER > c)
2606 iMER -= c;
2607 else
2608 iMER = 0;
2609 }
2610 *pSignalToNoise = iMER;
2611 } while (0);
2612 2637
2638error:
2639 if (status < 0)
2640 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2613 return status; 2641 return status;
2614} 2642}
2615 2643
@@ -2775,50 +2803,54 @@ static int GetQuality(struct drxk_state *state, s32 *pQuality)
2775 2803
2776static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) 2804static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2777{ 2805{
2778 int status; 2806 int status = -EINVAL;
2779 2807
2780 dprintk(1, "\n"); 2808 dprintk(1, "\n");
2781 2809
2782 if (state->m_DrxkState == DRXK_UNINITIALIZED) 2810 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2783 return -1; 2811 goto error;
2784 if (state->m_DrxkState == DRXK_POWERED_DOWN) 2812 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2785 return -1; 2813 goto error;
2786 2814
2787 if (state->no_i2c_bridge) 2815 if (state->no_i2c_bridge)
2788 return 0; 2816 return 0;
2789 do {
2790 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2791 if (status < 0)
2792 break;
2793 if (bEnableBridge) {
2794 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2795 if (status < 0)
2796 break;
2797 } else {
2798 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2799 if (status < 0)
2800 break;
2801 }
2802 2817
2803 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); 2818 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2819 if (status < 0)
2820 goto error;
2821 if (bEnableBridge) {
2822 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2804 if (status < 0) 2823 if (status < 0)
2805 break; 2824 goto error;
2806 } while (0); 2825 } else {
2826 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2827 if (status < 0)
2828 goto error;
2829 }
2830
2831 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2832
2833error:
2834 if (status < 0)
2835 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2807 return status; 2836 return status;
2808} 2837}
2809 2838
2810static int SetPreSaw(struct drxk_state *state, 2839static int SetPreSaw(struct drxk_state *state,
2811 struct SCfgPreSaw *pPreSawCfg) 2840 struct SCfgPreSaw *pPreSawCfg)
2812{ 2841{
2813 int status; 2842 int status = -EINVAL;
2814 2843
2815 dprintk(1, "\n"); 2844 dprintk(1, "\n");
2816 2845
2817 if ((pPreSawCfg == NULL) 2846 if ((pPreSawCfg == NULL)
2818 || (pPreSawCfg->reference > IQM_AF_PDREF__M)) 2847 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2819 return -1; 2848 goto error;
2820 2849
2821 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); 2850 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2851error:
2852 if (status < 0)
2853 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2822 return status; 2854 return status;
2823} 2855}
2824 2856
@@ -2834,38 +2866,40 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2834 dprintk(1, "\n"); 2866 dprintk(1, "\n");
2835 2867
2836 mutex_lock(&state->mutex); 2868 mutex_lock(&state->mutex);
2869 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2870 if (status < 0)
2871 goto error;
2872 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2873 if (status < 0)
2874 goto error;
2875 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2876 if (status < 0)
2877 goto error;
2878 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2879 if (status < 0)
2880 goto error;
2881 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2882 if (status < 0)
2883 goto error;
2884 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2885 if (status < 0)
2886 goto error;
2887
2888 end = jiffies + msecs_to_jiffies(timeOut);
2837 do { 2889 do {
2838 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); 2890 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2839 if (status < 0)
2840 break;
2841 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2842 if (status < 0) 2891 if (status < 0)
2843 break; 2892 goto error;
2844 status = write16(state, SIO_BL_TGT_ADDR__A, offset); 2893 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2845 if (status < 0) 2894 if (blStatus == 0x1) {
2846 break; 2895 printk(KERN_ERR "drxk: SIO not ready\n");
2847 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); 2896 status = -EINVAL;
2848 if (status < 0) 2897 goto error2;
2849 break; 2898 }
2850 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); 2899error:
2851 if (status < 0) 2900 if (status < 0)
2852 break; 2901 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2853 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2902error2:
2854 if (status < 0)
2855 break;
2856
2857 end = jiffies + msecs_to_jiffies(timeOut);
2858 do {
2859 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2860 if (status < 0)
2861 break;
2862 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2863 if (blStatus == 0x1) {
2864 printk(KERN_ERR "drxk: SIO not ready\n");
2865 mutex_unlock(&state->mutex);
2866 return -1;
2867 }
2868 } while (0);
2869 mutex_unlock(&state->mutex); 2903 mutex_unlock(&state->mutex);
2870 return status; 2904 return status;
2871 2905
@@ -2878,32 +2912,34 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2878 2912
2879 dprintk(1, "\n"); 2913 dprintk(1, "\n");
2880 2914
2881 do { 2915 /* Start measurement */
2882 /* Start measurement */ 2916 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2883 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2917 if (status < 0)
2884 if (status < 0) 2918 goto error;
2885 break; 2919 status = write16(state, IQM_AF_START_LOCK__A, 1);
2886 status = write16(state, IQM_AF_START_LOCK__A, 1); 2920 if (status < 0)
2887 if (status < 0) 2921 goto error;
2888 break;
2889 2922
2890 *count = 0; 2923 *count = 0;
2891 status = read16(state, IQM_AF_PHASE0__A, &data); 2924 status = read16(state, IQM_AF_PHASE0__A, &data);
2892 if (status < 0) 2925 if (status < 0)
2893 break; 2926 goto error;
2894 if (data == 127) 2927 if (data == 127)
2895 *count = *count + 1; 2928 *count = *count + 1;
2896 status = read16(state, IQM_AF_PHASE1__A, &data); 2929 status = read16(state, IQM_AF_PHASE1__A, &data);
2897 if (status < 0) 2930 if (status < 0)
2898 break; 2931 goto error;
2899 if (data == 127) 2932 if (data == 127)
2900 *count = *count + 1; 2933 *count = *count + 1;
2901 status = read16(state, IQM_AF_PHASE2__A, &data); 2934 status = read16(state, IQM_AF_PHASE2__A, &data);
2902 if (status < 0) 2935 if (status < 0)
2903 break; 2936 goto error;
2904 if (data == 127) 2937 if (data == 127)
2905 *count = *count + 1; 2938 *count = *count + 1;
2906 } while (0); 2939
2940error:
2941 if (status < 0)
2942 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2907 return status; 2943 return status;
2908} 2944}
2909 2945
@@ -2914,39 +2950,40 @@ static int ADCSynchronization(struct drxk_state *state)
2914 2950
2915 dprintk(1, "\n"); 2951 dprintk(1, "\n");
2916 2952
2917 do { 2953 status = ADCSyncMeasurement(state, &count);
2918 status = ADCSyncMeasurement(state, &count); 2954 if (status < 0)
2919 if (status < 0) 2955 goto error;
2920 break;
2921 2956
2922 if (count == 1) { 2957 if (count == 1) {
2923 /* Try sampling on a diffrent edge */ 2958 /* Try sampling on a diffrent edge */
2924 u16 clkNeg = 0; 2959 u16 clkNeg = 0;
2925 2960
2926 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); 2961 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2927 if (status < 0) 2962 if (status < 0)
2928 break; 2963 goto error;
2929 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == 2964 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2930 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2965 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2931 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2966 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2932 clkNeg |= 2967 clkNeg |=
2933 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; 2968 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2934 } else { 2969 } else {
2935 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2970 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2936 clkNeg |= 2971 clkNeg |=
2937 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2972 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2938 }
2939 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2940 if (status < 0)
2941 break;
2942 status = ADCSyncMeasurement(state, &count);
2943 if (status < 0)
2944 break;
2945 } 2973 }
2974 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2975 if (status < 0)
2976 goto error;
2977 status = ADCSyncMeasurement(state, &count);
2978 if (status < 0)
2979 goto error;
2980 }
2946 2981
2947 if (count < 2) 2982 if (count < 2)
2948 status = -1; 2983 status = -EINVAL;
2949 } while (0); 2984error:
2985 if (status < 0)
2986 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2950 return status; 2987 return status;
2951} 2988}
2952 2989
@@ -3011,6 +3048,8 @@ static int SetFrequencyShifter(struct drxk_state *state,
3011 /* frequencyShift += tunerFreqOffset; TODO */ 3048 /* frequencyShift += tunerFreqOffset; TODO */
3012 status = write32(state, IQM_FS_RATE_OFS_LO__A, 3049 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3013 state->m_IqmFsRateOfs); 3050 state->m_IqmFsRateOfs);
3051 if (status < 0)
3052 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3014 return status; 3053 return status;
3015} 3054}
3016 3055
@@ -3037,177 +3076,175 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
3037 3076
3038 dprintk(1, "\n"); 3077 dprintk(1, "\n");
3039 3078
3040 do { 3079 /* Common settings */
3041 /* Common settings */ 3080 snsSumMax = 1023;
3042 snsSumMax = 1023; 3081 ifIaccuHiTgtMin = 2047;
3043 ifIaccuHiTgtMin = 2047; 3082 clpCyclen = 500;
3044 clpCyclen = 500; 3083 clpSumMax = 1023;
3045 clpSumMax = 1023; 3084
3046 3085 if (IsQAM(state)) {
3047 if (IsQAM(state)) { 3086 /* Standard specific settings */
3048 /* Standard specific settings */ 3087 clpSumMin = 8;
3049 clpSumMin = 8; 3088 clpDirTo = (u16) -9;
3050 clpDirTo = (u16) -9; 3089 clpCtrlMode = 0;
3051 clpCtrlMode = 0; 3090 snsSumMin = 8;
3052 snsSumMin = 8; 3091 snsDirTo = (u16) -9;
3053 snsDirTo = (u16) -9; 3092 kiInnergainMin = (u16) -1030;
3054 kiInnergainMin = (u16) -1030; 3093 } else {
3055 } else 3094 status = -EINVAL;
3056 status = -1; 3095 goto error;
3057 status = (status); 3096 }
3058 if (status < 0) 3097 if (IsQAM(state)) {
3059 break; 3098 ifIaccuHiTgtMax = 0x2380;
3060 if (IsQAM(state)) { 3099 ifIaccuHiTgt = 0x2380;
3061 ifIaccuHiTgtMax = 0x2380; 3100 ingainTgtMin = 0x0511;
3062 ifIaccuHiTgt = 0x2380; 3101 ingainTgt = 0x0511;
3063 ingainTgtMin = 0x0511; 3102 ingainTgtMax = 5119;
3064 ingainTgt = 0x0511; 3103 fastClpCtrlDelay =
3065 ingainTgtMax = 5119; 3104 state->m_qamIfAgcCfg.FastClipCtrlDelay;
3066 fastClpCtrlDelay = 3105 } else {
3067 state->m_qamIfAgcCfg.FastClipCtrlDelay; 3106 ifIaccuHiTgtMax = 0x1200;
3068 } else { 3107 ifIaccuHiTgt = 0x1200;
3069 ifIaccuHiTgtMax = 0x1200; 3108 ingainTgtMin = 13424;
3070 ifIaccuHiTgt = 0x1200; 3109 ingainTgt = 13424;
3071 ingainTgtMin = 13424; 3110 ingainTgtMax = 30000;
3072 ingainTgt = 13424; 3111 fastClpCtrlDelay =
3073 ingainTgtMax = 30000; 3112 state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
3074 fastClpCtrlDelay = 3113 }
3075 state->m_dvbtIfAgcCfg.FastClipCtrlDelay; 3114 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3076 } 3115 if (status < 0)
3077 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); 3116 goto error;
3078 if (status < 0)
3079 break;
3080 3117
3081 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); 3118 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3082 if (status < 0) 3119 if (status < 0)
3083 break; 3120 goto error;
3084 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); 3121 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3085 if (status < 0) 3122 if (status < 0)
3086 break; 3123 goto error;
3087 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); 3124 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3088 if (status < 0) 3125 if (status < 0)
3089 break; 3126 goto error;
3090 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); 3127 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3091 if (status < 0) 3128 if (status < 0)
3092 break; 3129 goto error;
3093 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); 3130 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3094 if (status < 0) 3131 if (status < 0)
3095 break; 3132 goto error;
3096 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); 3133 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3097 if (status < 0) 3134 if (status < 0)
3098 break; 3135 goto error;
3099 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3136 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3100 if (status < 0) 3137 if (status < 0)
3101 break; 3138 goto error;
3102 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); 3139 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3103 if (status < 0) 3140 if (status < 0)
3104 break; 3141 goto error;
3105 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); 3142 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3106 if (status < 0) 3143 if (status < 0)
3107 break; 3144 goto error;
3108 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3145 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3109 if (status < 0) 3146 if (status < 0)
3110 break; 3147 goto error;
3111 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); 3148 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3112 if (status < 0) 3149 if (status < 0)
3113 break; 3150 goto error;
3114 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); 3151 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3115 if (status < 0) 3152 if (status < 0)
3116 break; 3153 goto error;
3117 3154
3118 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); 3155 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3119 if (status < 0) 3156 if (status < 0)
3120 break; 3157 goto error;
3121 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); 3158 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3122 if (status < 0) 3159 if (status < 0)
3123 break; 3160 goto error;
3124 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); 3161 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3125 if (status < 0) 3162 if (status < 0)
3126 break; 3163 goto error;
3127 3164
3128 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); 3165 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3129 if (status < 0) 3166 if (status < 0)
3130 break; 3167 goto error;
3131 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); 3168 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3132 if (status < 0) 3169 if (status < 0)
3133 break; 3170 goto error;
3134 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); 3171 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3135 if (status < 0) 3172 if (status < 0)
3136 break; 3173 goto error;
3137 3174
3138 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3175 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3139 if (status < 0) 3176 if (status < 0)
3140 break; 3177 goto error;
3141 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); 3178 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3142 if (status < 0) 3179 if (status < 0)
3143 break; 3180 goto error;
3144 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); 3181 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3145 if (status < 0) 3182 if (status < 0)
3146 break; 3183 goto error;
3147 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); 3184 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3148 if (status < 0) 3185 if (status < 0)
3149 break; 3186 goto error;
3150 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); 3187 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3151 if (status < 0) 3188 if (status < 0)
3152 break; 3189 goto error;
3153 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3190 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3154 if (status < 0) 3191 if (status < 0)
3155 break; 3192 goto error;
3156 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); 3193 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3157 if (status < 0) 3194 if (status < 0)
3158 break; 3195 goto error;
3159 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); 3196 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3160 if (status < 0) 3197 if (status < 0)
3161 break; 3198 goto error;
3162 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); 3199 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3163 if (status < 0) 3200 if (status < 0)
3164 break; 3201 goto error;
3165 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); 3202 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3166 if (status < 0) 3203 if (status < 0)
3167 break; 3204 goto error;
3168 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); 3205 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3169 if (status < 0) 3206 if (status < 0)
3170 break; 3207 goto error;
3171 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); 3208 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3172 if (status < 0) 3209 if (status < 0)
3173 break; 3210 goto error;
3174 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); 3211 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3175 if (status < 0) 3212 if (status < 0)
3176 break; 3213 goto error;
3177 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); 3214 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3178 if (status < 0) 3215 if (status < 0)
3179 break; 3216 goto error;
3180 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); 3217 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3181 if (status < 0) 3218 if (status < 0)
3182 break; 3219 goto error;
3183 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); 3220 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3184 if (status < 0) 3221 if (status < 0)
3185 break; 3222 goto error;
3186 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); 3223 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3187 if (status < 0) 3224 if (status < 0)
3188 break; 3225 goto error;
3189 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); 3226 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3190 if (status < 0) 3227 if (status < 0)
3191 break; 3228 goto error;
3192 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); 3229 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3193 if (status < 0) 3230 if (status < 0)
3194 break; 3231 goto error;
3195 3232
3196 /* Initialize inner-loop KI gain factors */ 3233 /* Initialize inner-loop KI gain factors */
3197 status = read16(state, SCU_RAM_AGC_KI__A, &data); 3234 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3198 if (status < 0) 3235 if (status < 0)
3199 break; 3236 goto error;
3200 if (IsQAM(state)) { 3237 if (IsQAM(state)) {
3201 data = 0x0657; 3238 data = 0x0657;
3202 data &= ~SCU_RAM_AGC_KI_RF__M; 3239 data &= ~SCU_RAM_AGC_KI_RF__M;
3203 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); 3240 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3204 data &= ~SCU_RAM_AGC_KI_IF__M; 3241 data &= ~SCU_RAM_AGC_KI_IF__M;
3205 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3242 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3206 } 3243 }
3207 status = write16(state, SCU_RAM_AGC_KI__A, data); 3244 status = write16(state, SCU_RAM_AGC_KI__A, data);
3208 if (status < 0) 3245error:
3209 break; 3246 if (status < 0)
3210 } while (0); 3247 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3211 return status; 3248 return status;
3212} 3249}
3213 3250
@@ -3216,17 +3253,12 @@ static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3216 int status; 3253 int status;
3217 3254
3218 dprintk(1, "\n"); 3255 dprintk(1, "\n");
3219 do { 3256 if (packetErr == NULL)
3220 if (packetErr == NULL) { 3257 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3221 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3258 else
3222 if (status < 0) 3259 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3223 break; 3260 if (status < 0)
3224 } else { 3261 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3225 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3226 if (status < 0)
3227 break;
3228 }
3229 } while (0);
3230 return status; 3262 return status;
3231} 3263}
3232 3264
@@ -3245,8 +3277,10 @@ static int DVBTScCommand(struct drxk_state *state,
3245 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); 3277 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3246 if (scExec != 1) { 3278 if (scExec != 1) {
3247 /* SC is not running */ 3279 /* SC is not running */
3248 return -1; 3280 status = -EINVAL;
3249 } 3281 }
3282 if (status < 0)
3283 goto error;
3250 3284
3251 /* Wait until sc is ready to receive command */ 3285 /* Wait until sc is ready to receive command */
3252 retryCnt = 0; 3286 retryCnt = 0;
@@ -3255,21 +3289,23 @@ static int DVBTScCommand(struct drxk_state *state,
3255 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3289 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3256 retryCnt++; 3290 retryCnt++;
3257 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3291 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3258 if (retryCnt >= DRXK_MAX_RETRIES) 3292 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3259 return -1; 3293 goto error;
3294
3260 /* Write sub-command */ 3295 /* Write sub-command */
3261 switch (cmd) { 3296 switch (cmd) {
3262 /* All commands using sub-cmd */ 3297 /* All commands using sub-cmd */
3263 case OFDM_SC_RA_RAM_CMD_PROC_START: 3298 case OFDM_SC_RA_RAM_CMD_PROC_START:
3264 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3299 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3265 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3300 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3266 status = 3301 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3267 write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); 3302 if (status < 0)
3303 goto error;
3268 break; 3304 break;
3269 default: 3305 default:
3270 /* Do nothing */ 3306 /* Do nothing */
3271 break; 3307 break;
3272 } /* switch (cmd->cmd) */ 3308 }
3273 3309
3274 /* Write needed parameters and the command */ 3310 /* Write needed parameters and the command */
3275 switch (cmd) { 3311 switch (cmd) {
@@ -3280,13 +3316,11 @@ static int DVBTScCommand(struct drxk_state *state,
3280 case OFDM_SC_RA_RAM_CMD_PROC_START: 3316 case OFDM_SC_RA_RAM_CMD_PROC_START:
3281 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3317 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3282 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3318 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3283 status = 3319 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3284 write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3285 /* All commands using 1 parameters */ 3320 /* All commands using 1 parameters */
3286 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3321 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3287 case OFDM_SC_RA_RAM_CMD_USER_IO: 3322 case OFDM_SC_RA_RAM_CMD_USER_IO:
3288 status = 3323 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3289 write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3290 /* All commands using 0 parameters */ 3324 /* All commands using 0 parameters */
3291 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3325 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3292 case OFDM_SC_RA_RAM_CMD_NULL: 3326 case OFDM_SC_RA_RAM_CMD_NULL:
@@ -3295,8 +3329,10 @@ static int DVBTScCommand(struct drxk_state *state,
3295 break; 3329 break;
3296 default: 3330 default:
3297 /* Unknown command */ 3331 /* Unknown command */
3298 return -EINVAL; 3332 status = -EINVAL;
3299 } /* switch (cmd->cmd) */ 3333 }
3334 if (status < 0)
3335 goto error;
3300 3336
3301 /* Wait until sc is ready processing command */ 3337 /* Wait until sc is ready processing command */
3302 retryCnt = 0; 3338 retryCnt = 0;
@@ -3305,15 +3341,17 @@ static int DVBTScCommand(struct drxk_state *state,
3305 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3341 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3306 retryCnt++; 3342 retryCnt++;
3307 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3343 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3308 if (retryCnt >= DRXK_MAX_RETRIES) 3344 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3309 return -1; 3345 goto error;
3310 3346
3311 /* Check for illegal cmd */ 3347 /* Check for illegal cmd */
3312 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); 3348 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3313 if (errCode == 0xFFFF) { 3349 if (errCode == 0xFFFF) {
3314 /* illegal command */ 3350 /* illegal command */
3315 return -EINVAL; 3351 status = -EINVAL;
3316 } 3352 }
3353 if (status < 0)
3354 goto error;
3317 3355
3318 /* Retreive results parameters from SC */ 3356 /* Retreive results parameters from SC */
3319 switch (cmd) { 3357 switch (cmd) {
@@ -3324,8 +3362,7 @@ static int DVBTScCommand(struct drxk_state *state,
3324 /* All commands yielding 1 result */ 3362 /* All commands yielding 1 result */
3325 case OFDM_SC_RA_RAM_CMD_USER_IO: 3363 case OFDM_SC_RA_RAM_CMD_USER_IO:
3326 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3364 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3327 status = 3365 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3328 read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3329 /* All commands yielding 0 results */ 3366 /* All commands yielding 0 results */
3330 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3367 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3331 case OFDM_SC_RA_RAM_CMD_SET_TIMER: 3368 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
@@ -3336,9 +3373,12 @@ static int DVBTScCommand(struct drxk_state *state,
3336 break; 3373 break;
3337 default: 3374 default:
3338 /* Unknown command */ 3375 /* Unknown command */
3339 return -EINVAL; 3376 status = -EINVAL;
3340 break; 3377 break;
3341 } /* switch (cmd->cmd) */ 3378 } /* switch (cmd->cmd) */
3379error:
3380 if (status < 0)
3381 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3342 return status; 3382 return status;
3343} 3383}
3344 3384
@@ -3348,11 +3388,9 @@ static int PowerUpDVBT(struct drxk_state *state)
3348 int status; 3388 int status;
3349 3389
3350 dprintk(1, "\n"); 3390 dprintk(1, "\n");
3351 do { 3391 status = CtrlPowerMode(state, &powerMode);
3352 status = CtrlPowerMode(state, &powerMode); 3392 if (status < 0)
3353 if (status < 0) 3393 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3354 break;
3355 } while (0);
3356 return status; 3394 return status;
3357} 3395}
3358 3396
@@ -3365,7 +3403,8 @@ static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3365 status = write16(state, IQM_CF_BYPASSDET__A, 0); 3403 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3366 else 3404 else
3367 status = write16(state, IQM_CF_BYPASSDET__A, 1); 3405 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3368 3406 if (status < 0)
3407 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3369 return status; 3408 return status;
3370} 3409}
3371 3410
@@ -3384,6 +3423,8 @@ static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3384 /* write mask to 0 */ 3423 /* write mask to 0 */
3385 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); 3424 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3386 } 3425 }
3426 if (status < 0)
3427 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3387 3428
3388 return status; 3429 return status;
3389} 3430}
@@ -3395,43 +3436,39 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3395 int status; 3436 int status;
3396 3437
3397 dprintk(1, "\n"); 3438 dprintk(1, "\n");
3398 do { 3439 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3399 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); 3440 if (status < 0)
3400 if (status < 0) 3441 goto error;
3401 break;
3402
3403 switch (echoThres->fftMode) {
3404 case DRX_FFTMODE_2K:
3405 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3406 data |=
3407 ((echoThres->threshold <<
3408 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3409 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3410 break;
3411 case DRX_FFTMODE_8K:
3412 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3413 data |=
3414 ((echoThres->threshold <<
3415 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3416 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3417 break;
3418 default:
3419 return -1;
3420 break;
3421 }
3422 3442
3423 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); 3443 switch (echoThres->fftMode) {
3424 if (status < 0) 3444 case DRX_FFTMODE_2K:
3425 break; 3445 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3426 } while (0); 3446 data |= ((echoThres->threshold <<
3447 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3448 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3449 goto error;
3450 case DRX_FFTMODE_8K:
3451 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3452 data |= ((echoThres->threshold <<
3453 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3454 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3455 goto error;
3456 default:
3457 return -EINVAL;
3458 goto error;
3459 }
3427 3460
3461 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3462error:
3463 if (status < 0)
3464 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3428 return status; 3465 return status;
3429} 3466}
3430 3467
3431static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, 3468static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3432 enum DRXKCfgDvbtSqiSpeed *speed) 3469 enum DRXKCfgDvbtSqiSpeed *speed)
3433{ 3470{
3434 int status; 3471 int status = -EINVAL;
3435 3472
3436 dprintk(1, "\n"); 3473 dprintk(1, "\n");
3437 3474
@@ -3441,10 +3478,13 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3441 case DRXK_DVBT_SQI_SPEED_SLOW: 3478 case DRXK_DVBT_SQI_SPEED_SLOW:
3442 break; 3479 break;
3443 default: 3480 default:
3444 return -EINVAL; 3481 goto error;
3445 } 3482 }
3446 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, 3483 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3447 (u16) *speed); 3484 (u16) *speed);
3485error:
3486 if (status < 0)
3487 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3448 return status; 3488 return status;
3449} 3489}
3450 3490
@@ -3461,31 +3501,29 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3461static int DVBTActivatePresets(struct drxk_state *state) 3501static int DVBTActivatePresets(struct drxk_state *state)
3462{ 3502{
3463 int status; 3503 int status;
3504 bool setincenable = false;
3505 bool setfrenable = true;
3464 3506
3465 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K }; 3507 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3466 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K }; 3508 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3467 3509
3468 dprintk(1, "\n"); 3510 dprintk(1, "\n");
3469 do { 3511 status = DVBTCtrlSetIncEnable(state, &setincenable);
3470 bool setincenable = false; 3512 if (status < 0)
3471 bool setfrenable = true; 3513 goto error;
3472 status = DVBTCtrlSetIncEnable(state, &setincenable); 3514 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3473 if (status < 0) 3515 if (status < 0)
3474 break; 3516 goto error;
3475 status = DVBTCtrlSetFrEnable(state, &setfrenable); 3517 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3476 if (status < 0) 3518 if (status < 0)
3477 break; 3519 goto error;
3478 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); 3520 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3479 if (status < 0) 3521 if (status < 0)
3480 break; 3522 goto error;
3481 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); 3523 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3482 if (status < 0) 3524error:
3483 break; 3525 if (status < 0)
3484 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); 3526 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3485 if (status < 0)
3486 break;
3487 } while (0);
3488
3489 return status; 3527 return status;
3490} 3528}
3491 3529
@@ -3509,192 +3547,189 @@ static int SetDVBTStandard(struct drxk_state *state,
3509 dprintk(1, "\n"); 3547 dprintk(1, "\n");
3510 3548
3511 PowerUpDVBT(state); 3549 PowerUpDVBT(state);
3512 do { 3550 /* added antenna switch */
3513 /* added antenna switch */ 3551 SwitchAntennaToDVBT(state);
3514 SwitchAntennaToDVBT(state); 3552 /* send OFDM reset command */
3515 /* send OFDM reset command */ 3553 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3516 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); 3554 if (status < 0)
3517 if (status < 0) 3555 goto error;
3518 break;
3519 3556
3520 /* send OFDM setenv command */ 3557 /* send OFDM setenv command */
3521 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult); 3558 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3522 if (status < 0) 3559 if (status < 0)
3523 break; 3560 goto error;
3524 3561
3525 /* reset datapath for OFDM, processors first */ 3562 /* reset datapath for OFDM, processors first */
3526 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3563 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3527 if (status < 0) 3564 if (status < 0)
3528 break; 3565 goto error;
3529 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3566 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3530 if (status < 0) 3567 if (status < 0)
3531 break; 3568 goto error;
3532 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 3569 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3533 if (status < 0) 3570 if (status < 0)
3534 break; 3571 goto error;
3535 3572
3536 /* IQM setup */ 3573 /* IQM setup */
3537 /* synchronize on ofdstate->m_festart */ 3574 /* synchronize on ofdstate->m_festart */
3538 status = write16(state, IQM_AF_UPD_SEL__A, 1); 3575 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3539 if (status < 0) 3576 if (status < 0)
3540 break; 3577 goto error;
3541 /* window size for clipping ADC detection */ 3578 /* window size for clipping ADC detection */
3542 status = write16(state, IQM_AF_CLP_LEN__A, 0); 3579 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3543 if (status < 0) 3580 if (status < 0)
3544 break; 3581 goto error;
3545 /* window size for for sense pre-SAW detection */ 3582 /* window size for for sense pre-SAW detection */
3546 status = write16(state, IQM_AF_SNS_LEN__A, 0); 3583 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3547 if (status < 0) 3584 if (status < 0)
3548 break; 3585 goto error;
3549 /* sense threshold for sense pre-SAW detection */ 3586 /* sense threshold for sense pre-SAW detection */
3550 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3587 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3551 if (status < 0) 3588 if (status < 0)
3552 break; 3589 goto error;
3553 status = SetIqmAf(state, true); 3590 status = SetIqmAf(state, true);
3554 if (status < 0) 3591 if (status < 0)
3555 break; 3592 goto error;
3556 3593
3557 status = write16(state, IQM_AF_AGC_RF__A, 0); 3594 status = write16(state, IQM_AF_AGC_RF__A, 0);
3558 if (status < 0) 3595 if (status < 0)
3559 break; 3596 goto error;
3560 3597
3561 /* Impulse noise cruncher setup */ 3598 /* Impulse noise cruncher setup */
3562 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ 3599 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3563 if (status < 0) 3600 if (status < 0)
3564 break; 3601 goto error;
3565 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ 3602 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3566 if (status < 0) 3603 if (status < 0)
3567 break; 3604 goto error;
3568 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ 3605 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3569 if (status < 0) 3606 if (status < 0)
3570 break; 3607 goto error;
3571 3608
3572 status = write16(state, IQM_RC_STRETCH__A, 16); 3609 status = write16(state, IQM_RC_STRETCH__A, 16);
3573 if (status < 0) 3610 if (status < 0)
3574 break; 3611 goto error;
3575 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3612 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3576 if (status < 0) 3613 if (status < 0)
3577 break; 3614 goto error;
3578 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3615 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3579 if (status < 0) 3616 if (status < 0)
3580 break; 3617 goto error;
3581 status = write16(state, IQM_CF_SCALE__A, 1600); 3618 status = write16(state, IQM_CF_SCALE__A, 1600);
3582 if (status < 0) 3619 if (status < 0)
3583 break; 3620 goto error;
3584 status = write16(state, IQM_CF_SCALE_SH__A, 0); 3621 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3585 if (status < 0) 3622 if (status < 0)
3586 break; 3623 goto error;
3587 3624
3588 /* virtual clipping threshold for clipping ADC detection */ 3625 /* virtual clipping threshold for clipping ADC detection */
3589 status = write16(state, IQM_AF_CLP_TH__A, 448); 3626 status = write16(state, IQM_AF_CLP_TH__A, 448);
3590 if (status < 0) 3627 if (status < 0)
3591 break; 3628 goto error;
3592 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ 3629 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3593 if (status < 0) 3630 if (status < 0)
3594 break; 3631 goto error;
3595 3632
3596 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3633 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3597 if (status < 0) 3634 if (status < 0)
3598 break; 3635 goto error;
3599 3636
3600 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ 3637 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3601 if (status < 0) 3638 if (status < 0)
3602 break; 3639 goto error;
3603 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); 3640 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3604 if (status < 0) 3641 if (status < 0)
3605 break; 3642 goto error;
3606 /* enable power measurement interrupt */ 3643 /* enable power measurement interrupt */
3607 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); 3644 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3608 if (status < 0) 3645 if (status < 0)
3609 break; 3646 goto error;
3610 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 3647 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3611 if (status < 0) 3648 if (status < 0)
3612 break; 3649 goto error;
3613 3650
3614 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3651 /* IQM will not be reset from here, sync ADC and update/init AGC */
3615 status = ADCSynchronization(state); 3652 status = ADCSynchronization(state);
3616 if (status < 0) 3653 if (status < 0)
3617 break; 3654 goto error;
3618 status = SetPreSaw(state, &state->m_dvbtPreSawCfg); 3655 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3619 if (status < 0) 3656 if (status < 0)
3620 break; 3657 goto error;
3621 3658
3622 /* Halt SCU to enable safe non-atomic accesses */ 3659 /* Halt SCU to enable safe non-atomic accesses */
3623 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3660 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3624 if (status < 0) 3661 if (status < 0)
3625 break; 3662 goto error;
3626 3663
3627 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); 3664 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3628 if (status < 0) 3665 if (status < 0)
3629 break; 3666 goto error;
3630 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); 3667 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3631 if (status < 0) 3668 if (status < 0)
3632 break; 3669 goto error;
3633 3670
3634 /* Set Noise Estimation notch width and enable DC fix */ 3671 /* Set Noise Estimation notch width and enable DC fix */
3635 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); 3672 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3636 if (status < 0) 3673 if (status < 0)
3637 break; 3674 goto error;
3638 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3675 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3639 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); 3676 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3640 if (status < 0) 3677 if (status < 0)
3641 break; 3678 goto error;
3642 3679
3643 /* Activate SCU to enable SCU commands */ 3680 /* Activate SCU to enable SCU commands */
3644 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3681 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3645 if (status < 0) 3682 if (status < 0)
3646 break; 3683 goto error;
3647 3684
3648 if (!state->m_DRXK_A3_ROM_CODE) { 3685 if (!state->m_DRXK_A3_ROM_CODE) {
3649 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ 3686 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3650 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); 3687 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3651 if (status < 0) 3688 if (status < 0)
3652 break; 3689 goto error;
3653 } 3690 }
3654 3691
3655 /* OFDM_SC setup */ 3692 /* OFDM_SC setup */
3656#ifdef COMPILE_FOR_NONRT 3693#ifdef COMPILE_FOR_NONRT
3657 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); 3694 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3658 if (status < 0) 3695 if (status < 0)
3659 break; 3696 goto error;
3660 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); 3697 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3661 if (status < 0) 3698 if (status < 0)
3662 break; 3699 goto error;
3663#endif 3700#endif
3664 3701
3665 /* FEC setup */ 3702 /* FEC setup */
3666 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ 3703 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3667 if (status < 0) 3704 if (status < 0)
3668 break; 3705 goto error;
3669 3706
3670 3707
3671#ifdef COMPILE_FOR_NONRT 3708#ifdef COMPILE_FOR_NONRT
3672 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); 3709 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3673 if (status < 0) 3710 if (status < 0)
3674 break; 3711 goto error;
3675#else 3712#else
3676 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); 3713 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3677 if (status < 0) 3714 if (status < 0)
3678 break; 3715 goto error;
3679#endif 3716#endif
3680 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); 3717 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3681 if (status < 0) 3718 if (status < 0)
3682 break; 3719 goto error;
3683
3684 /* Setup MPEG bus */
3685 status = MPEGTSDtoSetup(state, OM_DVBT);
3686 if (status < 0)
3687 break;
3688 /* Set DVBT Presets */
3689 status = DVBTActivatePresets(state);
3690 if (status < 0)
3691 break;
3692
3693 } while (0);
3694 3720
3721 /* Setup MPEG bus */
3722 status = MPEGTSDtoSetup(state, OM_DVBT);
3723 if (status < 0)
3724 goto error;
3725 /* Set DVBT Presets */
3726 status = DVBTActivatePresets(state);
3695 if (status < 0) 3727 if (status < 0)
3696 printk(KERN_ERR "drxk: %s status - %08x\n", __func__, status); 3728 goto error;
3697 3729
3730error:
3731 if (status < 0)
3732 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3698 return status; 3733 return status;
3699} 3734}
3700 3735
@@ -3713,19 +3748,20 @@ static int DVBTStart(struct drxk_state *state)
3713 dprintk(1, "\n"); 3748 dprintk(1, "\n");
3714 /* Start correct processes to get in lock */ 3749 /* Start correct processes to get in lock */
3715 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3750 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3716 do { 3751 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3717 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3752 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3718 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); 3753 if (status < 0)
3719 if (status < 0) 3754 goto error;
3720 break; 3755 /* Start FEC OC */
3721 /* Start FEC OC */ 3756 status = MPEGTSStart(state);
3722 status = MPEGTSStart(state); 3757 if (status < 0)
3723 if (status < 0) 3758 goto error;
3724 break; 3759 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3725 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3760 if (status < 0)
3726 if (status < 0) 3761 goto error;
3727 break; 3762error:
3728 } while (0); 3763 if (status < 0)
3764 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3729 return status; 3765 return status;
3730} 3766}
3731 3767
@@ -3749,318 +3785,300 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3749 u16 param1; 3785 u16 param1;
3750 int status; 3786 int status;
3751 3787
3752 dprintk(1, "\n"); 3788 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3753 /* printk(KERN_DEBUG "drxk: %s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */
3754 do {
3755 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3756 if (status < 0)
3757 break;
3758 3789
3759 /* Halt SCU to enable safe non-atomic accesses */ 3790 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3760 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3791 if (status < 0)
3761 if (status < 0) 3792 goto error;
3762 break;
3763 3793
3764 /* Stop processors */ 3794 /* Halt SCU to enable safe non-atomic accesses */
3765 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3795 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3766 if (status < 0) 3796 if (status < 0)
3767 break; 3797 goto error;
3768 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3769 if (status < 0)
3770 break;
3771 3798
3772 /* Mandatory fix, always stop CP, required to set spl offset back to 3799 /* Stop processors */
3773 hardware default (is set to 0 by ucode during pilot detection */ 3800 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3774 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); 3801 if (status < 0)
3775 if (status < 0) 3802 goto error;
3776 break; 3803 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3804 if (status < 0)
3805 goto error;
3777 3806
3778 /*== Write channel settings to device =====================================*/ 3807 /* Mandatory fix, always stop CP, required to set spl offset back to
3808 hardware default (is set to 0 by ucode during pilot detection */
3809 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3810 if (status < 0)
3811 goto error;
3779 3812
3780 /* mode */ 3813 /*== Write channel settings to device =====================================*/
3781 switch (state->param.u.ofdm.transmission_mode) {
3782 case TRANSMISSION_MODE_AUTO:
3783 default:
3784 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3785 /* fall through , try first guess DRX_FFTMODE_8K */
3786 case TRANSMISSION_MODE_8K:
3787 transmissionParams |=
3788 OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3789 break;
3790 case TRANSMISSION_MODE_2K:
3791 transmissionParams |=
3792 OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3793 break;
3794 }
3795 3814
3796 /* guard */ 3815 /* mode */
3797 switch (state->param.u.ofdm.guard_interval) { 3816 switch (state->param.u.ofdm.transmission_mode) {
3798 default: 3817 case TRANSMISSION_MODE_AUTO:
3799 case GUARD_INTERVAL_AUTO: 3818 default:
3800 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3819 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3801 /* fall through , try first guess DRX_GUARD_1DIV4 */ 3820 /* fall through , try first guess DRX_FFTMODE_8K */
3802 case GUARD_INTERVAL_1_4: 3821 case TRANSMISSION_MODE_8K:
3803 transmissionParams |= 3822 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3804 OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; 3823 goto error;
3805 break; 3824 case TRANSMISSION_MODE_2K:
3806 case GUARD_INTERVAL_1_32: 3825 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3807 transmissionParams |= 3826 goto error;
3808 OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; 3827 }
3809 break;
3810 case GUARD_INTERVAL_1_16:
3811 transmissionParams |=
3812 OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3813 break;
3814 case GUARD_INTERVAL_1_8:
3815 transmissionParams |=
3816 OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3817 break;
3818 }
3819 3828
3820 /* hierarchy */ 3829 /* guard */
3821 switch (state->param.u.ofdm.hierarchy_information) { 3830 switch (state->param.u.ofdm.guard_interval) {
3822 case HIERARCHY_AUTO: 3831 default:
3823 case HIERARCHY_NONE: 3832 case GUARD_INTERVAL_AUTO:
3824 default: 3833 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3825 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; 3834 /* fall through , try first guess DRX_GUARD_1DIV4 */
3826 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ 3835 case GUARD_INTERVAL_1_4:
3827 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ 3836 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3828 /* break; */ 3837 goto error;
3829 case HIERARCHY_1: 3838 case GUARD_INTERVAL_1_32:
3830 transmissionParams |= 3839 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3831 OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; 3840 goto error;
3832 break; 3841 case GUARD_INTERVAL_1_16:
3833 case HIERARCHY_2: 3842 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3834 transmissionParams |= 3843 goto error;
3835 OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; 3844 case GUARD_INTERVAL_1_8:
3836 break; 3845 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3837 case HIERARCHY_4: 3846 goto error;
3838 transmissionParams |= 3847 }
3839 OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3840 break;
3841 }
3842 3848
3849 /* hierarchy */
3850 switch (state->param.u.ofdm.hierarchy_information) {
3851 case HIERARCHY_AUTO:
3852 case HIERARCHY_NONE:
3853 default:
3854 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3855 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3856 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3857 /* break; */
3858 case HIERARCHY_1:
3859 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3860 break;
3861 case HIERARCHY_2:
3862 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3863 break;
3864 case HIERARCHY_4:
3865 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3866 break;
3867 }
3843 3868
3844 /* constellation */ 3869
3845 switch (state->param.u.ofdm.constellation) { 3870 /* constellation */
3846 case QAM_AUTO: 3871 switch (state->param.u.ofdm.constellation) {
3847 default: 3872 case QAM_AUTO:
3848 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3873 default:
3849 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ 3874 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3850 case QAM_64: 3875 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3851 transmissionParams |= 3876 case QAM_64:
3852 OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; 3877 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3853 break; 3878 break;
3854 case QPSK: 3879 case QPSK:
3855 transmissionParams |= 3880 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3856 OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; 3881 break;
3857 break; 3882 case QAM_16:
3858 case QAM_16: 3883 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3859 transmissionParams |= 3884 break;
3860 OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; 3885 }
3861 break;
3862 }
3863#if 0 3886#if 0
3864 /* No hierachical channels support in BDA */ 3887 /* No hierachical channels support in BDA */
3865 /* Priority (only for hierarchical channels) */ 3888 /* Priority (only for hierarchical channels) */
3866 switch (channel->priority) { 3889 switch (channel->priority) {
3867 case DRX_PRIORITY_LOW: 3890 case DRX_PRIORITY_LOW:
3868 transmissionParams |= 3891 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3869 OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; 3892 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3870 WR16(devAddr, OFDM_EC_SB_PRIOR__A, 3893 OFDM_EC_SB_PRIOR_LO);
3871 OFDM_EC_SB_PRIOR_LO); 3894 break;
3872 break; 3895 case DRX_PRIORITY_HIGH:
3873 case DRX_PRIORITY_HIGH:
3874 transmissionParams |=
3875 OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3876 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3877 OFDM_EC_SB_PRIOR_HI));
3878 break;
3879 case DRX_PRIORITY_UNKNOWN: /* fall through */
3880 default:
3881 return DRX_STS_INVALID_ARG;
3882 break;
3883 }
3884#else
3885 /* Set Priorty high */
3886 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3896 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3887 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3897 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3888 if (status < 0) 3898 OFDM_EC_SB_PRIOR_HI));
3889 break; 3899 break;
3900 case DRX_PRIORITY_UNKNOWN: /* fall through */
3901 default:
3902 status = -EINVAL;
3903 goto error;
3904 }
3905#else
3906 /* Set Priorty high */
3907 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3908 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3909 if (status < 0)
3910 goto error;
3890#endif 3911#endif
3891 3912
3892 /* coderate */ 3913 /* coderate */
3893 switch (state->param.u.ofdm.code_rate_HP) { 3914 switch (state->param.u.ofdm.code_rate_HP) {
3894 case FEC_AUTO: 3915 case FEC_AUTO:
3895 default: 3916 default:
3896 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3917 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3897 /* fall through , try first guess DRX_CODERATE_2DIV3 */ 3918 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3898 case FEC_2_3: 3919 case FEC_2_3:
3899 transmissionParams |= 3920 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3900 OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; 3921 break;
3901 break; 3922 case FEC_1_2:
3902 case FEC_1_2: 3923 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3903 transmissionParams |= 3924 break;
3904 OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; 3925 case FEC_3_4:
3905 break; 3926 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3906 case FEC_3_4: 3927 break;
3907 transmissionParams |= 3928 case FEC_5_6:
3908 OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; 3929 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3909 break; 3930 break;
3910 case FEC_5_6: 3931 case FEC_7_8:
3911 transmissionParams |= 3932 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3912 OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; 3933 break;
3913 break; 3934 }
3914 case FEC_7_8:
3915 transmissionParams |=
3916 OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3917 break;
3918 }
3919 3935
3920 /* SAW filter selection: normaly not necesarry, but if wanted 3936 /* SAW filter selection: normaly not necesarry, but if wanted
3921 the application can select a SAW filter via the driver by using UIOs */ 3937 the application can select a SAW filter via the driver by using UIOs */
3922 /* First determine real bandwidth (Hz) */ 3938 /* First determine real bandwidth (Hz) */
3923 /* Also set delay for impulse noise cruncher */ 3939 /* Also set delay for impulse noise cruncher */
3924 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed 3940 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3925 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC 3941 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3926 functions */ 3942 functions */
3927 switch (state->param.u.ofdm.bandwidth) { 3943 switch (state->param.u.ofdm.bandwidth) {
3928 case BANDWIDTH_AUTO: 3944 case BANDWIDTH_AUTO:
3929 case BANDWIDTH_8_MHZ: 3945 case BANDWIDTH_8_MHZ:
3930 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3946 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3931 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); 3947 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3932 if (status < 0) 3948 if (status < 0)
3933 break; 3949 goto error;
3934 /* cochannel protection for PAL 8 MHz */ 3950 /* cochannel protection for PAL 8 MHz */
3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); 3951 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3936 if (status < 0) 3952 if (status < 0)
3937 break; 3953 goto error;
3938 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); 3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3939 if (status < 0) 3955 if (status < 0)
3940 break; 3956 goto error;
3941 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); 3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3942 if (status < 0) 3958 if (status < 0)
3943 break; 3959 goto error;
3944 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3945 if (status < 0) 3961 if (status < 0)
3946 break; 3962 goto error;
3947 break; 3963 break;
3948 case BANDWIDTH_7_MHZ: 3964 case BANDWIDTH_7_MHZ:
3949 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3965 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3950 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); 3966 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3951 if (status < 0) 3967 if (status < 0)
3952 break; 3968 goto error;
3953 /* cochannel protection for PAL 7 MHz */ 3969 /* cochannel protection for PAL 7 MHz */
3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); 3970 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3955 if (status < 0) 3971 if (status < 0)
3956 break; 3972 goto error;
3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); 3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3958 if (status < 0) 3974 if (status < 0)
3959 break; 3975 goto error;
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); 3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3961 if (status < 0) 3977 if (status < 0)
3962 break; 3978 goto error;
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3964 if (status < 0) 3980 if (status < 0)
3965 break; 3981 goto error;
3966 break; 3982 break;
3967 case BANDWIDTH_6_MHZ: 3983 case BANDWIDTH_6_MHZ:
3968 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3984 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3969 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); 3985 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3970 if (status < 0) 3986 if (status < 0)
3971 break; 3987 goto error;
3972 /* cochannel protection for NTSC 6 MHz */ 3988 /* cochannel protection for NTSC 6 MHz */
3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); 3989 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3974 if (status < 0) 3990 if (status < 0)
3975 break; 3991 goto error;
3976 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); 3992 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3977 if (status < 0) 3993 if (status < 0)
3978 break; 3994 goto error;
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); 3995 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3980 if (status < 0) 3996 if (status < 0)
3981 break; 3997 goto error;
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); 3998 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3983 if (status < 0) 3999 if (status < 0)
3984 break; 4000 goto error;
3985 break; 4001 break;
3986 default: 4002 default:
3987 return -EINVAL; 4003 status = -EINVAL;
3988 } 4004 goto error;
4005 }
3989 4006
3990 if (iqmRcRateOfs == 0) { 4007 if (iqmRcRateOfs == 0) {
3991 /* Now compute IQM_RC_RATE_OFS 4008 /* Now compute IQM_RC_RATE_OFS
3992 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) 4009 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3993 => 4010 =>
3994 ((SysFreq / BandWidth) * (2^21)) - (2^23) 4011 ((SysFreq / BandWidth) * (2^21)) - (2^23)
3995 */ 4012 */
3996 /* (SysFreq / BandWidth) * (2^28) */ 4013 /* (SysFreq / BandWidth) * (2^28) */
3997 /* assert (MAX(sysClk)/MIN(bandwidth) < 16) 4014 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3998 => assert(MAX(sysClk) < 16*MIN(bandwidth)) 4015 => assert(MAX(sysClk) < 16*MIN(bandwidth))
3999 => assert(109714272 > 48000000) = true so Frac 28 can be used */ 4016 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4000 iqmRcRateOfs = Frac28a((u32) 4017 iqmRcRateOfs = Frac28a((u32)
4001 ((state->m_sysClockFreq * 4018 ((state->m_sysClockFreq *
4002 1000) / 3), bandwidth); 4019 1000) / 3), bandwidth);
4003 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 4020 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4004 if ((iqmRcRateOfs & 0x7fL) >= 0x40) 4021 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4005 iqmRcRateOfs += 0x80L; 4022 iqmRcRateOfs += 0x80L;
4006 iqmRcRateOfs = iqmRcRateOfs >> 7; 4023 iqmRcRateOfs = iqmRcRateOfs >> 7;
4007 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ 4024 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4008 iqmRcRateOfs = iqmRcRateOfs - (1 << 23); 4025 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4009 } 4026 }
4010 4027
4011 iqmRcRateOfs &= 4028 iqmRcRateOfs &=
4012 ((((u32) IQM_RC_RATE_OFS_HI__M) << 4029 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4013 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 4030 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4014 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); 4031 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4015 if (status < 0) 4032 if (status < 0)
4016 break; 4033 goto error;
4017 4034
4018 /* Bandwidth setting done */ 4035 /* Bandwidth setting done */
4019 4036
4020#if 0 4037#if 0
4021 status = DVBTSetFrequencyShift(demod, channel, tunerOffset); 4038 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4022 if (status < 0) 4039 if (status < 0)
4023 break; 4040 goto error;
4024#endif 4041#endif
4025 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); 4042 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4026 if (status < 0) 4043 if (status < 0)
4027 break; 4044 goto error;
4028 4045
4029 /*== Start SC, write channel settings to SC ===============================*/ 4046 /*== Start SC, write channel settings to SC ===============================*/
4030 4047
4031 /* Activate SCU to enable SCU commands */ 4048 /* Activate SCU to enable SCU commands */
4032 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4049 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4033 if (status < 0) 4050 if (status < 0)
4034 break; 4051 goto error;
4035 4052
4036 /* Enable SC after setting all other parameters */ 4053 /* Enable SC after setting all other parameters */
4037 status = write16(state, OFDM_SC_COMM_STATE__A, 0); 4054 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4038 if (status < 0) 4055 if (status < 0)
4039 break; 4056 goto error;
4040 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); 4057 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4041 if (status < 0) 4058 if (status < 0)
4042 break; 4059 goto error;
4043 4060
4044 4061
4045 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); 4062 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4046 if (status < 0) 4063 if (status < 0)
4047 break; 4064 goto error;
4048 4065
4049 /* Write SC parameter registers, set all AUTO flags in operation mode */ 4066 /* Write SC parameter registers, set all AUTO flags in operation mode */
4050 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | 4067 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4051 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | 4068 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4052 OFDM_SC_RA_RAM_OP_AUTO_CONST__M | 4069 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4053 OFDM_SC_RA_RAM_OP_AUTO_HIER__M | 4070 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4054 OFDM_SC_RA_RAM_OP_AUTO_RATE__M); 4071 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4055 status = 4072 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4056 DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 4073 0, transmissionParams, param1, 0, 0, 0);
4057 0, transmissionParams, param1, 0, 0, 0); 4074 if (status < 0)
4058 if (!state->m_DRXK_A3_ROM_CODE) 4075 goto error;
4059 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4060 if (status < 0)
4061 break;
4062 4076
4063 } while (0); 4077 if (!state->m_DRXK_A3_ROM_CODE)
4078 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4079error:
4080 if (status < 0)
4081 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4064 4082
4065 return status; 4083 return status;
4066} 4084}
@@ -4088,16 +4106,18 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4088 4106
4089 dprintk(1, "\n"); 4107 dprintk(1, "\n");
4090 4108
4109 *pLockStatus = NOT_LOCKED;
4091 /* driver 0.9.0 */ 4110 /* driver 0.9.0 */
4092 /* Check if SC is running */ 4111 /* Check if SC is running */
4093 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); 4112 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4094 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) { 4113 if (status < 0)
4095 /* SC not active; return DRX_NOT_LOCKED */ 4114 goto end;
4096 *pLockStatus = NOT_LOCKED; 4115 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4097 return status; 4116 goto end;
4098 }
4099 4117
4100 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); 4118 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4119 if (status < 0)
4120 goto end;
4101 4121
4102 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) 4122 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4103 *pLockStatus = MPEG_LOCK; 4123 *pLockStatus = MPEG_LOCK;
@@ -4107,8 +4127,9 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4107 *pLockStatus = DEMOD_LOCK; 4127 *pLockStatus = DEMOD_LOCK;
4108 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) 4128 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4109 *pLockStatus = NEVER_LOCK; 4129 *pLockStatus = NEVER_LOCK;
4110 else 4130end:
4111 *pLockStatus = NOT_LOCKED; 4131 if (status < 0)
4132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4112 4133
4113 return status; 4134 return status;
4114} 4135}
@@ -4116,15 +4137,12 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4116static int PowerUpQAM(struct drxk_state *state) 4137static int PowerUpQAM(struct drxk_state *state)
4117{ 4138{
4118 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; 4139 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4119 int status = 0; 4140 int status;
4120 4141
4121 dprintk(1, "\n"); 4142 dprintk(1, "\n");
4122 do { 4143 status = CtrlPowerMode(state, &powerMode);
4123 status = CtrlPowerMode(state, &powerMode); 4144 if (status < 0)
4124 if (status < 0) 4145 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4125 break;
4126
4127 } while (0);
4128 4146
4129 return status; 4147 return status;
4130} 4148}
@@ -4138,28 +4156,28 @@ static int PowerDownQAM(struct drxk_state *state)
4138 int status = 0; 4156 int status = 0;
4139 4157
4140 dprintk(1, "\n"); 4158 dprintk(1, "\n");
4141 do { 4159 status = read16(state, SCU_COMM_EXEC__A, &data);
4142 status = read16(state, SCU_COMM_EXEC__A, &data); 4160 if (status < 0)
4161 goto error;
4162 if (data == SCU_COMM_EXEC_ACTIVE) {
4163 /*
4164 STOP demodulator
4165 QAM and HW blocks
4166 */
4167 /* stop all comstate->m_exec */
4168 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4143 if (status < 0) 4169 if (status < 0)
4144 break; 4170 goto error;
4145 if (data == SCU_COMM_EXEC_ACTIVE) { 4171 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4146 /*
4147 STOP demodulator
4148 QAM and HW blocks
4149 */
4150 /* stop all comstate->m_exec */
4151 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4152 if (status < 0)
4153 break;
4154 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4155 if (status < 0)
4156 break;
4157 }
4158 /* powerdown AFE */
4159 status = SetIqmAf(state, false);
4160 if (status < 0) 4172 if (status < 0)
4161 break; 4173 goto error;
4162 } while (0); 4174 }
4175 /* powerdown AFE */
4176 status = SetIqmAf(state, false);
4177
4178error:
4179 if (status < 0)
4180 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4163 4181
4164 return status; 4182 return status;
4165} 4183}
@@ -4190,73 +4208,64 @@ static int SetQAMMeasurement(struct drxk_state *state,
4190 dprintk(1, "\n"); 4208 dprintk(1, "\n");
4191 4209
4192 fecRsPrescale = 1; 4210 fecRsPrescale = 1;
4193 do { 4211 /* fecBitsDesired = symbolRate [kHz] *
4194 4212 FrameLenght [ms] *
4195 /* fecBitsDesired = symbolRate [kHz] * 4213 (constellation + 1) *
4196 FrameLenght [ms] * 4214 SyncLoss (== 1) *
4197 (constellation + 1) * 4215 ViterbiLoss (==1)
4198 SyncLoss (== 1) * 4216 */
4199 ViterbiLoss (==1) 4217 switch (constellation) {
4200 */ 4218 case DRX_CONSTELLATION_QAM16:
4201 switch (constellation) { 4219 fecBitsDesired = 4 * symbolRate;
4202 case DRX_CONSTELLATION_QAM16: 4220 break;
4203 fecBitsDesired = 4 * symbolRate; 4221 case DRX_CONSTELLATION_QAM32:
4204 break; 4222 fecBitsDesired = 5 * symbolRate;
4205 case DRX_CONSTELLATION_QAM32: 4223 break;
4206 fecBitsDesired = 5 * symbolRate; 4224 case DRX_CONSTELLATION_QAM64:
4207 break; 4225 fecBitsDesired = 6 * symbolRate;
4208 case DRX_CONSTELLATION_QAM64: 4226 break;
4209 fecBitsDesired = 6 * symbolRate; 4227 case DRX_CONSTELLATION_QAM128:
4210 break; 4228 fecBitsDesired = 7 * symbolRate;
4211 case DRX_CONSTELLATION_QAM128: 4229 break;
4212 fecBitsDesired = 7 * symbolRate; 4230 case DRX_CONSTELLATION_QAM256:
4213 break; 4231 fecBitsDesired = 8 * symbolRate;
4214 case DRX_CONSTELLATION_QAM256: 4232 break;
4215 fecBitsDesired = 8 * symbolRate; 4233 default:
4216 break; 4234 status = -EINVAL;
4217 default: 4235 }
4218 status = -EINVAL; 4236 if (status < 0)
4219 } 4237 goto error;
4220 status = status;
4221 if (status < 0)
4222 break;
4223
4224 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4225 fecBitsDesired *= 500; /* meas. period [ms] */
4226 4238
4227 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4239 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4228 /* fecRsPeriodTotal = fecBitsDesired / 1632 */ 4240 fecBitsDesired *= 500; /* meas. period [ms] */
4229 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4230 4241
4231 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ 4242 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4232 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); 4243 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4233 if (fecRsPrescale == 0) { 4244 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4234 /* Divide by zero (though impossible) */
4235 status = -1;
4236 }
4237 status = status;
4238 if (status < 0)
4239 break;
4240 fecRsPeriod =
4241 ((u16) fecRsPeriodTotal +
4242 (fecRsPrescale >> 1)) / fecRsPrescale;
4243 4245
4244 /* write corresponding registers */ 4246 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4245 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); 4247 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4248 if (fecRsPrescale == 0) {
4249 /* Divide by zero (though impossible) */
4250 status = -EINVAL;
4246 if (status < 0) 4251 if (status < 0)
4247 break; 4252 goto error;
4248 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); 4253 }
4249 if (status < 0) 4254 fecRsPeriod =
4250 break; 4255 ((u16) fecRsPeriodTotal +
4251 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); 4256 (fecRsPrescale >> 1)) / fecRsPrescale;
4252 if (status < 0)
4253 break;
4254
4255 } while (0);
4256 4257
4258 /* write corresponding registers */
4259 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4257 if (status < 0) 4260 if (status < 0)
4258 printk(KERN_ERR "drxk: %s: status - %08x\n", __func__, status); 4261 goto error;
4259 4262 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4263 if (status < 0)
4264 goto error;
4265 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4266error:
4267 if (status < 0)
4268 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4260 return status; 4269 return status;
4261} 4270}
4262 4271
@@ -4265,183 +4274,184 @@ static int SetQAM16(struct drxk_state *state)
4265 int status = 0; 4274 int status = 0;
4266 4275
4267 dprintk(1, "\n"); 4276 dprintk(1, "\n");
4268 do { 4277 /* QAM Equalizer Setup */
4269 /* QAM Equalizer Setup */ 4278 /* Equalizer */
4270 /* Equalizer */ 4279 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4271 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); 4280 if (status < 0)
4272 if (status < 0) 4281 goto error;
4273 break; 4282 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4274 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); 4283 if (status < 0)
4275 if (status < 0) 4284 goto error;
4276 break; 4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4277 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); 4286 if (status < 0)
4278 if (status < 0) 4287 goto error;
4279 break; 4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); 4289 if (status < 0)
4281 if (status < 0) 4290 goto error;
4282 break; 4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); 4292 if (status < 0)
4284 if (status < 0) 4293 goto error;
4285 break; 4294 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); 4295 if (status < 0)
4287 if (status < 0) 4296 goto error;
4288 break; 4297 /* Decision Feedback Equalizer */
4289 /* Decision Feedback Equalizer */ 4298 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4290 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); 4299 if (status < 0)
4291 if (status < 0) 4300 goto error;
4292 break; 4301 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4293 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); 4302 if (status < 0)
4294 if (status < 0) 4303 goto error;
4295 break; 4304 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4296 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); 4305 if (status < 0)
4297 if (status < 0) 4306 goto error;
4298 break; 4307 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4299 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); 4308 if (status < 0)
4300 if (status < 0) 4309 goto error;
4301 break; 4310 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4302 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); 4311 if (status < 0)
4303 if (status < 0) 4312 goto error;
4304 break; 4313 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4305 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4314 if (status < 0)
4306 if (status < 0) 4315 goto error;
4307 break;
4308 4316
4309 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4317 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4310 if (status < 0) 4318 if (status < 0)
4311 break; 4319 goto error;
4312 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4320 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4313 if (status < 0) 4321 if (status < 0)
4314 break; 4322 goto error;
4315 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4323 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4316 if (status < 0) 4324 if (status < 0)
4317 break; 4325 goto error;
4318 4326
4319 /* QAM Slicer Settings */ 4327 /* QAM Slicer Settings */
4320 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); 4328 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4321 if (status < 0) 4329 if (status < 0)
4322 break; 4330 goto error;
4323 4331
4324 /* QAM Loop Controller Coeficients */ 4332 /* QAM Loop Controller Coeficients */
4325 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4333 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4326 if (status < 0) 4334 if (status < 0)
4327 break; 4335 goto error;
4328 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4336 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4329 if (status < 0) 4337 if (status < 0)
4330 break; 4338 goto error;
4331 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4339 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4332 if (status < 0) 4340 if (status < 0)
4333 break; 4341 goto error;
4334 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4342 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4335 if (status < 0) 4343 if (status < 0)
4336 break; 4344 goto error;
4337 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4345 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4338 if (status < 0) 4346 if (status < 0)
4339 break; 4347 goto error;
4340 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4348 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4341 if (status < 0) 4349 if (status < 0)
4342 break; 4350 goto error;
4343 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4351 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4344 if (status < 0) 4352 if (status < 0)
4345 break; 4353 goto error;
4346 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4354 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4347 if (status < 0) 4355 if (status < 0)
4348 break; 4356 goto error;
4349 4357
4350 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4358 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4351 if (status < 0) 4359 if (status < 0)
4352 break; 4360 goto error;
4353 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4361 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4354 if (status < 0) 4362 if (status < 0)
4355 break; 4363 goto error;
4356 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4364 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4357 if (status < 0) 4365 if (status < 0)
4358 break; 4366 goto error;
4359 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4367 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4360 if (status < 0) 4368 if (status < 0)
4361 break; 4369 goto error;
4362 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4370 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4363 if (status < 0) 4371 if (status < 0)
4364 break; 4372 goto error;
4365 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4373 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4366 if (status < 0) 4374 if (status < 0)
4367 break; 4375 goto error;
4368 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4376 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4369 if (status < 0) 4377 if (status < 0)
4370 break; 4378 goto error;
4371 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4379 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4372 if (status < 0) 4380 if (status < 0)
4373 break; 4381 goto error;
4374 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); 4382 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4375 if (status < 0) 4383 if (status < 0)
4376 break; 4384 goto error;
4377 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4385 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4378 if (status < 0) 4386 if (status < 0)
4379 break; 4387 goto error;
4380 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4388 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4381 if (status < 0) 4389 if (status < 0)
4382 break; 4390 goto error;
4383 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4391 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4384 if (status < 0) 4392 if (status < 0)
4385 break; 4393 goto error;
4386 4394
4387 4395
4388 /* QAM State Machine (FSM) Thresholds */ 4396 /* QAM State Machine (FSM) Thresholds */
4389 4397
4390 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); 4398 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4391 if (status < 0) 4399 if (status < 0)
4392 break; 4400 goto error;
4393 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4401 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4394 if (status < 0) 4402 if (status < 0)
4395 break; 4403 goto error;
4396 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); 4404 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4397 if (status < 0) 4405 if (status < 0)
4398 break; 4406 goto error;
4399 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); 4407 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4400 if (status < 0) 4408 if (status < 0)
4401 break; 4409 goto error;
4402 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); 4410 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4403 if (status < 0) 4411 if (status < 0)
4404 break; 4412 goto error;
4405 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); 4413 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4406 if (status < 0) 4414 if (status < 0)
4407 break; 4415 goto error;
4408 4416
4409 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4417 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4410 if (status < 0) 4418 if (status < 0)
4411 break; 4419 goto error;
4412 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4420 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4413 if (status < 0) 4421 if (status < 0)
4414 break; 4422 goto error;
4415 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); 4423 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4416 if (status < 0) 4424 if (status < 0)
4417 break; 4425 goto error;
4418 4426
4419 4427
4420 /* QAM FSM Tracking Parameters */ 4428 /* QAM FSM Tracking Parameters */
4421 4429
4422 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); 4430 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4423 if (status < 0) 4431 if (status < 0)
4424 break; 4432 goto error;
4425 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); 4433 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4426 if (status < 0) 4434 if (status < 0)
4427 break; 4435 goto error;
4428 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); 4436 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4429 if (status < 0) 4437 if (status < 0)
4430 break; 4438 goto error;
4431 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); 4439 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4432 if (status < 0) 4440 if (status < 0)
4433 break; 4441 goto error;
4434 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); 4442 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4435 if (status < 0) 4443 if (status < 0)
4436 break; 4444 goto error;
4437 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); 4445 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4438 if (status < 0) 4446 if (status < 0)
4439 break; 4447 goto error;
4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); 4448 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4441 if (status < 0) 4449 if (status < 0)
4442 break; 4450 goto error;
4443 } while (0);
4444 4451
4452error:
4453 if (status < 0)
4454 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4445 return status; 4455 return status;
4446} 4456}
4447 4457
@@ -4457,187 +4467,186 @@ static int SetQAM32(struct drxk_state *state)
4457 int status = 0; 4467 int status = 0;
4458 4468
4459 dprintk(1, "\n"); 4469 dprintk(1, "\n");
4460 do {
4461 /* QAM Equalizer Setup */
4462 /* Equalizer */
4463 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4464 if (status < 0)
4465 break;
4466 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4467 if (status < 0)
4468 break;
4469 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4470 if (status < 0)
4471 break;
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4473 if (status < 0)
4474 break;
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4476 if (status < 0)
4477 break;
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4479 if (status < 0)
4480 break;
4481 4470
4482 /* Decision Feedback Equalizer */ 4471 /* QAM Equalizer Setup */
4483 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); 4472 /* Equalizer */
4484 if (status < 0) 4473 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4485 break; 4474 if (status < 0)
4486 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); 4475 goto error;
4487 if (status < 0) 4476 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4488 break; 4477 if (status < 0)
4489 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); 4478 goto error;
4490 if (status < 0) 4479 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4491 break; 4480 if (status < 0)
4492 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); 4481 goto error;
4493 if (status < 0) 4482 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4494 break; 4483 if (status < 0)
4495 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4484 goto error;
4496 if (status < 0) 4485 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4497 break; 4486 if (status < 0)
4498 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4487 goto error;
4499 if (status < 0) 4488 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4500 break; 4489 if (status < 0)
4490 goto error;
4501 4491
4502 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4492 /* Decision Feedback Equalizer */
4503 if (status < 0) 4493 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4504 break; 4494 if (status < 0)
4505 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4495 goto error;
4506 if (status < 0) 4496 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4507 break; 4497 if (status < 0)
4508 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4498 goto error;
4509 if (status < 0) 4499 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4510 break; 4500 if (status < 0)
4501 goto error;
4502 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4503 if (status < 0)
4504 goto error;
4505 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4506 if (status < 0)
4507 goto error;
4508 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4509 if (status < 0)
4510 goto error;
4511 4511
4512 /* QAM Slicer Settings */ 4512 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4513 if (status < 0)
4514 goto error;
4515 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4516 if (status < 0)
4517 goto error;
4518 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4519 if (status < 0)
4520 goto error;
4513 4521
4514 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); 4522 /* QAM Slicer Settings */
4515 if (status < 0)
4516 break;
4517 4523
4524 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4525 if (status < 0)
4526 goto error;
4518 4527
4519 /* QAM Loop Controller Coeficients */
4520 4528
4521 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4529 /* QAM Loop Controller Coeficients */
4522 if (status < 0)
4523 break;
4524 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4525 if (status < 0)
4526 break;
4527 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4528 if (status < 0)
4529 break;
4530 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4531 if (status < 0)
4532 break;
4533 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4534 if (status < 0)
4535 break;
4536 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4537 if (status < 0)
4538 break;
4539 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4540 if (status < 0)
4541 break;
4542 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4543 if (status < 0)
4544 break;
4545 4530
4546 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4531 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4547 if (status < 0) 4532 if (status < 0)
4548 break; 4533 goto error;
4549 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4534 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4550 if (status < 0) 4535 if (status < 0)
4551 break; 4536 goto error;
4552 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4537 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4553 if (status < 0) 4538 if (status < 0)
4554 break; 4539 goto error;
4555 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4540 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4556 if (status < 0) 4541 if (status < 0)
4557 break; 4542 goto error;
4558 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4543 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4559 if (status < 0) 4544 if (status < 0)
4560 break; 4545 goto error;
4561 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4546 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4562 if (status < 0) 4547 if (status < 0)
4563 break; 4548 goto error;
4564 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4549 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4565 if (status < 0) 4550 if (status < 0)
4566 break; 4551 goto error;
4567 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4552 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4568 if (status < 0) 4553 if (status < 0)
4569 break; 4554 goto error;
4570 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4571 if (status < 0)
4572 break;
4573 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4574 if (status < 0)
4575 break;
4576 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4577 if (status < 0)
4578 break;
4579 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4580 if (status < 0)
4581 break;
4582 4555
4556 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4557 if (status < 0)
4558 goto error;
4559 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4560 if (status < 0)
4561 goto error;
4562 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4563 if (status < 0)
4564 goto error;
4565 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4566 if (status < 0)
4567 goto error;
4568 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4569 if (status < 0)
4570 goto error;
4571 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4572 if (status < 0)
4573 goto error;
4574 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4575 if (status < 0)
4576 goto error;
4577 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4578 if (status < 0)
4579 goto error;
4580 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4581 if (status < 0)
4582 goto error;
4583 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4584 if (status < 0)
4585 goto error;
4586 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4587 if (status < 0)
4588 goto error;
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4590 if (status < 0)
4591 goto error;
4583 4592
4584 /* QAM State Machine (FSM) Thresholds */
4585 4593
4586 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); 4594 /* QAM State Machine (FSM) Thresholds */
4587 if (status < 0)
4588 break;
4589 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4590 if (status < 0)
4591 break;
4592 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4593 if (status < 0)
4594 break;
4595 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4596 if (status < 0)
4597 break;
4598 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4599 if (status < 0)
4600 break;
4601 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4602 if (status < 0)
4603 break;
4604 4595
4605 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4596 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4606 if (status < 0) 4597 if (status < 0)
4607 break; 4598 goto error;
4608 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4599 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4609 if (status < 0) 4600 if (status < 0)
4610 break; 4601 goto error;
4611 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); 4602 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4612 if (status < 0) 4603 if (status < 0)
4613 break; 4604 goto error;
4605 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4606 if (status < 0)
4607 goto error;
4608 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4609 if (status < 0)
4610 goto error;
4611 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4612 if (status < 0)
4613 goto error;
4614 4614
4615 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4616 if (status < 0)
4617 goto error;
4618 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4619 if (status < 0)
4620 goto error;
4621 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4622 if (status < 0)
4623 goto error;
4615 4624
4616 /* QAM FSM Tracking Parameters */
4617 4625
4618 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4626 /* QAM FSM Tracking Parameters */
4619 if (status < 0)
4620 break;
4621 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4622 if (status < 0)
4623 break;
4624 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4625 if (status < 0)
4626 break;
4627 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4628 if (status < 0)
4629 break;
4630 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4631 if (status < 0)
4632 break;
4633 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4634 if (status < 0)
4635 break;
4636 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4637 if (status < 0)
4638 break;
4639 } while (0);
4640 4627
4628 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4629 if (status < 0)
4630 goto error;
4631 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4632 if (status < 0)
4633 goto error;
4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4635 if (status < 0)
4636 goto error;
4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4638 if (status < 0)
4639 goto error;
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4641 if (status < 0)
4642 goto error;
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4644 if (status < 0)
4645 goto error;
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4647error:
4648 if (status < 0)
4649 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4641 return status; 4650 return status;
4642} 4651}
4643 4652
@@ -4653,185 +4662,184 @@ static int SetQAM64(struct drxk_state *state)
4653 int status = 0; 4662 int status = 0;
4654 4663
4655 dprintk(1, "\n"); 4664 dprintk(1, "\n");
4656 do { 4665 /* QAM Equalizer Setup */
4657 /* QAM Equalizer Setup */ 4666 /* Equalizer */
4658 /* Equalizer */ 4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4659 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); 4668 if (status < 0)
4660 if (status < 0) 4669 goto error;
4661 break; 4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4662 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); 4671 if (status < 0)
4663 if (status < 0) 4672 goto error;
4664 break; 4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4665 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); 4674 if (status < 0)
4666 if (status < 0) 4675 goto error;
4667 break; 4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4668 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); 4677 if (status < 0)
4669 if (status < 0) 4678 goto error;
4670 break; 4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4671 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); 4680 if (status < 0)
4672 if (status < 0) 4681 goto error;
4673 break; 4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4674 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); 4683 if (status < 0)
4675 if (status < 0) 4684 goto error;
4676 break;
4677 4685
4678 /* Decision Feedback Equalizer */ 4686 /* Decision Feedback Equalizer */
4679 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); 4687 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4680 if (status < 0) 4688 if (status < 0)
4681 break; 4689 goto error;
4682 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); 4690 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4683 if (status < 0) 4691 if (status < 0)
4684 break; 4692 goto error;
4685 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); 4693 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4686 if (status < 0) 4694 if (status < 0)
4687 break; 4695 goto error;
4688 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); 4696 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4689 if (status < 0) 4697 if (status < 0)
4690 break; 4698 goto error;
4691 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4699 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4692 if (status < 0) 4700 if (status < 0)
4693 break; 4701 goto error;
4694 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4702 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4695 if (status < 0) 4703 if (status < 0)
4696 break; 4704 goto error;
4697 4705
4698 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4706 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4699 if (status < 0) 4707 if (status < 0)
4700 break; 4708 goto error;
4701 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4709 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4702 if (status < 0) 4710 if (status < 0)
4703 break; 4711 goto error;
4704 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4712 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4705 if (status < 0) 4713 if (status < 0)
4706 break; 4714 goto error;
4707 4715
4708 /* QAM Slicer Settings */ 4716 /* QAM Slicer Settings */
4709 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); 4717 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4710 if (status < 0) 4718 if (status < 0)
4711 break; 4719 goto error;
4712 4720
4713 4721
4714 /* QAM Loop Controller Coeficients */ 4722 /* QAM Loop Controller Coeficients */
4715 4723
4716 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4724 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4717 if (status < 0) 4725 if (status < 0)
4718 break; 4726 goto error;
4719 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4727 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4720 if (status < 0) 4728 if (status < 0)
4721 break; 4729 goto error;
4722 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4730 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4723 if (status < 0) 4731 if (status < 0)
4724 break; 4732 goto error;
4725 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4733 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4726 if (status < 0) 4734 if (status < 0)
4727 break; 4735 goto error;
4728 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4736 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4729 if (status < 0) 4737 if (status < 0)
4730 break; 4738 goto error;
4731 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4739 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4732 if (status < 0) 4740 if (status < 0)
4733 break; 4741 goto error;
4734 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4742 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4735 if (status < 0) 4743 if (status < 0)
4736 break; 4744 goto error;
4737 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4745 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4738 if (status < 0) 4746 if (status < 0)
4739 break; 4747 goto error;
4740 4748
4741 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4749 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4742 if (status < 0) 4750 if (status < 0)
4743 break; 4751 goto error;
4744 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); 4752 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4745 if (status < 0) 4753 if (status < 0)
4746 break; 4754 goto error;
4747 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); 4755 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4748 if (status < 0) 4756 if (status < 0)
4749 break; 4757 goto error;
4750 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4758 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4751 if (status < 0) 4759 if (status < 0)
4752 break; 4760 goto error;
4753 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); 4761 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4754 if (status < 0) 4762 if (status < 0)
4755 break; 4763 goto error;
4756 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4764 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4757 if (status < 0) 4765 if (status < 0)
4758 break; 4766 goto error;
4759 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4767 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4760 if (status < 0) 4768 if (status < 0)
4761 break; 4769 goto error;
4762 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4770 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4763 if (status < 0) 4771 if (status < 0)
4764 break; 4772 goto error;
4765 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 4773 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4766 if (status < 0) 4774 if (status < 0)
4767 break; 4775 goto error;
4768 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4776 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4769 if (status < 0) 4777 if (status < 0)
4770 break; 4778 goto error;
4771 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4779 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4772 if (status < 0) 4780 if (status < 0)
4773 break; 4781 goto error;
4774 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4782 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4775 if (status < 0) 4783 if (status < 0)
4776 break; 4784 goto error;
4777 4785
4778 4786
4779 /* QAM State Machine (FSM) Thresholds */ 4787 /* QAM State Machine (FSM) Thresholds */
4780 4788
4781 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); 4789 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4782 if (status < 0) 4790 if (status < 0)
4783 break; 4791 goto error;
4784 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4792 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4785 if (status < 0) 4793 if (status < 0)
4786 break; 4794 goto error;
4787 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4795 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4788 if (status < 0) 4796 if (status < 0)
4789 break; 4797 goto error;
4790 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); 4798 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4791 if (status < 0) 4799 if (status < 0)
4792 break; 4800 goto error;
4793 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); 4801 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4794 if (status < 0) 4802 if (status < 0)
4795 break; 4803 goto error;
4796 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); 4804 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4797 if (status < 0) 4805 if (status < 0)
4798 break; 4806 goto error;
4799 4807
4800 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4808 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4801 if (status < 0) 4809 if (status < 0)
4802 break; 4810 goto error;
4803 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4811 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4804 if (status < 0) 4812 if (status < 0)
4805 break; 4813 goto error;
4806 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); 4814 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4807 if (status < 0) 4815 if (status < 0)
4808 break; 4816 goto error;
4809 4817
4810 4818
4811 /* QAM FSM Tracking Parameters */ 4819 /* QAM FSM Tracking Parameters */
4812 4820
4813 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4821 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4814 if (status < 0) 4822 if (status < 0)
4815 break; 4823 goto error;
4816 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); 4824 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4817 if (status < 0) 4825 if (status < 0)
4818 break; 4826 goto error;
4819 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); 4827 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4820 if (status < 0) 4828 if (status < 0)
4821 break; 4829 goto error;
4822 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); 4830 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4823 if (status < 0) 4831 if (status < 0)
4824 break; 4832 goto error;
4825 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); 4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4826 if (status < 0) 4834 if (status < 0)
4827 break; 4835 goto error;
4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); 4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4829 if (status < 0) 4837 if (status < 0)
4830 break; 4838 goto error;
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); 4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4832 if (status < 0) 4840error:
4833 break; 4841 if (status < 0)
4834 } while (0); 4842 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4835 4843
4836 return status; 4844 return status;
4837} 4845}
@@ -4848,187 +4856,186 @@ static int SetQAM128(struct drxk_state *state)
4848 int status = 0; 4856 int status = 0;
4849 4857
4850 dprintk(1, "\n"); 4858 dprintk(1, "\n");
4851 do { 4859 /* QAM Equalizer Setup */
4852 /* QAM Equalizer Setup */ 4860 /* Equalizer */
4853 /* Equalizer */ 4861 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); 4862 if (status < 0)
4855 if (status < 0) 4863 goto error;
4856 break; 4864 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4857 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); 4865 if (status < 0)
4858 if (status < 0) 4866 goto error;
4859 break; 4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4860 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); 4868 if (status < 0)
4861 if (status < 0) 4869 goto error;
4862 break; 4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4863 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); 4871 if (status < 0)
4864 if (status < 0) 4872 goto error;
4865 break; 4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4866 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); 4874 if (status < 0)
4867 if (status < 0) 4875 goto error;
4868 break; 4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4869 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); 4877 if (status < 0)
4870 if (status < 0) 4878 goto error;
4871 break;
4872 4879
4873 /* Decision Feedback Equalizer */ 4880 /* Decision Feedback Equalizer */
4874 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); 4881 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4875 if (status < 0) 4882 if (status < 0)
4876 break; 4883 goto error;
4877 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); 4884 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4878 if (status < 0) 4885 if (status < 0)
4879 break; 4886 goto error;
4880 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); 4887 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4881 if (status < 0) 4888 if (status < 0)
4882 break; 4889 goto error;
4883 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); 4890 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4884 if (status < 0) 4891 if (status < 0)
4885 break; 4892 goto error;
4886 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); 4893 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4887 if (status < 0) 4894 if (status < 0)
4888 break; 4895 goto error;
4889 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4896 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4890 if (status < 0) 4897 if (status < 0)
4891 break; 4898 goto error;
4892 4899
4893 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4900 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4894 if (status < 0) 4901 if (status < 0)
4895 break; 4902 goto error;
4896 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4903 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4897 if (status < 0) 4904 if (status < 0)
4898 break; 4905 goto error;
4899 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4906 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4900 if (status < 0) 4907 if (status < 0)
4901 break; 4908 goto error;
4902 4909
4903 4910
4904 /* QAM Slicer Settings */ 4911 /* QAM Slicer Settings */
4905 4912
4906 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); 4913 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4907 if (status < 0) 4914 if (status < 0)
4908 break; 4915 goto error;
4909 4916
4910 4917
4911 /* QAM Loop Controller Coeficients */ 4918 /* QAM Loop Controller Coeficients */
4912 4919
4913 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4920 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4914 if (status < 0) 4921 if (status < 0)
4915 break; 4922 goto error;
4916 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4923 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4917 if (status < 0) 4924 if (status < 0)
4918 break; 4925 goto error;
4919 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4926 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4920 if (status < 0) 4927 if (status < 0)
4921 break; 4928 goto error;
4922 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4929 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4923 if (status < 0) 4930 if (status < 0)
4924 break; 4931 goto error;
4925 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4932 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4926 if (status < 0) 4933 if (status < 0)
4927 break; 4934 goto error;
4928 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4935 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4929 if (status < 0) 4936 if (status < 0)
4930 break; 4937 goto error;
4931 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4938 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4932 if (status < 0) 4939 if (status < 0)
4933 break; 4940 goto error;
4934 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4941 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4935 if (status < 0) 4942 if (status < 0)
4936 break; 4943 goto error;
4937 4944
4938 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4945 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4939 if (status < 0) 4946 if (status < 0)
4940 break; 4947 goto error;
4941 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); 4948 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4942 if (status < 0) 4949 if (status < 0)
4943 break; 4950 goto error;
4944 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); 4951 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4945 if (status < 0) 4952 if (status < 0)
4946 break; 4953 goto error;
4947 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4954 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4948 if (status < 0) 4955 if (status < 0)
4949 break; 4956 goto error;
4950 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); 4957 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4951 if (status < 0) 4958 if (status < 0)
4952 break; 4959 goto error;
4953 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); 4960 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4954 if (status < 0) 4961 if (status < 0)
4955 break; 4962 goto error;
4956 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4963 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4957 if (status < 0) 4964 if (status < 0)
4958 break; 4965 goto error;
4959 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4966 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4960 if (status < 0) 4967 if (status < 0)
4961 break; 4968 goto error;
4962 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); 4969 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4963 if (status < 0) 4970 if (status < 0)
4964 break; 4971 goto error;
4965 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4972 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4966 if (status < 0) 4973 if (status < 0)
4967 break; 4974 goto error;
4968 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4975 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4969 if (status < 0) 4976 if (status < 0)
4970 break; 4977 goto error;
4971 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4978 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4972 if (status < 0) 4979 if (status < 0)
4973 break; 4980 goto error;
4974 4981
4975 4982
4976 /* QAM State Machine (FSM) Thresholds */ 4983 /* QAM State Machine (FSM) Thresholds */
4977 4984
4978 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 4985 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4979 if (status < 0) 4986 if (status < 0)
4980 break; 4987 goto error;
4981 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4988 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4982 if (status < 0) 4989 if (status < 0)
4983 break; 4990 goto error;
4984 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4991 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4985 if (status < 0) 4992 if (status < 0)
4986 break; 4993 goto error;
4987 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4994 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4988 if (status < 0) 4995 if (status < 0)
4989 break; 4996 goto error;
4990 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); 4997 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4991 if (status < 0) 4998 if (status < 0)
4992 break; 4999 goto error;
4993 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 5000 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4994 if (status < 0) 5001 if (status < 0)
4995 break; 5002 goto error;
4996 5003
4997 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5004 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4998 if (status < 0) 5005 if (status < 0)
4999 break; 5006 goto error;
5000 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); 5007 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5001 if (status < 0) 5008 if (status < 0)
5002 break; 5009 goto error;
5003 5010
5004 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5011 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5005 if (status < 0) 5012 if (status < 0)
5006 break; 5013 goto error;
5007 5014
5008 /* QAM FSM Tracking Parameters */ 5015 /* QAM FSM Tracking Parameters */
5009 5016
5010 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5017 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5011 if (status < 0) 5018 if (status < 0)
5012 break; 5019 goto error;
5013 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); 5020 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5014 if (status < 0) 5021 if (status < 0)
5015 break; 5022 goto error;
5016 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); 5023 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5017 if (status < 0) 5024 if (status < 0)
5018 break; 5025 goto error;
5019 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); 5026 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5020 if (status < 0) 5027 if (status < 0)
5021 break; 5028 goto error;
5022 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); 5029 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5023 if (status < 0) 5030 if (status < 0)
5024 break; 5031 goto error;
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); 5032 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5026 if (status < 0) 5033 if (status < 0)
5027 break; 5034 goto error;
5028 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); 5035 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5029 if (status < 0) 5036error:
5030 break; 5037 if (status < 0)
5031 } while (0); 5038 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5032 5039
5033 return status; 5040 return status;
5034} 5041}
@@ -5045,187 +5052,185 @@ static int SetQAM256(struct drxk_state *state)
5045 int status = 0; 5052 int status = 0;
5046 5053
5047 dprintk(1, "\n"); 5054 dprintk(1, "\n");
5048 do { 5055 /* QAM Equalizer Setup */
5049 /* QAM Equalizer Setup */ 5056 /* Equalizer */
5050 /* Equalizer */ 5057 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5051 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); 5058 if (status < 0)
5052 if (status < 0) 5059 goto error;
5053 break; 5060 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5054 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); 5061 if (status < 0)
5055 if (status < 0) 5062 goto error;
5056 break; 5063 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5057 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); 5064 if (status < 0)
5058 if (status < 0) 5065 goto error;
5059 break; 5066 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5060 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); 5067 if (status < 0)
5061 if (status < 0) 5068 goto error;
5062 break; 5069 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5063 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); 5070 if (status < 0)
5064 if (status < 0) 5071 goto error;
5065 break; 5072 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5066 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); 5073 if (status < 0)
5067 if (status < 0) 5074 goto error;
5068 break;
5069
5070 /* Decision Feedback Equalizer */
5071 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5072 if (status < 0)
5073 break;
5074 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5075 if (status < 0)
5076 break;
5077 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5078 if (status < 0)
5079 break;
5080 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5081 if (status < 0)
5082 break;
5083 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5084 if (status < 0)
5085 break;
5086 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5087 if (status < 0)
5088 break;
5089 5075
5090 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 5076 /* Decision Feedback Equalizer */
5091 if (status < 0) 5077 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5092 break; 5078 if (status < 0)
5093 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 5079 goto error;
5094 if (status < 0) 5080 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5095 break; 5081 if (status < 0)
5096 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 5082 goto error;
5097 if (status < 0) 5083 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5098 break; 5084 if (status < 0)
5085 goto error;
5086 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5087 if (status < 0)
5088 goto error;
5089 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5090 if (status < 0)
5091 goto error;
5092 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5093 if (status < 0)
5094 goto error;
5099 5095
5100 /* QAM Slicer Settings */ 5096 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5097 if (status < 0)
5098 goto error;
5099 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5100 if (status < 0)
5101 goto error;
5102 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5103 if (status < 0)
5104 goto error;
5101 5105
5102 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); 5106 /* QAM Slicer Settings */
5103 if (status < 0)
5104 break;
5105 5107
5108 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5109 if (status < 0)
5110 goto error;
5106 5111
5107 /* QAM Loop Controller Coeficients */
5108 5112
5109 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 5113 /* QAM Loop Controller Coeficients */
5110 if (status < 0)
5111 break;
5112 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5113 if (status < 0)
5114 break;
5115 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5116 if (status < 0)
5117 break;
5118 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5119 if (status < 0)
5120 break;
5121 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5122 if (status < 0)
5123 break;
5124 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5125 if (status < 0)
5126 break;
5127 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5128 if (status < 0)
5129 break;
5130 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5131 if (status < 0)
5132 break;
5133 5114
5134 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 5115 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5135 if (status < 0) 5116 if (status < 0)
5136 break; 5117 goto error;
5137 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); 5118 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5138 if (status < 0) 5119 if (status < 0)
5139 break; 5120 goto error;
5140 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); 5121 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5141 if (status < 0) 5122 if (status < 0)
5142 break; 5123 goto error;
5143 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 5124 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5144 if (status < 0) 5125 if (status < 0)
5145 break; 5126 goto error;
5146 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); 5127 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5147 if (status < 0) 5128 if (status < 0)
5148 break; 5129 goto error;
5149 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); 5130 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5150 if (status < 0) 5131 if (status < 0)
5151 break; 5132 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 5133 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5153 if (status < 0) 5134 if (status < 0)
5154 break; 5135 goto error;
5155 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 5136 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5156 if (status < 0) 5137 if (status < 0)
5157 break; 5138 goto error;
5158 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5159 if (status < 0)
5160 break;
5161 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5162 if (status < 0)
5163 break;
5164 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5165 if (status < 0)
5166 break;
5167 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5168 if (status < 0)
5169 break;
5170 5139
5140 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5141 if (status < 0)
5142 goto error;
5143 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5144 if (status < 0)
5145 goto error;
5146 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5147 if (status < 0)
5148 goto error;
5149 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5150 if (status < 0)
5151 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5153 if (status < 0)
5154 goto error;
5155 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5156 if (status < 0)
5157 goto error;
5158 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5159 if (status < 0)
5160 goto error;
5161 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5162 if (status < 0)
5163 goto error;
5164 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5165 if (status < 0)
5166 goto error;
5167 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5168 if (status < 0)
5169 goto error;
5170 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5171 if (status < 0)
5172 goto error;
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5174 if (status < 0)
5175 goto error;
5171 5176
5172 /* QAM State Machine (FSM) Thresholds */
5173 5177
5174 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 5178 /* QAM State Machine (FSM) Thresholds */
5175 if (status < 0)
5176 break;
5177 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5178 if (status < 0)
5179 break;
5180 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5181 if (status < 0)
5182 break;
5183 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5184 if (status < 0)
5185 break;
5186 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5187 if (status < 0)
5188 break;
5189 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5190 if (status < 0)
5191 break;
5192 5179
5193 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5180 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5194 if (status < 0) 5181 if (status < 0)
5195 break; 5182 goto error;
5196 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 5183 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5197 if (status < 0) 5184 if (status < 0)
5198 break; 5185 goto error;
5199 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5186 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5200 if (status < 0) 5187 if (status < 0)
5201 break; 5188 goto error;
5189 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5190 if (status < 0)
5191 goto error;
5192 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5193 if (status < 0)
5194 goto error;
5195 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5196 if (status < 0)
5197 goto error;
5202 5198
5199 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5200 if (status < 0)
5201 goto error;
5202 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5203 if (status < 0)
5204 goto error;
5205 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5206 if (status < 0)
5207 goto error;
5203 5208
5204 /* QAM FSM Tracking Parameters */
5205 5209
5206 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5210 /* QAM FSM Tracking Parameters */
5207 if (status < 0)
5208 break;
5209 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5210 if (status < 0)
5211 break;
5212 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5213 if (status < 0)
5214 break;
5215 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5216 if (status < 0)
5217 break;
5218 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5219 if (status < 0)
5220 break;
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5222 if (status < 0)
5223 break;
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5225 if (status < 0)
5226 break;
5227 } while (0);
5228 5211
5212 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5213 if (status < 0)
5214 goto error;
5215 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5216 if (status < 0)
5217 goto error;
5218 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5219 if (status < 0)
5220 goto error;
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5222 if (status < 0)
5223 goto error;
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5225 if (status < 0)
5226 goto error;
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5228 if (status < 0)
5229 goto error;
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5231error:
5232 if (status < 0)
5233 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5229 return status; 5234 return status;
5230} 5235}
5231 5236
@@ -5243,18 +5248,15 @@ static int QAMResetQAM(struct drxk_state *state)
5243 u16 cmdResult; 5248 u16 cmdResult;
5244 5249
5245 dprintk(1, "\n"); 5250 dprintk(1, "\n");
5246 do { 5251 /* Stop QAM comstate->m_exec */
5247 /* Stop QAM comstate->m_exec */ 5252 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5248 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 5253 if (status < 0)
5249 if (status < 0) 5254 goto error;
5250 break;
5251
5252 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5253 if (status < 0)
5254 break;
5255 } while (0);
5256 5255
5257 /* All done, all OK */ 5256 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5257error:
5258 if (status < 0)
5259 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5258 return status; 5260 return status;
5259} 5261}
5260 5262
@@ -5276,54 +5278,55 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5276 int status; 5278 int status;
5277 5279
5278 dprintk(1, "\n"); 5280 dprintk(1, "\n");
5279 do { 5281 /* Select & calculate correct IQM rate */
5280 /* Select & calculate correct IQM rate */ 5282 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5281 adcFrequency = (state->m_sysClockFreq * 1000) / 3; 5283 ratesel = 0;
5282 ratesel = 0; 5284 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5283 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */ 5285 if (state->param.u.qam.symbol_rate <= 1188750)
5284 if (state->param.u.qam.symbol_rate <= 1188750) 5286 ratesel = 3;
5285 ratesel = 3; 5287 else if (state->param.u.qam.symbol_rate <= 2377500)
5286 else if (state->param.u.qam.symbol_rate <= 2377500) 5288 ratesel = 2;
5287 ratesel = 2; 5289 else if (state->param.u.qam.symbol_rate <= 4755000)
5288 else if (state->param.u.qam.symbol_rate <= 4755000) 5290 ratesel = 1;
5289 ratesel = 1; 5291 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5290 status = write16(state, IQM_FD_RATESEL__A, ratesel); 5292 if (status < 0)
5291 if (status < 0) 5293 goto error;
5292 break;
5293 5294
5294 /* 5295 /*
5295 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5296 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5296 */ 5297 */
5297 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel); 5298 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
5298 if (symbFreq == 0) { 5299 if (symbFreq == 0) {
5299 /* Divide by zero */ 5300 /* Divide by zero */
5300 return -1; 5301 status = -EINVAL;
5301 } 5302 goto error;
5302 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + 5303 }
5303 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - 5304 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5304 (1 << 23); 5305 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5305 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); 5306 (1 << 23);
5306 if (status < 0) 5307 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5307 break; 5308 if (status < 0)
5308 state->m_iqmRcRate = iqmRcRate; 5309 goto error;
5309 /* 5310 state->m_iqmRcRate = iqmRcRate;
5310 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) 5311 /*
5311 */ 5312 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5312 symbFreq = state->param.u.qam.symbol_rate; 5313 */
5313 if (adcFrequency == 0) { 5314 symbFreq = state->param.u.qam.symbol_rate;
5314 /* Divide by zero */ 5315 if (adcFrequency == 0) {
5315 return -1; 5316 /* Divide by zero */
5316 } 5317 status = -EINVAL;
5317 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + 5318 goto error;
5318 (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 5319 }
5319 16); 5320 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5320 if (lcSymbRate > 511) 5321 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5321 lcSymbRate = 511; 5322 16);
5322 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); 5323 if (lcSymbRate > 511)
5323 if (status < 0) 5324 lcSymbRate = 511;
5324 break; 5325 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5325 } while (0);
5326 5326
5327error:
5328 if (status < 0)
5329 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5327 return status; 5330 return status;
5328} 5331}
5329 5332
@@ -5342,8 +5345,8 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5342 u16 Result[2] = { 0, 0 }; 5345 u16 Result[2] = { 0, 0 };
5343 5346
5344 dprintk(1, "\n"); 5347 dprintk(1, "\n");
5345 status = 5348 *pLockStatus = NOT_LOCKED;
5346 scu_command(state, 5349 status = scu_command(state,
5347 SCU_RAM_COMMAND_STANDARD_QAM | 5350 SCU_RAM_COMMAND_STANDARD_QAM |
5348 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, 5351 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5349 Result); 5352 Result);
@@ -5352,7 +5355,6 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5352 5355
5353 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { 5356 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5354 /* 0x0000 NOT LOCKED */ 5357 /* 0x0000 NOT LOCKED */
5355 *pLockStatus = NOT_LOCKED;
5356 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { 5358 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5357 /* 0x4000 DEMOD LOCKED */ 5359 /* 0x4000 DEMOD LOCKED */
5358 *pLockStatus = DEMOD_LOCK; 5360 *pLockStatus = DEMOD_LOCK;
@@ -5379,416 +5381,395 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5379static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, 5381static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5380 s32 tunerFreqOffset) 5382 s32 tunerFreqOffset)
5381{ 5383{
5382 int status = 0; 5384 int status;
5383 u8 parameterLen; 5385 u8 parameterLen;
5384 u16 setEnvParameters[5]; 5386 u16 setEnvParameters[5];
5385 u16 setParamParameters[4] = { 0, 0, 0, 0 }; 5387 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5386 u16 cmdResult; 5388 u16 cmdResult;
5387 5389
5388 dprintk(1, "\n"); 5390 dprintk(1, "\n");
5389 do { 5391 /*
5390 /* 5392 STEP 1: reset demodulator
5391 STEP 1: reset demodulator 5393 resets FEC DI and FEC RS
5392 resets FEC DI and FEC RS 5394 resets QAM block
5393 resets QAM block 5395 resets SCU variables
5394 resets SCU variables 5396 */
5395 */ 5397 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5396 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); 5398 if (status < 0)
5397 if (status < 0) 5399 goto error;
5398 break; 5400 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5399 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5401 if (status < 0)
5400 if (status < 0) 5402 goto error;
5401 break; 5403 status = QAMResetQAM(state);
5402 status = QAMResetQAM(state); 5404 if (status < 0)
5403 if (status < 0) 5405 goto error;
5404 break;
5405
5406 /*
5407 STEP 2: configure demodulator
5408 -set env
5409 -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
5410 */
5411 status = QAMSetSymbolrate(state);
5412 if (status < 0)
5413 break;
5414 5406
5415 /* Env parameters */ 5407 /*
5416 setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ 5408 STEP 2: configure demodulator
5417 if (state->m_OperationMode == OM_QAM_ITU_C) 5409 -set env
5418 setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ 5410 -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
5419 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); 5411 */
5420 /* check for LOCKRANGE Extented */ 5412 status = QAMSetSymbolrate(state);
5421 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5413 if (status < 0)
5422 parameterLen = 4; 5414 goto error;
5423 5415
5424 /* Set params */ 5416 /* Env parameters */
5425 switch (state->param.u.qam.modulation) { 5417 setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */
5426 case QAM_256: 5418 if (state->m_OperationMode == OM_QAM_ITU_C)
5427 state->m_Constellation = DRX_CONSTELLATION_QAM256; 5419 setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */
5428 break; 5420 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5429 case QAM_AUTO: 5421 /* check for LOCKRANGE Extented */
5430 case QAM_64: 5422 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5431 state->m_Constellation = DRX_CONSTELLATION_QAM64; 5423 parameterLen = 4;
5432 break; 5424
5433 case QAM_16: 5425 /* Set params */
5434 state->m_Constellation = DRX_CONSTELLATION_QAM16; 5426 switch (state->param.u.qam.modulation) {
5435 break; 5427 case QAM_256:
5436 case QAM_32: 5428 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5437 state->m_Constellation = DRX_CONSTELLATION_QAM32; 5429 break;
5438 break; 5430 case QAM_AUTO:
5439 case QAM_128: 5431 case QAM_64:
5440 state->m_Constellation = DRX_CONSTELLATION_QAM128; 5432 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5441 break; 5433 break;
5442 default: 5434 case QAM_16:
5443 status = -EINVAL; 5435 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5444 break; 5436 break;
5445 } 5437 case QAM_32:
5446 status = status; 5438 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5447 if (status < 0) 5439 break;
5448 break; 5440 case QAM_128:
5449 setParamParameters[0] = state->m_Constellation; /* constellation */ 5441 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5450 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5442 break;
5443 default:
5444 status = -EINVAL;
5445 break;
5446 }
5447 if (status < 0)
5448 goto error;
5449 setParamParameters[0] = state->m_Constellation; /* constellation */
5450 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5451 5451
5452 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult); 5452 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5453 if (status < 0) 5453 if (status < 0)
5454 break; 5454 goto error;
5455 5455
5456 5456
5457 /* STEP 3: enable the system in a mode where the ADC provides valid signal 5457 /* STEP 3: enable the system in a mode where the ADC provides valid signal
5458 setup constellation independent registers */ 5458 setup constellation independent registers */
5459#if 0 5459#if 0
5460 status = SetFrequency (channel, tunerFreqOffset)); 5460 status = SetFrequency(channel, tunerFreqOffset));
5461 if (status < 0) 5461 if (status < 0)
5462 break; 5462 goto error;
5463#endif 5463#endif
5464 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); 5464 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5465 if (status < 0) 5465 if (status < 0)
5466 break; 5466 goto error;
5467
5468 /* Setup BER measurement */
5469 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5470 if (status < 0)
5471 break;
5472 5467
5473 /* Reset default values */ 5468 /* Setup BER measurement */
5474 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); 5469 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5475 if (status < 0) 5470 if (status < 0)
5476 break; 5471 goto error;
5477 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5478 if (status < 0)
5479 break;
5480 5472
5481 /* Reset default LC values */ 5473 /* Reset default values */
5482 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); 5474 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5483 if (status < 0) 5475 if (status < 0)
5484 break; 5476 goto error;
5485 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); 5477 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5486 if (status < 0) 5478 if (status < 0)
5487 break; 5479 goto error;
5488 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5489 if (status < 0)
5490 break;
5491 status = write16(state, QAM_LC_MODE__A, 7);
5492 if (status < 0)
5493 break;
5494 5480
5495 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); 5481 /* Reset default LC values */
5496 if (status < 0) 5482 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5497 break; 5483 if (status < 0)
5498 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); 5484 goto error;
5499 if (status < 0) 5485 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5500 break; 5486 if (status < 0)
5501 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); 5487 goto error;
5502 if (status < 0) 5488 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5503 break; 5489 if (status < 0)
5504 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); 5490 goto error;
5505 if (status < 0) 5491 status = write16(state, QAM_LC_MODE__A, 7);
5506 break; 5492 if (status < 0)
5507 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); 5493 goto error;
5508 if (status < 0)
5509 break;
5510 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5511 if (status < 0)
5512 break;
5513 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5514 if (status < 0)
5515 break;
5516 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5517 if (status < 0)
5518 break;
5519 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5520 if (status < 0)
5521 break;
5522 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5523 if (status < 0)
5524 break;
5525 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5526 if (status < 0)
5527 break;
5528 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5529 if (status < 0)
5530 break;
5531 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5532 if (status < 0)
5533 break;
5534 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5535 if (status < 0)
5536 break;
5537 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5538 if (status < 0)
5539 break;
5540 5494
5541 /* Mirroring, QAM-block starting point not inverted */ 5495 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5542 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5496 if (status < 0)
5543 if (status < 0) 5497 goto error;
5544 break; 5498 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5499 if (status < 0)
5500 goto error;
5501 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5502 if (status < 0)
5503 goto error;
5504 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5505 if (status < 0)
5506 goto error;
5507 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5508 if (status < 0)
5509 goto error;
5510 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5511 if (status < 0)
5512 goto error;
5513 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5514 if (status < 0)
5515 goto error;
5516 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5517 if (status < 0)
5518 goto error;
5519 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5520 if (status < 0)
5521 goto error;
5522 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5523 if (status < 0)
5524 goto error;
5525 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5526 if (status < 0)
5527 goto error;
5528 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5529 if (status < 0)
5530 goto error;
5531 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5532 if (status < 0)
5533 goto error;
5534 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5535 if (status < 0)
5536 goto error;
5537 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5538 if (status < 0)
5539 goto error;
5545 5540
5546 /* Halt SCU to enable safe non-atomic accesses */ 5541 /* Mirroring, QAM-block starting point not inverted */
5547 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5542 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5548 if (status < 0) 5543 if (status < 0)
5549 break; 5544 goto error;
5550 5545
5551 /* STEP 4: constellation specific setup */ 5546 /* Halt SCU to enable safe non-atomic accesses */
5552 switch (state->param.u.qam.modulation) { 5547 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5553 case QAM_16: 5548 if (status < 0)
5554 status = SetQAM16(state); 5549 goto error;
5555 if (status < 0)
5556 break;
5557 break;
5558 case QAM_32:
5559 status = SetQAM32(state);
5560 if (status < 0)
5561 break;
5562 break;
5563 case QAM_AUTO:
5564 case QAM_64:
5565 status = SetQAM64(state);
5566 if (status < 0)
5567 break;
5568 break;
5569 case QAM_128:
5570 status = SetQAM128(state);
5571 if (status < 0)
5572 break;
5573 break;
5574 case QAM_256:
5575 status = SetQAM256(state);
5576 if (status < 0)
5577 break;
5578 break;
5579 default:
5580 return -1;
5581 break;
5582 } /* switch */
5583 /* Activate SCU to enable SCU commands */
5584 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5585 if (status < 0)
5586 break;
5587 5550
5551 /* STEP 4: constellation specific setup */
5552 switch (state->param.u.qam.modulation) {
5553 case QAM_16:
5554 status = SetQAM16(state);
5555 break;
5556 case QAM_32:
5557 status = SetQAM32(state);
5558 break;
5559 case QAM_AUTO:
5560 case QAM_64:
5561 status = SetQAM64(state);
5562 break;
5563 case QAM_128:
5564 status = SetQAM128(state);
5565 break;
5566 case QAM_256:
5567 status = SetQAM256(state);
5568 break;
5569 default:
5570 status = -EINVAL;
5571 break;
5572 }
5573 if (status < 0)
5574 goto error;
5588 5575
5589 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5576 /* Activate SCU to enable SCU commands */
5590 /* extAttr->currentChannel.constellation = channel->constellation; */ 5577 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5591 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5578 if (status < 0)
5592 status = MPEGTSDtoSetup(state, state->m_OperationMode); 5579 goto error;
5593 if (status < 0)
5594 break;
5595 5580
5596 /* Start processes */ 5581 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5597 status = MPEGTSStart(state); 5582 /* extAttr->currentChannel.constellation = channel->constellation; */
5598 if (status < 0) 5583 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5599 break; 5584 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5600 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5585 if (status < 0)
5601 if (status < 0) 5586 goto error;
5602 break;
5603 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5604 if (status < 0)
5605 break;
5606 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5607 if (status < 0)
5608 break;
5609 5587
5610 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5588 /* Start processes */
5611 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); 5589 status = MPEGTSStart(state);
5612 if (status < 0) 5590 if (status < 0)
5613 break; 5591 goto error;
5592 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5593 if (status < 0)
5594 goto error;
5595 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5596 if (status < 0)
5597 goto error;
5598 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5599 if (status < 0)
5600 goto error;
5614 5601
5615 /* update global DRXK data container */ 5602 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5616 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ 5603 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5604 if (status < 0)
5605 goto error;
5617 5606
5618 /* All done, all OK */ 5607 /* update global DRXK data container */
5619 } while (0); 5608/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5620 5609
5610error:
5621 if (status < 0) 5611 if (status < 0)
5622 printk(KERN_ERR "drxk: %s %d\n", __func__, status); 5612 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5623
5624 return status; 5613 return status;
5625} 5614}
5626 5615
5627static int SetQAMStandard(struct drxk_state *state, 5616static int SetQAMStandard(struct drxk_state *state,
5628 enum OperationMode oMode) 5617 enum OperationMode oMode)
5629{ 5618{
5619 int status;
5630#ifdef DRXK_QAM_TAPS 5620#ifdef DRXK_QAM_TAPS
5631#define DRXK_QAMA_TAPS_SELECT 5621#define DRXK_QAMA_TAPS_SELECT
5632#include "drxk_filters.h" 5622#include "drxk_filters.h"
5633#undef DRXK_QAMA_TAPS_SELECT 5623#undef DRXK_QAMA_TAPS_SELECT
5634#else
5635 int status;
5636#endif 5624#endif
5637 5625
5638 dprintk(1, "\n"); 5626 /* added antenna switch */
5639 do { 5627 SwitchAntennaToQAM(state);
5640 /* added antenna switch */
5641 SwitchAntennaToQAM(state);
5642 5628
5643 /* Ensure correct power-up mode */ 5629 /* Ensure correct power-up mode */
5644 status = PowerUpQAM(state); 5630 status = PowerUpQAM(state);
5645 if (status < 0) 5631 if (status < 0)
5646 break; 5632 goto error;
5647 /* Reset QAM block */ 5633 /* Reset QAM block */
5648 status = QAMResetQAM(state); 5634 status = QAMResetQAM(state);
5649 if (status < 0) 5635 if (status < 0)
5650 break; 5636 goto error;
5651 5637
5652 /* Setup IQM */ 5638 /* Setup IQM */
5653 5639
5654 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 5640 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5655 if (status < 0) 5641 if (status < 0)
5656 break; 5642 goto error;
5657 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 5643 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5658 if (status < 0) 5644 if (status < 0)
5659 break; 5645 goto error;
5660 5646
5661 /* Upload IQM Channel Filter settings by 5647 /* Upload IQM Channel Filter settings by
5662 boot loader from ROM table */ 5648 boot loader from ROM table */
5663 switch (oMode) { 5649 switch (oMode) {
5664 case OM_QAM_ITU_A: 5650 case OM_QAM_ITU_A:
5665 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5651 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5666 if (status < 0) 5652 break;
5667 break; 5653 case OM_QAM_ITU_C:
5668 break; 5654 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5669 case OM_QAM_ITU_C:
5670 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5671 if (status < 0)
5672 break;
5673 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5674 if (status < 0)
5675 break;
5676 break;
5677 default:
5678 status = -EINVAL;
5679 }
5680 status = status;
5681 if (status < 0) 5655 if (status < 0)
5682 break; 5656 goto error;
5657 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5658 break;
5659 default:
5660 status = -EINVAL;
5661 }
5662 if (status < 0)
5663 goto error;
5683 5664
5684 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); 5665 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5685 if (status < 0) 5666 if (status < 0)
5686 break; 5667 goto error;
5687 status = write16(state, IQM_CF_SYMMETRIC__A, 0); 5668 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5688 if (status < 0) 5669 if (status < 0)
5689 break; 5670 goto error;
5690 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5671 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5691 if (status < 0) 5672 if (status < 0)
5692 break; 5673 goto error;
5693 5674
5694 status = write16(state, IQM_RC_STRETCH__A, 21); 5675 status = write16(state, IQM_RC_STRETCH__A, 21);
5695 if (status < 0) 5676 if (status < 0)
5696 break; 5677 goto error;
5697 status = write16(state, IQM_AF_CLP_LEN__A, 0); 5678 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5698 if (status < 0) 5679 if (status < 0)
5699 break; 5680 goto error;
5700 status = write16(state, IQM_AF_CLP_TH__A, 448); 5681 status = write16(state, IQM_AF_CLP_TH__A, 448);
5701 if (status < 0) 5682 if (status < 0)
5702 break; 5683 goto error;
5703 status = write16(state, IQM_AF_SNS_LEN__A, 0); 5684 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5704 if (status < 0) 5685 if (status < 0)
5705 break; 5686 goto error;
5706 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); 5687 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5707 if (status < 0) 5688 if (status < 0)
5708 break; 5689 goto error;
5709 5690
5710 status = write16(state, IQM_FS_ADJ_SEL__A, 1); 5691 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5711 if (status < 0) 5692 if (status < 0)
5712 break; 5693 goto error;
5713 status = write16(state, IQM_RC_ADJ_SEL__A, 1); 5694 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5714 if (status < 0) 5695 if (status < 0)
5715 break; 5696 goto error;
5716 status = write16(state, IQM_CF_ADJ_SEL__A, 1); 5697 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5717 if (status < 0) 5698 if (status < 0)
5718 break; 5699 goto error;
5719 status = write16(state, IQM_AF_UPD_SEL__A, 0); 5700 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5720 if (status < 0) 5701 if (status < 0)
5721 break; 5702 goto error;
5722 5703
5723 /* IQM Impulse Noise Processing Unit */ 5704 /* IQM Impulse Noise Processing Unit */
5724 status = write16(state, IQM_CF_CLP_VAL__A, 500); 5705 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5725 if (status < 0) 5706 if (status < 0)
5726 break; 5707 goto error;
5727 status = write16(state, IQM_CF_DATATH__A, 1000); 5708 status = write16(state, IQM_CF_DATATH__A, 1000);
5728 if (status < 0) 5709 if (status < 0)
5729 break; 5710 goto error;
5730 status = write16(state, IQM_CF_BYPASSDET__A, 1); 5711 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5731 if (status < 0) 5712 if (status < 0)
5732 break; 5713 goto error;
5733 status = write16(state, IQM_CF_DET_LCT__A, 0); 5714 status = write16(state, IQM_CF_DET_LCT__A, 0);
5734 if (status < 0) 5715 if (status < 0)
5735 break; 5716 goto error;
5736 status = write16(state, IQM_CF_WND_LEN__A, 1); 5717 status = write16(state, IQM_CF_WND_LEN__A, 1);
5737 if (status < 0) 5718 if (status < 0)
5738 break; 5719 goto error;
5739 status = write16(state, IQM_CF_PKDTH__A, 1); 5720 status = write16(state, IQM_CF_PKDTH__A, 1);
5740 if (status < 0) 5721 if (status < 0)
5741 break; 5722 goto error;
5742 status = write16(state, IQM_AF_INC_BYPASS__A, 1); 5723 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5743 if (status < 0) 5724 if (status < 0)
5744 break; 5725 goto error;
5745 5726
5746 /* turn on IQMAF. Must be done before setAgc**() */ 5727 /* turn on IQMAF. Must be done before setAgc**() */
5747 status = SetIqmAf(state, true); 5728 status = SetIqmAf(state, true);
5748 if (status < 0) 5729 if (status < 0)
5749 break; 5730 goto error;
5750 status = write16(state, IQM_AF_START_LOCK__A, 0x01); 5731 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5751 if (status < 0) 5732 if (status < 0)
5752 break; 5733 goto error;
5753 5734
5754 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5735 /* IQM will not be reset from here, sync ADC and update/init AGC */
5755 status = ADCSynchronization(state); 5736 status = ADCSynchronization(state);
5756 if (status < 0) 5737 if (status < 0)
5757 break; 5738 goto error;
5758 5739
5759 /* Set the FSM step period */ 5740 /* Set the FSM step period */
5760 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); 5741 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5761 if (status < 0) 5742 if (status < 0)
5762 break; 5743 goto error;
5763 5744
5764 /* Halt SCU to enable safe non-atomic accesses */ 5745 /* Halt SCU to enable safe non-atomic accesses */
5765 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5746 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5766 if (status < 0) 5747 if (status < 0)
5767 break; 5748 goto error;
5768 5749
5769 /* No more resets of the IQM, current standard correctly set => 5750 /* No more resets of the IQM, current standard correctly set =>
5770 now AGCs can be configured. */ 5751 now AGCs can be configured. */
5771 5752
5772 status = InitAGC(state, true); 5753 status = InitAGC(state, true);
5773 if (status < 0) 5754 if (status < 0)
5774 break; 5755 goto error;
5775 status = SetPreSaw(state, &(state->m_qamPreSawCfg)); 5756 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5776 if (status < 0) 5757 if (status < 0)
5777 break; 5758 goto error;
5778 5759
5779 /* Configure AGC's */ 5760 /* Configure AGC's */
5780 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); 5761 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5781 if (status < 0) 5762 if (status < 0)
5782 break; 5763 goto error;
5783 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); 5764 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5784 if (status < 0) 5765 if (status < 0)
5785 break; 5766 goto error;
5786 5767
5787 /* Activate SCU to enable SCU commands */ 5768 /* Activate SCU to enable SCU commands */
5788 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5769 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5789 if (status < 0) 5770error:
5790 break; 5771 if (status < 0)
5791 } while (0); 5772 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5792 return status; 5773 return status;
5793} 5774}
5794 5775
@@ -5798,48 +5779,47 @@ static int WriteGPIO(struct drxk_state *state)
5798 u16 value = 0; 5779 u16 value = 0;
5799 5780
5800 dprintk(1, "\n"); 5781 dprintk(1, "\n");
5801 do { 5782 /* stop lock indicator process */
5802 /* stop lock indicator process */ 5783 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5803 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5784 if (status < 0)
5804 if (status < 0) 5785 goto error;
5805 break;
5806
5807 /* Write magic word to enable pdr reg write */
5808 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5809 if (status < 0)
5810 break;
5811 5786
5812 if (state->m_hasSAWSW) { 5787 /* Write magic word to enable pdr reg write */
5813 /* write to io pad configuration register - output mode */ 5788 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5814 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); 5789 if (status < 0)
5815 if (status < 0) 5790 goto error;
5816 break;
5817 5791
5818 /* use corresponding bit in io data output registar */ 5792 if (state->m_hasSAWSW) {
5819 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5793 /* write to io pad configuration register - output mode */
5820 if (status < 0) 5794 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5821 break; 5795 if (status < 0)
5822 if (state->m_GPIO == 0) 5796 goto error;
5823 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5824 else
5825 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5826 /* write back to io data output register */
5827 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5828 if (status < 0)
5829 break;
5830 5797
5831 } 5798 /* use corresponding bit in io data output registar */
5832 /* Write magic word to disable pdr reg write */ 5799 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5833 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5834 if (status < 0) 5800 if (status < 0)
5835 break; 5801 goto error;
5836 } while (0); 5802 if (state->m_GPIO == 0)
5803 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5804 else
5805 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5806 /* write back to io data output register */
5807 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5808 if (status < 0)
5809 goto error;
5810
5811 }
5812 /* Write magic word to disable pdr reg write */
5813 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5814error:
5815 if (status < 0)
5816 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5837 return status; 5817 return status;
5838} 5818}
5839 5819
5840static int SwitchAntennaToQAM(struct drxk_state *state) 5820static int SwitchAntennaToQAM(struct drxk_state *state)
5841{ 5821{
5842 int status = -1; 5822 int status = -EINVAL;
5843 5823
5844 dprintk(1, "\n"); 5824 dprintk(1, "\n");
5845 if (state->m_AntennaSwitchDVBTDVBC != 0) { 5825 if (state->m_AntennaSwitchDVBTDVBC != 0) {
@@ -5848,12 +5828,14 @@ static int SwitchAntennaToQAM(struct drxk_state *state)
5848 status = WriteGPIO(state); 5828 status = WriteGPIO(state);
5849 } 5829 }
5850 } 5830 }
5831 if (status < 0)
5832 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5851 return status; 5833 return status;
5852} 5834}
5853 5835
5854static int SwitchAntennaToDVBT(struct drxk_state *state) 5836static int SwitchAntennaToDVBT(struct drxk_state *state)
5855{ 5837{
5856 int status = -1; 5838 int status = -EINVAL;
5857 5839
5858 dprintk(1, "\n"); 5840 dprintk(1, "\n");
5859 if (state->m_AntennaSwitchDVBTDVBC != 0) { 5841 if (state->m_AntennaSwitchDVBTDVBC != 0) {
@@ -5862,6 +5844,8 @@ static int SwitchAntennaToDVBT(struct drxk_state *state)
5862 status = WriteGPIO(state); 5844 status = WriteGPIO(state);
5863 } 5845 }
5864 } 5846 }
5847 if (status < 0)
5848 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5865 return status; 5849 return status;
5866} 5850}
5867 5851
@@ -5877,34 +5861,30 @@ static int PowerDownDevice(struct drxk_state *state)
5877 int status; 5861 int status;
5878 5862
5879 dprintk(1, "\n"); 5863 dprintk(1, "\n");
5880 do { 5864 if (state->m_bPDownOpenBridge) {
5881 if (state->m_bPDownOpenBridge) { 5865 /* Open I2C bridge before power down of DRXK */
5882 /* Open I2C bridge before power down of DRXK */ 5866 status = ConfigureI2CBridge(state, true);
5883 status = ConfigureI2CBridge(state, true);
5884 if (status < 0)
5885 break;
5886 }
5887 /* driver 0.9.0 */
5888 status = DVBTEnableOFDMTokenRing(state, false);
5889 if (status < 0) 5867 if (status < 0)
5890 break; 5868 goto error;
5891 5869 }
5892 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); 5870 /* driver 0.9.0 */
5893 if (status < 0) 5871 status = DVBTEnableOFDMTokenRing(state, false);
5894 break; 5872 if (status < 0)
5895 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 5873 goto error;
5896 if (status < 0)
5897 break;
5898 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5899 status = HI_CfgCommand(state);
5900 if (status < 0)
5901 break;
5902 } while (0);
5903 5874
5875 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5904 if (status < 0) 5876 if (status < 0)
5905 return -1; 5877 goto error;
5878 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5879 if (status < 0)
5880 goto error;
5881 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5882 status = HI_CfgCommand(state);
5883error:
5884 if (status < 0)
5885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5906 5886
5907 return 0; 5887 return status;
5908} 5888}
5909 5889
5910static int load_microcode(struct drxk_state *state, const char *mc_name) 5890static int load_microcode(struct drxk_state *state, const char *mc_name)
@@ -5929,188 +5909,189 @@ static int load_microcode(struct drxk_state *state, const char *mc_name)
5929 5909
5930static int init_drxk(struct drxk_state *state) 5910static int init_drxk(struct drxk_state *state)
5931{ 5911{
5932 int status; 5912 int status = 0;
5933 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; 5913 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5934 u16 driverVersion; 5914 u16 driverVersion;
5935 5915
5936 dprintk(1, "\n"); 5916 dprintk(1, "\n");
5937 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { 5917 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5938 do { 5918 status = PowerUpDevice(state);
5939 status = PowerUpDevice(state); 5919 if (status < 0)
5940 if (status < 0) 5920 goto error;
5941 break; 5921 status = DRXX_Open(state);
5942 status = DRXX_Open(state); 5922 if (status < 0)
5943 if (status < 0) 5923 goto error;
5944 break; 5924 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5945 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 5925 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5946 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); 5926 if (status < 0)
5947 if (status < 0) 5927 goto error;
5948 break; 5928 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5949 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 5929 if (status < 0)
5950 if (status < 0) 5930 goto error;
5951 break; 5931 /* TODO is this needed, if yes how much delay in worst case scenario */
5952 /* TODO is this needed, if yes how much delay in worst case scenario */ 5932 msleep(1);
5953 msleep(1); 5933 state->m_DRXK_A3_PATCH_CODE = true;
5954 state->m_DRXK_A3_PATCH_CODE = true; 5934 status = GetDeviceCapabilities(state);
5955 status = GetDeviceCapabilities(state); 5935 if (status < 0)
5956 if (status < 0) 5936 goto error;
5957 break; 5937
5958 5938 /* Bridge delay, uses oscilator clock */
5959 /* Bridge delay, uses oscilator clock */ 5939 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5960 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 5940 /* SDA brdige delay */
5961 /* SDA brdige delay */ 5941 state->m_HICfgBridgeDelay =
5942 (u16) ((state->m_oscClockFreq / 1000) *
5943 HI_I2C_BRIDGE_DELAY) / 1000;
5944 /* Clipping */
5945 if (state->m_HICfgBridgeDelay >
5946 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5962 state->m_HICfgBridgeDelay = 5947 state->m_HICfgBridgeDelay =
5963 (u16) ((state->m_oscClockFreq / 1000) * 5948 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5964 HI_I2C_BRIDGE_DELAY) / 1000; 5949 }
5965 /* Clipping */ 5950 /* SCL bridge delay, same as SDA for now */
5966 if (state->m_HICfgBridgeDelay > 5951 state->m_HICfgBridgeDelay +=
5967 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { 5952 state->m_HICfgBridgeDelay <<
5968 state->m_HICfgBridgeDelay = 5953 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5969 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 5954
5970 } 5955 status = InitHI(state);
5971 /* SCL bridge delay, same as SDA for now */ 5956 if (status < 0)
5972 state->m_HICfgBridgeDelay += 5957 goto error;
5973 state->m_HICfgBridgeDelay << 5958 /* disable various processes */
5974 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5975
5976 status = InitHI(state);
5977 if (status < 0)
5978 break;
5979 /* disable various processes */
5980#if NOA1ROM 5959#if NOA1ROM
5981 if (!(state->m_DRXK_A1_ROM_CODE) 5960 if (!(state->m_DRXK_A1_ROM_CODE)
5982 && !(state->m_DRXK_A2_ROM_CODE)) 5961 && !(state->m_DRXK_A2_ROM_CODE))
5983#endif 5962#endif
5984 { 5963 {
5985 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5964 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5986 if (status < 0)
5987 break;
5988 }
5989
5990 /* disable MPEG port */
5991 status = MPEGTSDisable(state);
5992 if (status < 0)
5993 break;
5994
5995 /* Stop AUD and SCU */
5996 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5997 if (status < 0)
5998 break;
5999 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6000 if (status < 0) 5965 if (status < 0)
6001 break; 5966 goto error;
6002 5967 }
6003 /* enable token-ring bus through OFDM block for possible ucode upload */
6004 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6005 if (status < 0)
6006 break;
6007 5968
6008 /* include boot loader section */ 5969 /* disable MPEG port */
6009 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); 5970 status = MPEGTSDisable(state);
6010 if (status < 0) 5971 if (status < 0)
6011 break; 5972 goto error;
6012 status = BLChainCmd(state, 0, 6, 100);
6013 if (status < 0)
6014 break;
6015 5973
6016 if (!state->microcode_name) 5974 /* Stop AUD and SCU */
6017 load_microcode(state, "drxk_a3.mc"); 5975 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6018 else 5976 if (status < 0)
6019 load_microcode(state, state->microcode_name); 5977 goto error;
5978 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
5979 if (status < 0)
5980 goto error;
6020 5981
6021 /* disable token-ring bus through OFDM block for possible ucode upload */ 5982 /* enable token-ring bus through OFDM block for possible ucode upload */
6022 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 5983 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6023 if (status < 0) 5984 if (status < 0)
6024 break; 5985 goto error;
6025 5986
6026 /* Run SCU for a little while to initialize microcode version numbers */ 5987 /* include boot loader section */
6027 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5988 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6028 if (status < 0) 5989 if (status < 0)
6029 break; 5990 goto error;
6030 status = DRXX_Open(state); 5991 status = BLChainCmd(state, 0, 6, 100);
6031 if (status < 0) 5992 if (status < 0)
6032 break; 5993 goto error;
6033 /* added for test */
6034 msleep(30);
6035 5994
6036 powerMode = DRXK_POWER_DOWN_OFDM; 5995 if (!state->microcode_name)
6037 status = CtrlPowerMode(state, &powerMode); 5996 load_microcode(state, "drxk_a3.mc");
6038 if (status < 0) 5997 else
6039 break; 5998 load_microcode(state, state->microcode_name);
6040 5999
6041 /* Stamp driver version number in SCU data RAM in BCD code 6000 /* disable token-ring bus through OFDM block for possible ucode upload */
6042 Done to enable field application engineers to retreive drxdriver version 6001 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6043 via I2C from SCU RAM. 6002 if (status < 0)
6044 Not using SCU command interface for SCU register access since no 6003 goto error;
6045 microcode may be present.
6046 */
6047 driverVersion =
6048 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6049 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6050 ((DRXK_VERSION_MAJOR % 10) << 4) +
6051 (DRXK_VERSION_MINOR % 10);
6052 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6053 if (status < 0)
6054 break;
6055 driverVersion =
6056 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6057 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6058 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6059 (DRXK_VERSION_PATCH % 10);
6060 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6061 if (status < 0)
6062 break;
6063 6004
6064 printk(KERN_INFO "DRXK driver version %d.%d.%d\n", 6005 /* Run SCU for a little while to initialize microcode version numbers */
6065 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 6006 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6066 DRXK_VERSION_PATCH); 6007 if (status < 0)
6008 goto error;
6009 status = DRXX_Open(state);
6010 if (status < 0)
6011 goto error;
6012 /* added for test */
6013 msleep(30);
6067 6014
6068 /* Dirty fix of default values for ROM/PATCH microcode 6015 powerMode = DRXK_POWER_DOWN_OFDM;
6069 Dirty because this fix makes it impossible to setup suitable values 6016 status = CtrlPowerMode(state, &powerMode);
6070 before calling DRX_Open. This solution requires changes to RF AGC speed 6017 if (status < 0)
6071 to be done via the CTRL function after calling DRX_Open */ 6018 goto error;
6019
6020 /* Stamp driver version number in SCU data RAM in BCD code
6021 Done to enable field application engineers to retreive drxdriver version
6022 via I2C from SCU RAM.
6023 Not using SCU command interface for SCU register access since no
6024 microcode may be present.
6025 */
6026 driverVersion =
6027 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6028 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6029 ((DRXK_VERSION_MAJOR % 10) << 4) +
6030 (DRXK_VERSION_MINOR % 10);
6031 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6032 if (status < 0)
6033 goto error;
6034 driverVersion =
6035 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6036 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6037 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6038 (DRXK_VERSION_PATCH % 10);
6039 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6040 if (status < 0)
6041 goto error;
6042
6043 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6044 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6045 DRXK_VERSION_PATCH);
6046
6047 /* Dirty fix of default values for ROM/PATCH microcode
6048 Dirty because this fix makes it impossible to setup suitable values
6049 before calling DRX_Open. This solution requires changes to RF AGC speed
6050 to be done via the CTRL function after calling DRX_Open */
6051
6052 /* m_dvbtRfAgcCfg.speed = 3; */
6053
6054 /* Reset driver debug flags to 0 */
6055 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6056 if (status < 0)
6057 goto error;
6058 /* driver 0.9.0 */
6059 /* Setup FEC OC:
6060 NOTE: No more full FEC resets allowed afterwards!! */
6061 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6062 if (status < 0)
6063 goto error;
6064 /* MPEGTS functions are still the same */
6065 status = MPEGTSDtoInit(state);
6066 if (status < 0)
6067 goto error;
6068 status = MPEGTSStop(state);
6069 if (status < 0)
6070 goto error;
6071 status = MPEGTSConfigurePolarity(state);
6072 if (status < 0)
6073 goto error;
6074 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6075 if (status < 0)
6076 goto error;
6077 /* added: configure GPIO */
6078 status = WriteGPIO(state);
6079 if (status < 0)
6080 goto error;
6072 6081
6073 /* m_dvbtRfAgcCfg.speed = 3; */ 6082 state->m_DrxkState = DRXK_STOPPED;
6074 6083
6075 /* Reset driver debug flags to 0 */ 6084 if (state->m_bPowerDown) {
6076 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6085 status = PowerDownDevice(state);
6077 if (status < 0)
6078 break;
6079 /* driver 0.9.0 */
6080 /* Setup FEC OC:
6081 NOTE: No more full FEC resets allowed afterwards!! */
6082 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6083 if (status < 0)
6084 break;
6085 /* MPEGTS functions are still the same */
6086 status = MPEGTSDtoInit(state);
6087 if (status < 0)
6088 break;
6089 status = MPEGTSStop(state);
6090 if (status < 0) 6086 if (status < 0)
6091 break; 6087 goto error;
6092 status = MPEGTSConfigurePolarity(state); 6088 state->m_DrxkState = DRXK_POWERED_DOWN;
6093 if (status < 0) 6089 } else
6094 break;
6095 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6096 if (status < 0)
6097 break;
6098 /* added: configure GPIO */
6099 status = WriteGPIO(state);
6100 if (status < 0)
6101 break;
6102
6103 state->m_DrxkState = DRXK_STOPPED; 6090 state->m_DrxkState = DRXK_STOPPED;
6104
6105 if (state->m_bPowerDown) {
6106 status = PowerDownDevice(state);
6107 if (status < 0)
6108 break;
6109 state->m_DrxkState = DRXK_POWERED_DOWN;
6110 } else
6111 state->m_DrxkState = DRXK_STOPPED;
6112 } while (0);
6113 } 6091 }
6092error:
6093 if (status < 0)
6094 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6114 6095
6115 return 0; 6096 return 0;
6116} 6097}
@@ -6210,7 +6191,7 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe,
6210 u16 *strength) 6191 u16 *strength)
6211{ 6192{
6212 struct drxk_state *state = fe->demodulator_priv; 6193 struct drxk_state *state = fe->demodulator_priv;
6213 u32 val; 6194 u32 val = 0;
6214 6195
6215 dprintk(1, "\n"); 6196 dprintk(1, "\n");
6216 ReadIFAgc(state, &val); 6197 ReadIFAgc(state, &val);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 16:24:32 -0400