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authorDevin Heitmueller <dheitmueller@kernellabs.com>2010-06-27 17:01:40 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-12-29 05:16:34 -0500
commitd2c194ce4781d62bf671aa6b65a2fccb39feb50e (patch)
treea398a8d8b6f5a225ff925614ce907d78377781d5 /drivers/media/dvb/frontends/au8522_decoder.c
parent2428a2ed6a7cbc7be6db5c70c3838a4bf0de9f48 (diff)
[media] au8522: fix clamp control for different video modes
Straighten out the clamp control configurations for the various video modes, based off of register diffs done against the Hauppauge Windows driver. This work was sponsored by GetWellNetwork Inc. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends/au8522_decoder.c')
-rw-r--r--drivers/media/dvb/frontends/au8522_decoder.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c
index 55b12ceb3ebc..5ec869706409 100644
--- a/drivers/media/dvb/frontends/au8522_decoder.c
+++ b/drivers/media/dvb/frontends/au8522_decoder.c
@@ -347,9 +347,11 @@ static void au8522_setup_cvbs_mode(struct au8522_state *state)
347 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, 347 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
348 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS); 348 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
349 349
350 /* PGA in automatic mode */
350 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); 351 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
351 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e); 352
352 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10); 353 /* Enable clamping control */
354 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
353 355
354 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, 356 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
355 AU8522_INPUT_CONTROL_REG081H_CVBS_CH1); 357 AU8522_INPUT_CONTROL_REG081H_CVBS_CH1);
@@ -366,14 +368,14 @@ static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state)
366 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H, 368 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
367 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS); 369 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
368 370
369 /* It's not clear why they turn off the PGA before enabling the clamp 371 /* It's not clear why we have to have the PGA in automatic mode while
370 control, but the Windows trace does it so we will too... */ 372 enabling clamp control, but it's what Windows does */
371 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00); 373 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
372 374
373 /* Enable clamping control */ 375 /* Enable clamping control */
374 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e); 376 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
375 377
376 /* Turn on the PGA */ 378 /* Disable automatic PGA (since the CVBS is coming from the tuner) */
377 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10); 379 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
378 380
379 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */ 381 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
@@ -396,7 +398,10 @@ static void au8522_setup_svideo_mode(struct au8522_state *state)
396 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, 398 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
397 AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13); 399 AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13);
398 400
399 /* Disable clamping control (required for S-video) */ 401 /* PGA in automatic mode */
402 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
403
404 /* Enable clamping control */
400 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00); 405 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
401 406
402 setup_decoder_defaults(state, 407 setup_decoder_defaults(state,