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authorMauro Carvalho Chehab <mchehab@redhat.com>2013-04-28 10:47:44 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2013-06-08 21:04:23 -0400
commitcd7a67a4f18047ca7b8ce2f48b4c540d69c9b793 (patch)
tree4160c4df8f29c6ac0d6dcfce0ca73169f7aaedc7 /drivers/media/dvb-frontends
parentb5e9eb6f529b5741322d1981bb176785f115d446 (diff)
[media] drxk_hard: Don't use CamelCase
X-Patchwork-Delegate: mchehab@redhat.com Thare are lots of CamelCase warnings produced by checkpatch.pl. This weren't fixed at the time the driver got submitted due to the lack of manpower do to such cleanup. Now that I have one script that automates this task, cleans it. That makes the driver almost checkpatch-compliant, except for 80 column warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb-frontends')
-rw-r--r--drivers/media/dvb-frontends/drxk.h2
-rw-r--r--drivers/media/dvb-frontends/drxk_hard.c2558
-rw-r--r--drivers/media/dvb-frontends/drxk_hard.h248
3 files changed, 1404 insertions, 1404 deletions
diff --git a/drivers/media/dvb-frontends/drxk.h b/drivers/media/dvb-frontends/drxk.h
index e6667189ddce..f22eb9f13ad5 100644
--- a/drivers/media/dvb-frontends/drxk.h
+++ b/drivers/media/dvb-frontends/drxk.h
@@ -8,7 +8,7 @@
8/** 8/**
9 * struct drxk_config - Configure the initial parameters for DRX-K 9 * struct drxk_config - Configure the initial parameters for DRX-K
10 * 10 *
11 * @adr: I2C Address of the DRX-K 11 * @adr: I2C address of the DRX-K
12 * @parallel_ts: True means that the device uses parallel TS, 12 * @parallel_ts: True means that the device uses parallel TS,
13 * Serial otherwise. 13 * Serial otherwise.
14 * @dynamic_clk: True means that the clock will be dynamically 14 * @dynamic_clk: True means that the clock will be dynamically
diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c
index 41b637534ed4..d2b331a46a6d 100644
--- a/drivers/media/dvb-frontends/drxk_hard.c
+++ b/drivers/media/dvb-frontends/drxk_hard.c
@@ -36,34 +36,34 @@
36#include "drxk_hard.h" 36#include "drxk_hard.h"
37#include "dvb_math.h" 37#include "dvb_math.h"
38 38
39static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); 39static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
40static int PowerDownQAM(struct drxk_state *state); 40static int power_down_qam(struct drxk_state *state);
41static int SetDVBTStandard(struct drxk_state *state, 41static int set_dvbt_standard(struct drxk_state *state,
42 enum OperationMode oMode); 42 enum operation_mode o_mode);
43static int SetQAMStandard(struct drxk_state *state, 43static int set_qam_standard(struct drxk_state *state,
44 enum OperationMode oMode); 44 enum operation_mode o_mode);
45static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, 45static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
46 s32 tunerFreqOffset); 46 s32 tuner_freq_offset);
47static int SetDVBTStandard(struct drxk_state *state, 47static int set_dvbt_standard(struct drxk_state *state,
48 enum OperationMode oMode); 48 enum operation_mode o_mode);
49static int DVBTStart(struct drxk_state *state); 49static int dvbt_start(struct drxk_state *state);
50static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, 50static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
51 s32 tunerFreqOffset); 51 s32 tuner_freq_offset);
52static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); 52static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
53static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); 53static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
54static int SwitchAntennaToQAM(struct drxk_state *state); 54static int switch_antenna_to_qam(struct drxk_state *state);
55static int SwitchAntennaToDVBT(struct drxk_state *state); 55static int switch_antenna_to_dvbt(struct drxk_state *state);
56 56
57static bool IsDVBT(struct drxk_state *state) 57static bool is_dvbt(struct drxk_state *state)
58{ 58{
59 return state->m_OperationMode == OM_DVBT; 59 return state->m_operation_mode == OM_DVBT;
60} 60}
61 61
62static bool IsQAM(struct drxk_state *state) 62static bool is_qam(struct drxk_state *state)
63{ 63{
64 return state->m_OperationMode == OM_QAM_ITU_A || 64 return state->m_operation_mode == OM_QAM_ITU_A ||
65 state->m_OperationMode == OM_QAM_ITU_B || 65 state->m_operation_mode == OM_QAM_ITU_B ||
66 state->m_OperationMode == OM_QAM_ITU_C; 66 state->m_operation_mode == OM_QAM_ITU_C;
67} 67}
68 68
69#define NOA1ROM 0 69#define NOA1ROM 0
@@ -432,55 +432,55 @@ static int write32(struct drxk_state *state, u32 reg, u32 data)
432 return write32_flags(state, reg, data, 0); 432 return write32_flags(state, reg, data, 0);
433} 433}
434 434
435static int write_block(struct drxk_state *state, u32 Address, 435static int write_block(struct drxk_state *state, u32 address,
436 const int BlockSize, const u8 pBlock[]) 436 const int block_size, const u8 p_block[])
437{ 437{
438 int status = 0, BlkSize = BlockSize; 438 int status = 0, blk_size = block_size;
439 u8 Flags = 0; 439 u8 flags = 0;
440 440
441 if (state->single_master) 441 if (state->single_master)
442 Flags |= 0xC0; 442 flags |= 0xC0;
443 443
444 while (BlkSize > 0) { 444 while (blk_size > 0) {
445 int Chunk = BlkSize > state->m_ChunkSize ? 445 int chunk = blk_size > state->m_chunk_size ?
446 state->m_ChunkSize : BlkSize; 446 state->m_chunk_size : blk_size;
447 u8 *AdrBuf = &state->Chunk[0]; 447 u8 *adr_buf = &state->chunk[0];
448 u32 AdrLength = 0; 448 u32 adr_length = 0;
449 449
450 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { 450 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
451 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); 451 adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
452 AdrBuf[1] = ((Address >> 16) & 0xFF); 452 adr_buf[1] = ((address >> 16) & 0xFF);
453 AdrBuf[2] = ((Address >> 24) & 0xFF); 453 adr_buf[2] = ((address >> 24) & 0xFF);
454 AdrBuf[3] = ((Address >> 7) & 0xFF); 454 adr_buf[3] = ((address >> 7) & 0xFF);
455 AdrBuf[2] |= Flags; 455 adr_buf[2] |= flags;
456 AdrLength = 4; 456 adr_length = 4;
457 if (Chunk == state->m_ChunkSize) 457 if (chunk == state->m_chunk_size)
458 Chunk -= 2; 458 chunk -= 2;
459 } else { 459 } else {
460 AdrBuf[0] = ((Address << 1) & 0xFF); 460 adr_buf[0] = ((address << 1) & 0xFF);
461 AdrBuf[1] = (((Address >> 16) & 0x0F) | 461 adr_buf[1] = (((address >> 16) & 0x0F) |
462 ((Address >> 18) & 0xF0)); 462 ((address >> 18) & 0xF0));
463 AdrLength = 2; 463 adr_length = 2;
464 } 464 }
465 memcpy(&state->Chunk[AdrLength], pBlock, Chunk); 465 memcpy(&state->chunk[adr_length], p_block, chunk);
466 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags); 466 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
467 if (debug > 1) { 467 if (debug > 1) {
468 int i; 468 int i;
469 if (pBlock) 469 if (p_block)
470 for (i = 0; i < Chunk; i++) 470 for (i = 0; i < chunk; i++)
471 printk(KERN_CONT " %02x", pBlock[i]); 471 printk(KERN_CONT " %02x", p_block[i]);
472 printk(KERN_CONT "\n"); 472 printk(KERN_CONT "\n");
473 } 473 }
474 status = i2c_write(state, state->demod_address, 474 status = i2c_write(state, state->demod_address,
475 &state->Chunk[0], Chunk + AdrLength); 475 &state->chunk[0], chunk + adr_length);
476 if (status < 0) { 476 if (status < 0) {
477 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n", 477 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
478 __func__, Address); 478 __func__, address);
479 break; 479 break;
480 } 480 }
481 pBlock += Chunk; 481 p_block += chunk;
482 Address += (Chunk >> 1); 482 address += (chunk >> 1);
483 BlkSize -= Chunk; 483 blk_size -= chunk;
484 } 484 }
485 return status; 485 return status;
486} 486}
@@ -489,11 +489,11 @@ static int write_block(struct drxk_state *state, u32 Address,
489#define DRXK_MAX_RETRIES_POWERUP 20 489#define DRXK_MAX_RETRIES_POWERUP 20
490#endif 490#endif
491 491
492static int PowerUpDevice(struct drxk_state *state) 492static int power_up_device(struct drxk_state *state)
493{ 493{
494 int status; 494 int status;
495 u8 data = 0; 495 u8 data = 0;
496 u16 retryCount = 0; 496 u16 retry_count = 0;
497 497
498 dprintk(1, "\n"); 498 dprintk(1, "\n");
499 499
@@ -504,14 +504,14 @@ static int PowerUpDevice(struct drxk_state *state)
504 status = i2c_write(state, state->demod_address, 504 status = i2c_write(state, state->demod_address,
505 &data, 1); 505 &data, 1);
506 msleep(10); 506 msleep(10);
507 retryCount++; 507 retry_count++;
508 if (status < 0) 508 if (status < 0)
509 continue; 509 continue;
510 status = i2c_read1(state, state->demod_address, 510 status = i2c_read1(state, state->demod_address,
511 &data); 511 &data);
512 } while (status < 0 && 512 } while (status < 0 &&
513 (retryCount < DRXK_MAX_RETRIES_POWERUP)); 513 (retry_count < DRXK_MAX_RETRIES_POWERUP));
514 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP) 514 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
515 goto error; 515 goto error;
516 } 516 }
517 517
@@ -527,7 +527,7 @@ static int PowerUpDevice(struct drxk_state *state)
527 if (status < 0) 527 if (status < 0)
528 goto error; 528 goto error;
529 529
530 state->m_currentPowerMode = DRX_POWER_UP; 530 state->m_current_power_mode = DRX_POWER_UP;
531 531
532error: 532error:
533 if (status < 0) 533 if (status < 0)
@@ -543,106 +543,106 @@ static int init_state(struct drxk_state *state)
543 * FIXME: most (all?) of the values bellow should be moved into 543 * FIXME: most (all?) of the values bellow should be moved into
544 * struct drxk_config, as they are probably board-specific 544 * struct drxk_config, as they are probably board-specific
545 */ 545 */
546 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; 546 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
547 u32 ulVSBIfAgcOutputLevel = 0; 547 u32 ul_vsb_if_agc_output_level = 0;
548 u32 ulVSBIfAgcMinLevel = 0; 548 u32 ul_vsb_if_agc_min_level = 0;
549 u32 ulVSBIfAgcMaxLevel = 0x7FFF; 549 u32 ul_vsb_if_agc_max_level = 0x7FFF;
550 u32 ulVSBIfAgcSpeed = 3; 550 u32 ul_vsb_if_agc_speed = 3;
551 551
552 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; 552 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
553 u32 ulVSBRfAgcOutputLevel = 0; 553 u32 ul_vsb_rf_agc_output_level = 0;
554 u32 ulVSBRfAgcMinLevel = 0; 554 u32 ul_vsb_rf_agc_min_level = 0;
555 u32 ulVSBRfAgcMaxLevel = 0x7FFF; 555 u32 ul_vsb_rf_agc_max_level = 0x7FFF;
556 u32 ulVSBRfAgcSpeed = 3; 556 u32 ul_vsb_rf_agc_speed = 3;
557 u32 ulVSBRfAgcTop = 9500; 557 u32 ul_vsb_rf_agc_top = 9500;
558 u32 ulVSBRfAgcCutOffCurrent = 4000; 558 u32 ul_vsb_rf_agc_cut_off_current = 4000;
559 559
560 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; 560 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
561 u32 ulATVIfAgcOutputLevel = 0; 561 u32 ul_atv_if_agc_output_level = 0;
562 u32 ulATVIfAgcMinLevel = 0; 562 u32 ul_atv_if_agc_min_level = 0;
563 u32 ulATVIfAgcMaxLevel = 0; 563 u32 ul_atv_if_agc_max_level = 0;
564 u32 ulATVIfAgcSpeed = 3; 564 u32 ul_atv_if_agc_speed = 3;
565 565
566 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; 566 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
567 u32 ulATVRfAgcOutputLevel = 0; 567 u32 ul_atv_rf_agc_output_level = 0;
568 u32 ulATVRfAgcMinLevel = 0; 568 u32 ul_atv_rf_agc_min_level = 0;
569 u32 ulATVRfAgcMaxLevel = 0; 569 u32 ul_atv_rf_agc_max_level = 0;
570 u32 ulATVRfAgcTop = 9500; 570 u32 ul_atv_rf_agc_top = 9500;
571 u32 ulATVRfAgcCutOffCurrent = 4000; 571 u32 ul_atv_rf_agc_cut_off_current = 4000;
572 u32 ulATVRfAgcSpeed = 3; 572 u32 ul_atv_rf_agc_speed = 3;
573 573
574 u32 ulQual83 = DEFAULT_MER_83; 574 u32 ulQual83 = DEFAULT_MER_83;
575 u32 ulQual93 = DEFAULT_MER_93; 575 u32 ulQual93 = DEFAULT_MER_93;
576 576
577 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 577 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
578 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 578 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
579 579
580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
581 /* io_pad_cfg_mode output mode is drive always */ 581 /* io_pad_cfg_mode output mode is drive always */
582 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 582 /* io_pad_cfg_drive is set to power 2 (23 mA) */
583 u32 ulGPIOCfg = 0x0113; 583 u32 ul_gpio_cfg = 0x0113;
584 u32 ulInvertTSClock = 0; 584 u32 ul_invert_ts_clock = 0;
585 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; 585 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
586 u32 ulDVBTBitrate = 50000000; 586 u32 ul_dvbt_bitrate = 50000000;
587 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; 587 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
588 588
589 u32 ulInsertRSByte = 0; 589 u32 ul_insert_rs_byte = 0;
590 590
591 u32 ulRfMirror = 1; 591 u32 ul_rf_mirror = 1;
592 u32 ulPowerDown = 0; 592 u32 ul_power_down = 0;
593 593
594 dprintk(1, "\n"); 594 dprintk(1, "\n");
595 595
596 state->m_hasLNA = false; 596 state->m_has_lna = false;
597 state->m_hasDVBT = false; 597 state->m_has_dvbt = false;
598 state->m_hasDVBC = false; 598 state->m_has_dvbc = false;
599 state->m_hasATV = false; 599 state->m_has_atv = false;
600 state->m_hasOOB = false; 600 state->m_has_oob = false;
601 state->m_hasAudio = false; 601 state->m_has_audio = false;
602 602
603 if (!state->m_ChunkSize) 603 if (!state->m_chunk_size)
604 state->m_ChunkSize = 124; 604 state->m_chunk_size = 124;
605 605
606 state->m_oscClockFreq = 0; 606 state->m_osc_clock_freq = 0;
607 state->m_smartAntInverted = false; 607 state->m_smart_ant_inverted = false;
608 state->m_bPDownOpenBridge = false; 608 state->m_b_p_down_open_bridge = false;
609 609
610 /* real system clock frequency in kHz */ 610 /* real system clock frequency in kHz */
611 state->m_sysClockFreq = 151875; 611 state->m_sys_clock_freq = 151875;
612 /* Timing div, 250ns/Psys */ 612 /* Timing div, 250ns/Psys */
613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ 613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
614 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * 614 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
615 HI_I2C_DELAY) / 1000; 615 HI_I2C_DELAY) / 1000;
616 /* Clipping */ 616 /* Clipping */
617 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) 617 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
618 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; 618 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
619 state->m_HICfgWakeUpKey = (state->demod_address << 1); 619 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
620 /* port/bridge/power down ctrl */ 620 /* port/bridge/power down ctrl */
621 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 621 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
622 622
623 state->m_bPowerDown = (ulPowerDown != 0); 623 state->m_b_power_down = (ul_power_down != 0);
624 624
625 state->m_DRXK_A3_PATCH_CODE = false; 625 state->m_drxk_a3_patch_code = false;
626 626
627 /* Init AGC and PGA parameters */ 627 /* Init AGC and PGA parameters */
628 /* VSB IF */ 628 /* VSB IF */
629 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); 629 state->m_vsb_if_agc_cfg.ctrl_mode = (ul_vsb_if_agc_mode);
630 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); 630 state->m_vsb_if_agc_cfg.output_level = (ul_vsb_if_agc_output_level);
631 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); 631 state->m_vsb_if_agc_cfg.min_output_level = (ul_vsb_if_agc_min_level);
632 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); 632 state->m_vsb_if_agc_cfg.max_output_level = (ul_vsb_if_agc_max_level);
633 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); 633 state->m_vsb_if_agc_cfg.speed = (ul_vsb_if_agc_speed);
634 state->m_vsbPgaCfg = 140; 634 state->m_vsb_pga_cfg = 140;
635 635
636 /* VSB RF */ 636 /* VSB RF */
637 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); 637 state->m_vsb_rf_agc_cfg.ctrl_mode = (ul_vsb_rf_agc_mode);
638 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); 638 state->m_vsb_rf_agc_cfg.output_level = (ul_vsb_rf_agc_output_level);
639 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); 639 state->m_vsb_rf_agc_cfg.min_output_level = (ul_vsb_rf_agc_min_level);
640 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); 640 state->m_vsb_rf_agc_cfg.max_output_level = (ul_vsb_rf_agc_max_level);
641 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); 641 state->m_vsb_rf_agc_cfg.speed = (ul_vsb_rf_agc_speed);
642 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); 642 state->m_vsb_rf_agc_cfg.top = (ul_vsb_rf_agc_top);
643 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); 643 state->m_vsb_rf_agc_cfg.cut_off_current = (ul_vsb_rf_agc_cut_off_current);
644 state->m_vsbPreSawCfg.reference = 0x07; 644 state->m_vsb_pre_saw_cfg.reference = 0x07;
645 state->m_vsbPreSawCfg.usePreSaw = true; 645 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
646 646
647 state->m_Quality83percent = DEFAULT_MER_83; 647 state->m_Quality83percent = DEFAULT_MER_83;
648 state->m_Quality93percent = DEFAULT_MER_93; 648 state->m_Quality93percent = DEFAULT_MER_93;
@@ -652,127 +652,127 @@ static int init_state(struct drxk_state *state)
652 } 652 }
653 653
654 /* ATV IF */ 654 /* ATV IF */
655 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); 655 state->m_atv_if_agc_cfg.ctrl_mode = (ul_atv_if_agc_mode);
656 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); 656 state->m_atv_if_agc_cfg.output_level = (ul_atv_if_agc_output_level);
657 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); 657 state->m_atv_if_agc_cfg.min_output_level = (ul_atv_if_agc_min_level);
658 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); 658 state->m_atv_if_agc_cfg.max_output_level = (ul_atv_if_agc_max_level);
659 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); 659 state->m_atv_if_agc_cfg.speed = (ul_atv_if_agc_speed);
660 660
661 /* ATV RF */ 661 /* ATV RF */
662 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); 662 state->m_atv_rf_agc_cfg.ctrl_mode = (ul_atv_rf_agc_mode);
663 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); 663 state->m_atv_rf_agc_cfg.output_level = (ul_atv_rf_agc_output_level);
664 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); 664 state->m_atv_rf_agc_cfg.min_output_level = (ul_atv_rf_agc_min_level);
665 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); 665 state->m_atv_rf_agc_cfg.max_output_level = (ul_atv_rf_agc_max_level);
666 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); 666 state->m_atv_rf_agc_cfg.speed = (ul_atv_rf_agc_speed);
667 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); 667 state->m_atv_rf_agc_cfg.top = (ul_atv_rf_agc_top);
668 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); 668 state->m_atv_rf_agc_cfg.cut_off_current = (ul_atv_rf_agc_cut_off_current);
669 state->m_atvPreSawCfg.reference = 0x04; 669 state->m_atv_pre_saw_cfg.reference = 0x04;
670 state->m_atvPreSawCfg.usePreSaw = true; 670 state->m_atv_pre_saw_cfg.use_pre_saw = true;
671 671
672 672
673 /* DVBT RF */ 673 /* DVBT RF */
674 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; 674 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
675 state->m_dvbtRfAgcCfg.outputLevel = 0; 675 state->m_dvbt_rf_agc_cfg.output_level = 0;
676 state->m_dvbtRfAgcCfg.minOutputLevel = 0; 676 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
677 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; 677 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
678 state->m_dvbtRfAgcCfg.top = 0x2100; 678 state->m_dvbt_rf_agc_cfg.top = 0x2100;
679 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; 679 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
680 state->m_dvbtRfAgcCfg.speed = 1; 680 state->m_dvbt_rf_agc_cfg.speed = 1;
681 681
682 682
683 /* DVBT IF */ 683 /* DVBT IF */
684 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; 684 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
685 state->m_dvbtIfAgcCfg.outputLevel = 0; 685 state->m_dvbt_if_agc_cfg.output_level = 0;
686 state->m_dvbtIfAgcCfg.minOutputLevel = 0; 686 state->m_dvbt_if_agc_cfg.min_output_level = 0;
687 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; 687 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
688 state->m_dvbtIfAgcCfg.top = 13424; 688 state->m_dvbt_if_agc_cfg.top = 13424;
689 state->m_dvbtIfAgcCfg.cutOffCurrent = 0; 689 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
690 state->m_dvbtIfAgcCfg.speed = 3; 690 state->m_dvbt_if_agc_cfg.speed = 3;
691 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; 691 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
692 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; 692 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
693 /* state->m_dvbtPgaCfg = 140; */ 693 /* state->m_dvbtPgaCfg = 140; */
694 694
695 state->m_dvbtPreSawCfg.reference = 4; 695 state->m_dvbt_pre_saw_cfg.reference = 4;
696 state->m_dvbtPreSawCfg.usePreSaw = false; 696 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
697 697
698 /* QAM RF */ 698 /* QAM RF */
699 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; 699 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
700 state->m_qamRfAgcCfg.outputLevel = 0; 700 state->m_qam_rf_agc_cfg.output_level = 0;
701 state->m_qamRfAgcCfg.minOutputLevel = 6023; 701 state->m_qam_rf_agc_cfg.min_output_level = 6023;
702 state->m_qamRfAgcCfg.maxOutputLevel = 27000; 702 state->m_qam_rf_agc_cfg.max_output_level = 27000;
703 state->m_qamRfAgcCfg.top = 0x2380; 703 state->m_qam_rf_agc_cfg.top = 0x2380;
704 state->m_qamRfAgcCfg.cutOffCurrent = 4000; 704 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
705 state->m_qamRfAgcCfg.speed = 3; 705 state->m_qam_rf_agc_cfg.speed = 3;
706 706
707 /* QAM IF */ 707 /* QAM IF */
708 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; 708 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
709 state->m_qamIfAgcCfg.outputLevel = 0; 709 state->m_qam_if_agc_cfg.output_level = 0;
710 state->m_qamIfAgcCfg.minOutputLevel = 0; 710 state->m_qam_if_agc_cfg.min_output_level = 0;
711 state->m_qamIfAgcCfg.maxOutputLevel = 9000; 711 state->m_qam_if_agc_cfg.max_output_level = 9000;
712 state->m_qamIfAgcCfg.top = 0x0511; 712 state->m_qam_if_agc_cfg.top = 0x0511;
713 state->m_qamIfAgcCfg.cutOffCurrent = 0; 713 state->m_qam_if_agc_cfg.cut_off_current = 0;
714 state->m_qamIfAgcCfg.speed = 3; 714 state->m_qam_if_agc_cfg.speed = 3;
715 state->m_qamIfAgcCfg.IngainTgtMax = 5119; 715 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
716 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; 716 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
717 717
718 state->m_qamPgaCfg = 140; 718 state->m_qam_pga_cfg = 140;
719 state->m_qamPreSawCfg.reference = 4; 719 state->m_qam_pre_saw_cfg.reference = 4;
720 state->m_qamPreSawCfg.usePreSaw = false; 720 state->m_qam_pre_saw_cfg.use_pre_saw = false;
721 721
722 state->m_OperationMode = OM_NONE; 722 state->m_operation_mode = OM_NONE;
723 state->m_DrxkState = DRXK_UNINITIALIZED; 723 state->m_drxk_state = DRXK_UNINITIALIZED;
724 724
725 /* MPEG output configuration */ 725 /* MPEG output configuration */
726 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ 726 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */
727 state->m_insertRSByte = false; /* If TRUE; insert RS byte */ 727 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
728 state->m_invertDATA = false; /* If TRUE; invert DATA signals */ 728 state->m_invert_data = false; /* If TRUE; invert DATA signals */
729 state->m_invertERR = false; /* If TRUE; invert ERR signal */ 729 state->m_invert_err = false; /* If TRUE; invert ERR signal */
730 state->m_invertSTR = false; /* If TRUE; invert STR signals */ 730 state->m_invert_str = false; /* If TRUE; invert STR signals */
731 state->m_invertVAL = false; /* If TRUE; invert VAL signals */ 731 state->m_invert_val = false; /* If TRUE; invert VAL signals */
732 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ 732 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
733 733
734 /* If TRUE; static MPEG clockrate will be used; 734 /* If TRUE; static MPEG clockrate will be used;
735 otherwise clockrate will adapt to the bitrate of the TS */ 735 otherwise clockrate will adapt to the bitrate of the TS */
736 736
737 state->m_DVBTBitrate = ulDVBTBitrate; 737 state->m_dvbt_bitrate = ul_dvbt_bitrate;
738 state->m_DVBCBitrate = ulDVBCBitrate; 738 state->m_dvbc_bitrate = ul_dvbc_bitrate;
739 739
740 state->m_TSDataStrength = (ulTSDataStrength & 0x07); 740 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
741 741
742 /* Maximum bitrate in b/s in case static clockrate is selected */ 742 /* Maximum bitrate in b/s in case static clockrate is selected */
743 state->m_mpegTsStaticBitrate = 19392658; 743 state->m_mpeg_ts_static_bitrate = 19392658;
744 state->m_disableTEIhandling = false; 744 state->m_disable_te_ihandling = false;
745 745
746 if (ulInsertRSByte) 746 if (ul_insert_rs_byte)
747 state->m_insertRSByte = true; 747 state->m_insert_rs_byte = true;
748 748
749 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 749 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
750 if (ulMpegLockTimeOut < 10000) 750 if (ul_mpeg_lock_time_out < 10000)
751 state->m_MpegLockTimeOut = ulMpegLockTimeOut; 751 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
752 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 752 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
753 if (ulDemodLockTimeOut < 10000) 753 if (ul_demod_lock_time_out < 10000)
754 state->m_DemodLockTimeOut = ulDemodLockTimeOut; 754 state->m_demod_lock_time_out = ul_demod_lock_time_out;
755 755
756 /* QAM defaults */ 756 /* QAM defaults */
757 state->m_Constellation = DRX_CONSTELLATION_AUTO; 757 state->m_constellation = DRX_CONSTELLATION_AUTO;
758 state->m_qamInterleaveMode = DRXK_QAM_I12_J17; 758 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
759 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ 759 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
760 state->m_fecRsPrescale = 1; 760 state->m_fec_rs_prescale = 1;
761 761
762 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; 762 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
763 state->m_agcFastClipCtrlDelay = 0; 763 state->m_agcfast_clip_ctrl_delay = 0;
764 764
765 state->m_GPIOCfg = (ulGPIOCfg); 765 state->m_gpio_cfg = (ul_gpio_cfg);
766 766
767 state->m_bPowerDown = false; 767 state->m_b_power_down = false;
768 state->m_currentPowerMode = DRX_POWER_DOWN; 768 state->m_current_power_mode = DRX_POWER_DOWN;
769 769
770 state->m_rfmirror = (ulRfMirror == 0); 770 state->m_rfmirror = (ul_rf_mirror == 0);
771 state->m_IfAgcPol = false; 771 state->m_if_agc_pol = false;
772 return 0; 772 return 0;
773} 773}
774 774
775static int DRXX_Open(struct drxk_state *state) 775static int drxx_open(struct drxk_state *state)
776{ 776{
777 int status = 0; 777 int status = 0;
778 u32 jtag = 0; 778 u32 jtag = 0;
@@ -804,10 +804,10 @@ error:
804 return status; 804 return status;
805} 805}
806 806
807static int GetDeviceCapabilities(struct drxk_state *state) 807static int get_device_capabilities(struct drxk_state *state)
808{ 808{
809 u16 sioPdrOhwCfg = 0; 809 u16 sio_pdr_ohw_cfg = 0;
810 u32 sioTopJtagidLo = 0; 810 u32 sio_top_jtagid_lo = 0;
811 int status; 811 int status;
812 const char *spin = ""; 812 const char *spin = "";
813 813
@@ -821,28 +821,28 @@ static int GetDeviceCapabilities(struct drxk_state *state)
821 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 821 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
822 if (status < 0) 822 if (status < 0)
823 goto error; 823 goto error;
824 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); 824 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
825 if (status < 0) 825 if (status < 0)
826 goto error; 826 goto error;
827 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 827 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
828 if (status < 0) 828 if (status < 0)
829 goto error; 829 goto error;
830 830
831 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 831 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
832 case 0: 832 case 0:
833 /* ignore (bypass ?) */ 833 /* ignore (bypass ?) */
834 break; 834 break;
835 case 1: 835 case 1:
836 /* 27 MHz */ 836 /* 27 MHz */
837 state->m_oscClockFreq = 27000; 837 state->m_osc_clock_freq = 27000;
838 break; 838 break;
839 case 2: 839 case 2:
840 /* 20.25 MHz */ 840 /* 20.25 MHz */
841 state->m_oscClockFreq = 20250; 841 state->m_osc_clock_freq = 20250;
842 break; 842 break;
843 case 3: 843 case 3:
844 /* 4 MHz */ 844 /* 4 MHz */
845 state->m_oscClockFreq = 20250; 845 state->m_osc_clock_freq = 20250;
846 break; 846 break;
847 default: 847 default:
848 printk(KERN_ERR "drxk: Clock Frequency is unknown\n"); 848 printk(KERN_ERR "drxk: Clock Frequency is unknown\n");
@@ -852,150 +852,150 @@ static int GetDeviceCapabilities(struct drxk_state *state)
852 Determine device capabilities 852 Determine device capabilities
853 Based on pinning v14 853 Based on pinning v14
854 */ 854 */
855 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); 855 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
856 if (status < 0) 856 if (status < 0)
857 goto error; 857 goto error;
858 858
859 printk(KERN_INFO "drxk: status = 0x%08x\n", sioTopJtagidLo); 859 printk(KERN_INFO "drxk: status = 0x%08x\n", sio_top_jtagid_lo);
860 860
861 /* driver 0.9.0 */ 861 /* driver 0.9.0 */
862 switch ((sioTopJtagidLo >> 29) & 0xF) { 862 switch ((sio_top_jtagid_lo >> 29) & 0xF) {
863 case 0: 863 case 0:
864 state->m_deviceSpin = DRXK_SPIN_A1; 864 state->m_device_spin = DRXK_SPIN_A1;
865 spin = "A1"; 865 spin = "A1";
866 break; 866 break;
867 case 2: 867 case 2:
868 state->m_deviceSpin = DRXK_SPIN_A2; 868 state->m_device_spin = DRXK_SPIN_A2;
869 spin = "A2"; 869 spin = "A2";
870 break; 870 break;
871 case 3: 871 case 3:
872 state->m_deviceSpin = DRXK_SPIN_A3; 872 state->m_device_spin = DRXK_SPIN_A3;
873 spin = "A3"; 873 spin = "A3";
874 break; 874 break;
875 default: 875 default:
876 state->m_deviceSpin = DRXK_SPIN_UNKNOWN; 876 state->m_device_spin = DRXK_SPIN_UNKNOWN;
877 status = -EINVAL; 877 status = -EINVAL;
878 printk(KERN_ERR "drxk: Spin %d unknown\n", 878 printk(KERN_ERR "drxk: Spin %d unknown\n",
879 (sioTopJtagidLo >> 29) & 0xF); 879 (sio_top_jtagid_lo >> 29) & 0xF);
880 goto error2; 880 goto error2;
881 } 881 }
882 switch ((sioTopJtagidLo >> 12) & 0xFF) { 882 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
883 case 0x13: 883 case 0x13:
884 /* typeId = DRX3913K_TYPE_ID */ 884 /* typeId = DRX3913K_TYPE_ID */
885 state->m_hasLNA = false; 885 state->m_has_lna = false;
886 state->m_hasOOB = false; 886 state->m_has_oob = false;
887 state->m_hasATV = false; 887 state->m_has_atv = false;
888 state->m_hasAudio = false; 888 state->m_has_audio = false;
889 state->m_hasDVBT = true; 889 state->m_has_dvbt = true;
890 state->m_hasDVBC = true; 890 state->m_has_dvbc = true;
891 state->m_hasSAWSW = true; 891 state->m_has_sawsw = true;
892 state->m_hasGPIO2 = false; 892 state->m_has_gpio2 = false;
893 state->m_hasGPIO1 = false; 893 state->m_has_gpio1 = false;
894 state->m_hasIRQN = false; 894 state->m_has_irqn = false;
895 break; 895 break;
896 case 0x15: 896 case 0x15:
897 /* typeId = DRX3915K_TYPE_ID */ 897 /* typeId = DRX3915K_TYPE_ID */
898 state->m_hasLNA = false; 898 state->m_has_lna = false;
899 state->m_hasOOB = false; 899 state->m_has_oob = false;
900 state->m_hasATV = true; 900 state->m_has_atv = true;
901 state->m_hasAudio = false; 901 state->m_has_audio = false;
902 state->m_hasDVBT = true; 902 state->m_has_dvbt = true;
903 state->m_hasDVBC = false; 903 state->m_has_dvbc = false;
904 state->m_hasSAWSW = true; 904 state->m_has_sawsw = true;
905 state->m_hasGPIO2 = true; 905 state->m_has_gpio2 = true;
906 state->m_hasGPIO1 = true; 906 state->m_has_gpio1 = true;
907 state->m_hasIRQN = false; 907 state->m_has_irqn = false;
908 break; 908 break;
909 case 0x16: 909 case 0x16:
910 /* typeId = DRX3916K_TYPE_ID */ 910 /* typeId = DRX3916K_TYPE_ID */
911 state->m_hasLNA = false; 911 state->m_has_lna = false;
912 state->m_hasOOB = false; 912 state->m_has_oob = false;
913 state->m_hasATV = true; 913 state->m_has_atv = true;
914 state->m_hasAudio = false; 914 state->m_has_audio = false;
915 state->m_hasDVBT = true; 915 state->m_has_dvbt = true;
916 state->m_hasDVBC = false; 916 state->m_has_dvbc = false;
917 state->m_hasSAWSW = true; 917 state->m_has_sawsw = true;
918 state->m_hasGPIO2 = true; 918 state->m_has_gpio2 = true;
919 state->m_hasGPIO1 = true; 919 state->m_has_gpio1 = true;
920 state->m_hasIRQN = false; 920 state->m_has_irqn = false;
921 break; 921 break;
922 case 0x18: 922 case 0x18:
923 /* typeId = DRX3918K_TYPE_ID */ 923 /* typeId = DRX3918K_TYPE_ID */
924 state->m_hasLNA = false; 924 state->m_has_lna = false;
925 state->m_hasOOB = false; 925 state->m_has_oob = false;
926 state->m_hasATV = true; 926 state->m_has_atv = true;
927 state->m_hasAudio = true; 927 state->m_has_audio = true;
928 state->m_hasDVBT = true; 928 state->m_has_dvbt = true;
929 state->m_hasDVBC = false; 929 state->m_has_dvbc = false;
930 state->m_hasSAWSW = true; 930 state->m_has_sawsw = true;
931 state->m_hasGPIO2 = true; 931 state->m_has_gpio2 = true;
932 state->m_hasGPIO1 = true; 932 state->m_has_gpio1 = true;
933 state->m_hasIRQN = false; 933 state->m_has_irqn = false;
934 break; 934 break;
935 case 0x21: 935 case 0x21:
936 /* typeId = DRX3921K_TYPE_ID */ 936 /* typeId = DRX3921K_TYPE_ID */
937 state->m_hasLNA = false; 937 state->m_has_lna = false;
938 state->m_hasOOB = false; 938 state->m_has_oob = false;
939 state->m_hasATV = true; 939 state->m_has_atv = true;
940 state->m_hasAudio = true; 940 state->m_has_audio = true;
941 state->m_hasDVBT = true; 941 state->m_has_dvbt = true;
942 state->m_hasDVBC = true; 942 state->m_has_dvbc = true;
943 state->m_hasSAWSW = true; 943 state->m_has_sawsw = true;
944 state->m_hasGPIO2 = true; 944 state->m_has_gpio2 = true;
945 state->m_hasGPIO1 = true; 945 state->m_has_gpio1 = true;
946 state->m_hasIRQN = false; 946 state->m_has_irqn = false;
947 break; 947 break;
948 case 0x23: 948 case 0x23:
949 /* typeId = DRX3923K_TYPE_ID */ 949 /* typeId = DRX3923K_TYPE_ID */
950 state->m_hasLNA = false; 950 state->m_has_lna = false;
951 state->m_hasOOB = false; 951 state->m_has_oob = false;
952 state->m_hasATV = true; 952 state->m_has_atv = true;
953 state->m_hasAudio = true; 953 state->m_has_audio = true;
954 state->m_hasDVBT = true; 954 state->m_has_dvbt = true;
955 state->m_hasDVBC = true; 955 state->m_has_dvbc = true;
956 state->m_hasSAWSW = true; 956 state->m_has_sawsw = true;
957 state->m_hasGPIO2 = true; 957 state->m_has_gpio2 = true;
958 state->m_hasGPIO1 = true; 958 state->m_has_gpio1 = true;
959 state->m_hasIRQN = false; 959 state->m_has_irqn = false;
960 break; 960 break;
961 case 0x25: 961 case 0x25:
962 /* typeId = DRX3925K_TYPE_ID */ 962 /* typeId = DRX3925K_TYPE_ID */
963 state->m_hasLNA = false; 963 state->m_has_lna = false;
964 state->m_hasOOB = false; 964 state->m_has_oob = false;
965 state->m_hasATV = true; 965 state->m_has_atv = true;
966 state->m_hasAudio = true; 966 state->m_has_audio = true;
967 state->m_hasDVBT = true; 967 state->m_has_dvbt = true;
968 state->m_hasDVBC = true; 968 state->m_has_dvbc = true;
969 state->m_hasSAWSW = true; 969 state->m_has_sawsw = true;
970 state->m_hasGPIO2 = true; 970 state->m_has_gpio2 = true;
971 state->m_hasGPIO1 = true; 971 state->m_has_gpio1 = true;
972 state->m_hasIRQN = false; 972 state->m_has_irqn = false;
973 break; 973 break;
974 case 0x26: 974 case 0x26:
975 /* typeId = DRX3926K_TYPE_ID */ 975 /* typeId = DRX3926K_TYPE_ID */
976 state->m_hasLNA = false; 976 state->m_has_lna = false;
977 state->m_hasOOB = false; 977 state->m_has_oob = false;
978 state->m_hasATV = true; 978 state->m_has_atv = true;
979 state->m_hasAudio = false; 979 state->m_has_audio = false;
980 state->m_hasDVBT = true; 980 state->m_has_dvbt = true;
981 state->m_hasDVBC = true; 981 state->m_has_dvbc = true;
982 state->m_hasSAWSW = true; 982 state->m_has_sawsw = true;
983 state->m_hasGPIO2 = true; 983 state->m_has_gpio2 = true;
984 state->m_hasGPIO1 = true; 984 state->m_has_gpio1 = true;
985 state->m_hasIRQN = false; 985 state->m_has_irqn = false;
986 break; 986 break;
987 default: 987 default:
988 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n", 988 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
989 ((sioTopJtagidLo >> 12) & 0xFF)); 989 ((sio_top_jtagid_lo >> 12) & 0xFF));
990 status = -EINVAL; 990 status = -EINVAL;
991 goto error2; 991 goto error2;
992 } 992 }
993 993
994 printk(KERN_INFO 994 printk(KERN_INFO
995 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", 995 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
996 ((sioTopJtagidLo >> 12) & 0xFF), spin, 996 ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
997 state->m_oscClockFreq / 1000, 997 state->m_osc_clock_freq / 1000,
998 state->m_oscClockFreq % 1000); 998 state->m_osc_clock_freq % 1000);
999 999
1000error: 1000error:
1001 if (status < 0) 1001 if (status < 0)
@@ -1005,7 +1005,7 @@ error2:
1005 return status; 1005 return status;
1006} 1006}
1007 1007
1008static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) 1008static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
1009{ 1009{
1010 int status; 1010 int status;
1011 bool powerdown_cmd; 1011 bool powerdown_cmd;
@@ -1021,24 +1021,24 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1021 1021
1022 powerdown_cmd = 1022 powerdown_cmd =
1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && 1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1024 ((state->m_HICfgCtrl) & 1024 ((state->m_hi_cfg_ctrl) &
1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == 1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); 1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1027 if (powerdown_cmd == false) { 1027 if (powerdown_cmd == false) {
1028 /* Wait until command rdy */ 1028 /* Wait until command rdy */
1029 u32 retryCount = 0; 1029 u32 retry_count = 0;
1030 u16 waitCmd; 1030 u16 wait_cmd;
1031 1031
1032 do { 1032 do {
1033 msleep(1); 1033 msleep(1);
1034 retryCount += 1; 1034 retry_count += 1;
1035 status = read16(state, SIO_HI_RA_RAM_CMD__A, 1035 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1036 &waitCmd); 1036 &wait_cmd);
1037 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) 1037 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1038 && (waitCmd != 0)); 1038 && (wait_cmd != 0));
1039 if (status < 0) 1039 if (status < 0)
1040 goto error; 1040 goto error;
1041 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); 1041 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1042 } 1042 }
1043error: 1043error:
1044 if (status < 0) 1044 if (status < 0)
@@ -1047,7 +1047,7 @@ error:
1047 return status; 1047 return status;
1048} 1048}
1049 1049
1050static int HI_CfgCommand(struct drxk_state *state) 1050static int hi_cfg_command(struct drxk_state *state)
1051{ 1051{
1052 int status; 1052 int status;
1053 1053
@@ -1055,29 +1055,29 @@ static int HI_CfgCommand(struct drxk_state *state)
1055 1055
1056 mutex_lock(&state->mutex); 1056 mutex_lock(&state->mutex);
1057 1057
1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); 1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_hi_cfg_timeout);
1059 if (status < 0) 1059 if (status < 0)
1060 goto error; 1060 goto error;
1061 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); 1061 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_hi_cfg_ctrl);
1062 if (status < 0) 1062 if (status < 0)
1063 goto error; 1063 goto error;
1064 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); 1064 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_hi_cfg_wake_up_key);
1065 if (status < 0) 1065 if (status < 0)
1066 goto error; 1066 goto error;
1067 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); 1067 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_hi_cfg_bridge_delay);
1068 if (status < 0) 1068 if (status < 0)
1069 goto error; 1069 goto error;
1070 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); 1070 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_hi_cfg_timing_div);
1071 if (status < 0) 1071 if (status < 0)
1072 goto error; 1072 goto error;
1073 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1073 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1074 if (status < 0) 1074 if (status < 0)
1075 goto error; 1075 goto error;
1076 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); 1076 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1077 if (status < 0) 1077 if (status < 0)
1078 goto error; 1078 goto error;
1079 1079
1080 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1080 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1081error: 1081error:
1082 mutex_unlock(&state->mutex); 1082 mutex_unlock(&state->mutex);
1083 if (status < 0) 1083 if (status < 0)
@@ -1085,28 +1085,28 @@ error:
1085 return status; 1085 return status;
1086} 1086}
1087 1087
1088static int InitHI(struct drxk_state *state) 1088static int init_hi(struct drxk_state *state)
1089{ 1089{
1090 dprintk(1, "\n"); 1090 dprintk(1, "\n");
1091 1091
1092 state->m_HICfgWakeUpKey = (state->demod_address << 1); 1092 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1093 state->m_HICfgTimeout = 0x96FF; 1093 state->m_hi_cfg_timeout = 0x96FF;
1094 /* port/bridge/power down ctrl */ 1094 /* port/bridge/power down ctrl */
1095 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 1095 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1096 1096
1097 return HI_CfgCommand(state); 1097 return hi_cfg_command(state);
1098} 1098}
1099 1099
1100static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) 1100static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1101{ 1101{
1102 int status = -1; 1102 int status = -1;
1103 u16 sioPdrMclkCfg = 0; 1103 u16 sio_pdr_mclk_cfg = 0;
1104 u16 sioPdrMdxCfg = 0; 1104 u16 sio_pdr_mdx_cfg = 0;
1105 u16 err_cfg = 0; 1105 u16 err_cfg = 0;
1106 1106
1107 dprintk(1, ": mpeg %s, %s mode\n", 1107 dprintk(1, ": mpeg %s, %s mode\n",
1108 mpegEnable ? "enable" : "disable", 1108 mpeg_enable ? "enable" : "disable",
1109 state->m_enableParallel ? "parallel" : "serial"); 1109 state->m_enable_parallel ? "parallel" : "serial");
1110 1110
1111 /* stop lock indicator process */ 1111 /* stop lock indicator process */
1112 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1112 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
@@ -1118,7 +1118,7 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1118 if (status < 0) 1118 if (status < 0)
1119 goto error; 1119 goto error;
1120 1120
1121 if (mpegEnable == false) { 1121 if (mpeg_enable == false) {
1122 /* Set MPEG TS pads to inputmode */ 1122 /* Set MPEG TS pads to inputmode */
1123 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1123 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1124 if (status < 0) 1124 if (status < 0)
@@ -1158,19 +1158,19 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1158 goto error; 1158 goto error;
1159 } else { 1159 } else {
1160 /* Enable MPEG output */ 1160 /* Enable MPEG output */
1161 sioPdrMdxCfg = 1161 sio_pdr_mdx_cfg =
1162 ((state->m_TSDataStrength << 1162 ((state->m_ts_data_strength <<
1163 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); 1163 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1164 sioPdrMclkCfg = ((state->m_TSClockkStrength << 1164 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1165 SIO_PDR_MCLK_CFG_DRIVE__B) | 1165 SIO_PDR_MCLK_CFG_DRIVE__B) |
1166 0x0003); 1166 0x0003);
1167 1167
1168 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); 1168 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1169 if (status < 0) 1169 if (status < 0)
1170 goto error; 1170 goto error;
1171 1171
1172 if (state->enable_merr_cfg) 1172 if (state->enable_merr_cfg)
1173 err_cfg = sioPdrMdxCfg; 1173 err_cfg = sio_pdr_mdx_cfg;
1174 1174
1175 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); 1175 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1176 if (status < 0) 1176 if (status < 0)
@@ -1179,31 +1179,31 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1179 if (status < 0) 1179 if (status < 0)
1180 goto error; 1180 goto error;
1181 1181
1182 if (state->m_enableParallel == true) { 1182 if (state->m_enable_parallel == true) {
1183 /* paralel -> enable MD1 to MD7 */ 1183 /* paralel -> enable MD1 to MD7 */
1184 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); 1184 status = write16(state, SIO_PDR_MD1_CFG__A, sio_pdr_mdx_cfg);
1185 if (status < 0) 1185 if (status < 0)
1186 goto error; 1186 goto error;
1187 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); 1187 status = write16(state, SIO_PDR_MD2_CFG__A, sio_pdr_mdx_cfg);
1188 if (status < 0) 1188 if (status < 0)
1189 goto error; 1189 goto error;
1190 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); 1190 status = write16(state, SIO_PDR_MD3_CFG__A, sio_pdr_mdx_cfg);
1191 if (status < 0) 1191 if (status < 0)
1192 goto error; 1192 goto error;
1193 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); 1193 status = write16(state, SIO_PDR_MD4_CFG__A, sio_pdr_mdx_cfg);
1194 if (status < 0) 1194 if (status < 0)
1195 goto error; 1195 goto error;
1196 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); 1196 status = write16(state, SIO_PDR_MD5_CFG__A, sio_pdr_mdx_cfg);
1197 if (status < 0) 1197 if (status < 0)
1198 goto error; 1198 goto error;
1199 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); 1199 status = write16(state, SIO_PDR_MD6_CFG__A, sio_pdr_mdx_cfg);
1200 if (status < 0) 1200 if (status < 0)
1201 goto error; 1201 goto error;
1202 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); 1202 status = write16(state, SIO_PDR_MD7_CFG__A, sio_pdr_mdx_cfg);
1203 if (status < 0) 1203 if (status < 0)
1204 goto error; 1204 goto error;
1205 } else { 1205 } else {
1206 sioPdrMdxCfg = ((state->m_TSDataStrength << 1206 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1207 SIO_PDR_MD0_CFG_DRIVE__B) 1207 SIO_PDR_MD0_CFG_DRIVE__B)
1208 | 0x0003); 1208 | 0x0003);
1209 /* serial -> disable MD1 to MD7 */ 1209 /* serial -> disable MD1 to MD7 */
@@ -1229,10 +1229,10 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1229 if (status < 0) 1229 if (status < 0)
1230 goto error; 1230 goto error;
1231 } 1231 }
1232 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); 1232 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1233 if (status < 0) 1233 if (status < 0)
1234 goto error; 1234 goto error;
1235 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); 1235 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1236 if (status < 0) 1236 if (status < 0)
1237 goto error; 1237 goto error;
1238 } 1238 }
@@ -1248,17 +1248,17 @@ error:
1248 return status; 1248 return status;
1249} 1249}
1250 1250
1251static int MPEGTSDisable(struct drxk_state *state) 1251static int mpegts_disable(struct drxk_state *state)
1252{ 1252{
1253 dprintk(1, "\n"); 1253 dprintk(1, "\n");
1254 1254
1255 return MPEGTSConfigurePins(state, false); 1255 return mpegts_configure_pins(state, false);
1256} 1256}
1257 1257
1258static int BLChainCmd(struct drxk_state *state, 1258static int bl_chain_cmd(struct drxk_state *state,
1259 u16 romOffset, u16 nrOfElements, u32 timeOut) 1259 u16 rom_offset, u16 nr_of_elements, u32 time_out)
1260{ 1260{
1261 u16 blStatus = 0; 1261 u16 bl_status = 0;
1262 int status; 1262 int status;
1263 unsigned long end; 1263 unsigned long end;
1264 1264
@@ -1267,26 +1267,26 @@ static int BLChainCmd(struct drxk_state *state,
1267 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1267 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1268 if (status < 0) 1268 if (status < 0)
1269 goto error; 1269 goto error;
1270 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); 1270 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1271 if (status < 0) 1271 if (status < 0)
1272 goto error; 1272 goto error;
1273 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); 1273 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1274 if (status < 0) 1274 if (status < 0)
1275 goto error; 1275 goto error;
1276 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 1276 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1277 if (status < 0) 1277 if (status < 0)
1278 goto error; 1278 goto error;
1279 1279
1280 end = jiffies + msecs_to_jiffies(timeOut); 1280 end = jiffies + msecs_to_jiffies(time_out);
1281 do { 1281 do {
1282 msleep(1); 1282 msleep(1);
1283 status = read16(state, SIO_BL_STATUS__A, &blStatus); 1283 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1284 if (status < 0) 1284 if (status < 0)
1285 goto error; 1285 goto error;
1286 } while ((blStatus == 0x1) && 1286 } while ((bl_status == 0x1) &&
1287 ((time_is_after_jiffies(end)))); 1287 ((time_is_after_jiffies(end))));
1288 1288
1289 if (blStatus == 0x1) { 1289 if (bl_status == 0x1) {
1290 printk(KERN_ERR "drxk: SIO not ready\n"); 1290 printk(KERN_ERR "drxk: SIO not ready\n");
1291 status = -EINVAL; 1291 status = -EINVAL;
1292 goto error2; 1292 goto error2;
@@ -1300,13 +1300,13 @@ error2:
1300} 1300}
1301 1301
1302 1302
1303static int DownloadMicrocode(struct drxk_state *state, 1303static int download_microcode(struct drxk_state *state,
1304 const u8 pMCImage[], u32 Length) 1304 const u8 p_mc_image[], u32 length)
1305{ 1305{
1306 const u8 *pSrc = pMCImage; 1306 const u8 *p_src = p_mc_image;
1307 u32 Address; 1307 u32 address;
1308 u16 nBlocks; 1308 u16 n_blocks;
1309 u16 BlockSize; 1309 u16 block_size;
1310 u32 offset = 0; 1310 u32 offset = 0;
1311 u32 i; 1311 u32 i;
1312 int status = 0; 1312 int status = 0;
@@ -1316,114 +1316,114 @@ static int DownloadMicrocode(struct drxk_state *state,
1316 /* down the drain (we don't care about MAGIC_WORD) */ 1316 /* down the drain (we don't care about MAGIC_WORD) */
1317#if 0 1317#if 0
1318 /* For future reference */ 1318 /* For future reference */
1319 Drain = (pSrc[0] << 8) | pSrc[1]; 1319 drain = (p_src[0] << 8) | p_src[1];
1320#endif 1320#endif
1321 pSrc += sizeof(u16); 1321 p_src += sizeof(u16);
1322 offset += sizeof(u16); 1322 offset += sizeof(u16);
1323 nBlocks = (pSrc[0] << 8) | pSrc[1]; 1323 n_blocks = (p_src[0] << 8) | p_src[1];
1324 pSrc += sizeof(u16); 1324 p_src += sizeof(u16);
1325 offset += sizeof(u16); 1325 offset += sizeof(u16);
1326 1326
1327 for (i = 0; i < nBlocks; i += 1) { 1327 for (i = 0; i < n_blocks; i += 1) {
1328 Address = (pSrc[0] << 24) | (pSrc[1] << 16) | 1328 address = (p_src[0] << 24) | (p_src[1] << 16) |
1329 (pSrc[2] << 8) | pSrc[3]; 1329 (p_src[2] << 8) | p_src[3];
1330 pSrc += sizeof(u32); 1330 p_src += sizeof(u32);
1331 offset += sizeof(u32); 1331 offset += sizeof(u32);
1332 1332
1333 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); 1333 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1334 pSrc += sizeof(u16); 1334 p_src += sizeof(u16);
1335 offset += sizeof(u16); 1335 offset += sizeof(u16);
1336 1336
1337#if 0 1337#if 0
1338 /* For future reference */ 1338 /* For future reference */
1339 Flags = (pSrc[0] << 8) | pSrc[1]; 1339 flags = (p_src[0] << 8) | p_src[1];
1340#endif 1340#endif
1341 pSrc += sizeof(u16); 1341 p_src += sizeof(u16);
1342 offset += sizeof(u16); 1342 offset += sizeof(u16);
1343 1343
1344#if 0 1344#if 0
1345 /* For future reference */ 1345 /* For future reference */
1346 BlockCRC = (pSrc[0] << 8) | pSrc[1]; 1346 block_crc = (p_src[0] << 8) | p_src[1];
1347#endif 1347#endif
1348 pSrc += sizeof(u16); 1348 p_src += sizeof(u16);
1349 offset += sizeof(u16); 1349 offset += sizeof(u16);
1350 1350
1351 if (offset + BlockSize > Length) { 1351 if (offset + block_size > length) {
1352 printk(KERN_ERR "drxk: Firmware is corrupted.\n"); 1352 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1353 return -EINVAL; 1353 return -EINVAL;
1354 } 1354 }
1355 1355
1356 status = write_block(state, Address, BlockSize, pSrc); 1356 status = write_block(state, address, block_size, p_src);
1357 if (status < 0) { 1357 if (status < 0) {
1358 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status); 1358 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1359 break; 1359 break;
1360 } 1360 }
1361 pSrc += BlockSize; 1361 p_src += block_size;
1362 offset += BlockSize; 1362 offset += block_size;
1363 } 1363 }
1364 return status; 1364 return status;
1365} 1365}
1366 1366
1367static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) 1367static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1368{ 1368{
1369 int status; 1369 int status;
1370 u16 data = 0; 1370 u16 data = 0;
1371 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; 1371 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1372 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; 1372 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1373 unsigned long end; 1373 unsigned long end;
1374 1374
1375 dprintk(1, "\n"); 1375 dprintk(1, "\n");
1376 1376
1377 if (enable == false) { 1377 if (enable == false) {
1378 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; 1378 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1379 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1379 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1380 } 1380 }
1381 1381
1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1382 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383 if (status >= 0 && data == desiredStatus) { 1383 if (status >= 0 && data == desired_status) {
1384 /* tokenring already has correct status */ 1384 /* tokenring already has correct status */
1385 return status; 1385 return status;
1386 } 1386 }
1387 /* Disable/enable dvbt tokenring bridge */ 1387 /* Disable/enable dvbt tokenring bridge */
1388 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); 1388 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1389 1389
1390 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1390 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1391 do { 1391 do {
1392 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1392 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1393 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end)) 1393 if ((status >= 0 && data == desired_status) || time_is_after_jiffies(end))
1394 break; 1394 break;
1395 msleep(1); 1395 msleep(1);
1396 } while (1); 1396 } while (1);
1397 if (data != desiredStatus) { 1397 if (data != desired_status) {
1398 printk(KERN_ERR "drxk: SIO not ready\n"); 1398 printk(KERN_ERR "drxk: SIO not ready\n");
1399 return -EINVAL; 1399 return -EINVAL;
1400 } 1400 }
1401 return status; 1401 return status;
1402} 1402}
1403 1403
1404static int MPEGTSStop(struct drxk_state *state) 1404static int mpegts_stop(struct drxk_state *state)
1405{ 1405{
1406 int status = 0; 1406 int status = 0;
1407 u16 fecOcSncMode = 0; 1407 u16 fec_oc_snc_mode = 0;
1408 u16 fecOcIprMode = 0; 1408 u16 fec_oc_ipr_mode = 0;
1409 1409
1410 dprintk(1, "\n"); 1410 dprintk(1, "\n");
1411 1411
1412 /* Gracefull shutdown (byte boundaries) */ 1412 /* Gracefull shutdown (byte boundaries) */
1413 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1413 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1414 if (status < 0) 1414 if (status < 0)
1415 goto error; 1415 goto error;
1416 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1416 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1417 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1417 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1418 if (status < 0) 1418 if (status < 0)
1419 goto error; 1419 goto error;
1420 1420
1421 /* Suppress MCLK during absence of data */ 1421 /* Suppress MCLK during absence of data */
1422 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); 1422 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1423 if (status < 0) 1423 if (status < 0)
1424 goto error; 1424 goto error;
1425 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1425 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1426 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); 1426 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1427 1427
1428error: 1428error:
1429 if (status < 0) 1429 if (status < 0)
@@ -1433,13 +1433,13 @@ error:
1433} 1433}
1434 1434
1435static int scu_command(struct drxk_state *state, 1435static int scu_command(struct drxk_state *state,
1436 u16 cmd, u8 parameterLen, 1436 u16 cmd, u8 parameter_len,
1437 u16 *parameter, u8 resultLen, u16 *result) 1437 u16 *parameter, u8 result_len, u16 *result)
1438{ 1438{
1439#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 1439#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1440#error DRXK register mapping no longer compatible with this routine! 1440#error DRXK register mapping no longer compatible with this routine!
1441#endif 1441#endif
1442 u16 curCmd = 0; 1442 u16 cur_cmd = 0;
1443 int status = -EINVAL; 1443 int status = -EINVAL;
1444 unsigned long end; 1444 unsigned long end;
1445 u8 buffer[34]; 1445 u8 buffer[34];
@@ -1449,8 +1449,8 @@ static int scu_command(struct drxk_state *state,
1449 1449
1450 dprintk(1, "\n"); 1450 dprintk(1, "\n");
1451 1451
1452 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || 1452 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1453 ((resultLen > 0) && (result == NULL))) { 1453 ((result_len > 0) && (result == NULL))) {
1454 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 1454 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1455 return status; 1455 return status;
1456 } 1456 }
@@ -1459,7 +1459,7 @@ static int scu_command(struct drxk_state *state,
1459 1459
1460 /* assume that the command register is ready 1460 /* assume that the command register is ready
1461 since it is checked afterwards */ 1461 since it is checked afterwards */
1462 for (ii = parameterLen - 1; ii >= 0; ii -= 1) { 1462 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1463 buffer[cnt++] = (parameter[ii] & 0xFF); 1463 buffer[cnt++] = (parameter[ii] & 0xFF);
1464 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); 1464 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1465 } 1465 }
@@ -1467,26 +1467,26 @@ static int scu_command(struct drxk_state *state,
1467 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1467 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1468 1468
1469 write_block(state, SCU_RAM_PARAM_0__A - 1469 write_block(state, SCU_RAM_PARAM_0__A -
1470 (parameterLen - 1), cnt, buffer); 1470 (parameter_len - 1), cnt, buffer);
1471 /* Wait until SCU has processed command */ 1471 /* Wait until SCU has processed command */
1472 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1472 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1473 do { 1473 do {
1474 msleep(1); 1474 msleep(1);
1475 status = read16(state, SCU_RAM_COMMAND__A, &curCmd); 1475 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1476 if (status < 0) 1476 if (status < 0)
1477 goto error; 1477 goto error;
1478 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); 1478 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1479 if (curCmd != DRX_SCU_READY) { 1479 if (cur_cmd != DRX_SCU_READY) {
1480 printk(KERN_ERR "drxk: SCU not ready\n"); 1480 printk(KERN_ERR "drxk: SCU not ready\n");
1481 status = -EIO; 1481 status = -EIO;
1482 goto error2; 1482 goto error2;
1483 } 1483 }
1484 /* read results */ 1484 /* read results */
1485 if ((resultLen > 0) && (result != NULL)) { 1485 if ((result_len > 0) && (result != NULL)) {
1486 s16 err; 1486 s16 err;
1487 int ii; 1487 int ii;
1488 1488
1489 for (ii = resultLen - 1; ii >= 0; ii -= 1) { 1489 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1490 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); 1490 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1491 if (status < 0) 1491 if (status < 0)
1492 goto error; 1492 goto error;
@@ -1529,7 +1529,7 @@ error2:
1529 return status; 1529 return status;
1530} 1530}
1531 1531
1532static int SetIqmAf(struct drxk_state *state, bool active) 1532static int set_iqm_af(struct drxk_state *state, bool active)
1533{ 1533{
1534 u16 data = 0; 1534 u16 data = 0;
1535 int status; 1535 int status;
@@ -1563,10 +1563,10 @@ error:
1563 return status; 1563 return status;
1564} 1564}
1565 1565
1566static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) 1566static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1567{ 1567{
1568 int status = 0; 1568 int status = 0;
1569 u16 sioCcPwdMode = 0; 1569 u16 sio_cc_pwd_mode = 0;
1570 1570
1571 dprintk(1, "\n"); 1571 dprintk(1, "\n");
1572 1572
@@ -1576,19 +1576,19 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1576 1576
1577 switch (*mode) { 1577 switch (*mode) {
1578 case DRX_POWER_UP: 1578 case DRX_POWER_UP:
1579 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; 1579 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1580 break; 1580 break;
1581 case DRXK_POWER_DOWN_OFDM: 1581 case DRXK_POWER_DOWN_OFDM:
1582 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; 1582 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1583 break; 1583 break;
1584 case DRXK_POWER_DOWN_CORE: 1584 case DRXK_POWER_DOWN_CORE:
1585 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; 1585 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1586 break; 1586 break;
1587 case DRXK_POWER_DOWN_PLL: 1587 case DRXK_POWER_DOWN_PLL:
1588 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; 1588 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1589 break; 1589 break;
1590 case DRX_POWER_DOWN: 1590 case DRX_POWER_DOWN:
1591 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; 1591 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1592 break; 1592 break;
1593 default: 1593 default:
1594 /* Unknow sleep mode */ 1594 /* Unknow sleep mode */
@@ -1596,15 +1596,15 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1596 } 1596 }
1597 1597
1598 /* If already in requested power mode, do nothing */ 1598 /* If already in requested power mode, do nothing */
1599 if (state->m_currentPowerMode == *mode) 1599 if (state->m_current_power_mode == *mode)
1600 return 0; 1600 return 0;
1601 1601
1602 /* For next steps make sure to start from DRX_POWER_UP mode */ 1602 /* For next steps make sure to start from DRX_POWER_UP mode */
1603 if (state->m_currentPowerMode != DRX_POWER_UP) { 1603 if (state->m_current_power_mode != DRX_POWER_UP) {
1604 status = PowerUpDevice(state); 1604 status = power_up_device(state);
1605 if (status < 0) 1605 if (status < 0)
1606 goto error; 1606 goto error;
1607 status = DVBTEnableOFDMTokenRing(state, true); 1607 status = dvbt_enable_ofdm_token_ring(state, true);
1608 if (status < 0) 1608 if (status < 0)
1609 goto error; 1609 goto error;
1610 } 1610 }
@@ -1621,31 +1621,31 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1621 /* Power down device */ 1621 /* Power down device */
1622 /* stop all comm_exec */ 1622 /* stop all comm_exec */
1623 /* Stop and power down previous standard */ 1623 /* Stop and power down previous standard */
1624 switch (state->m_OperationMode) { 1624 switch (state->m_operation_mode) {
1625 case OM_DVBT: 1625 case OM_DVBT:
1626 status = MPEGTSStop(state); 1626 status = mpegts_stop(state);
1627 if (status < 0) 1627 if (status < 0)
1628 goto error; 1628 goto error;
1629 status = PowerDownDVBT(state, false); 1629 status = power_down_dvbt(state, false);
1630 if (status < 0) 1630 if (status < 0)
1631 goto error; 1631 goto error;
1632 break; 1632 break;
1633 case OM_QAM_ITU_A: 1633 case OM_QAM_ITU_A:
1634 case OM_QAM_ITU_C: 1634 case OM_QAM_ITU_C:
1635 status = MPEGTSStop(state); 1635 status = mpegts_stop(state);
1636 if (status < 0) 1636 if (status < 0)
1637 goto error; 1637 goto error;
1638 status = PowerDownQAM(state); 1638 status = power_down_qam(state);
1639 if (status < 0) 1639 if (status < 0)
1640 goto error; 1640 goto error;
1641 break; 1641 break;
1642 default: 1642 default:
1643 break; 1643 break;
1644 } 1644 }
1645 status = DVBTEnableOFDMTokenRing(state, false); 1645 status = dvbt_enable_ofdm_token_ring(state, false);
1646 if (status < 0) 1646 if (status < 0)
1647 goto error; 1647 goto error;
1648 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); 1648 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1649 if (status < 0) 1649 if (status < 0)
1650 goto error; 1650 goto error;
1651 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1651 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
@@ -1653,14 +1653,14 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1653 goto error; 1653 goto error;
1654 1654
1655 if (*mode != DRXK_POWER_DOWN_OFDM) { 1655 if (*mode != DRXK_POWER_DOWN_OFDM) {
1656 state->m_HICfgCtrl |= 1656 state->m_hi_cfg_ctrl |=
1657 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1657 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1658 status = HI_CfgCommand(state); 1658 status = hi_cfg_command(state);
1659 if (status < 0) 1659 if (status < 0)
1660 goto error; 1660 goto error;
1661 } 1661 }
1662 } 1662 }
1663 state->m_currentPowerMode = *mode; 1663 state->m_current_power_mode = *mode;
1664 1664
1665error: 1665error:
1666 if (status < 0) 1666 if (status < 0)
@@ -1669,10 +1669,10 @@ error:
1669 return status; 1669 return status;
1670} 1670}
1671 1671
1672static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) 1672static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1673{ 1673{
1674 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; 1674 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1675 u16 cmdResult = 0; 1675 u16 cmd_result = 0;
1676 u16 data = 0; 1676 u16 data = 0;
1677 int status; 1677 int status;
1678 1678
@@ -1683,11 +1683,11 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1683 goto error; 1683 goto error;
1684 if (data == SCU_COMM_EXEC_ACTIVE) { 1684 if (data == SCU_COMM_EXEC_ACTIVE) {
1685 /* Send OFDM stop command */ 1685 /* Send OFDM stop command */
1686 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); 1686 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
1687 if (status < 0) 1687 if (status < 0)
1688 goto error; 1688 goto error;
1689 /* Send OFDM reset command */ 1689 /* Send OFDM reset command */
1690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); 1690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
1691 if (status < 0) 1691 if (status < 0)
1692 goto error; 1692 goto error;
1693 } 1693 }
@@ -1704,13 +1704,13 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1704 goto error; 1704 goto error;
1705 1705
1706 /* powerdown AFE */ 1706 /* powerdown AFE */
1707 status = SetIqmAf(state, false); 1707 status = set_iqm_af(state, false);
1708 if (status < 0) 1708 if (status < 0)
1709 goto error; 1709 goto error;
1710 1710
1711 /* powerdown to OFDM mode */ 1711 /* powerdown to OFDM mode */
1712 if (setPowerMode) { 1712 if (set_power_mode) {
1713 status = CtrlPowerMode(state, &powerMode); 1713 status = ctrl_power_mode(state, &power_mode);
1714 if (status < 0) 1714 if (status < 0)
1715 goto error; 1715 goto error;
1716 } 1716 }
@@ -1720,8 +1720,8 @@ error:
1720 return status; 1720 return status;
1721} 1721}
1722 1722
1723static int SetOperationMode(struct drxk_state *state, 1723static int setoperation_mode(struct drxk_state *state,
1724 enum OperationMode oMode) 1724 enum operation_mode o_mode)
1725{ 1725{
1726 int status = 0; 1726 int status = 0;
1727 1727
@@ -1738,31 +1738,31 @@ static int SetOperationMode(struct drxk_state *state,
1738 goto error; 1738 goto error;
1739 1739
1740 /* Device is already at the required mode */ 1740 /* Device is already at the required mode */
1741 if (state->m_OperationMode == oMode) 1741 if (state->m_operation_mode == o_mode)
1742 return 0; 1742 return 0;
1743 1743
1744 switch (state->m_OperationMode) { 1744 switch (state->m_operation_mode) {
1745 /* OM_NONE was added for start up */ 1745 /* OM_NONE was added for start up */
1746 case OM_NONE: 1746 case OM_NONE:
1747 break; 1747 break;
1748 case OM_DVBT: 1748 case OM_DVBT:
1749 status = MPEGTSStop(state); 1749 status = mpegts_stop(state);
1750 if (status < 0) 1750 if (status < 0)
1751 goto error; 1751 goto error;
1752 status = PowerDownDVBT(state, true); 1752 status = power_down_dvbt(state, true);
1753 if (status < 0) 1753 if (status < 0)
1754 goto error; 1754 goto error;
1755 state->m_OperationMode = OM_NONE; 1755 state->m_operation_mode = OM_NONE;
1756 break; 1756 break;
1757 case OM_QAM_ITU_A: /* fallthrough */ 1757 case OM_QAM_ITU_A: /* fallthrough */
1758 case OM_QAM_ITU_C: 1758 case OM_QAM_ITU_C:
1759 status = MPEGTSStop(state); 1759 status = mpegts_stop(state);
1760 if (status < 0) 1760 if (status < 0)
1761 goto error; 1761 goto error;
1762 status = PowerDownQAM(state); 1762 status = power_down_qam(state);
1763 if (status < 0) 1763 if (status < 0)
1764 goto error; 1764 goto error;
1765 state->m_OperationMode = OM_NONE; 1765 state->m_operation_mode = OM_NONE;
1766 break; 1766 break;
1767 case OM_QAM_ITU_B: 1767 case OM_QAM_ITU_B:
1768 default: 1768 default:
@@ -1773,20 +1773,20 @@ static int SetOperationMode(struct drxk_state *state,
1773 /* 1773 /*
1774 Power up new standard 1774 Power up new standard
1775 */ 1775 */
1776 switch (oMode) { 1776 switch (o_mode) {
1777 case OM_DVBT: 1777 case OM_DVBT:
1778 dprintk(1, ": DVB-T\n"); 1778 dprintk(1, ": DVB-T\n");
1779 state->m_OperationMode = oMode; 1779 state->m_operation_mode = o_mode;
1780 status = SetDVBTStandard(state, oMode); 1780 status = set_dvbt_standard(state, o_mode);
1781 if (status < 0) 1781 if (status < 0)
1782 goto error; 1782 goto error;
1783 break; 1783 break;
1784 case OM_QAM_ITU_A: /* fallthrough */ 1784 case OM_QAM_ITU_A: /* fallthrough */
1785 case OM_QAM_ITU_C: 1785 case OM_QAM_ITU_C:
1786 dprintk(1, ": DVB-C Annex %c\n", 1786 dprintk(1, ": DVB-C Annex %c\n",
1787 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); 1787 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1788 state->m_OperationMode = oMode; 1788 state->m_operation_mode = o_mode;
1789 status = SetQAMStandard(state, oMode); 1789 status = set_qam_standard(state, o_mode);
1790 if (status < 0) 1790 if (status < 0)
1791 goto error; 1791 goto error;
1792 break; 1792 break;
@@ -1800,47 +1800,47 @@ error:
1800 return status; 1800 return status;
1801} 1801}
1802 1802
1803static int Start(struct drxk_state *state, s32 offsetFreq, 1803static int start(struct drxk_state *state, s32 offset_freq,
1804 s32 IntermediateFrequency) 1804 s32 intermediate_frequency)
1805{ 1805{
1806 int status = -EINVAL; 1806 int status = -EINVAL;
1807 1807
1808 u16 IFreqkHz; 1808 u16 i_freqk_hz;
1809 s32 OffsetkHz = offsetFreq / 1000; 1809 s32 offsetk_hz = offset_freq / 1000;
1810 1810
1811 dprintk(1, "\n"); 1811 dprintk(1, "\n");
1812 if (state->m_DrxkState != DRXK_STOPPED && 1812 if (state->m_drxk_state != DRXK_STOPPED &&
1813 state->m_DrxkState != DRXK_DTV_STARTED) 1813 state->m_drxk_state != DRXK_DTV_STARTED)
1814 goto error; 1814 goto error;
1815 1815
1816 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); 1816 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1817 1817
1818 if (IntermediateFrequency < 0) { 1818 if (intermediate_frequency < 0) {
1819 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; 1819 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1820 IntermediateFrequency = -IntermediateFrequency; 1820 intermediate_frequency = -intermediate_frequency;
1821 } 1821 }
1822 1822
1823 switch (state->m_OperationMode) { 1823 switch (state->m_operation_mode) {
1824 case OM_QAM_ITU_A: 1824 case OM_QAM_ITU_A:
1825 case OM_QAM_ITU_C: 1825 case OM_QAM_ITU_C:
1826 IFreqkHz = (IntermediateFrequency / 1000); 1826 i_freqk_hz = (intermediate_frequency / 1000);
1827 status = SetQAM(state, IFreqkHz, OffsetkHz); 1827 status = set_qam(state, i_freqk_hz, offsetk_hz);
1828 if (status < 0) 1828 if (status < 0)
1829 goto error; 1829 goto error;
1830 state->m_DrxkState = DRXK_DTV_STARTED; 1830 state->m_drxk_state = DRXK_DTV_STARTED;
1831 break; 1831 break;
1832 case OM_DVBT: 1832 case OM_DVBT:
1833 IFreqkHz = (IntermediateFrequency / 1000); 1833 i_freqk_hz = (intermediate_frequency / 1000);
1834 status = MPEGTSStop(state); 1834 status = mpegts_stop(state);
1835 if (status < 0) 1835 if (status < 0)
1836 goto error; 1836 goto error;
1837 status = SetDVBT(state, IFreqkHz, OffsetkHz); 1837 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1838 if (status < 0) 1838 if (status < 0)
1839 goto error; 1839 goto error;
1840 status = DVBTStart(state); 1840 status = dvbt_start(state);
1841 if (status < 0) 1841 if (status < 0)
1842 goto error; 1842 goto error;
1843 state->m_DrxkState = DRXK_DTV_STARTED; 1843 state->m_drxk_state = DRXK_DTV_STARTED;
1844 break; 1844 break;
1845 default: 1845 default:
1846 break; 1846 break;
@@ -1851,34 +1851,34 @@ error:
1851 return status; 1851 return status;
1852} 1852}
1853 1853
1854static int ShutDown(struct drxk_state *state) 1854static int shut_down(struct drxk_state *state)
1855{ 1855{
1856 dprintk(1, "\n"); 1856 dprintk(1, "\n");
1857 1857
1858 MPEGTSStop(state); 1858 mpegts_stop(state);
1859 return 0; 1859 return 0;
1860} 1860}
1861 1861
1862static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus) 1862static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1863{ 1863{
1864 int status = -EINVAL; 1864 int status = -EINVAL;
1865 1865
1866 dprintk(1, "\n"); 1866 dprintk(1, "\n");
1867 1867
1868 if (pLockStatus == NULL) 1868 if (p_lock_status == NULL)
1869 goto error; 1869 goto error;
1870 1870
1871 *pLockStatus = NOT_LOCKED; 1871 *p_lock_status = NOT_LOCKED;
1872 1872
1873 /* define the SCU command code */ 1873 /* define the SCU command code */
1874 switch (state->m_OperationMode) { 1874 switch (state->m_operation_mode) {
1875 case OM_QAM_ITU_A: 1875 case OM_QAM_ITU_A:
1876 case OM_QAM_ITU_B: 1876 case OM_QAM_ITU_B:
1877 case OM_QAM_ITU_C: 1877 case OM_QAM_ITU_C:
1878 status = GetQAMLockStatus(state, pLockStatus); 1878 status = get_qam_lock_status(state, p_lock_status);
1879 break; 1879 break;
1880 case OM_DVBT: 1880 case OM_DVBT:
1881 status = GetDVBTLockStatus(state, pLockStatus); 1881 status = get_dvbt_lock_status(state, p_lock_status);
1882 break; 1882 break;
1883 default: 1883 default:
1884 break; 1884 break;
@@ -1889,18 +1889,18 @@ error:
1889 return status; 1889 return status;
1890} 1890}
1891 1891
1892static int MPEGTSStart(struct drxk_state *state) 1892static int mpegts_start(struct drxk_state *state)
1893{ 1893{
1894 int status; 1894 int status;
1895 1895
1896 u16 fecOcSncMode = 0; 1896 u16 fec_oc_snc_mode = 0;
1897 1897
1898 /* Allow OC to sync again */ 1898 /* Allow OC to sync again */
1899 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); 1899 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1900 if (status < 0) 1900 if (status < 0)
1901 goto error; 1901 goto error;
1902 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1902 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1903 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); 1903 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1904 if (status < 0) 1904 if (status < 0)
1905 goto error; 1905 goto error;
1906 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); 1906 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
@@ -1910,7 +1910,7 @@ error:
1910 return status; 1910 return status;
1911} 1911}
1912 1912
1913static int MPEGTSDtoInit(struct drxk_state *state) 1913static int mpegts_dto_init(struct drxk_state *state)
1914{ 1914{
1915 int status; 1915 int status;
1916 1916
@@ -1957,63 +1957,63 @@ error:
1957 return status; 1957 return status;
1958} 1958}
1959 1959
1960static int MPEGTSDtoSetup(struct drxk_state *state, 1960static int mpegts_dto_setup(struct drxk_state *state,
1961 enum OperationMode oMode) 1961 enum operation_mode o_mode)
1962{ 1962{
1963 int status; 1963 int status;
1964 1964
1965 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ 1965 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */
1966 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ 1966 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */
1967 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ 1967 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */
1968 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ 1968 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */
1969 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ 1969 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */
1970 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ 1970 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1971 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ 1971 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */
1972 u16 fecOcTmdMode = 0; 1972 u16 fec_oc_tmd_mode = 0;
1973 u16 fecOcTmdIntUpdRate = 0; 1973 u16 fec_oc_tmd_int_upd_rate = 0;
1974 u32 maxBitRate = 0; 1974 u32 max_bit_rate = 0;
1975 bool staticCLK = false; 1975 bool static_clk = false;
1976 1976
1977 dprintk(1, "\n"); 1977 dprintk(1, "\n");
1978 1978
1979 /* Check insertion of the Reed-Solomon parity bytes */ 1979 /* Check insertion of the Reed-Solomon parity bytes */
1980 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); 1980 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1981 if (status < 0) 1981 if (status < 0)
1982 goto error; 1982 goto error;
1983 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); 1983 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1984 if (status < 0) 1984 if (status < 0)
1985 goto error; 1985 goto error;
1986 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); 1986 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1987 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 1987 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1988 if (state->m_insertRSByte == true) { 1988 if (state->m_insert_rs_byte == true) {
1989 /* enable parity symbol forward */ 1989 /* enable parity symbol forward */
1990 fecOcRegMode |= FEC_OC_MODE_PARITY__M; 1990 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1991 /* MVAL disable during parity bytes */ 1991 /* MVAL disable during parity bytes */
1992 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 1992 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1993 /* TS burst length to 204 */ 1993 /* TS burst length to 204 */
1994 fecOcDtoBurstLen = 204; 1994 fec_oc_dto_burst_len = 204;
1995 } 1995 }
1996 1996
1997 /* Check serial or parrallel output */ 1997 /* Check serial or parrallel output */
1998 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 1998 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
1999 if (state->m_enableParallel == false) { 1999 if (state->m_enable_parallel == false) {
2000 /* MPEG data output is serial -> set ipr_mode[0] */ 2000 /* MPEG data output is serial -> set ipr_mode[0] */
2001 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; 2001 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2002 } 2002 }
2003 2003
2004 switch (oMode) { 2004 switch (o_mode) {
2005 case OM_DVBT: 2005 case OM_DVBT:
2006 maxBitRate = state->m_DVBTBitrate; 2006 max_bit_rate = state->m_dvbt_bitrate;
2007 fecOcTmdMode = 3; 2007 fec_oc_tmd_mode = 3;
2008 fecOcRcnCtlRate = 0xC00000; 2008 fec_oc_rcn_ctl_rate = 0xC00000;
2009 staticCLK = state->m_DVBTStaticCLK; 2009 static_clk = state->m_dvbt_static_clk;
2010 break; 2010 break;
2011 case OM_QAM_ITU_A: /* fallthrough */ 2011 case OM_QAM_ITU_A: /* fallthrough */
2012 case OM_QAM_ITU_C: 2012 case OM_QAM_ITU_C:
2013 fecOcTmdMode = 0x0004; 2013 fec_oc_tmd_mode = 0x0004;
2014 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ 2014 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2015 maxBitRate = state->m_DVBCBitrate; 2015 max_bit_rate = state->m_dvbc_bitrate;
2016 staticCLK = state->m_DVBCStaticCLK; 2016 static_clk = state->m_dvbc_static_clk;
2017 break; 2017 break;
2018 default: 2018 default:
2019 status = -EINVAL; 2019 status = -EINVAL;
@@ -2022,83 +2022,83 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
2022 goto error; 2022 goto error;
2023 2023
2024 /* Configure DTO's */ 2024 /* Configure DTO's */
2025 if (staticCLK) { 2025 if (static_clk) {
2026 u32 bitRate = 0; 2026 u32 bit_rate = 0;
2027 2027
2028 /* Rational DTO for MCLK source (static MCLK rate), 2028 /* Rational DTO for MCLK source (static MCLK rate),
2029 Dynamic DTO for optimal grouping 2029 Dynamic DTO for optimal grouping
2030 (avoid intra-packet gaps), 2030 (avoid intra-packet gaps),
2031 DTO offset enable to sync TS burst with MSTRT */ 2031 DTO offset enable to sync TS burst with MSTRT */
2032 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | 2032 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2033 FEC_OC_DTO_MODE_OFFSET_ENABLE__M); 2033 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2034 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | 2034 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2035 FEC_OC_FCT_MODE_VIRT_ENA__M); 2035 FEC_OC_FCT_MODE_VIRT_ENA__M);
2036 2036
2037 /* Check user defined bitrate */ 2037 /* Check user defined bitrate */
2038 bitRate = maxBitRate; 2038 bit_rate = max_bit_rate;
2039 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */ 2039 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */
2040 bitRate = 75900000UL; 2040 bit_rate = 75900000UL;
2041 } 2041 }
2042 /* Rational DTO period: 2042 /* Rational DTO period:
2043 dto_period = (Fsys / bitrate) - 2 2043 dto_period = (Fsys / bitrate) - 2
2044 2044
2045 Result should be floored, 2045 result should be floored,
2046 to make sure >= requested bitrate 2046 to make sure >= requested bitrate
2047 */ 2047 */
2048 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) 2048 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2049 * 1000) / bitRate); 2049 * 1000) / bit_rate);
2050 if (fecOcDtoPeriod <= 2) 2050 if (fec_oc_dto_period <= 2)
2051 fecOcDtoPeriod = 0; 2051 fec_oc_dto_period = 0;
2052 else 2052 else
2053 fecOcDtoPeriod -= 2; 2053 fec_oc_dto_period -= 2;
2054 fecOcTmdIntUpdRate = 8; 2054 fec_oc_tmd_int_upd_rate = 8;
2055 } else { 2055 } else {
2056 /* (commonAttr->staticCLK == false) => dynamic mode */ 2056 /* (commonAttr->static_clk == false) => dynamic mode */
2057 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; 2057 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2058 fecOcFctMode = FEC_OC_FCT_MODE__PRE; 2058 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2059 fecOcTmdIntUpdRate = 5; 2059 fec_oc_tmd_int_upd_rate = 5;
2060 } 2060 }
2061 2061
2062 /* Write appropriate registers with requested configuration */ 2062 /* Write appropriate registers with requested configuration */
2063 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); 2063 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2064 if (status < 0) 2064 if (status < 0)
2065 goto error; 2065 goto error;
2066 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); 2066 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2067 if (status < 0) 2067 if (status < 0)
2068 goto error; 2068 goto error;
2069 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); 2069 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2070 if (status < 0) 2070 if (status < 0)
2071 goto error; 2071 goto error;
2072 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); 2072 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2073 if (status < 0) 2073 if (status < 0)
2074 goto error; 2074 goto error;
2075 status = write16(state, FEC_OC_MODE__A, fecOcRegMode); 2075 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2076 if (status < 0) 2076 if (status < 0)
2077 goto error; 2077 goto error;
2078 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); 2078 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2079 if (status < 0) 2079 if (status < 0)
2080 goto error; 2080 goto error;
2081 2081
2082 /* Rate integration settings */ 2082 /* Rate integration settings */
2083 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); 2083 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2084 if (status < 0) 2084 if (status < 0)
2085 goto error; 2085 goto error;
2086 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); 2086 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fec_oc_tmd_int_upd_rate);
2087 if (status < 0) 2087 if (status < 0)
2088 goto error; 2088 goto error;
2089 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); 2089 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2090error: 2090error:
2091 if (status < 0) 2091 if (status < 0)
2092 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 2092 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2093 return status; 2093 return status;
2094} 2094}
2095 2095
2096static int MPEGTSConfigurePolarity(struct drxk_state *state) 2096static int mpegts_configure_polarity(struct drxk_state *state)
2097{ 2097{
2098 u16 fecOcRegIprInvert = 0; 2098 u16 fec_oc_reg_ipr_invert = 0;
2099 2099
2100 /* Data mask for the output data byte */ 2100 /* Data mask for the output data byte */
2101 u16 InvertDataMask = 2101 u16 invert_data_mask =
2102 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2102 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2103 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | 2103 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2104 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2104 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
@@ -2107,40 +2107,40 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)
2107 dprintk(1, "\n"); 2107 dprintk(1, "\n");
2108 2108
2109 /* Control selective inversion of output bits */ 2109 /* Control selective inversion of output bits */
2110 fecOcRegIprInvert &= (~(InvertDataMask)); 2110 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2111 if (state->m_invertDATA == true) 2111 if (state->m_invert_data == true)
2112 fecOcRegIprInvert |= InvertDataMask; 2112 fec_oc_reg_ipr_invert |= invert_data_mask;
2113 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); 2113 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2114 if (state->m_invertERR == true) 2114 if (state->m_invert_err == true)
2115 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; 2115 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2116 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); 2116 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2117 if (state->m_invertSTR == true) 2117 if (state->m_invert_str == true)
2118 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; 2118 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2119 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); 2119 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2120 if (state->m_invertVAL == true) 2120 if (state->m_invert_val == true)
2121 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; 2121 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2122 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2122 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2123 if (state->m_invertCLK == true) 2123 if (state->m_invert_clk == true)
2124 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; 2124 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2125 2125
2126 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); 2126 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2127} 2127}
2128 2128
2129#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 2129#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2130 2130
2131static int SetAgcRf(struct drxk_state *state, 2131static int set_agc_rf(struct drxk_state *state,
2132 struct SCfgAgc *pAgcCfg, bool isDTV) 2132 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2133{ 2133{
2134 int status = -EINVAL; 2134 int status = -EINVAL;
2135 u16 data = 0; 2135 u16 data = 0;
2136 struct SCfgAgc *pIfAgcSettings; 2136 struct s_cfg_agc *p_if_agc_settings;
2137 2137
2138 dprintk(1, "\n"); 2138 dprintk(1, "\n");
2139 2139
2140 if (pAgcCfg == NULL) 2140 if (p_agc_cfg == NULL)
2141 goto error; 2141 goto error;
2142 2142
2143 switch (pAgcCfg->ctrlMode) { 2143 switch (p_agc_cfg->ctrl_mode) {
2144 case DRXK_AGC_CTRL_AUTO: 2144 case DRXK_AGC_CTRL_AUTO:
2145 /* Enable RF AGC DAC */ 2145 /* Enable RF AGC DAC */
2146 status = read16(state, IQM_AF_STDBY__A, &data); 2146 status = read16(state, IQM_AF_STDBY__A, &data);
@@ -2158,7 +2158,7 @@ static int SetAgcRf(struct drxk_state *state,
2158 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2158 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2159 2159
2160 /* Polarity */ 2160 /* Polarity */
2161 if (state->m_RfAgcPol) 2161 if (state->m_rf_agc_pol)
2162 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2162 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2163 else 2163 else
2164 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2164 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
@@ -2172,7 +2172,7 @@ static int SetAgcRf(struct drxk_state *state,
2172 goto error; 2172 goto error;
2173 2173
2174 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2174 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2175 data |= (~(pAgcCfg->speed << 2175 data |= (~(p_agc_cfg->speed <<
2176 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2176 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2177 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2177 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2178 2178
@@ -2180,30 +2180,30 @@ static int SetAgcRf(struct drxk_state *state,
2180 if (status < 0) 2180 if (status < 0)
2181 goto error; 2181 goto error;
2182 2182
2183 if (IsDVBT(state)) 2183 if (is_dvbt(state))
2184 pIfAgcSettings = &state->m_dvbtIfAgcCfg; 2184 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2185 else if (IsQAM(state)) 2185 else if (is_qam(state))
2186 pIfAgcSettings = &state->m_qamIfAgcCfg; 2186 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2187 else 2187 else
2188 pIfAgcSettings = &state->m_atvIfAgcCfg; 2188 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2189 if (pIfAgcSettings == NULL) { 2189 if (p_if_agc_settings == NULL) {
2190 status = -EINVAL; 2190 status = -EINVAL;
2191 goto error; 2191 goto error;
2192 } 2192 }
2193 2193
2194 /* Set TOP, only if IF-AGC is in AUTO mode */ 2194 /* Set TOP, only if IF-AGC is in AUTO mode */
2195 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) 2195 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO)
2196 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); 2196 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->top);
2197 if (status < 0) 2197 if (status < 0)
2198 goto error; 2198 goto error;
2199 2199
2200 /* Cut-Off current */ 2200 /* Cut-Off current */
2201 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); 2201 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, p_agc_cfg->cut_off_current);
2202 if (status < 0) 2202 if (status < 0)
2203 goto error; 2203 goto error;
2204 2204
2205 /* Max. output level */ 2205 /* Max. output level */
2206 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); 2206 status = write16(state, SCU_RAM_AGC_RF_MAX__A, p_agc_cfg->max_output_level);
2207 if (status < 0) 2207 if (status < 0)
2208 goto error; 2208 goto error;
2209 2209
@@ -2224,7 +2224,7 @@ static int SetAgcRf(struct drxk_state *state,
2224 if (status < 0) 2224 if (status < 0)
2225 goto error; 2225 goto error;
2226 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2226 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2227 if (state->m_RfAgcPol) 2227 if (state->m_rf_agc_pol)
2228 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2228 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2229 else 2229 else
2230 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2230 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
@@ -2238,7 +2238,7 @@ static int SetAgcRf(struct drxk_state *state,
2238 goto error; 2238 goto error;
2239 2239
2240 /* Write value to output pin */ 2240 /* Write value to output pin */
2241 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); 2241 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, p_agc_cfg->output_level);
2242 if (status < 0) 2242 if (status < 0)
2243 goto error; 2243 goto error;
2244 break; 2244 break;
@@ -2275,16 +2275,16 @@ error:
2275 2275
2276#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 2276#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2277 2277
2278static int SetAgcIf(struct drxk_state *state, 2278static int set_agc_if(struct drxk_state *state,
2279 struct SCfgAgc *pAgcCfg, bool isDTV) 2279 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2280{ 2280{
2281 u16 data = 0; 2281 u16 data = 0;
2282 int status = 0; 2282 int status = 0;
2283 struct SCfgAgc *pRfAgcSettings; 2283 struct s_cfg_agc *p_rf_agc_settings;
2284 2284
2285 dprintk(1, "\n"); 2285 dprintk(1, "\n");
2286 2286
2287 switch (pAgcCfg->ctrlMode) { 2287 switch (p_agc_cfg->ctrl_mode) {
2288 case DRXK_AGC_CTRL_AUTO: 2288 case DRXK_AGC_CTRL_AUTO:
2289 2289
2290 /* Enable IF AGC DAC */ 2290 /* Enable IF AGC DAC */
@@ -2304,7 +2304,7 @@ static int SetAgcIf(struct drxk_state *state,
2304 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2304 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2305 2305
2306 /* Polarity */ 2306 /* Polarity */
2307 if (state->m_IfAgcPol) 2307 if (state->m_if_agc_pol)
2308 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2308 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2309 else 2309 else
2310 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2310 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
@@ -2317,7 +2317,7 @@ static int SetAgcIf(struct drxk_state *state,
2317 if (status < 0) 2317 if (status < 0)
2318 goto error; 2318 goto error;
2319 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2319 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2320 data |= (~(pAgcCfg->speed << 2320 data |= (~(p_agc_cfg->speed <<
2321 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2321 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2322 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2322 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2323 2323
@@ -2325,14 +2325,14 @@ static int SetAgcIf(struct drxk_state *state,
2325 if (status < 0) 2325 if (status < 0)
2326 goto error; 2326 goto error;
2327 2327
2328 if (IsQAM(state)) 2328 if (is_qam(state))
2329 pRfAgcSettings = &state->m_qamRfAgcCfg; 2329 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2330 else 2330 else
2331 pRfAgcSettings = &state->m_atvRfAgcCfg; 2331 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2332 if (pRfAgcSettings == NULL) 2332 if (p_rf_agc_settings == NULL)
2333 return -1; 2333 return -1;
2334 /* Restore TOP */ 2334 /* Restore TOP */
2335 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); 2335 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_rf_agc_settings->top);
2336 if (status < 0) 2336 if (status < 0)
2337 goto error; 2337 goto error;
2338 break; 2338 break;
@@ -2356,7 +2356,7 @@ static int SetAgcIf(struct drxk_state *state,
2356 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2356 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2357 2357
2358 /* Polarity */ 2358 /* Polarity */
2359 if (state->m_IfAgcPol) 2359 if (state->m_if_agc_pol)
2360 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2360 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2361 else 2361 else
2362 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2362 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
@@ -2365,7 +2365,7 @@ static int SetAgcIf(struct drxk_state *state,
2365 goto error; 2365 goto error;
2366 2366
2367 /* Write value to output pin */ 2367 /* Write value to output pin */
2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); 2368 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->output_level);
2369 if (status < 0) 2369 if (status < 0)
2370 goto error; 2370 goto error;
2371 break; 2371 break;
@@ -2390,33 +2390,33 @@ static int SetAgcIf(struct drxk_state *state,
2390 if (status < 0) 2390 if (status < 0)
2391 goto error; 2391 goto error;
2392 break; 2392 break;
2393 } /* switch (agcSettingsIf->ctrlMode) */ 2393 } /* switch (agcSettingsIf->ctrl_mode) */
2394 2394
2395 /* always set the top to support 2395 /* always set the top to support
2396 configurations without if-loop */ 2396 configurations without if-loop */
2397 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); 2397 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2398error: 2398error:
2399 if (status < 0) 2399 if (status < 0)
2400 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 2400 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2401 return status; 2401 return status;
2402} 2402}
2403 2403
2404static int GetQAMSignalToNoise(struct drxk_state *state, 2404static int get_qam_signal_to_noise(struct drxk_state *state,
2405 s32 *pSignalToNoise) 2405 s32 *p_signal_to_noise)
2406{ 2406{
2407 int status = 0; 2407 int status = 0;
2408 u16 qamSlErrPower = 0; /* accum. error between 2408 u16 qam_sl_err_power = 0; /* accum. error between
2409 raw and sliced symbols */ 2409 raw and sliced symbols */
2410 u32 qamSlSigPower = 0; /* used for MER, depends of 2410 u32 qam_sl_sig_power = 0; /* used for MER, depends of
2411 QAM modulation */ 2411 QAM modulation */
2412 u32 qamSlMer = 0; /* QAM MER */ 2412 u32 qam_sl_mer = 0; /* QAM MER */
2413 2413
2414 dprintk(1, "\n"); 2414 dprintk(1, "\n");
2415 2415
2416 /* MER calculation */ 2416 /* MER calculation */
2417 2417
2418 /* get the register value needed for MER */ 2418 /* get the register value needed for MER */
2419 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); 2419 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2420 if (status < 0) { 2420 if (status < 0) {
2421 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 2421 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2422 return -EINVAL; 2422 return -EINVAL;
@@ -2424,124 +2424,124 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2424 2424
2425 switch (state->props.modulation) { 2425 switch (state->props.modulation) {
2426 case QAM_16: 2426 case QAM_16:
2427 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2427 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2428 break; 2428 break;
2429 case QAM_32: 2429 case QAM_32:
2430 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; 2430 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2431 break; 2431 break;
2432 case QAM_64: 2432 case QAM_64:
2433 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; 2433 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2434 break; 2434 break;
2435 case QAM_128: 2435 case QAM_128:
2436 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; 2436 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2437 break; 2437 break;
2438 default: 2438 default:
2439 case QAM_256: 2439 case QAM_256:
2440 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; 2440 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2441 break; 2441 break;
2442 } 2442 }
2443 2443
2444 if (qamSlErrPower > 0) { 2444 if (qam_sl_err_power > 0) {
2445 qamSlMer = log10times100(qamSlSigPower) - 2445 qam_sl_mer = log10times100(qam_sl_sig_power) -
2446 log10times100((u32) qamSlErrPower); 2446 log10times100((u32) qam_sl_err_power);
2447 } 2447 }
2448 *pSignalToNoise = qamSlMer; 2448 *p_signal_to_noise = qam_sl_mer;
2449 2449
2450 return status; 2450 return status;
2451} 2451}
2452 2452
2453static int GetDVBTSignalToNoise(struct drxk_state *state, 2453static int get_dvbt_signal_to_noise(struct drxk_state *state,
2454 s32 *pSignalToNoise) 2454 s32 *p_signal_to_noise)
2455{ 2455{
2456 int status; 2456 int status;
2457 u16 regData = 0; 2457 u16 reg_data = 0;
2458 u32 EqRegTdSqrErrI = 0; 2458 u32 eq_reg_td_sqr_err_i = 0;
2459 u32 EqRegTdSqrErrQ = 0; 2459 u32 eq_reg_td_sqr_err_q = 0;
2460 u16 EqRegTdSqrErrExp = 0; 2460 u16 eq_reg_td_sqr_err_exp = 0;
2461 u16 EqRegTdTpsPwrOfs = 0; 2461 u16 eq_reg_td_tps_pwr_ofs = 0;
2462 u16 EqRegTdReqSmbCnt = 0; 2462 u16 eq_reg_td_req_smb_cnt = 0;
2463 u32 tpsCnt = 0; 2463 u32 tps_cnt = 0;
2464 u32 SqrErrIQ = 0; 2464 u32 sqr_err_iq = 0;
2465 u32 a = 0; 2465 u32 a = 0;
2466 u32 b = 0; 2466 u32 b = 0;
2467 u32 c = 0; 2467 u32 c = 0;
2468 u32 iMER = 0; 2468 u32 i_mer = 0;
2469 u16 transmissionParams = 0; 2469 u16 transmission_params = 0;
2470 2470
2471 dprintk(1, "\n"); 2471 dprintk(1, "\n");
2472 2472
2473 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); 2473 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &eq_reg_td_tps_pwr_ofs);
2474 if (status < 0) 2474 if (status < 0)
2475 goto error; 2475 goto error;
2476 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); 2476 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &eq_reg_td_req_smb_cnt);
2477 if (status < 0) 2477 if (status < 0)
2478 goto error; 2478 goto error;
2479 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); 2479 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &eq_reg_td_sqr_err_exp);
2480 if (status < 0) 2480 if (status < 0)
2481 goto error; 2481 goto error;
2482 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData); 2482 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &reg_data);
2483 if (status < 0) 2483 if (status < 0)
2484 goto error; 2484 goto error;
2485 /* Extend SQR_ERR_I operational range */ 2485 /* Extend SQR_ERR_I operational range */
2486 EqRegTdSqrErrI = (u32) regData; 2486 eq_reg_td_sqr_err_i = (u32) reg_data;
2487 if ((EqRegTdSqrErrExp > 11) && 2487 if ((eq_reg_td_sqr_err_exp > 11) &&
2488 (EqRegTdSqrErrI < 0x00000FFFUL)) { 2488 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2489 EqRegTdSqrErrI += 0x00010000UL; 2489 eq_reg_td_sqr_err_i += 0x00010000UL;
2490 } 2490 }
2491 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData); 2491 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2492 if (status < 0) 2492 if (status < 0)
2493 goto error; 2493 goto error;
2494 /* Extend SQR_ERR_Q operational range */ 2494 /* Extend SQR_ERR_Q operational range */
2495 EqRegTdSqrErrQ = (u32) regData; 2495 eq_reg_td_sqr_err_q = (u32) reg_data;
2496 if ((EqRegTdSqrErrExp > 11) && 2496 if ((eq_reg_td_sqr_err_exp > 11) &&
2497 (EqRegTdSqrErrQ < 0x00000FFFUL)) 2497 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2498 EqRegTdSqrErrQ += 0x00010000UL; 2498 eq_reg_td_sqr_err_q += 0x00010000UL;
2499 2499
2500 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); 2500 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmission_params);
2501 if (status < 0) 2501 if (status < 0)
2502 goto error; 2502 goto error;
2503 2503
2504 /* Check input data for MER */ 2504 /* Check input data for MER */
2505 2505
2506 /* MER calculation (in 0.1 dB) without math.h */ 2506 /* MER calculation (in 0.1 dB) without math.h */
2507 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) 2507 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2508 iMER = 0; 2508 i_mer = 0;
2509 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { 2509 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2510 /* No error at all, this must be the HW reset value 2510 /* No error at all, this must be the HW reset value
2511 * Apparently no first measurement yet 2511 * Apparently no first measurement yet
2512 * Set MER to 0.0 */ 2512 * Set MER to 0.0 */
2513 iMER = 0; 2513 i_mer = 0;
2514 } else { 2514 } else {
2515 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << 2515 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2516 EqRegTdSqrErrExp; 2516 eq_reg_td_sqr_err_exp;
2517 if ((transmissionParams & 2517 if ((transmission_params &
2518 OFDM_SC_RA_RAM_OP_PARAM_MODE__M) 2518 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2519 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) 2519 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2520 tpsCnt = 17; 2520 tps_cnt = 17;
2521 else 2521 else
2522 tpsCnt = 68; 2522 tps_cnt = 68;
2523 2523
2524 /* IMER = 100 * log10 (x) 2524 /* IMER = 100 * log10 (x)
2525 where x = (EqRegTdTpsPwrOfs^2 * 2525 where x = (eq_reg_td_tps_pwr_ofs^2 *
2526 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ 2526 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2527 2527
2528 => IMER = a + b -c 2528 => IMER = a + b -c
2529 where a = 100 * log10 (EqRegTdTpsPwrOfs^2) 2529 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2530 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) 2530 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2531 c = 100 * log10 (SqrErrIQ) 2531 c = 100 * log10 (sqr_err_iq)
2532 */ 2532 */
2533 2533
2534 /* log(x) x = 9bits * 9bits->18 bits */ 2534 /* log(x) x = 9bits * 9bits->18 bits */
2535 a = log10times100(EqRegTdTpsPwrOfs * 2535 a = log10times100(eq_reg_td_tps_pwr_ofs *
2536 EqRegTdTpsPwrOfs); 2536 eq_reg_td_tps_pwr_ofs);
2537 /* log(x) x = 16bits * 7bits->23 bits */ 2537 /* log(x) x = 16bits * 7bits->23 bits */
2538 b = log10times100(EqRegTdReqSmbCnt * tpsCnt); 2538 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2539 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ 2539 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2540 c = log10times100(SqrErrIQ); 2540 c = log10times100(sqr_err_iq);
2541 2541
2542 iMER = a + b - c; 2542 i_mer = a + b - c;
2543 } 2543 }
2544 *pSignalToNoise = iMER; 2544 *p_signal_to_noise = i_mer;
2545 2545
2546error: 2546error:
2547 if (status < 0) 2547 if (status < 0)
@@ -2549,17 +2549,17 @@ error:
2549 return status; 2549 return status;
2550} 2550}
2551 2551
2552static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) 2552static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2553{ 2553{
2554 dprintk(1, "\n"); 2554 dprintk(1, "\n");
2555 2555
2556 *pSignalToNoise = 0; 2556 *p_signal_to_noise = 0;
2557 switch (state->m_OperationMode) { 2557 switch (state->m_operation_mode) {
2558 case OM_DVBT: 2558 case OM_DVBT:
2559 return GetDVBTSignalToNoise(state, pSignalToNoise); 2559 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2560 case OM_QAM_ITU_A: 2560 case OM_QAM_ITU_A:
2561 case OM_QAM_ITU_C: 2561 case OM_QAM_ITU_C:
2562 return GetQAMSignalToNoise(state, pSignalToNoise); 2562 return get_qam_signal_to_noise(state, p_signal_to_noise);
2563 default: 2563 default:
2564 break; 2564 break;
2565 } 2565 }
@@ -2567,7 +2567,7 @@ static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2567} 2567}
2568 2568
2569#if 0 2569#if 0
2570static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) 2570static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2571{ 2571{
2572 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ 2572 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2573 int status = 0; 2573 int status = 0;
@@ -2592,102 +2592,102 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2592 225, /* 64-QAM 7/8 */ 2592 225, /* 64-QAM 7/8 */
2593 }; 2593 };
2594 2594
2595 *pQuality = 0; 2595 *p_quality = 0;
2596 2596
2597 do { 2597 do {
2598 s32 SignalToNoise = 0; 2598 s32 signal_to_noise = 0;
2599 u16 Constellation = 0; 2599 u16 constellation = 0;
2600 u16 CodeRate = 0; 2600 u16 code_rate = 0;
2601 u32 SignalToNoiseRel; 2601 u32 signal_to_noise_rel;
2602 u32 BERQuality; 2602 u32 ber_quality;
2603 2603
2604 status = GetDVBTSignalToNoise(state, &SignalToNoise); 2604 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2605 if (status < 0) 2605 if (status < 0)
2606 break; 2606 break;
2607 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation); 2607 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &constellation);
2608 if (status < 0) 2608 if (status < 0)
2609 break; 2609 break;
2610 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2610 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2611 2611
2612 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate); 2612 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &code_rate);
2613 if (status < 0) 2613 if (status < 0)
2614 break; 2614 break;
2615 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2615 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2616 2616
2617 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || 2617 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2618 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) 2618 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2619 break; 2619 break;
2620 SignalToNoiseRel = SignalToNoise - 2620 signal_to_noise_rel = signal_to_noise -
2621 QE_SN[Constellation * 5 + CodeRate]; 2621 QE_SN[constellation * 5 + code_rate];
2622 BERQuality = 100; 2622 ber_quality = 100;
2623 2623
2624 if (SignalToNoiseRel < -70) 2624 if (signal_to_noise_rel < -70)
2625 *pQuality = 0; 2625 *p_quality = 0;
2626 else if (SignalToNoiseRel < 30) 2626 else if (signal_to_noise_rel < 30)
2627 *pQuality = ((SignalToNoiseRel + 70) * 2627 *p_quality = ((signal_to_noise_rel + 70) *
2628 BERQuality) / 100; 2628 ber_quality) / 100;
2629 else 2629 else
2630 *pQuality = BERQuality; 2630 *p_quality = ber_quality;
2631 } while (0); 2631 } while (0);
2632 return 0; 2632 return 0;
2633}; 2633};
2634 2634
2635static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) 2635static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2636{ 2636{
2637 int status = 0; 2637 int status = 0;
2638 *pQuality = 0; 2638 *p_quality = 0;
2639 2639
2640 dprintk(1, "\n"); 2640 dprintk(1, "\n");
2641 2641
2642 do { 2642 do {
2643 u32 SignalToNoise = 0; 2643 u32 signal_to_noise = 0;
2644 u32 BERQuality = 100; 2644 u32 ber_quality = 100;
2645 u32 SignalToNoiseRel = 0; 2645 u32 signal_to_noise_rel = 0;
2646 2646
2647 status = GetQAMSignalToNoise(state, &SignalToNoise); 2647 status = get_qam_signal_to_noise(state, &signal_to_noise);
2648 if (status < 0) 2648 if (status < 0)
2649 break; 2649 break;
2650 2650
2651 switch (state->props.modulation) { 2651 switch (state->props.modulation) {
2652 case QAM_16: 2652 case QAM_16:
2653 SignalToNoiseRel = SignalToNoise - 200; 2653 signal_to_noise_rel = signal_to_noise - 200;
2654 break; 2654 break;
2655 case QAM_32: 2655 case QAM_32:
2656 SignalToNoiseRel = SignalToNoise - 230; 2656 signal_to_noise_rel = signal_to_noise - 230;
2657 break; /* Not in NorDig */ 2657 break; /* Not in NorDig */
2658 case QAM_64: 2658 case QAM_64:
2659 SignalToNoiseRel = SignalToNoise - 260; 2659 signal_to_noise_rel = signal_to_noise - 260;
2660 break; 2660 break;
2661 case QAM_128: 2661 case QAM_128:
2662 SignalToNoiseRel = SignalToNoise - 290; 2662 signal_to_noise_rel = signal_to_noise - 290;
2663 break; 2663 break;
2664 default: 2664 default:
2665 case QAM_256: 2665 case QAM_256:
2666 SignalToNoiseRel = SignalToNoise - 320; 2666 signal_to_noise_rel = signal_to_noise - 320;
2667 break; 2667 break;
2668 } 2668 }
2669 2669
2670 if (SignalToNoiseRel < -70) 2670 if (signal_to_noise_rel < -70)
2671 *pQuality = 0; 2671 *p_quality = 0;
2672 else if (SignalToNoiseRel < 30) 2672 else if (signal_to_noise_rel < 30)
2673 *pQuality = ((SignalToNoiseRel + 70) * 2673 *p_quality = ((signal_to_noise_rel + 70) *
2674 BERQuality) / 100; 2674 ber_quality) / 100;
2675 else 2675 else
2676 *pQuality = BERQuality; 2676 *p_quality = ber_quality;
2677 } while (0); 2677 } while (0);
2678 2678
2679 return status; 2679 return status;
2680} 2680}
2681 2681
2682static int GetQuality(struct drxk_state *state, s32 *pQuality) 2682static int get_quality(struct drxk_state *state, s32 *p_quality)
2683{ 2683{
2684 dprintk(1, "\n"); 2684 dprintk(1, "\n");
2685 2685
2686 switch (state->m_OperationMode) { 2686 switch (state->m_operation_mode) {
2687 case OM_DVBT: 2687 case OM_DVBT:
2688 return GetDVBTQuality(state, pQuality); 2688 return get_dvbt_quality(state, p_quality);
2689 case OM_QAM_ITU_A: 2689 case OM_QAM_ITU_A:
2690 return GetDVBCQuality(state, pQuality); 2690 return get_dvbc_quality(state, p_quality);
2691 default: 2691 default:
2692 break; 2692 break;
2693 } 2693 }
@@ -2709,15 +2709,15 @@ static int GetQuality(struct drxk_state *state, s32 *pQuality)
2709#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) 2709#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2710#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) 2710#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2711 2711
2712static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) 2712static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2713{ 2713{
2714 int status = -EINVAL; 2714 int status = -EINVAL;
2715 2715
2716 dprintk(1, "\n"); 2716 dprintk(1, "\n");
2717 2717
2718 if (state->m_DrxkState == DRXK_UNINITIALIZED) 2718 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2719 return 0; 2719 return 0;
2720 if (state->m_DrxkState == DRXK_POWERED_DOWN) 2720 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2721 goto error; 2721 goto error;
2722 2722
2723 if (state->no_i2c_bridge) 2723 if (state->no_i2c_bridge)
@@ -2726,7 +2726,7 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2727 if (status < 0) 2727 if (status < 0)
2728 goto error; 2728 goto error;
2729 if (bEnableBridge) { 2729 if (b_enable_bridge) {
2730 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2730 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2731 if (status < 0) 2731 if (status < 0)
2732 goto error; 2732 goto error;
@@ -2736,7 +2736,7 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2736 goto error; 2736 goto error;
2737 } 2737 }
2738 2738
2739 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); 2739 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2740 2740
2741error: 2741error:
2742 if (status < 0) 2742 if (status < 0)
@@ -2744,30 +2744,30 @@ error:
2744 return status; 2744 return status;
2745} 2745}
2746 2746
2747static int SetPreSaw(struct drxk_state *state, 2747static int set_pre_saw(struct drxk_state *state,
2748 struct SCfgPreSaw *pPreSawCfg) 2748 struct s_cfg_pre_saw *p_pre_saw_cfg)
2749{ 2749{
2750 int status = -EINVAL; 2750 int status = -EINVAL;
2751 2751
2752 dprintk(1, "\n"); 2752 dprintk(1, "\n");
2753 2753
2754 if ((pPreSawCfg == NULL) 2754 if ((p_pre_saw_cfg == NULL)
2755 || (pPreSawCfg->reference > IQM_AF_PDREF__M)) 2755 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2756 goto error; 2756 goto error;
2757 2757
2758 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); 2758 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2759error: 2759error:
2760 if (status < 0) 2760 if (status < 0)
2761 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 2761 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2762 return status; 2762 return status;
2763} 2763}
2764 2764
2765static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, 2765static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2766 u16 romOffset, u16 nrOfElements, u32 timeOut) 2766 u16 rom_offset, u16 nr_of_elements, u32 time_out)
2767{ 2767{
2768 u16 blStatus = 0; 2768 u16 bl_status = 0;
2769 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF); 2769 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2770 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF); 2770 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2771 int status; 2771 int status;
2772 unsigned long end; 2772 unsigned long end;
2773 2773
@@ -2783,23 +2783,23 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2783 status = write16(state, SIO_BL_TGT_ADDR__A, offset); 2783 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2784 if (status < 0) 2784 if (status < 0)
2785 goto error; 2785 goto error;
2786 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); 2786 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2787 if (status < 0) 2787 if (status < 0)
2788 goto error; 2788 goto error;
2789 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); 2789 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2790 if (status < 0) 2790 if (status < 0)
2791 goto error; 2791 goto error;
2792 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2792 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2793 if (status < 0) 2793 if (status < 0)
2794 goto error; 2794 goto error;
2795 2795
2796 end = jiffies + msecs_to_jiffies(timeOut); 2796 end = jiffies + msecs_to_jiffies(time_out);
2797 do { 2797 do {
2798 status = read16(state, SIO_BL_STATUS__A, &blStatus); 2798 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2799 if (status < 0) 2799 if (status < 0)
2800 goto error; 2800 goto error;
2801 } while ((blStatus == 0x1) && time_is_after_jiffies(end)); 2801 } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2802 if (blStatus == 0x1) { 2802 if (bl_status == 0x1) {
2803 printk(KERN_ERR "drxk: SIO not ready\n"); 2803 printk(KERN_ERR "drxk: SIO not ready\n");
2804 status = -EINVAL; 2804 status = -EINVAL;
2805 goto error2; 2805 goto error2;
@@ -2813,14 +2813,14 @@ error2:
2813 2813
2814} 2814}
2815 2815
2816static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) 2816static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2817{ 2817{
2818 u16 data = 0; 2818 u16 data = 0;
2819 int status; 2819 int status;
2820 2820
2821 dprintk(1, "\n"); 2821 dprintk(1, "\n");
2822 2822
2823 /* Start measurement */ 2823 /* start measurement */
2824 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2824 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2825 if (status < 0) 2825 if (status < 0)
2826 goto error; 2826 goto error;
@@ -2851,38 +2851,38 @@ error:
2851 return status; 2851 return status;
2852} 2852}
2853 2853
2854static int ADCSynchronization(struct drxk_state *state) 2854static int adc_synchronization(struct drxk_state *state)
2855{ 2855{
2856 u16 count = 0; 2856 u16 count = 0;
2857 int status; 2857 int status;
2858 2858
2859 dprintk(1, "\n"); 2859 dprintk(1, "\n");
2860 2860
2861 status = ADCSyncMeasurement(state, &count); 2861 status = adc_sync_measurement(state, &count);
2862 if (status < 0) 2862 if (status < 0)
2863 goto error; 2863 goto error;
2864 2864
2865 if (count == 1) { 2865 if (count == 1) {
2866 /* Try sampling on a diffrent edge */ 2866 /* Try sampling on a diffrent edge */
2867 u16 clkNeg = 0; 2867 u16 clk_neg = 0;
2868 2868
2869 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); 2869 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2870 if (status < 0) 2870 if (status < 0)
2871 goto error; 2871 goto error;
2872 if ((clkNeg & IQM_AF_CLKNEG_CLKNEGDATA__M) == 2872 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2873 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2873 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2874 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2874 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2875 clkNeg |= 2875 clk_neg |=
2876 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; 2876 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2877 } else { 2877 } else {
2878 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2878 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2879 clkNeg |= 2879 clk_neg |=
2880 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2880 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2881 } 2881 }
2882 status = write16(state, IQM_AF_CLKNEG__A, clkNeg); 2882 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2883 if (status < 0) 2883 if (status < 0)
2884 goto error; 2884 goto error;
2885 status = ADCSyncMeasurement(state, &count); 2885 status = adc_sync_measurement(state, &count);
2886 if (status < 0) 2886 if (status < 0)
2887 goto error; 2887 goto error;
2888 } 2888 }
@@ -2895,21 +2895,21 @@ error:
2895 return status; 2895 return status;
2896} 2896}
2897 2897
2898static int SetFrequencyShifter(struct drxk_state *state, 2898static int set_frequency_shifter(struct drxk_state *state,
2899 u16 intermediateFreqkHz, 2899 u16 intermediate_freqk_hz,
2900 s32 tunerFreqOffset, bool isDTV) 2900 s32 tuner_freq_offset, bool is_dtv)
2901{ 2901{
2902 bool selectPosImage = false; 2902 bool select_pos_image = false;
2903 u32 rfFreqResidual = tunerFreqOffset; 2903 u32 rf_freq_residual = tuner_freq_offset;
2904 u32 fmFrequencyShift = 0; 2904 u32 fm_frequency_shift = 0;
2905 bool tunerMirror = !state->m_bMirrorFreqSpect; 2905 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2906 u32 adcFreq; 2906 u32 adc_freq;
2907 bool adcFlip; 2907 bool adc_flip;
2908 int status; 2908 int status;
2909 u32 ifFreqActual; 2909 u32 if_freq_actual;
2910 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); 2910 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2911 u32 frequencyShift; 2911 u32 frequency_shift;
2912 bool imageToSelect; 2912 bool image_to_select;
2913 2913
2914 dprintk(1, "\n"); 2914 dprintk(1, "\n");
2915 2915
@@ -2917,121 +2917,121 @@ static int SetFrequencyShifter(struct drxk_state *state,
2917 Program frequency shifter 2917 Program frequency shifter
2918 No need to account for mirroring on RF 2918 No need to account for mirroring on RF
2919 */ 2919 */
2920 if (isDTV) { 2920 if (is_dtv) {
2921 if ((state->m_OperationMode == OM_QAM_ITU_A) || 2921 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2922 (state->m_OperationMode == OM_QAM_ITU_C) || 2922 (state->m_operation_mode == OM_QAM_ITU_C) ||
2923 (state->m_OperationMode == OM_DVBT)) 2923 (state->m_operation_mode == OM_DVBT))
2924 selectPosImage = true; 2924 select_pos_image = true;
2925 else 2925 else
2926 selectPosImage = false; 2926 select_pos_image = false;
2927 } 2927 }
2928 if (tunerMirror) 2928 if (tuner_mirror)
2929 /* tuner doesn't mirror */ 2929 /* tuner doesn't mirror */
2930 ifFreqActual = intermediateFreqkHz + 2930 if_freq_actual = intermediate_freqk_hz +
2931 rfFreqResidual + fmFrequencyShift; 2931 rf_freq_residual + fm_frequency_shift;
2932 else 2932 else
2933 /* tuner mirrors */ 2933 /* tuner mirrors */
2934 ifFreqActual = intermediateFreqkHz - 2934 if_freq_actual = intermediate_freqk_hz -
2935 rfFreqResidual - fmFrequencyShift; 2935 rf_freq_residual - fm_frequency_shift;
2936 if (ifFreqActual > samplingFrequency / 2) { 2936 if (if_freq_actual > sampling_frequency / 2) {
2937 /* adc mirrors */ 2937 /* adc mirrors */
2938 adcFreq = samplingFrequency - ifFreqActual; 2938 adc_freq = sampling_frequency - if_freq_actual;
2939 adcFlip = true; 2939 adc_flip = true;
2940 } else { 2940 } else {
2941 /* adc doesn't mirror */ 2941 /* adc doesn't mirror */
2942 adcFreq = ifFreqActual; 2942 adc_freq = if_freq_actual;
2943 adcFlip = false; 2943 adc_flip = false;
2944 } 2944 }
2945 2945
2946 frequencyShift = adcFreq; 2946 frequency_shift = adc_freq;
2947 imageToSelect = state->m_rfmirror ^ tunerMirror ^ 2947 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2948 adcFlip ^ selectPosImage; 2948 adc_flip ^ select_pos_image;
2949 state->m_IqmFsRateOfs = 2949 state->m_iqm_fs_rate_ofs =
2950 Frac28a((frequencyShift), samplingFrequency); 2950 Frac28a((frequency_shift), sampling_frequency);
2951 2951
2952 if (imageToSelect) 2952 if (image_to_select)
2953 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; 2953 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2954 2954
2955 /* Program frequency shifter with tuner offset compensation */ 2955 /* Program frequency shifter with tuner offset compensation */
2956 /* frequencyShift += tunerFreqOffset; TODO */ 2956 /* frequency_shift += tuner_freq_offset; TODO */
2957 status = write32(state, IQM_FS_RATE_OFS_LO__A, 2957 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2958 state->m_IqmFsRateOfs); 2958 state->m_iqm_fs_rate_ofs);
2959 if (status < 0) 2959 if (status < 0)
2960 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 2960 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2961 return status; 2961 return status;
2962} 2962}
2963 2963
2964static int InitAGC(struct drxk_state *state, bool isDTV) 2964static int init_agc(struct drxk_state *state, bool is_dtv)
2965{ 2965{
2966 u16 ingainTgt = 0; 2966 u16 ingain_tgt = 0;
2967 u16 ingainTgtMin = 0; 2967 u16 ingain_tgt_min = 0;
2968 u16 ingainTgtMax = 0; 2968 u16 ingain_tgt_max = 0;
2969 u16 clpCyclen = 0; 2969 u16 clp_cyclen = 0;
2970 u16 clpSumMin = 0; 2970 u16 clp_sum_min = 0;
2971 u16 clpDirTo = 0; 2971 u16 clp_dir_to = 0;
2972 u16 snsSumMin = 0; 2972 u16 sns_sum_min = 0;
2973 u16 snsSumMax = 0; 2973 u16 sns_sum_max = 0;
2974 u16 clpSumMax = 0; 2974 u16 clp_sum_max = 0;
2975 u16 snsDirTo = 0; 2975 u16 sns_dir_to = 0;
2976 u16 kiInnergainMin = 0; 2976 u16 ki_innergain_min = 0;
2977 u16 ifIaccuHiTgt = 0; 2977 u16 if_iaccu_hi_tgt = 0;
2978 u16 ifIaccuHiTgtMin = 0; 2978 u16 if_iaccu_hi_tgt_min = 0;
2979 u16 ifIaccuHiTgtMax = 0; 2979 u16 if_iaccu_hi_tgt_max = 0;
2980 u16 data = 0; 2980 u16 data = 0;
2981 u16 fastClpCtrlDelay = 0; 2981 u16 fast_clp_ctrl_delay = 0;
2982 u16 clpCtrlMode = 0; 2982 u16 clp_ctrl_mode = 0;
2983 int status = 0; 2983 int status = 0;
2984 2984
2985 dprintk(1, "\n"); 2985 dprintk(1, "\n");
2986 2986
2987 /* Common settings */ 2987 /* Common settings */
2988 snsSumMax = 1023; 2988 sns_sum_max = 1023;
2989 ifIaccuHiTgtMin = 2047; 2989 if_iaccu_hi_tgt_min = 2047;
2990 clpCyclen = 500; 2990 clp_cyclen = 500;
2991 clpSumMax = 1023; 2991 clp_sum_max = 1023;
2992 2992
2993 /* AGCInit() not available for DVBT; init done in microcode */ 2993 /* AGCInit() not available for DVBT; init done in microcode */
2994 if (!IsQAM(state)) { 2994 if (!is_qam(state)) {
2995 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); 2995 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_operation_mode);
2996 return -EINVAL; 2996 return -EINVAL;
2997 } 2997 }
2998 2998
2999 /* FIXME: Analog TV AGC require different settings */ 2999 /* FIXME: Analog TV AGC require different settings */
3000 3000
3001 /* Standard specific settings */ 3001 /* Standard specific settings */
3002 clpSumMin = 8; 3002 clp_sum_min = 8;
3003 clpDirTo = (u16) -9; 3003 clp_dir_to = (u16) -9;
3004 clpCtrlMode = 0; 3004 clp_ctrl_mode = 0;
3005 snsSumMin = 8; 3005 sns_sum_min = 8;
3006 snsDirTo = (u16) -9; 3006 sns_dir_to = (u16) -9;
3007 kiInnergainMin = (u16) -1030; 3007 ki_innergain_min = (u16) -1030;
3008 ifIaccuHiTgtMax = 0x2380; 3008 if_iaccu_hi_tgt_max = 0x2380;
3009 ifIaccuHiTgt = 0x2380; 3009 if_iaccu_hi_tgt = 0x2380;
3010 ingainTgtMin = 0x0511; 3010 ingain_tgt_min = 0x0511;
3011 ingainTgt = 0x0511; 3011 ingain_tgt = 0x0511;
3012 ingainTgtMax = 5119; 3012 ingain_tgt_max = 5119;
3013 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; 3013 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3014 3014
3015 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); 3015 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fast_clp_ctrl_delay);
3016 if (status < 0) 3016 if (status < 0)
3017 goto error; 3017 goto error;
3018 3018
3019 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); 3019 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3020 if (status < 0) 3020 if (status < 0)
3021 goto error; 3021 goto error;
3022 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); 3022 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3023 if (status < 0) 3023 if (status < 0)
3024 goto error; 3024 goto error;
3025 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); 3025 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3026 if (status < 0) 3026 if (status < 0)
3027 goto error; 3027 goto error;
3028 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); 3028 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3029 if (status < 0) 3029 if (status < 0)
3030 goto error; 3030 goto error;
3031 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); 3031 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min);
3032 if (status < 0) 3032 if (status < 0)
3033 goto error; 3033 goto error;
3034 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); 3034 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, if_iaccu_hi_tgt_max);
3035 if (status < 0) 3035 if (status < 0)
3036 goto error; 3036 goto error;
3037 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3037 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
@@ -3046,20 +3046,20 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
3046 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3046 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3047 if (status < 0) 3047 if (status < 0)
3048 goto error; 3048 goto error;
3049 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); 3049 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3050 if (status < 0) 3050 if (status < 0)
3051 goto error; 3051 goto error;
3052 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); 3052 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3053 if (status < 0) 3053 if (status < 0)
3054 goto error; 3054 goto error;
3055 3055
3056 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); 3056 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min);
3057 if (status < 0) 3057 if (status < 0)
3058 goto error; 3058 goto error;
3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); 3059 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, if_iaccu_hi_tgt);
3060 if (status < 0) 3060 if (status < 0)
3061 goto error; 3061 goto error;
3062 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); 3062 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3063 if (status < 0) 3063 if (status < 0)
3064 goto error; 3064 goto error;
3065 3065
@@ -3076,16 +3076,16 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
3076 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3076 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3077 if (status < 0) 3077 if (status < 0)
3078 goto error; 3078 goto error;
3079 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); 3079 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3080 if (status < 0) 3080 if (status < 0)
3081 goto error; 3081 goto error;
3082 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); 3082 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3083 if (status < 0) 3083 if (status < 0)
3084 goto error; 3084 goto error;
3085 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); 3085 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3086 if (status < 0) 3086 if (status < 0)
3087 goto error; 3087 goto error;
3088 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); 3088 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3089 if (status < 0) 3089 if (status < 0)
3090 goto error; 3090 goto error;
3091 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3091 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
@@ -3149,34 +3149,34 @@ error:
3149 return status; 3149 return status;
3150} 3150}
3151 3151
3152static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) 3152static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3153{ 3153{
3154 int status; 3154 int status;
3155 3155
3156 dprintk(1, "\n"); 3156 dprintk(1, "\n");
3157 if (packetErr == NULL) 3157 if (packet_err == NULL)
3158 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3158 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3159 else 3159 else
3160 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); 3160 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packet_err);
3161 if (status < 0) 3161 if (status < 0)
3162 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 3162 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3163 return status; 3163 return status;
3164} 3164}
3165 3165
3166static int DVBTScCommand(struct drxk_state *state, 3166static int dvbt_sc_command(struct drxk_state *state,
3167 u16 cmd, u16 subcmd, 3167 u16 cmd, u16 subcmd,
3168 u16 param0, u16 param1, u16 param2, 3168 u16 param0, u16 param1, u16 param2,
3169 u16 param3, u16 param4) 3169 u16 param3, u16 param4)
3170{ 3170{
3171 u16 curCmd = 0; 3171 u16 cur_cmd = 0;
3172 u16 errCode = 0; 3172 u16 err_code = 0;
3173 u16 retryCnt = 0; 3173 u16 retry_cnt = 0;
3174 u16 scExec = 0; 3174 u16 sc_exec = 0;
3175 int status; 3175 int status;
3176 3176
3177 dprintk(1, "\n"); 3177 dprintk(1, "\n");
3178 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); 3178 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3179 if (scExec != 1) { 3179 if (sc_exec != 1) {
3180 /* SC is not running */ 3180 /* SC is not running */
3181 status = -EINVAL; 3181 status = -EINVAL;
3182 } 3182 }
@@ -3184,13 +3184,13 @@ static int DVBTScCommand(struct drxk_state *state,
3184 goto error; 3184 goto error;
3185 3185
3186 /* Wait until sc is ready to receive command */ 3186 /* Wait until sc is ready to receive command */
3187 retryCnt = 0; 3187 retry_cnt = 0;
3188 do { 3188 do {
3189 msleep(1); 3189 msleep(1);
3190 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3190 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3191 retryCnt++; 3191 retry_cnt++;
3192 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3192 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3193 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) 3193 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3194 goto error; 3194 goto error;
3195 3195
3196 /* Write sub-command */ 3196 /* Write sub-command */
@@ -3236,18 +3236,18 @@ static int DVBTScCommand(struct drxk_state *state,
3236 goto error; 3236 goto error;
3237 3237
3238 /* Wait until sc is ready processing command */ 3238 /* Wait until sc is ready processing command */
3239 retryCnt = 0; 3239 retry_cnt = 0;
3240 do { 3240 do {
3241 msleep(1); 3241 msleep(1);
3242 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); 3242 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3243 retryCnt++; 3243 retry_cnt++;
3244 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); 3244 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3245 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) 3245 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3246 goto error; 3246 goto error;
3247 3247
3248 /* Check for illegal cmd */ 3248 /* Check for illegal cmd */
3249 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); 3249 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3250 if (errCode == 0xFFFF) { 3250 if (err_code == 0xFFFF) {
3251 /* illegal command */ 3251 /* illegal command */
3252 status = -EINVAL; 3252 status = -EINVAL;
3253 } 3253 }
@@ -3283,19 +3283,19 @@ error:
3283 return status; 3283 return status;
3284} 3284}
3285 3285
3286static int PowerUpDVBT(struct drxk_state *state) 3286static int power_up_dvbt(struct drxk_state *state)
3287{ 3287{
3288 enum DRXPowerMode powerMode = DRX_POWER_UP; 3288 enum drx_power_mode power_mode = DRX_POWER_UP;
3289 int status; 3289 int status;
3290 3290
3291 dprintk(1, "\n"); 3291 dprintk(1, "\n");
3292 status = CtrlPowerMode(state, &powerMode); 3292 status = ctrl_power_mode(state, &power_mode);
3293 if (status < 0) 3293 if (status < 0)
3294 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 3294 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3295 return status; 3295 return status;
3296} 3296}
3297 3297
3298static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) 3298static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3299{ 3299{
3300 int status; 3300 int status;
3301 3301
@@ -3310,7 +3310,7 @@ static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3310} 3310}
3311 3311
3312#define DEFAULT_FR_THRES_8K 4000 3312#define DEFAULT_FR_THRES_8K 4000
3313static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) 3313static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3314{ 3314{
3315 3315
3316 int status; 3316 int status;
@@ -3330,8 +3330,8 @@ static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3330 return status; 3330 return status;
3331} 3331}
3332 3332
3333static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, 3333static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3334 struct DRXKCfgDvbtEchoThres_t *echoThres) 3334 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3335{ 3335{
3336 u16 data = 0; 3336 u16 data = 0;
3337 int status; 3337 int status;
@@ -3341,16 +3341,16 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3341 if (status < 0) 3341 if (status < 0)
3342 goto error; 3342 goto error;
3343 3343
3344 switch (echoThres->fftMode) { 3344 switch (echo_thres->fft_mode) {
3345 case DRX_FFTMODE_2K: 3345 case DRX_FFTMODE_2K:
3346 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; 3346 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3347 data |= ((echoThres->threshold << 3347 data |= ((echo_thres->threshold <<
3348 OFDM_SC_RA_RAM_ECHO_THRES_2K__B) 3348 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3349 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); 3349 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3350 break; 3350 break;
3351 case DRX_FFTMODE_8K: 3351 case DRX_FFTMODE_8K:
3352 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; 3352 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3353 data |= ((echoThres->threshold << 3353 data |= ((echo_thres->threshold <<
3354 OFDM_SC_RA_RAM_ECHO_THRES_8K__B) 3354 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3355 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); 3355 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3356 break; 3356 break;
@@ -3365,8 +3365,8 @@ error:
3365 return status; 3365 return status;
3366} 3366}
3367 3367
3368static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, 3368static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3369 enum DRXKCfgDvbtSqiSpeed *speed) 3369 enum drxk_cfg_dvbt_sqi_speed *speed)
3370{ 3370{
3371 int status = -EINVAL; 3371 int status = -EINVAL;
3372 3372
@@ -3398,29 +3398,29 @@ error:
3398* Called in DVBTSetStandard 3398* Called in DVBTSetStandard
3399* 3399*
3400*/ 3400*/
3401static int DVBTActivatePresets(struct drxk_state *state) 3401static int dvbt_activate_presets(struct drxk_state *state)
3402{ 3402{
3403 int status; 3403 int status;
3404 bool setincenable = false; 3404 bool setincenable = false;
3405 bool setfrenable = true; 3405 bool setfrenable = true;
3406 3406
3407 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K }; 3407 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3408 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K }; 3408 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3409 3409
3410 dprintk(1, "\n"); 3410 dprintk(1, "\n");
3411 status = DVBTCtrlSetIncEnable(state, &setincenable); 3411 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3412 if (status < 0) 3412 if (status < 0)
3413 goto error; 3413 goto error;
3414 status = DVBTCtrlSetFrEnable(state, &setfrenable); 3414 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3415 if (status < 0) 3415 if (status < 0)
3416 goto error; 3416 goto error;
3417 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); 3417 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3418 if (status < 0) 3418 if (status < 0)
3419 goto error; 3419 goto error;
3420 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); 3420 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3421 if (status < 0) 3421 if (status < 0)
3422 goto error; 3422 goto error;
3423 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); 3423 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3424error: 3424error:
3425 if (status < 0) 3425 if (status < 0)
3426 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 3426 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -3437,25 +3437,25 @@ error:
3437* For ROM code channel filter taps are loaded from the bootloader. For microcode 3437* For ROM code channel filter taps are loaded from the bootloader. For microcode
3438* the DVB-T taps from the drxk_filters.h are used. 3438* the DVB-T taps from the drxk_filters.h are used.
3439*/ 3439*/
3440static int SetDVBTStandard(struct drxk_state *state, 3440static int set_dvbt_standard(struct drxk_state *state,
3441 enum OperationMode oMode) 3441 enum operation_mode o_mode)
3442{ 3442{
3443 u16 cmdResult = 0; 3443 u16 cmd_result = 0;
3444 u16 data = 0; 3444 u16 data = 0;
3445 int status; 3445 int status;
3446 3446
3447 dprintk(1, "\n"); 3447 dprintk(1, "\n");
3448 3448
3449 PowerUpDVBT(state); 3449 power_up_dvbt(state);
3450 /* added antenna switch */ 3450 /* added antenna switch */
3451 SwitchAntennaToDVBT(state); 3451 switch_antenna_to_dvbt(state);
3452 /* send OFDM reset command */ 3452 /* send OFDM reset command */
3453 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); 3453 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
3454 if (status < 0) 3454 if (status < 0)
3455 goto error; 3455 goto error;
3456 3456
3457 /* send OFDM setenv command */ 3457 /* send OFDM setenv command */
3458 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult); 3458 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmd_result);
3459 if (status < 0) 3459 if (status < 0)
3460 goto error; 3460 goto error;
3461 3461
@@ -3487,7 +3487,7 @@ static int SetDVBTStandard(struct drxk_state *state,
3487 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3487 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3488 if (status < 0) 3488 if (status < 0)
3489 goto error; 3489 goto error;
3490 status = SetIqmAf(state, true); 3490 status = set_iqm_af(state, true);
3491 if (status < 0) 3491 if (status < 0)
3492 goto error; 3492 goto error;
3493 3493
@@ -3530,7 +3530,7 @@ static int SetDVBTStandard(struct drxk_state *state,
3530 if (status < 0) 3530 if (status < 0)
3531 goto error; 3531 goto error;
3532 3532
3533 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3533 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3534 if (status < 0) 3534 if (status < 0)
3535 goto error; 3535 goto error;
3536 3536
@@ -3549,10 +3549,10 @@ static int SetDVBTStandard(struct drxk_state *state,
3549 goto error; 3549 goto error;
3550 3550
3551 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3551 /* IQM will not be reset from here, sync ADC and update/init AGC */
3552 status = ADCSynchronization(state); 3552 status = adc_synchronization(state);
3553 if (status < 0) 3553 if (status < 0)
3554 goto error; 3554 goto error;
3555 status = SetPreSaw(state, &state->m_dvbtPreSawCfg); 3555 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3556 if (status < 0) 3556 if (status < 0)
3557 goto error; 3557 goto error;
3558 3558
@@ -3561,10 +3561,10 @@ static int SetDVBTStandard(struct drxk_state *state,
3561 if (status < 0) 3561 if (status < 0)
3562 goto error; 3562 goto error;
3563 3563
3564 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); 3564 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3565 if (status < 0) 3565 if (status < 0)
3566 goto error; 3566 goto error;
3567 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); 3567 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3568 if (status < 0) 3568 if (status < 0)
3569 goto error; 3569 goto error;
3570 3570
@@ -3582,9 +3582,9 @@ static int SetDVBTStandard(struct drxk_state *state,
3582 if (status < 0) 3582 if (status < 0)
3583 goto error; 3583 goto error;
3584 3584
3585 if (!state->m_DRXK_A3_ROM_CODE) { 3585 if (!state->m_drxk_a3_rom_code) {
3586 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ 3586 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
3587 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); 3587 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3588 if (status < 0) 3588 if (status < 0)
3589 goto error; 3589 goto error;
3590 } 3590 }
@@ -3619,11 +3619,11 @@ static int SetDVBTStandard(struct drxk_state *state,
3619 goto error; 3619 goto error;
3620 3620
3621 /* Setup MPEG bus */ 3621 /* Setup MPEG bus */
3622 status = MPEGTSDtoSetup(state, OM_DVBT); 3622 status = mpegts_dto_setup(state, OM_DVBT);
3623 if (status < 0) 3623 if (status < 0)
3624 goto error; 3624 goto error;
3625 /* Set DVBT Presets */ 3625 /* Set DVBT Presets */
3626 status = DVBTActivatePresets(state); 3626 status = dvbt_activate_presets(state);
3627 if (status < 0) 3627 if (status < 0)
3628 goto error; 3628 goto error;
3629 3629
@@ -3635,25 +3635,25 @@ error:
3635 3635
3636/*============================================================================*/ 3636/*============================================================================*/
3637/** 3637/**
3638* \brief Start dvbt demodulating for channel. 3638* \brief start dvbt demodulating for channel.
3639* \param demod instance of demodulator. 3639* \param demod instance of demodulator.
3640* \return DRXStatus_t. 3640* \return DRXStatus_t.
3641*/ 3641*/
3642static int DVBTStart(struct drxk_state *state) 3642static int dvbt_start(struct drxk_state *state)
3643{ 3643{
3644 u16 param1; 3644 u16 param1;
3645 int status; 3645 int status;
3646 /* DRXKOfdmScCmd_t scCmd; */ 3646 /* drxk_ofdm_sc_cmd_t scCmd; */
3647 3647
3648 dprintk(1, "\n"); 3648 dprintk(1, "\n");
3649 /* Start correct processes to get in lock */ 3649 /* start correct processes to get in lock */
3650 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3650 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3651 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3651 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3652 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); 3652 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3653 if (status < 0) 3653 if (status < 0)
3654 goto error; 3654 goto error;
3655 /* Start FEC OC */ 3655 /* start FEC OC */
3656 status = MPEGTSStart(state); 3656 status = mpegts_start(state);
3657 if (status < 0) 3657 if (status < 0)
3658 goto error; 3658 goto error;
3659 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3659 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
@@ -3674,20 +3674,20 @@ error:
3674* \return DRXStatus_t. 3674* \return DRXStatus_t.
3675* // original DVBTSetChannel() 3675* // original DVBTSetChannel()
3676*/ 3676*/
3677static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, 3677static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3678 s32 tunerFreqOffset) 3678 s32 tuner_freq_offset)
3679{ 3679{
3680 u16 cmdResult = 0; 3680 u16 cmd_result = 0;
3681 u16 transmissionParams = 0; 3681 u16 transmission_params = 0;
3682 u16 operationMode = 0; 3682 u16 operation_mode = 0;
3683 u32 iqmRcRateOfs = 0; 3683 u32 iqm_rc_rate_ofs = 0;
3684 u32 bandwidth = 0; 3684 u32 bandwidth = 0;
3685 u16 param1; 3685 u16 param1;
3686 int status; 3686 int status;
3687 3687
3688 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset); 3688 dprintk(1, "IF =%d, TFO = %d\n", intermediate_freqk_hz, tuner_freq_offset);
3689 3689
3690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); 3690 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
3691 if (status < 0) 3691 if (status < 0)
3692 goto error; 3692 goto error;
3693 3693
@@ -3716,13 +3716,13 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3716 switch (state->props.transmission_mode) { 3716 switch (state->props.transmission_mode) {
3717 case TRANSMISSION_MODE_AUTO: 3717 case TRANSMISSION_MODE_AUTO:
3718 default: 3718 default:
3719 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; 3719 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3720 /* fall through , try first guess DRX_FFTMODE_8K */ 3720 /* fall through , try first guess DRX_FFTMODE_8K */
3721 case TRANSMISSION_MODE_8K: 3721 case TRANSMISSION_MODE_8K:
3722 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; 3722 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3723 break; 3723 break;
3724 case TRANSMISSION_MODE_2K: 3724 case TRANSMISSION_MODE_2K:
3725 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; 3725 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3726 break; 3726 break;
3727 } 3727 }
3728 3728
@@ -3730,19 +3730,19 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3730 switch (state->props.guard_interval) { 3730 switch (state->props.guard_interval) {
3731 default: 3731 default:
3732 case GUARD_INTERVAL_AUTO: 3732 case GUARD_INTERVAL_AUTO:
3733 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3733 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3734 /* fall through , try first guess DRX_GUARD_1DIV4 */ 3734 /* fall through , try first guess DRX_GUARD_1DIV4 */
3735 case GUARD_INTERVAL_1_4: 3735 case GUARD_INTERVAL_1_4:
3736 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; 3736 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3737 break; 3737 break;
3738 case GUARD_INTERVAL_1_32: 3738 case GUARD_INTERVAL_1_32:
3739 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; 3739 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3740 break; 3740 break;
3741 case GUARD_INTERVAL_1_16: 3741 case GUARD_INTERVAL_1_16:
3742 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; 3742 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3743 break; 3743 break;
3744 case GUARD_INTERVAL_1_8: 3744 case GUARD_INTERVAL_1_8:
3745 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; 3745 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3746 break; 3746 break;
3747 } 3747 }
3748 3748
@@ -3751,18 +3751,18 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3751 case HIERARCHY_AUTO: 3751 case HIERARCHY_AUTO:
3752 case HIERARCHY_NONE: 3752 case HIERARCHY_NONE:
3753 default: 3753 default:
3754 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; 3754 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3755 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ 3755 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3756 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ 3756 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3757 /* break; */ 3757 /* break; */
3758 case HIERARCHY_1: 3758 case HIERARCHY_1:
3759 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; 3759 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3760 break; 3760 break;
3761 case HIERARCHY_2: 3761 case HIERARCHY_2:
3762 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; 3762 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3763 break; 3763 break;
3764 case HIERARCHY_4: 3764 case HIERARCHY_4:
3765 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; 3765 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3766 break; 3766 break;
3767 } 3767 }
3768 3768
@@ -3771,16 +3771,16 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3771 switch (state->props.modulation) { 3771 switch (state->props.modulation) {
3772 case QAM_AUTO: 3772 case QAM_AUTO:
3773 default: 3773 default:
3774 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3774 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3775 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ 3775 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3776 case QAM_64: 3776 case QAM_64:
3777 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; 3777 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3778 break; 3778 break;
3779 case QPSK: 3779 case QPSK:
3780 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; 3780 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3781 break; 3781 break;
3782 case QAM_16: 3782 case QAM_16:
3783 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; 3783 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3784 break; 3784 break;
3785 } 3785 }
3786#if 0 3786#if 0
@@ -3788,13 +3788,13 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3788 /* Priority (only for hierarchical channels) */ 3788 /* Priority (only for hierarchical channels) */
3789 switch (channel->priority) { 3789 switch (channel->priority) {
3790 case DRX_PRIORITY_LOW: 3790 case DRX_PRIORITY_LOW:
3791 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; 3791 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3792 WR16(devAddr, OFDM_EC_SB_PRIOR__A, 3792 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3793 OFDM_EC_SB_PRIOR_LO); 3793 OFDM_EC_SB_PRIOR_LO);
3794 break; 3794 break;
3795 case DRX_PRIORITY_HIGH: 3795 case DRX_PRIORITY_HIGH:
3796 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3796 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3797 WR16(devAddr, OFDM_EC_SB_PRIOR__A, 3797 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3798 OFDM_EC_SB_PRIOR_HI)); 3798 OFDM_EC_SB_PRIOR_HI));
3799 break; 3799 break;
3800 case DRX_PRIORITY_UNKNOWN: /* fall through */ 3800 case DRX_PRIORITY_UNKNOWN: /* fall through */
@@ -3804,7 +3804,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3804 } 3804 }
3805#else 3805#else
3806 /* Set Priorty high */ 3806 /* Set Priorty high */
3807 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3807 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3808 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3808 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3809 if (status < 0) 3809 if (status < 0)
3810 goto error; 3810 goto error;
@@ -3814,22 +3814,22 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3814 switch (state->props.code_rate_HP) { 3814 switch (state->props.code_rate_HP) {
3815 case FEC_AUTO: 3815 case FEC_AUTO:
3816 default: 3816 default:
3817 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3817 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3818 /* fall through , try first guess DRX_CODERATE_2DIV3 */ 3818 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3819 case FEC_2_3: 3819 case FEC_2_3:
3820 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; 3820 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3821 break; 3821 break;
3822 case FEC_1_2: 3822 case FEC_1_2:
3823 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; 3823 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3824 break; 3824 break;
3825 case FEC_3_4: 3825 case FEC_3_4:
3826 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; 3826 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3827 break; 3827 break;
3828 case FEC_5_6: 3828 case FEC_5_6:
3829 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; 3829 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3830 break; 3830 break;
3831 case FEC_7_8: 3831 case FEC_7_8:
3832 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; 3832 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3833 break; 3833 break;
3834 } 3834 }
3835 3835
@@ -3906,7 +3906,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3906 goto error; 3906 goto error;
3907 } 3907 }
3908 3908
3909 if (iqmRcRateOfs == 0) { 3909 if (iqm_rc_rate_ofs == 0) {
3910 /* Now compute IQM_RC_RATE_OFS 3910 /* Now compute IQM_RC_RATE_OFS
3911 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) 3911 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3912 => 3912 =>
@@ -3916,36 +3916,36 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3916 /* assert (MAX(sysClk)/MIN(bandwidth) < 16) 3916 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3917 => assert(MAX(sysClk) < 16*MIN(bandwidth)) 3917 => assert(MAX(sysClk) < 16*MIN(bandwidth))
3918 => assert(109714272 > 48000000) = true so Frac 28 can be used */ 3918 => assert(109714272 > 48000000) = true so Frac 28 can be used */
3919 iqmRcRateOfs = Frac28a((u32) 3919 iqm_rc_rate_ofs = Frac28a((u32)
3920 ((state->m_sysClockFreq * 3920 ((state->m_sys_clock_freq *
3921 1000) / 3), bandwidth); 3921 1000) / 3), bandwidth);
3922 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 3922 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3923 if ((iqmRcRateOfs & 0x7fL) >= 0x40) 3923 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3924 iqmRcRateOfs += 0x80L; 3924 iqm_rc_rate_ofs += 0x80L;
3925 iqmRcRateOfs = iqmRcRateOfs >> 7; 3925 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3926 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ 3926 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
3927 iqmRcRateOfs = iqmRcRateOfs - (1 << 23); 3927 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3928 } 3928 }
3929 3929
3930 iqmRcRateOfs &= 3930 iqm_rc_rate_ofs &=
3931 ((((u32) IQM_RC_RATE_OFS_HI__M) << 3931 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3932 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 3932 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3933 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); 3933 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
3934 if (status < 0) 3934 if (status < 0)
3935 goto error; 3935 goto error;
3936 3936
3937 /* Bandwidth setting done */ 3937 /* Bandwidth setting done */
3938 3938
3939#if 0 3939#if 0
3940 status = DVBTSetFrequencyShift(demod, channel, tunerOffset); 3940 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
3941 if (status < 0) 3941 if (status < 0)
3942 goto error; 3942 goto error;
3943#endif 3943#endif
3944 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); 3944 status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
3945 if (status < 0) 3945 if (status < 0)
3946 goto error; 3946 goto error;
3947 3947
3948 /*== Start SC, write channel settings to SC ===============================*/ 3948 /*== start SC, write channel settings to SC ===============================*/
3949 3949
3950 /* Activate SCU to enable SCU commands */ 3950 /* Activate SCU to enable SCU commands */
3951 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3951 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
@@ -3961,7 +3961,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3961 goto error; 3961 goto error;
3962 3962
3963 3963
3964 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); 3964 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
3965 if (status < 0) 3965 if (status < 0)
3966 goto error; 3966 goto error;
3967 3967
@@ -3971,13 +3971,13 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3971 OFDM_SC_RA_RAM_OP_AUTO_CONST__M | 3971 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
3972 OFDM_SC_RA_RAM_OP_AUTO_HIER__M | 3972 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
3973 OFDM_SC_RA_RAM_OP_AUTO_RATE__M); 3973 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
3974 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 3974 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
3975 0, transmissionParams, param1, 0, 0, 0); 3975 0, transmission_params, param1, 0, 0, 0);
3976 if (status < 0) 3976 if (status < 0)
3977 goto error; 3977 goto error;
3978 3978
3979 if (!state->m_DRXK_A3_ROM_CODE) 3979 if (!state->m_drxk_a3_rom_code)
3980 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); 3980 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
3981error: 3981error:
3982 if (status < 0) 3982 if (status < 0)
3983 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 3983 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -3995,7 +3995,7 @@ error:
3995* \return DRXStatus_t. 3995* \return DRXStatus_t.
3996* 3996*
3997*/ 3997*/
3998static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) 3998static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
3999{ 3999{
4000 int status; 4000 int status;
4001 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | 4001 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
@@ -4003,32 +4003,32 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4003 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); 4003 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4004 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; 4004 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4005 4005
4006 u16 ScRaRamLock = 0; 4006 u16 sc_ra_ram_lock = 0;
4007 u16 ScCommExec = 0; 4007 u16 sc_comm_exec = 0;
4008 4008
4009 dprintk(1, "\n"); 4009 dprintk(1, "\n");
4010 4010
4011 *pLockStatus = NOT_LOCKED; 4011 *p_lock_status = NOT_LOCKED;
4012 /* driver 0.9.0 */ 4012 /* driver 0.9.0 */
4013 /* Check if SC is running */ 4013 /* Check if SC is running */
4014 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); 4014 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4015 if (status < 0) 4015 if (status < 0)
4016 goto end; 4016 goto end;
4017 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) 4017 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4018 goto end; 4018 goto end;
4019 4019
4020 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); 4020 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4021 if (status < 0) 4021 if (status < 0)
4022 goto end; 4022 goto end;
4023 4023
4024 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) 4024 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4025 *pLockStatus = MPEG_LOCK; 4025 *p_lock_status = MPEG_LOCK;
4026 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) 4026 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4027 *pLockStatus = FEC_LOCK; 4027 *p_lock_status = FEC_LOCK;
4028 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) 4028 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4029 *pLockStatus = DEMOD_LOCK; 4029 *p_lock_status = DEMOD_LOCK;
4030 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) 4030 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4031 *pLockStatus = NEVER_LOCK; 4031 *p_lock_status = NEVER_LOCK;
4032end: 4032end:
4033 if (status < 0) 4033 if (status < 0)
4034 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 4034 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -4036,13 +4036,13 @@ end:
4036 return status; 4036 return status;
4037} 4037}
4038 4038
4039static int PowerUpQAM(struct drxk_state *state) 4039static int power_up_qam(struct drxk_state *state)
4040{ 4040{
4041 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; 4041 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4042 int status; 4042 int status;
4043 4043
4044 dprintk(1, "\n"); 4044 dprintk(1, "\n");
4045 status = CtrlPowerMode(state, &powerMode); 4045 status = ctrl_power_mode(state, &power_mode);
4046 if (status < 0) 4046 if (status < 0)
4047 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 4047 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4048 4048
@@ -4051,10 +4051,10 @@ static int PowerUpQAM(struct drxk_state *state)
4051 4051
4052 4052
4053/** Power Down QAM */ 4053/** Power Down QAM */
4054static int PowerDownQAM(struct drxk_state *state) 4054static int power_down_qam(struct drxk_state *state)
4055{ 4055{
4056 u16 data = 0; 4056 u16 data = 0;
4057 u16 cmdResult; 4057 u16 cmd_result;
4058 int status = 0; 4058 int status = 0;
4059 4059
4060 dprintk(1, "\n"); 4060 dprintk(1, "\n");
@@ -4070,12 +4070,12 @@ static int PowerDownQAM(struct drxk_state *state)
4070 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4070 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4071 if (status < 0) 4071 if (status < 0)
4072 goto error; 4072 goto error;
4073 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); 4073 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
4074 if (status < 0) 4074 if (status < 0)
4075 goto error; 4075 goto error;
4076 } 4076 }
4077 /* powerdown AFE */ 4077 /* powerdown AFE */
4078 status = SetIqmAf(state, false); 4078 status = set_iqm_af(state, false);
4079 4079
4080error: 4080error:
4081 if (status < 0) 4081 if (status < 0)
@@ -4097,20 +4097,20 @@ error:
4097* The implementation does not check this. 4097* The implementation does not check this.
4098* 4098*
4099*/ 4099*/
4100static int SetQAMMeasurement(struct drxk_state *state, 4100static int set_qam_measurement(struct drxk_state *state,
4101 enum EDrxkConstellation modulation, 4101 enum e_drxk_constellation modulation,
4102 u32 symbolRate) 4102 u32 symbol_rate)
4103{ 4103{
4104 u32 fecBitsDesired = 0; /* BER accounting period */ 4104 u32 fec_bits_desired = 0; /* BER accounting period */
4105 u32 fecRsPeriodTotal = 0; /* Total period */ 4105 u32 fec_rs_period_total = 0; /* Total period */
4106 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ 4106 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
4107 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ 4107 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
4108 int status = 0; 4108 int status = 0;
4109 4109
4110 dprintk(1, "\n"); 4110 dprintk(1, "\n");
4111 4111
4112 fecRsPrescale = 1; 4112 fec_rs_prescale = 1;
4113 /* fecBitsDesired = symbolRate [kHz] * 4113 /* fec_bits_desired = symbol_rate [kHz] *
4114 FrameLenght [ms] * 4114 FrameLenght [ms] *
4115 (modulation + 1) * 4115 (modulation + 1) *
4116 SyncLoss (== 1) * 4116 SyncLoss (== 1) *
@@ -4118,19 +4118,19 @@ static int SetQAMMeasurement(struct drxk_state *state,
4118 */ 4118 */
4119 switch (modulation) { 4119 switch (modulation) {
4120 case DRX_CONSTELLATION_QAM16: 4120 case DRX_CONSTELLATION_QAM16:
4121 fecBitsDesired = 4 * symbolRate; 4121 fec_bits_desired = 4 * symbol_rate;
4122 break; 4122 break;
4123 case DRX_CONSTELLATION_QAM32: 4123 case DRX_CONSTELLATION_QAM32:
4124 fecBitsDesired = 5 * symbolRate; 4124 fec_bits_desired = 5 * symbol_rate;
4125 break; 4125 break;
4126 case DRX_CONSTELLATION_QAM64: 4126 case DRX_CONSTELLATION_QAM64:
4127 fecBitsDesired = 6 * symbolRate; 4127 fec_bits_desired = 6 * symbol_rate;
4128 break; 4128 break;
4129 case DRX_CONSTELLATION_QAM128: 4129 case DRX_CONSTELLATION_QAM128:
4130 fecBitsDesired = 7 * symbolRate; 4130 fec_bits_desired = 7 * symbol_rate;
4131 break; 4131 break;
4132 case DRX_CONSTELLATION_QAM256: 4132 case DRX_CONSTELLATION_QAM256:
4133 fecBitsDesired = 8 * symbolRate; 4133 fec_bits_desired = 8 * symbol_rate;
4134 break; 4134 break;
4135 default: 4135 default:
4136 status = -EINVAL; 4136 status = -EINVAL;
@@ -4138,40 +4138,40 @@ static int SetQAMMeasurement(struct drxk_state *state,
4138 if (status < 0) 4138 if (status < 0)
4139 goto error; 4139 goto error;
4140 4140
4141 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ 4141 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
4142 fecBitsDesired *= 500; /* meas. period [ms] */ 4142 fec_bits_desired *= 500; /* meas. period [ms] */
4143 4143
4144 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4144 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4145 /* fecRsPeriodTotal = fecBitsDesired / 1632 */ 4145 /* fec_rs_period_total = fec_bits_desired / 1632 */
4146 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */ 4146 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */
4147 4147
4148 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ 4148 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */
4149 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); 4149 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4150 if (fecRsPrescale == 0) { 4150 if (fec_rs_prescale == 0) {
4151 /* Divide by zero (though impossible) */ 4151 /* Divide by zero (though impossible) */
4152 status = -EINVAL; 4152 status = -EINVAL;
4153 if (status < 0) 4153 if (status < 0)
4154 goto error; 4154 goto error;
4155 } 4155 }
4156 fecRsPeriod = 4156 fec_rs_period =
4157 ((u16) fecRsPeriodTotal + 4157 ((u16) fec_rs_period_total +
4158 (fecRsPrescale >> 1)) / fecRsPrescale; 4158 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4159 4159
4160 /* write corresponding registers */ 4160 /* write corresponding registers */
4161 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); 4161 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4162 if (status < 0) 4162 if (status < 0)
4163 goto error; 4163 goto error;
4164 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); 4164 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale);
4165 if (status < 0) 4165 if (status < 0)
4166 goto error; 4166 goto error;
4167 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); 4167 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4168error: 4168error:
4169 if (status < 0) 4169 if (status < 0)
4170 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 4170 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4171 return status; 4171 return status;
4172} 4172}
4173 4173
4174static int SetQAM16(struct drxk_state *state) 4174static int set_qam16(struct drxk_state *state)
4175{ 4175{
4176 int status = 0; 4176 int status = 0;
4177 4177
@@ -4364,7 +4364,7 @@ error:
4364* \param demod instance of demod. 4364* \param demod instance of demod.
4365* \return DRXStatus_t. 4365* \return DRXStatus_t.
4366*/ 4366*/
4367static int SetQAM32(struct drxk_state *state) 4367static int set_qam32(struct drxk_state *state)
4368{ 4368{
4369 int status = 0; 4369 int status = 0;
4370 4370
@@ -4559,7 +4559,7 @@ error:
4559* \param demod instance of demod. 4559* \param demod instance of demod.
4560* \return DRXStatus_t. 4560* \return DRXStatus_t.
4561*/ 4561*/
4562static int SetQAM64(struct drxk_state *state) 4562static int set_qam64(struct drxk_state *state)
4563{ 4563{
4564 int status = 0; 4564 int status = 0;
4565 4565
@@ -4753,7 +4753,7 @@ error:
4753* \param demod: instance of demod. 4753* \param demod: instance of demod.
4754* \return DRXStatus_t. 4754* \return DRXStatus_t.
4755*/ 4755*/
4756static int SetQAM128(struct drxk_state *state) 4756static int set_qam128(struct drxk_state *state)
4757{ 4757{
4758 int status = 0; 4758 int status = 0;
4759 4759
@@ -4949,7 +4949,7 @@ error:
4949* \param demod: instance of demod. 4949* \param demod: instance of demod.
4950* \return DRXStatus_t. 4950* \return DRXStatus_t.
4951*/ 4951*/
4952static int SetQAM256(struct drxk_state *state) 4952static int set_qam256(struct drxk_state *state)
4953{ 4953{
4954 int status = 0; 4954 int status = 0;
4955 4955
@@ -5144,10 +5144,10 @@ error:
5144* \param channel: pointer to channel data. 5144* \param channel: pointer to channel data.
5145* \return DRXStatus_t. 5145* \return DRXStatus_t.
5146*/ 5146*/
5147static int QAMResetQAM(struct drxk_state *state) 5147static int qam_reset_qam(struct drxk_state *state)
5148{ 5148{
5149 int status; 5149 int status;
5150 u16 cmdResult; 5150 u16 cmd_result;
5151 5151
5152 dprintk(1, "\n"); 5152 dprintk(1, "\n");
5153 /* Stop QAM comstate->m_exec */ 5153 /* Stop QAM comstate->m_exec */
@@ -5155,7 +5155,7 @@ static int QAMResetQAM(struct drxk_state *state)
5155 if (status < 0) 5155 if (status < 0)
5156 goto error; 5156 goto error;
5157 5157
5158 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); 5158 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
5159error: 5159error:
5160 if (status < 0) 5160 if (status < 0)
5161 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 5161 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -5170,18 +5170,18 @@ error:
5170* \param channel: pointer to channel data. 5170* \param channel: pointer to channel data.
5171* \return DRXStatus_t. 5171* \return DRXStatus_t.
5172*/ 5172*/
5173static int QAMSetSymbolrate(struct drxk_state *state) 5173static int qam_set_symbolrate(struct drxk_state *state)
5174{ 5174{
5175 u32 adcFrequency = 0; 5175 u32 adc_frequency = 0;
5176 u32 symbFreq = 0; 5176 u32 symb_freq = 0;
5177 u32 iqmRcRate = 0; 5177 u32 iqm_rc_rate = 0;
5178 u16 ratesel = 0; 5178 u16 ratesel = 0;
5179 u32 lcSymbRate = 0; 5179 u32 lc_symb_rate = 0;
5180 int status; 5180 int status;
5181 5181
5182 dprintk(1, "\n"); 5182 dprintk(1, "\n");
5183 /* Select & calculate correct IQM rate */ 5183 /* Select & calculate correct IQM rate */
5184 adcFrequency = (state->m_sysClockFreq * 1000) / 3; 5184 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5185 ratesel = 0; 5185 ratesel = 0;
5186 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ 5186 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5187 if (state->props.symbol_rate <= 1188750) 5187 if (state->props.symbol_rate <= 1188750)
@@ -5197,34 +5197,34 @@ static int QAMSetSymbolrate(struct drxk_state *state)
5197 /* 5197 /*
5198 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5198 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5199 */ 5199 */
5200 symbFreq = state->props.symbol_rate * (1 << ratesel); 5200 symb_freq = state->props.symbol_rate * (1 << ratesel);
5201 if (symbFreq == 0) { 5201 if (symb_freq == 0) {
5202 /* Divide by zero */ 5202 /* Divide by zero */
5203 status = -EINVAL; 5203 status = -EINVAL;
5204 goto error; 5204 goto error;
5205 } 5205 }
5206 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + 5206 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5207 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - 5207 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5208 (1 << 23); 5208 (1 << 23);
5209 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); 5209 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5210 if (status < 0) 5210 if (status < 0)
5211 goto error; 5211 goto error;
5212 state->m_iqmRcRate = iqmRcRate; 5212 state->m_iqm_rc_rate = iqm_rc_rate;
5213 /* 5213 /*
5214 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) 5214 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15))
5215 */ 5215 */
5216 symbFreq = state->props.symbol_rate; 5216 symb_freq = state->props.symbol_rate;
5217 if (adcFrequency == 0) { 5217 if (adc_frequency == 0) {
5218 /* Divide by zero */ 5218 /* Divide by zero */
5219 status = -EINVAL; 5219 status = -EINVAL;
5220 goto error; 5220 goto error;
5221 } 5221 }
5222 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + 5222 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5223 (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 5223 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5224 16); 5224 16);
5225 if (lcSymbRate > 511) 5225 if (lc_symb_rate > 511)
5226 lcSymbRate = 511; 5226 lc_symb_rate = 511;
5227 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); 5227 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5228 5228
5229error: 5229error:
5230 if (status < 0) 5230 if (status < 0)
@@ -5241,34 +5241,34 @@ error:
5241* \return DRXStatus_t. 5241* \return DRXStatus_t.
5242*/ 5242*/
5243 5243
5244static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) 5244static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5245{ 5245{
5246 int status; 5246 int status;
5247 u16 Result[2] = { 0, 0 }; 5247 u16 result[2] = { 0, 0 };
5248 5248
5249 dprintk(1, "\n"); 5249 dprintk(1, "\n");
5250 *pLockStatus = NOT_LOCKED; 5250 *p_lock_status = NOT_LOCKED;
5251 status = scu_command(state, 5251 status = scu_command(state,
5252 SCU_RAM_COMMAND_STANDARD_QAM | 5252 SCU_RAM_COMMAND_STANDARD_QAM |
5253 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, 5253 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5254 Result); 5254 result);
5255 if (status < 0) 5255 if (status < 0)
5256 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 5256 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5257 5257
5258 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { 5258 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5259 /* 0x0000 NOT LOCKED */ 5259 /* 0x0000 NOT LOCKED */
5260 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { 5260 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5261 /* 0x4000 DEMOD LOCKED */ 5261 /* 0x4000 DEMOD LOCKED */
5262 *pLockStatus = DEMOD_LOCK; 5262 *p_lock_status = DEMOD_LOCK;
5263 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { 5263 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5264 /* 0x8000 DEMOD + FEC LOCKED (system lock) */ 5264 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5265 *pLockStatus = MPEG_LOCK; 5265 *p_lock_status = MPEG_LOCK;
5266 } else { 5266 } else {
5267 /* 0xC000 NEVER LOCKED */ 5267 /* 0xC000 NEVER LOCKED */
5268 /* (system will never be able to lock to the signal) */ 5268 /* (system will never be able to lock to the signal) */
5269 /* TODO: check this, intermediate & standard specific lock states are not 5269 /* TODO: check this, intermediate & standard specific lock states are not
5270 taken into account here */ 5270 taken into account here */
5271 *pLockStatus = NEVER_LOCK; 5271 *p_lock_status = NEVER_LOCK;
5272 } 5272 }
5273 return status; 5273 return status;
5274} 5274}
@@ -5280,52 +5280,52 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5280#define QAM_LOCKRANGE__M 0x10 5280#define QAM_LOCKRANGE__M 0x10
5281#define QAM_LOCKRANGE_NORMAL 0x10 5281#define QAM_LOCKRANGE_NORMAL 0x10
5282 5282
5283static int QAMDemodulatorCommand(struct drxk_state *state, 5283static int qam_demodulator_command(struct drxk_state *state,
5284 int numberOfParameters) 5284 int number_of_parameters)
5285{ 5285{
5286 int status; 5286 int status;
5287 u16 cmdResult; 5287 u16 cmd_result;
5288 u16 setParamParameters[4] = { 0, 0, 0, 0 }; 5288 u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5289 5289
5290 setParamParameters[0] = state->m_Constellation; /* modulation */ 5290 set_param_parameters[0] = state->m_constellation; /* modulation */
5291 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5291 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5292 5292
5293 if (numberOfParameters == 2) { 5293 if (number_of_parameters == 2) {
5294 u16 setEnvParameters[1] = { 0 }; 5294 u16 set_env_parameters[1] = { 0 };
5295 5295
5296 if (state->m_OperationMode == OM_QAM_ITU_C) 5296 if (state->m_operation_mode == OM_QAM_ITU_C)
5297 setEnvParameters[0] = QAM_TOP_ANNEX_C; 5297 set_env_parameters[0] = QAM_TOP_ANNEX_C;
5298 else 5298 else
5299 setEnvParameters[0] = QAM_TOP_ANNEX_A; 5299 set_env_parameters[0] = QAM_TOP_ANNEX_A;
5300 5300
5301 status = scu_command(state, 5301 status = scu_command(state,
5302 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 5302 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5303 1, setEnvParameters, 1, &cmdResult); 5303 1, set_env_parameters, 1, &cmd_result);
5304 if (status < 0) 5304 if (status < 0)
5305 goto error; 5305 goto error;
5306 5306
5307 status = scu_command(state, 5307 status = scu_command(state,
5308 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5308 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5309 numberOfParameters, setParamParameters, 5309 number_of_parameters, set_param_parameters,
5310 1, &cmdResult); 5310 1, &cmd_result);
5311 } else if (numberOfParameters == 4) { 5311 } else if (number_of_parameters == 4) {
5312 if (state->m_OperationMode == OM_QAM_ITU_C) 5312 if (state->m_operation_mode == OM_QAM_ITU_C)
5313 setParamParameters[2] = QAM_TOP_ANNEX_C; 5313 set_param_parameters[2] = QAM_TOP_ANNEX_C;
5314 else 5314 else
5315 setParamParameters[2] = QAM_TOP_ANNEX_A; 5315 set_param_parameters[2] = QAM_TOP_ANNEX_A;
5316 5316
5317 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); 5317 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5318 /* Env parameters */ 5318 /* Env parameters */
5319 /* check for LOCKRANGE Extented */ 5319 /* check for LOCKRANGE Extented */
5320 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5320 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5321 5321
5322 status = scu_command(state, 5322 status = scu_command(state,
5323 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5323 SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5324 numberOfParameters, setParamParameters, 5324 number_of_parameters, set_param_parameters,
5325 1, &cmdResult); 5325 1, &cmd_result);
5326 } else { 5326 } else {
5327 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter " 5327 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5328 "count %d\n", numberOfParameters); 5328 "count %d\n", number_of_parameters);
5329 status = -EINVAL; 5329 status = -EINVAL;
5330 } 5330 }
5331 5331
@@ -5336,12 +5336,12 @@ error:
5336 return status; 5336 return status;
5337} 5337}
5338 5338
5339static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, 5339static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5340 s32 tunerFreqOffset) 5340 s32 tuner_freq_offset)
5341{ 5341{
5342 int status; 5342 int status;
5343 u16 cmdResult; 5343 u16 cmd_result;
5344 int qamDemodParamCount = state->qam_demod_parameter_count; 5344 int qam_demod_param_count = state->qam_demod_parameter_count;
5345 5345
5346 dprintk(1, "\n"); 5346 dprintk(1, "\n");
5347 /* 5347 /*
@@ -5356,7 +5356,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5356 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5356 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5357 if (status < 0) 5357 if (status < 0)
5358 goto error; 5358 goto error;
5359 status = QAMResetQAM(state); 5359 status = qam_reset_qam(state);
5360 if (status < 0) 5360 if (status < 0)
5361 goto error; 5361 goto error;
5362 5362
@@ -5365,27 +5365,27 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5365 * -set params; resets IQM,QAM,FEC HW; initializes some 5365 * -set params; resets IQM,QAM,FEC HW; initializes some
5366 * SCU variables 5366 * SCU variables
5367 */ 5367 */
5368 status = QAMSetSymbolrate(state); 5368 status = qam_set_symbolrate(state);
5369 if (status < 0) 5369 if (status < 0)
5370 goto error; 5370 goto error;
5371 5371
5372 /* Set params */ 5372 /* Set params */
5373 switch (state->props.modulation) { 5373 switch (state->props.modulation) {
5374 case QAM_256: 5374 case QAM_256:
5375 state->m_Constellation = DRX_CONSTELLATION_QAM256; 5375 state->m_constellation = DRX_CONSTELLATION_QAM256;
5376 break; 5376 break;
5377 case QAM_AUTO: 5377 case QAM_AUTO:
5378 case QAM_64: 5378 case QAM_64:
5379 state->m_Constellation = DRX_CONSTELLATION_QAM64; 5379 state->m_constellation = DRX_CONSTELLATION_QAM64;
5380 break; 5380 break;
5381 case QAM_16: 5381 case QAM_16:
5382 state->m_Constellation = DRX_CONSTELLATION_QAM16; 5382 state->m_constellation = DRX_CONSTELLATION_QAM16;
5383 break; 5383 break;
5384 case QAM_32: 5384 case QAM_32:
5385 state->m_Constellation = DRX_CONSTELLATION_QAM32; 5385 state->m_constellation = DRX_CONSTELLATION_QAM32;
5386 break; 5386 break;
5387 case QAM_128: 5387 case QAM_128:
5388 state->m_Constellation = DRX_CONSTELLATION_QAM128; 5388 state->m_constellation = DRX_CONSTELLATION_QAM128;
5389 break; 5389 break;
5390 default: 5390 default:
5391 status = -EINVAL; 5391 status = -EINVAL;
@@ -5398,8 +5398,8 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5398 * the correct command. */ 5398 * the correct command. */
5399 if (state->qam_demod_parameter_count == 4 5399 if (state->qam_demod_parameter_count == 4
5400 || !state->qam_demod_parameter_count) { 5400 || !state->qam_demod_parameter_count) {
5401 qamDemodParamCount = 4; 5401 qam_demod_param_count = 4;
5402 status = QAMDemodulatorCommand(state, qamDemodParamCount); 5402 status = qam_demodulator_command(state, qam_demod_param_count);
5403 } 5403 }
5404 5404
5405 /* Use the 2-parameter command if it was requested or if we're 5405 /* Use the 2-parameter command if it was requested or if we're
@@ -5407,8 +5407,8 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5407 * failed. */ 5407 * failed. */
5408 if (state->qam_demod_parameter_count == 2 5408 if (state->qam_demod_parameter_count == 2
5409 || (!state->qam_demod_parameter_count && status < 0)) { 5409 || (!state->qam_demod_parameter_count && status < 0)) {
5410 qamDemodParamCount = 2; 5410 qam_demod_param_count = 2;
5411 status = QAMDemodulatorCommand(state, qamDemodParamCount); 5411 status = qam_demodulator_command(state, qam_demod_param_count);
5412 } 5412 }
5413 5413
5414 if (status < 0) { 5414 if (status < 0) {
@@ -5421,13 +5421,13 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5421 } else if (!state->qam_demod_parameter_count) { 5421 } else if (!state->qam_demod_parameter_count) {
5422 dprintk(1, "Auto-probing the correct QAM demodulator command " 5422 dprintk(1, "Auto-probing the correct QAM demodulator command "
5423 "parameters was successful - using %d parameters.\n", 5423 "parameters was successful - using %d parameters.\n",
5424 qamDemodParamCount); 5424 qam_demod_param_count);
5425 5425
5426 /* 5426 /*
5427 * One of our commands was successful. We don't need to 5427 * One of our commands was successful. We don't need to
5428 * auto-probe anymore, now that we got the correct command. 5428 * auto-probe anymore, now that we got the correct command.
5429 */ 5429 */
5430 state->qam_demod_parameter_count = qamDemodParamCount; 5430 state->qam_demod_parameter_count = qam_demod_param_count;
5431 } 5431 }
5432 5432
5433 /* 5433 /*
@@ -5435,16 +5435,16 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5435 * signal setup modulation independent registers 5435 * signal setup modulation independent registers
5436 */ 5436 */
5437#if 0 5437#if 0
5438 status = SetFrequency(channel, tunerFreqOffset)); 5438 status = set_frequency(channel, tuner_freq_offset));
5439 if (status < 0) 5439 if (status < 0)
5440 goto error; 5440 goto error;
5441#endif 5441#endif
5442 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); 5442 status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
5443 if (status < 0) 5443 if (status < 0)
5444 goto error; 5444 goto error;
5445 5445
5446 /* Setup BER measurement */ 5446 /* Setup BER measurement */
5447 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); 5447 status = set_qam_measurement(state, state->m_constellation, state->props.symbol_rate);
5448 if (status < 0) 5448 if (status < 0)
5449 goto error; 5449 goto error;
5450 5450
@@ -5529,20 +5529,20 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5529 /* STEP 4: modulation specific setup */ 5529 /* STEP 4: modulation specific setup */
5530 switch (state->props.modulation) { 5530 switch (state->props.modulation) {
5531 case QAM_16: 5531 case QAM_16:
5532 status = SetQAM16(state); 5532 status = set_qam16(state);
5533 break; 5533 break;
5534 case QAM_32: 5534 case QAM_32:
5535 status = SetQAM32(state); 5535 status = set_qam32(state);
5536 break; 5536 break;
5537 case QAM_AUTO: 5537 case QAM_AUTO:
5538 case QAM_64: 5538 case QAM_64:
5539 status = SetQAM64(state); 5539 status = set_qam64(state);
5540 break; 5540 break;
5541 case QAM_128: 5541 case QAM_128:
5542 status = SetQAM128(state); 5542 status = set_qam128(state);
5543 break; 5543 break;
5544 case QAM_256: 5544 case QAM_256:
5545 status = SetQAM256(state); 5545 status = set_qam256(state);
5546 break; 5546 break;
5547 default: 5547 default:
5548 status = -EINVAL; 5548 status = -EINVAL;
@@ -5559,12 +5559,12 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5559 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5559 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5560 /* extAttr->currentChannel.modulation = channel->modulation; */ 5560 /* extAttr->currentChannel.modulation = channel->modulation; */
5561 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5561 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5562 status = MPEGTSDtoSetup(state, state->m_OperationMode); 5562 status = mpegts_dto_setup(state, state->m_operation_mode);
5563 if (status < 0) 5563 if (status < 0)
5564 goto error; 5564 goto error;
5565 5565
5566 /* Start processes */ 5566 /* start processes */
5567 status = MPEGTSStart(state); 5567 status = mpegts_start(state);
5568 if (status < 0) 5568 if (status < 0)
5569 goto error; 5569 goto error;
5570 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5570 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
@@ -5578,7 +5578,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5578 goto error; 5578 goto error;
5579 5579
5580 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5580 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5581 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); 5581 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
5582 if (status < 0) 5582 if (status < 0)
5583 goto error; 5583 goto error;
5584 5584
@@ -5591,8 +5591,8 @@ error:
5591 return status; 5591 return status;
5592} 5592}
5593 5593
5594static int SetQAMStandard(struct drxk_state *state, 5594static int set_qam_standard(struct drxk_state *state,
5595 enum OperationMode oMode) 5595 enum operation_mode o_mode)
5596{ 5596{
5597 int status; 5597 int status;
5598#ifdef DRXK_QAM_TAPS 5598#ifdef DRXK_QAM_TAPS
@@ -5604,14 +5604,14 @@ static int SetQAMStandard(struct drxk_state *state,
5604 dprintk(1, "\n"); 5604 dprintk(1, "\n");
5605 5605
5606 /* added antenna switch */ 5606 /* added antenna switch */
5607 SwitchAntennaToQAM(state); 5607 switch_antenna_to_qam(state);
5608 5608
5609 /* Ensure correct power-up mode */ 5609 /* Ensure correct power-up mode */
5610 status = PowerUpQAM(state); 5610 status = power_up_qam(state);
5611 if (status < 0) 5611 if (status < 0)
5612 goto error; 5612 goto error;
5613 /* Reset QAM block */ 5613 /* Reset QAM block */
5614 status = QAMResetQAM(state); 5614 status = qam_reset_qam(state);
5615 if (status < 0) 5615 if (status < 0)
5616 goto error; 5616 goto error;
5617 5617
@@ -5626,15 +5626,15 @@ static int SetQAMStandard(struct drxk_state *state,
5626 5626
5627 /* Upload IQM Channel Filter settings by 5627 /* Upload IQM Channel Filter settings by
5628 boot loader from ROM table */ 5628 boot loader from ROM table */
5629 switch (oMode) { 5629 switch (o_mode) {
5630 case OM_QAM_ITU_A: 5630 case OM_QAM_ITU_A:
5631 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5631 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5632 break; 5632 break;
5633 case OM_QAM_ITU_C: 5633 case OM_QAM_ITU_C:
5634 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5634 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5635 if (status < 0) 5635 if (status < 0)
5636 goto error; 5636 goto error;
5637 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 5637 status = bl_direct_cmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5638 break; 5638 break;
5639 default: 5639 default:
5640 status = -EINVAL; 5640 status = -EINVAL;
@@ -5705,7 +5705,7 @@ static int SetQAMStandard(struct drxk_state *state,
5705 goto error; 5705 goto error;
5706 5706
5707 /* turn on IQMAF. Must be done before setAgc**() */ 5707 /* turn on IQMAF. Must be done before setAgc**() */
5708 status = SetIqmAf(state, true); 5708 status = set_iqm_af(state, true);
5709 if (status < 0) 5709 if (status < 0)
5710 goto error; 5710 goto error;
5711 status = write16(state, IQM_AF_START_LOCK__A, 0x01); 5711 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
@@ -5713,7 +5713,7 @@ static int SetQAMStandard(struct drxk_state *state,
5713 goto error; 5713 goto error;
5714 5714
5715 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5715 /* IQM will not be reset from here, sync ADC and update/init AGC */
5716 status = ADCSynchronization(state); 5716 status = adc_synchronization(state);
5717 if (status < 0) 5717 if (status < 0)
5718 goto error; 5718 goto error;
5719 5719
@@ -5730,18 +5730,18 @@ static int SetQAMStandard(struct drxk_state *state,
5730 /* No more resets of the IQM, current standard correctly set => 5730 /* No more resets of the IQM, current standard correctly set =>
5731 now AGCs can be configured. */ 5731 now AGCs can be configured. */
5732 5732
5733 status = InitAGC(state, true); 5733 status = init_agc(state, true);
5734 if (status < 0) 5734 if (status < 0)
5735 goto error; 5735 goto error;
5736 status = SetPreSaw(state, &(state->m_qamPreSawCfg)); 5736 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5737 if (status < 0) 5737 if (status < 0)
5738 goto error; 5738 goto error;
5739 5739
5740 /* Configure AGC's */ 5740 /* Configure AGC's */
5741 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); 5741 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5742 if (status < 0) 5742 if (status < 0)
5743 goto error; 5743 goto error;
5744 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); 5744 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5745 if (status < 0) 5745 if (status < 0)
5746 goto error; 5746 goto error;
5747 5747
@@ -5753,7 +5753,7 @@ error:
5753 return status; 5753 return status;
5754} 5754}
5755 5755
5756static int WriteGPIO(struct drxk_state *state) 5756static int write_gpio(struct drxk_state *state)
5757{ 5757{
5758 int status; 5758 int status;
5759 u16 value = 0; 5759 u16 value = 0;
@@ -5769,10 +5769,10 @@ static int WriteGPIO(struct drxk_state *state)
5769 if (status < 0) 5769 if (status < 0)
5770 goto error; 5770 goto error;
5771 5771
5772 if (state->m_hasSAWSW) { 5772 if (state->m_has_sawsw) {
5773 if (state->UIO_mask & 0x0001) { /* UIO-1 */ 5773 if (state->uio_mask & 0x0001) { /* UIO-1 */
5774 /* write to io pad configuration register - output mode */ 5774 /* write to io pad configuration register - output mode */
5775 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); 5775 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_gpio_cfg);
5776 if (status < 0) 5776 if (status < 0)
5777 goto error; 5777 goto error;
5778 5778
@@ -5780,7 +5780,7 @@ static int WriteGPIO(struct drxk_state *state)
5780 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5780 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5781 if (status < 0) 5781 if (status < 0)
5782 goto error; 5782 goto error;
5783 if ((state->m_GPIO & 0x0001) == 0) 5783 if ((state->m_gpio & 0x0001) == 0)
5784 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 5784 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5785 else 5785 else
5786 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5786 value |= 0x8000; /* write one to 15th bit - 1st UIO */
@@ -5789,9 +5789,9 @@ static int WriteGPIO(struct drxk_state *state)
5789 if (status < 0) 5789 if (status < 0)
5790 goto error; 5790 goto error;
5791 } 5791 }
5792 if (state->UIO_mask & 0x0002) { /* UIO-2 */ 5792 if (state->uio_mask & 0x0002) { /* UIO-2 */
5793 /* write to io pad configuration register - output mode */ 5793 /* write to io pad configuration register - output mode */
5794 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg); 5794 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_gpio_cfg);
5795 if (status < 0) 5795 if (status < 0)
5796 goto error; 5796 goto error;
5797 5797
@@ -5799,7 +5799,7 @@ static int WriteGPIO(struct drxk_state *state)
5799 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5799 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5800 if (status < 0) 5800 if (status < 0)
5801 goto error; 5801 goto error;
5802 if ((state->m_GPIO & 0x0002) == 0) 5802 if ((state->m_gpio & 0x0002) == 0)
5803 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ 5803 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5804 else 5804 else
5805 value |= 0x4000; /* write one to 14th bit - 2st UIO */ 5805 value |= 0x4000; /* write one to 14th bit - 2st UIO */
@@ -5808,9 +5808,9 @@ static int WriteGPIO(struct drxk_state *state)
5808 if (status < 0) 5808 if (status < 0)
5809 goto error; 5809 goto error;
5810 } 5810 }
5811 if (state->UIO_mask & 0x0004) { /* UIO-3 */ 5811 if (state->uio_mask & 0x0004) { /* UIO-3 */
5812 /* write to io pad configuration register - output mode */ 5812 /* write to io pad configuration register - output mode */
5813 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg); 5813 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_gpio_cfg);
5814 if (status < 0) 5814 if (status < 0)
5815 goto error; 5815 goto error;
5816 5816
@@ -5818,7 +5818,7 @@ static int WriteGPIO(struct drxk_state *state)
5818 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5818 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5819 if (status < 0) 5819 if (status < 0)
5820 goto error; 5820 goto error;
5821 if ((state->m_GPIO & 0x0004) == 0) 5821 if ((state->m_gpio & 0x0004) == 0)
5822 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ 5822 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5823 else 5823 else
5824 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ 5824 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
@@ -5836,7 +5836,7 @@ error:
5836 return status; 5836 return status;
5837} 5837}
5838 5838
5839static int SwitchAntennaToQAM(struct drxk_state *state) 5839static int switch_antenna_to_qam(struct drxk_state *state)
5840{ 5840{
5841 int status = 0; 5841 int status = 0;
5842 bool gpio_state; 5842 bool gpio_state;
@@ -5846,22 +5846,22 @@ static int SwitchAntennaToQAM(struct drxk_state *state)
5846 if (!state->antenna_gpio) 5846 if (!state->antenna_gpio)
5847 return 0; 5847 return 0;
5848 5848
5849 gpio_state = state->m_GPIO & state->antenna_gpio; 5849 gpio_state = state->m_gpio & state->antenna_gpio;
5850 5850
5851 if (state->antenna_dvbt ^ gpio_state) { 5851 if (state->antenna_dvbt ^ gpio_state) {
5852 /* Antenna is on DVB-T mode. Switch */ 5852 /* Antenna is on DVB-T mode. Switch */
5853 if (state->antenna_dvbt) 5853 if (state->antenna_dvbt)
5854 state->m_GPIO &= ~state->antenna_gpio; 5854 state->m_gpio &= ~state->antenna_gpio;
5855 else 5855 else
5856 state->m_GPIO |= state->antenna_gpio; 5856 state->m_gpio |= state->antenna_gpio;
5857 status = WriteGPIO(state); 5857 status = write_gpio(state);
5858 } 5858 }
5859 if (status < 0) 5859 if (status < 0)
5860 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 5860 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5861 return status; 5861 return status;
5862} 5862}
5863 5863
5864static int SwitchAntennaToDVBT(struct drxk_state *state) 5864static int switch_antenna_to_dvbt(struct drxk_state *state)
5865{ 5865{
5866 int status = 0; 5866 int status = 0;
5867 bool gpio_state; 5867 bool gpio_state;
@@ -5871,15 +5871,15 @@ static int SwitchAntennaToDVBT(struct drxk_state *state)
5871 if (!state->antenna_gpio) 5871 if (!state->antenna_gpio)
5872 return 0; 5872 return 0;
5873 5873
5874 gpio_state = state->m_GPIO & state->antenna_gpio; 5874 gpio_state = state->m_gpio & state->antenna_gpio;
5875 5875
5876 if (!(state->antenna_dvbt ^ gpio_state)) { 5876 if (!(state->antenna_dvbt ^ gpio_state)) {
5877 /* Antenna is on DVB-C mode. Switch */ 5877 /* Antenna is on DVB-C mode. Switch */
5878 if (state->antenna_dvbt) 5878 if (state->antenna_dvbt)
5879 state->m_GPIO |= state->antenna_gpio; 5879 state->m_gpio |= state->antenna_gpio;
5880 else 5880 else
5881 state->m_GPIO &= ~state->antenna_gpio; 5881 state->m_gpio &= ~state->antenna_gpio;
5882 status = WriteGPIO(state); 5882 status = write_gpio(state);
5883 } 5883 }
5884 if (status < 0) 5884 if (status < 0)
5885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 5885 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -5887,7 +5887,7 @@ static int SwitchAntennaToDVBT(struct drxk_state *state)
5887} 5887}
5888 5888
5889 5889
5890static int PowerDownDevice(struct drxk_state *state) 5890static int power_down_device(struct drxk_state *state)
5891{ 5891{
5892 /* Power down to requested mode */ 5892 /* Power down to requested mode */
5893 /* Backup some register settings */ 5893 /* Backup some register settings */
@@ -5898,14 +5898,14 @@ static int PowerDownDevice(struct drxk_state *state)
5898 int status; 5898 int status;
5899 5899
5900 dprintk(1, "\n"); 5900 dprintk(1, "\n");
5901 if (state->m_bPDownOpenBridge) { 5901 if (state->m_b_p_down_open_bridge) {
5902 /* Open I2C bridge before power down of DRXK */ 5902 /* Open I2C bridge before power down of DRXK */
5903 status = ConfigureI2CBridge(state, true); 5903 status = ConfigureI2CBridge(state, true);
5904 if (status < 0) 5904 if (status < 0)
5905 goto error; 5905 goto error;
5906 } 5906 }
5907 /* driver 0.9.0 */ 5907 /* driver 0.9.0 */
5908 status = DVBTEnableOFDMTokenRing(state, false); 5908 status = dvbt_enable_ofdm_token_ring(state, false);
5909 if (status < 0) 5909 if (status < 0)
5910 goto error; 5910 goto error;
5911 5911
@@ -5915,8 +5915,8 @@ static int PowerDownDevice(struct drxk_state *state)
5915 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 5915 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5916 if (status < 0) 5916 if (status < 0)
5917 goto error; 5917 goto error;
5918 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 5918 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5919 status = HI_CfgCommand(state); 5919 status = hi_cfg_command(state);
5920error: 5920error:
5921 if (status < 0) 5921 if (status < 0)
5922 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 5922 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
@@ -5927,16 +5927,16 @@ error:
5927static int init_drxk(struct drxk_state *state) 5927static int init_drxk(struct drxk_state *state)
5928{ 5928{
5929 int status = 0, n = 0; 5929 int status = 0, n = 0;
5930 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; 5930 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
5931 u16 driverVersion; 5931 u16 driver_version;
5932 5932
5933 dprintk(1, "\n"); 5933 dprintk(1, "\n");
5934 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { 5934 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {
5935 drxk_i2c_lock(state); 5935 drxk_i2c_lock(state);
5936 status = PowerUpDevice(state); 5936 status = power_up_device(state);
5937 if (status < 0) 5937 if (status < 0)
5938 goto error; 5938 goto error;
5939 status = DRXX_Open(state); 5939 status = drxx_open(state);
5940 if (status < 0) 5940 if (status < 0)
5941 goto error; 5941 goto error;
5942 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 5942 /* Soft reset of OFDM-, sys- and osc-clockdomain */
@@ -5948,29 +5948,29 @@ static int init_drxk(struct drxk_state *state)
5948 goto error; 5948 goto error;
5949 /* TODO is this needed, if yes how much delay in worst case scenario */ 5949 /* TODO is this needed, if yes how much delay in worst case scenario */
5950 msleep(1); 5950 msleep(1);
5951 state->m_DRXK_A3_PATCH_CODE = true; 5951 state->m_drxk_a3_patch_code = true;
5952 status = GetDeviceCapabilities(state); 5952 status = get_device_capabilities(state);
5953 if (status < 0) 5953 if (status < 0)
5954 goto error; 5954 goto error;
5955 5955
5956 /* Bridge delay, uses oscilator clock */ 5956 /* Bridge delay, uses oscilator clock */
5957 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 5957 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5958 /* SDA brdige delay */ 5958 /* SDA brdige delay */
5959 state->m_HICfgBridgeDelay = 5959 state->m_hi_cfg_bridge_delay =
5960 (u16) ((state->m_oscClockFreq / 1000) * 5960 (u16) ((state->m_osc_clock_freq / 1000) *
5961 HI_I2C_BRIDGE_DELAY) / 1000; 5961 HI_I2C_BRIDGE_DELAY) / 1000;
5962 /* Clipping */ 5962 /* Clipping */
5963 if (state->m_HICfgBridgeDelay > 5963 if (state->m_hi_cfg_bridge_delay >
5964 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { 5964 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5965 state->m_HICfgBridgeDelay = 5965 state->m_hi_cfg_bridge_delay =
5966 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 5966 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5967 } 5967 }
5968 /* SCL bridge delay, same as SDA for now */ 5968 /* SCL bridge delay, same as SDA for now */
5969 state->m_HICfgBridgeDelay += 5969 state->m_hi_cfg_bridge_delay +=
5970 state->m_HICfgBridgeDelay << 5970 state->m_hi_cfg_bridge_delay <<
5971 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; 5971 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5972 5972
5973 status = InitHI(state); 5973 status = init_hi(state);
5974 if (status < 0) 5974 if (status < 0)
5975 goto error; 5975 goto error;
5976 /* disable various processes */ 5976 /* disable various processes */
@@ -5985,7 +5985,7 @@ static int init_drxk(struct drxk_state *state)
5985 } 5985 }
5986 5986
5987 /* disable MPEG port */ 5987 /* disable MPEG port */
5988 status = MPEGTSDisable(state); 5988 status = mpegts_disable(state);
5989 if (status < 0) 5989 if (status < 0)
5990 goto error; 5990 goto error;
5991 5991
@@ -6006,12 +6006,12 @@ static int init_drxk(struct drxk_state *state)
6006 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); 6006 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6007 if (status < 0) 6007 if (status < 0)
6008 goto error; 6008 goto error;
6009 status = BLChainCmd(state, 0, 6, 100); 6009 status = bl_chain_cmd(state, 0, 6, 100);
6010 if (status < 0) 6010 if (status < 0)
6011 goto error; 6011 goto error;
6012 6012
6013 if (state->fw) { 6013 if (state->fw) {
6014 status = DownloadMicrocode(state, state->fw->data, 6014 status = download_microcode(state, state->fw->data,
6015 state->fw->size); 6015 state->fw->size);
6016 if (status < 0) 6016 if (status < 0)
6017 goto error; 6017 goto error;
@@ -6026,14 +6026,14 @@ static int init_drxk(struct drxk_state *state)
6026 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 6026 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6027 if (status < 0) 6027 if (status < 0)
6028 goto error; 6028 goto error;
6029 status = DRXX_Open(state); 6029 status = drxx_open(state);
6030 if (status < 0) 6030 if (status < 0)
6031 goto error; 6031 goto error;
6032 /* added for test */ 6032 /* added for test */
6033 msleep(30); 6033 msleep(30);
6034 6034
6035 powerMode = DRXK_POWER_DOWN_OFDM; 6035 power_mode = DRXK_POWER_DOWN_OFDM;
6036 status = CtrlPowerMode(state, &powerMode); 6036 status = ctrl_power_mode(state, &power_mode);
6037 if (status < 0) 6037 if (status < 0)
6038 goto error; 6038 goto error;
6039 6039
@@ -6043,20 +6043,20 @@ static int init_drxk(struct drxk_state *state)
6043 Not using SCU command interface for SCU register access since no 6043 Not using SCU command interface for SCU register access since no
6044 microcode may be present. 6044 microcode may be present.
6045 */ 6045 */
6046 driverVersion = 6046 driver_version =
6047 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + 6047 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6048 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6048 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6049 ((DRXK_VERSION_MAJOR % 10) << 4) + 6049 ((DRXK_VERSION_MAJOR % 10) << 4) +
6050 (DRXK_VERSION_MINOR % 10); 6050 (DRXK_VERSION_MINOR % 10);
6051 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); 6051 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driver_version);
6052 if (status < 0) 6052 if (status < 0)
6053 goto error; 6053 goto error;
6054 driverVersion = 6054 driver_version =
6055 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + 6055 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6056 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6056 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6057 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6057 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6058 (DRXK_VERSION_PATCH % 10); 6058 (DRXK_VERSION_PATCH % 10);
6059 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); 6059 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driver_version);
6060 if (status < 0) 6060 if (status < 0)
6061 goto error; 6061 goto error;
6062 6062
@@ -6069,7 +6069,7 @@ static int init_drxk(struct drxk_state *state)
6069 before calling DRX_Open. This solution requires changes to RF AGC speed 6069 before calling DRX_Open. This solution requires changes to RF AGC speed
6070 to be done via the CTRL function after calling DRX_Open */ 6070 to be done via the CTRL function after calling DRX_Open */
6071 6071
6072 /* m_dvbtRfAgcCfg.speed = 3; */ 6072 /* m_dvbt_rf_agc_cfg.speed = 3; */
6073 6073
6074 /* Reset driver debug flags to 0 */ 6074 /* Reset driver debug flags to 0 */
6075 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6075 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
@@ -6082,42 +6082,42 @@ static int init_drxk(struct drxk_state *state)
6082 if (status < 0) 6082 if (status < 0)
6083 goto error; 6083 goto error;
6084 /* MPEGTS functions are still the same */ 6084 /* MPEGTS functions are still the same */
6085 status = MPEGTSDtoInit(state); 6085 status = mpegts_dto_init(state);
6086 if (status < 0) 6086 if (status < 0)
6087 goto error; 6087 goto error;
6088 status = MPEGTSStop(state); 6088 status = mpegts_stop(state);
6089 if (status < 0) 6089 if (status < 0)
6090 goto error; 6090 goto error;
6091 status = MPEGTSConfigurePolarity(state); 6091 status = mpegts_configure_polarity(state);
6092 if (status < 0) 6092 if (status < 0)
6093 goto error; 6093 goto error;
6094 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); 6094 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6095 if (status < 0) 6095 if (status < 0)
6096 goto error; 6096 goto error;
6097 /* added: configure GPIO */ 6097 /* added: configure GPIO */
6098 status = WriteGPIO(state); 6098 status = write_gpio(state);
6099 if (status < 0) 6099 if (status < 0)
6100 goto error; 6100 goto error;
6101 6101
6102 state->m_DrxkState = DRXK_STOPPED; 6102 state->m_drxk_state = DRXK_STOPPED;
6103 6103
6104 if (state->m_bPowerDown) { 6104 if (state->m_b_power_down) {
6105 status = PowerDownDevice(state); 6105 status = power_down_device(state);
6106 if (status < 0) 6106 if (status < 0)
6107 goto error; 6107 goto error;
6108 state->m_DrxkState = DRXK_POWERED_DOWN; 6108 state->m_drxk_state = DRXK_POWERED_DOWN;
6109 } else 6109 } else
6110 state->m_DrxkState = DRXK_STOPPED; 6110 state->m_drxk_state = DRXK_STOPPED;
6111 6111
6112 /* Initialize the supported delivery systems */ 6112 /* Initialize the supported delivery systems */
6113 n = 0; 6113 n = 0;
6114 if (state->m_hasDVBC) { 6114 if (state->m_has_dvbc) {
6115 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; 6115 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6116 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; 6116 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6117 strlcat(state->frontend.ops.info.name, " DVB-C", 6117 strlcat(state->frontend.ops.info.name, " DVB-C",
6118 sizeof(state->frontend.ops.info.name)); 6118 sizeof(state->frontend.ops.info.name));
6119 } 6119 }
6120 if (state->m_hasDVBT) { 6120 if (state->m_has_dvbt) {
6121 state->frontend.ops.delsys[n++] = SYS_DVBT; 6121 state->frontend.ops.delsys[n++] = SYS_DVBT;
6122 strlcat(state->frontend.ops.info.name, " DVB-T", 6122 strlcat(state->frontend.ops.info.name, " DVB-T",
6123 sizeof(state->frontend.ops.info.name)); 6123 sizeof(state->frontend.ops.info.name));
@@ -6126,7 +6126,7 @@ static int init_drxk(struct drxk_state *state)
6126 } 6126 }
6127error: 6127error:
6128 if (status < 0) { 6128 if (status < 0) {
6129 state->m_DrxkState = DRXK_NO_DEV; 6129 state->m_drxk_state = DRXK_NO_DEV;
6130 drxk_i2c_unlock(state); 6130 drxk_i2c_unlock(state);
6131 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); 6131 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6132 } 6132 }
@@ -6182,12 +6182,12 @@ static int drxk_sleep(struct dvb_frontend *fe)
6182 6182
6183 dprintk(1, "\n"); 6183 dprintk(1, "\n");
6184 6184
6185 if (state->m_DrxkState == DRXK_NO_DEV) 6185 if (state->m_drxk_state == DRXK_NO_DEV)
6186 return -ENODEV; 6186 return -ENODEV;
6187 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6187 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6188 return 0; 6188 return 0;
6189 6189
6190 ShutDown(state); 6190 shut_down(state);
6191 return 0; 6191 return 0;
6192} 6192}
6193 6193
@@ -6197,7 +6197,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6197 6197
6198 dprintk(1, ": %s\n", enable ? "enable" : "disable"); 6198 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6199 6199
6200 if (state->m_DrxkState == DRXK_NO_DEV) 6200 if (state->m_drxk_state == DRXK_NO_DEV)
6201 return -ENODEV; 6201 return -ENODEV;
6202 6202
6203 return ConfigureI2CBridge(state, enable ? true : false); 6203 return ConfigureI2CBridge(state, enable ? true : false);
@@ -6212,10 +6212,10 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
6212 6212
6213 dprintk(1, "\n"); 6213 dprintk(1, "\n");
6214 6214
6215 if (state->m_DrxkState == DRXK_NO_DEV) 6215 if (state->m_drxk_state == DRXK_NO_DEV)
6216 return -ENODEV; 6216 return -ENODEV;
6217 6217
6218 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6218 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6219 return -EAGAIN; 6219 return -EAGAIN;
6220 6220
6221 if (!fe->ops.tuner_ops.get_if_frequency) { 6221 if (!fe->ops.tuner_ops.get_if_frequency) {
@@ -6235,22 +6235,22 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
6235 state->props = *p; 6235 state->props = *p;
6236 6236
6237 if (old_delsys != delsys) { 6237 if (old_delsys != delsys) {
6238 ShutDown(state); 6238 shut_down(state);
6239 switch (delsys) { 6239 switch (delsys) {
6240 case SYS_DVBC_ANNEX_A: 6240 case SYS_DVBC_ANNEX_A:
6241 case SYS_DVBC_ANNEX_C: 6241 case SYS_DVBC_ANNEX_C:
6242 if (!state->m_hasDVBC) 6242 if (!state->m_has_dvbc)
6243 return -EINVAL; 6243 return -EINVAL;
6244 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; 6244 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6245 if (state->m_itut_annex_c) 6245 if (state->m_itut_annex_c)
6246 SetOperationMode(state, OM_QAM_ITU_C); 6246 setoperation_mode(state, OM_QAM_ITU_C);
6247 else 6247 else
6248 SetOperationMode(state, OM_QAM_ITU_A); 6248 setoperation_mode(state, OM_QAM_ITU_A);
6249 break; 6249 break;
6250 case SYS_DVBT: 6250 case SYS_DVBT:
6251 if (!state->m_hasDVBT) 6251 if (!state->m_has_dvbt)
6252 return -EINVAL; 6252 return -EINVAL;
6253 SetOperationMode(state, OM_DVBT); 6253 setoperation_mode(state, OM_DVBT);
6254 break; 6254 break;
6255 default: 6255 default:
6256 return -EINVAL; 6256 return -EINVAL;
@@ -6258,7 +6258,7 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
6258 } 6258 }
6259 6259
6260 fe->ops.tuner_ops.get_if_frequency(fe, &IF); 6260 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6261 Start(state, 0, IF); 6261 start(state, 0, IF);
6262 6262
6263 /* After set_frontend, stats aren't avaliable */ 6263 /* After set_frontend, stats aren't avaliable */
6264 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6264 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
@@ -6278,31 +6278,31 @@ static int drxk_set_parameters(struct dvb_frontend *fe)
6278static int get_strength(struct drxk_state *state, u64 *strength) 6278static int get_strength(struct drxk_state *state, u64 *strength)
6279{ 6279{
6280 int status; 6280 int status;
6281 struct SCfgAgc rfAgc, ifAgc; 6281 struct s_cfg_agc rf_agc, if_agc;
6282 u32 totalGain = 0; 6282 u32 total_gain = 0;
6283 u32 atten = 0; 6283 u32 atten = 0;
6284 u32 agcRange = 0; 6284 u32 agc_range = 0;
6285 u16 scu_lvl = 0; 6285 u16 scu_lvl = 0;
6286 u16 scu_coc = 0; 6286 u16 scu_coc = 0;
6287 /* FIXME: those are part of the tuner presets */ 6287 /* FIXME: those are part of the tuner presets */
6288 u16 tunerRfGain = 50; /* Default value on az6007 driver */ 6288 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */
6289 u16 tunerIfGain = 40; /* Default value on az6007 driver */ 6289 u16 tuner_if_gain = 40; /* Default value on az6007 driver */
6290 6290
6291 *strength = 0; 6291 *strength = 0;
6292 6292
6293 if (IsDVBT(state)) { 6293 if (is_dvbt(state)) {
6294 rfAgc = state->m_dvbtRfAgcCfg; 6294 rf_agc = state->m_dvbt_rf_agc_cfg;
6295 ifAgc = state->m_dvbtIfAgcCfg; 6295 if_agc = state->m_dvbt_if_agc_cfg;
6296 } else if (IsQAM(state)) { 6296 } else if (is_qam(state)) {
6297 rfAgc = state->m_qamRfAgcCfg; 6297 rf_agc = state->m_qam_rf_agc_cfg;
6298 ifAgc = state->m_qamIfAgcCfg; 6298 if_agc = state->m_qam_if_agc_cfg;
6299 } else { 6299 } else {
6300 rfAgc = state->m_atvRfAgcCfg; 6300 rf_agc = state->m_atv_rf_agc_cfg;
6301 ifAgc = state->m_atvIfAgcCfg; 6301 if_agc = state->m_atv_if_agc_cfg;
6302 } 6302 }
6303 6303
6304 if (rfAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) { 6304 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6305 /* SCU outputLevel */ 6305 /* SCU output_level */
6306 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); 6306 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6307 if (status < 0) 6307 if (status < 0)
6308 return status; 6308 return status;
@@ -6313,54 +6313,54 @@ static int get_strength(struct drxk_state *state, u64 *strength)
6313 return status; 6313 return status;
6314 6314
6315 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) 6315 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6316 rfAgc.outputLevel = scu_lvl + scu_coc; 6316 rf_agc.output_level = scu_lvl + scu_coc;
6317 else 6317 else
6318 rfAgc.outputLevel = 0xffff; 6318 rf_agc.output_level = 0xffff;
6319 6319
6320 /* Take RF gain into account */ 6320 /* Take RF gain into account */
6321 totalGain += tunerRfGain; 6321 total_gain += tuner_rf_gain;
6322 6322
6323 /* clip output value */ 6323 /* clip output value */
6324 if (rfAgc.outputLevel < rfAgc.minOutputLevel) 6324 if (rf_agc.output_level < rf_agc.min_output_level)
6325 rfAgc.outputLevel = rfAgc.minOutputLevel; 6325 rf_agc.output_level = rf_agc.min_output_level;
6326 if (rfAgc.outputLevel > rfAgc.maxOutputLevel) 6326 if (rf_agc.output_level > rf_agc.max_output_level)
6327 rfAgc.outputLevel = rfAgc.maxOutputLevel; 6327 rf_agc.output_level = rf_agc.max_output_level;
6328 6328
6329 agcRange = (u32) (rfAgc.maxOutputLevel - rfAgc.minOutputLevel); 6329 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6330 if (agcRange > 0) { 6330 if (agc_range > 0) {
6331 atten += 100UL * 6331 atten += 100UL *
6332 ((u32)(tunerRfGain)) * 6332 ((u32)(tuner_rf_gain)) *
6333 ((u32)(rfAgc.outputLevel - rfAgc.minOutputLevel)) 6333 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6334 / agcRange; 6334 / agc_range;
6335 } 6335 }
6336 } 6336 }
6337 6337
6338 if (ifAgc.ctrlMode == DRXK_AGC_CTRL_AUTO) { 6338 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6339 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 6339 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6340 &ifAgc.outputLevel); 6340 &if_agc.output_level);
6341 if (status < 0) 6341 if (status < 0)
6342 return status; 6342 return status;
6343 6343
6344 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 6344 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6345 &ifAgc.top); 6345 &if_agc.top);
6346 if (status < 0) 6346 if (status < 0)
6347 return status; 6347 return status;
6348 6348
6349 /* Take IF gain into account */ 6349 /* Take IF gain into account */
6350 totalGain += (u32) tunerIfGain; 6350 total_gain += (u32) tuner_if_gain;
6351 6351
6352 /* clip output value */ 6352 /* clip output value */
6353 if (ifAgc.outputLevel < ifAgc.minOutputLevel) 6353 if (if_agc.output_level < if_agc.min_output_level)
6354 ifAgc.outputLevel = ifAgc.minOutputLevel; 6354 if_agc.output_level = if_agc.min_output_level;
6355 if (ifAgc.outputLevel > ifAgc.maxOutputLevel) 6355 if (if_agc.output_level > if_agc.max_output_level)
6356 ifAgc.outputLevel = ifAgc.maxOutputLevel; 6356 if_agc.output_level = if_agc.max_output_level;
6357 6357
6358 agcRange = (u32) (ifAgc.maxOutputLevel - ifAgc.minOutputLevel); 6358 agc_range = (u32) (if_agc.max_output_level - if_agc.min_output_level);
6359 if (agcRange > 0) { 6359 if (agc_range > 0) {
6360 atten += 100UL * 6360 atten += 100UL *
6361 ((u32)(tunerIfGain)) * 6361 ((u32)(tuner_if_gain)) *
6362 ((u32)(ifAgc.outputLevel - ifAgc.minOutputLevel)) 6362 ((u32)(if_agc.output_level - if_agc.min_output_level))
6363 / agcRange; 6363 / agc_range;
6364 } 6364 }
6365 } 6365 }
6366 6366
@@ -6368,8 +6368,8 @@ static int get_strength(struct drxk_state *state, u64 *strength)
6368 * Convert to 0..65535 scale. 6368 * Convert to 0..65535 scale.
6369 * If it can't be measured (AGC is disabled), just show 100%. 6369 * If it can't be measured (AGC is disabled), just show 100%.
6370 */ 6370 */
6371 if (totalGain > 0) 6371 if (total_gain > 0)
6372 *strength = (65535UL * atten / totalGain / 100); 6372 *strength = (65535UL * atten / total_gain / 100);
6373 else 6373 else
6374 *strength = 65535; 6374 *strength = 65535;
6375 6375
@@ -6392,14 +6392,14 @@ static int drxk_get_stats(struct dvb_frontend *fe)
6392 u32 pkt_error_count; 6392 u32 pkt_error_count;
6393 s32 cnr; 6393 s32 cnr;
6394 6394
6395 if (state->m_DrxkState == DRXK_NO_DEV) 6395 if (state->m_drxk_state == DRXK_NO_DEV)
6396 return -ENODEV; 6396 return -ENODEV;
6397 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6397 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6398 return -EAGAIN; 6398 return -EAGAIN;
6399 6399
6400 /* get status */ 6400 /* get status */
6401 state->fe_status = 0; 6401 state->fe_status = 0;
6402 GetLockStatus(state, &stat); 6402 get_lock_status(state, &stat);
6403 if (stat == MPEG_LOCK) 6403 if (stat == MPEG_LOCK)
6404 state->fe_status |= 0x1f; 6404 state->fe_status |= 0x1f;
6405 if (stat == FEC_LOCK) 6405 if (stat == FEC_LOCK)
@@ -6415,7 +6415,7 @@ static int drxk_get_stats(struct dvb_frontend *fe)
6415 6415
6416 6416
6417 if (stat >= DEMOD_LOCK) { 6417 if (stat >= DEMOD_LOCK) {
6418 GetSignalToNoise(state, &cnr); 6418 get_signal_to_noise(state, &cnr);
6419 c->cnr.stat[0].svalue = cnr * 100; 6419 c->cnr.stat[0].svalue = cnr * 100;
6420 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 6420 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6421 } else { 6421 } else {
@@ -6522,9 +6522,9 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe,
6522 6522
6523 dprintk(1, "\n"); 6523 dprintk(1, "\n");
6524 6524
6525 if (state->m_DrxkState == DRXK_NO_DEV) 6525 if (state->m_drxk_state == DRXK_NO_DEV)
6526 return -ENODEV; 6526 return -ENODEV;
6527 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6527 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6528 return -EAGAIN; 6528 return -EAGAIN;
6529 6529
6530 *strength = c->strength.stat[0].uvalue; 6530 *strength = c->strength.stat[0].uvalue;
@@ -6538,12 +6538,12 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6538 6538
6539 dprintk(1, "\n"); 6539 dprintk(1, "\n");
6540 6540
6541 if (state->m_DrxkState == DRXK_NO_DEV) 6541 if (state->m_drxk_state == DRXK_NO_DEV)
6542 return -ENODEV; 6542 return -ENODEV;
6543 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6543 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6544 return -EAGAIN; 6544 return -EAGAIN;
6545 6545
6546 GetSignalToNoise(state, &snr2); 6546 get_signal_to_noise(state, &snr2);
6547 6547
6548 /* No negative SNR, clip to zero */ 6548 /* No negative SNR, clip to zero */
6549 if (snr2 < 0) 6549 if (snr2 < 0)
@@ -6559,12 +6559,12 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6559 6559
6560 dprintk(1, "\n"); 6560 dprintk(1, "\n");
6561 6561
6562 if (state->m_DrxkState == DRXK_NO_DEV) 6562 if (state->m_drxk_state == DRXK_NO_DEV)
6563 return -ENODEV; 6563 return -ENODEV;
6564 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6564 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6565 return -EAGAIN; 6565 return -EAGAIN;
6566 6566
6567 DVBTQAMGetAccPktErr(state, &err); 6567 dvbtqam_get_acc_pkt_err(state, &err);
6568 *ucblocks = (u32) err; 6568 *ucblocks = (u32) err;
6569 return 0; 6569 return 0;
6570} 6570}
@@ -6577,9 +6577,9 @@ static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_t
6577 6577
6578 dprintk(1, "\n"); 6578 dprintk(1, "\n");
6579 6579
6580 if (state->m_DrxkState == DRXK_NO_DEV) 6580 if (state->m_drxk_state == DRXK_NO_DEV)
6581 return -ENODEV; 6581 return -ENODEV;
6582 if (state->m_DrxkState == DRXK_UNINITIALIZED) 6582 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6583 return -EAGAIN; 6583 return -EAGAIN;
6584 6584
6585 switch (p->delivery_system) { 6585 switch (p->delivery_system) {
@@ -6649,36 +6649,36 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6649 state->no_i2c_bridge = config->no_i2c_bridge; 6649 state->no_i2c_bridge = config->no_i2c_bridge;
6650 state->antenna_gpio = config->antenna_gpio; 6650 state->antenna_gpio = config->antenna_gpio;
6651 state->antenna_dvbt = config->antenna_dvbt; 6651 state->antenna_dvbt = config->antenna_dvbt;
6652 state->m_ChunkSize = config->chunk_size; 6652 state->m_chunk_size = config->chunk_size;
6653 state->enable_merr_cfg = config->enable_merr_cfg; 6653 state->enable_merr_cfg = config->enable_merr_cfg;
6654 6654
6655 if (config->dynamic_clk) { 6655 if (config->dynamic_clk) {
6656 state->m_DVBTStaticCLK = 0; 6656 state->m_dvbt_static_clk = 0;
6657 state->m_DVBCStaticCLK = 0; 6657 state->m_dvbc_static_clk = 0;
6658 } else { 6658 } else {
6659 state->m_DVBTStaticCLK = 1; 6659 state->m_dvbt_static_clk = 1;
6660 state->m_DVBCStaticCLK = 1; 6660 state->m_dvbc_static_clk = 1;
6661 } 6661 }
6662 6662
6663 6663
6664 if (config->mpeg_out_clk_strength) 6664 if (config->mpeg_out_clk_strength)
6665 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07; 6665 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6666 else 6666 else
6667 state->m_TSClockkStrength = 0x06; 6667 state->m_ts_clockk_strength = 0x06;
6668 6668
6669 if (config->parallel_ts) 6669 if (config->parallel_ts)
6670 state->m_enableParallel = true; 6670 state->m_enable_parallel = true;
6671 else 6671 else
6672 state->m_enableParallel = false; 6672 state->m_enable_parallel = false;
6673 6673
6674 /* NOTE: as more UIO bits will be used, add them to the mask */ 6674 /* NOTE: as more UIO bits will be used, add them to the mask */
6675 state->UIO_mask = config->antenna_gpio; 6675 state->uio_mask = config->antenna_gpio;
6676 6676
6677 /* Default gpio to DVB-C */ 6677 /* Default gpio to DVB-C */
6678 if (!state->antenna_dvbt && state->antenna_gpio) 6678 if (!state->antenna_dvbt && state->antenna_gpio)
6679 state->m_GPIO |= state->antenna_gpio; 6679 state->m_gpio |= state->antenna_gpio;
6680 else 6680 else
6681 state->m_GPIO &= ~state->antenna_gpio; 6681 state->m_gpio &= ~state->antenna_gpio;
6682 6682
6683 mutex_init(&state->mutex); 6683 mutex_init(&state->mutex);
6684 6684
diff --git a/drivers/media/dvb-frontends/drxk_hard.h b/drivers/media/dvb-frontends/drxk_hard.h
index b8424f15f9a6..db87a6d75720 100644
--- a/drivers/media/dvb-frontends/drxk_hard.h
+++ b/drivers/media/dvb-frontends/drxk_hard.h
@@ -46,7 +46,7 @@
46#define IQM_RC_ADJ_SEL_B_QAM 0x1 46#define IQM_RC_ADJ_SEL_B_QAM 0x1
47#define IQM_RC_ADJ_SEL_B_VSB 0x2 47#define IQM_RC_ADJ_SEL_B_VSB 0x2
48 48
49enum OperationMode { 49enum operation_mode {
50 OM_NONE, 50 OM_NONE,
51 OM_QAM_ITU_A, 51 OM_QAM_ITU_A,
52 OM_QAM_ITU_B, 52 OM_QAM_ITU_B,
@@ -54,7 +54,7 @@ enum OperationMode {
54 OM_DVBT 54 OM_DVBT
55}; 55};
56 56
57enum DRXPowerMode { 57enum drx_power_mode {
58 DRX_POWER_UP = 0, 58 DRX_POWER_UP = 0,
59 DRX_POWER_MODE_1, 59 DRX_POWER_MODE_1,
60 DRX_POWER_MODE_2, 60 DRX_POWER_MODE_2,
@@ -93,8 +93,8 @@ enum DRXPowerMode {
93#endif 93#endif
94 94
95 95
96enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; 96enum agc_ctrl_mode { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
97enum EDrxkState { 97enum e_drxk_state {
98 DRXK_UNINITIALIZED = 0, 98 DRXK_UNINITIALIZED = 0,
99 DRXK_STOPPED, 99 DRXK_STOPPED,
100 DRXK_DTV_STARTED, 100 DRXK_DTV_STARTED,
@@ -103,7 +103,7 @@ enum EDrxkState {
103 DRXK_NO_DEV /* If drxk init failed */ 103 DRXK_NO_DEV /* If drxk init failed */
104}; 104};
105 105
106enum EDrxkCoefArrayIndex { 106enum e_drxk_coef_array_index {
107 DRXK_COEF_IDX_MN = 0, 107 DRXK_COEF_IDX_MN = 0,
108 DRXK_COEF_IDX_FM , 108 DRXK_COEF_IDX_FM ,
109 DRXK_COEF_IDX_L , 109 DRXK_COEF_IDX_L ,
@@ -113,13 +113,13 @@ enum EDrxkCoefArrayIndex {
113 DRXK_COEF_IDX_I , 113 DRXK_COEF_IDX_I ,
114 DRXK_COEF_IDX_MAX 114 DRXK_COEF_IDX_MAX
115}; 115};
116enum EDrxkSifAttenuation { 116enum e_drxk_sif_attenuation {
117 DRXK_SIF_ATTENUATION_0DB, 117 DRXK_SIF_ATTENUATION_0DB,
118 DRXK_SIF_ATTENUATION_3DB, 118 DRXK_SIF_ATTENUATION_3DB,
119 DRXK_SIF_ATTENUATION_6DB, 119 DRXK_SIF_ATTENUATION_6DB,
120 DRXK_SIF_ATTENUATION_9DB 120 DRXK_SIF_ATTENUATION_9DB
121}; 121};
122enum EDrxkConstellation { 122enum e_drxk_constellation {
123 DRX_CONSTELLATION_BPSK = 0, 123 DRX_CONSTELLATION_BPSK = 0,
124 DRX_CONSTELLATION_QPSK, 124 DRX_CONSTELLATION_QPSK,
125 DRX_CONSTELLATION_PSK8, 125 DRX_CONSTELLATION_PSK8,
@@ -133,7 +133,7 @@ enum EDrxkConstellation {
133 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, 133 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
134 DRX_CONSTELLATION_AUTO = DRX_AUTO 134 DRX_CONSTELLATION_AUTO = DRX_AUTO
135}; 135};
136enum EDrxkInterleaveMode { 136enum e_drxk_interleave_mode {
137 DRXK_QAM_I12_J17 = 16, 137 DRXK_QAM_I12_J17 = 16,
138 DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN 138 DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
139}; 139};
@@ -144,14 +144,14 @@ enum {
144 DRXK_SPIN_UNKNOWN 144 DRXK_SPIN_UNKNOWN
145}; 145};
146 146
147enum DRXKCfgDvbtSqiSpeed { 147enum drxk_cfg_dvbt_sqi_speed {
148 DRXK_DVBT_SQI_SPEED_FAST = 0, 148 DRXK_DVBT_SQI_SPEED_FAST = 0,
149 DRXK_DVBT_SQI_SPEED_MEDIUM, 149 DRXK_DVBT_SQI_SPEED_MEDIUM,
150 DRXK_DVBT_SQI_SPEED_SLOW, 150 DRXK_DVBT_SQI_SPEED_SLOW,
151 DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN 151 DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
152} ; 152} ;
153 153
154enum DRXFftmode_t { 154enum drx_fftmode_t {
155 DRX_FFTMODE_2K = 0, 155 DRX_FFTMODE_2K = 0,
156 DRX_FFTMODE_4K, 156 DRX_FFTMODE_4K,
157 DRX_FFTMODE_8K, 157 DRX_FFTMODE_8K,
@@ -159,40 +159,40 @@ enum DRXFftmode_t {
159 DRX_FFTMODE_AUTO = DRX_AUTO 159 DRX_FFTMODE_AUTO = DRX_AUTO
160}; 160};
161 161
162enum DRXMPEGStrWidth_t { 162enum drxmpeg_str_width_t {
163 DRX_MPEG_STR_WIDTH_1, 163 DRX_MPEG_STR_WIDTH_1,
164 DRX_MPEG_STR_WIDTH_8 164 DRX_MPEG_STR_WIDTH_8
165}; 165};
166 166
167enum DRXQamLockRange_t { 167enum drx_qam_lock_range_t {
168 DRX_QAM_LOCKRANGE_NORMAL, 168 DRX_QAM_LOCKRANGE_NORMAL,
169 DRX_QAM_LOCKRANGE_EXTENDED 169 DRX_QAM_LOCKRANGE_EXTENDED
170}; 170};
171 171
172struct DRXKCfgDvbtEchoThres_t { 172struct drxk_cfg_dvbt_echo_thres_t {
173 u16 threshold; 173 u16 threshold;
174 enum DRXFftmode_t fftMode; 174 enum drx_fftmode_t fft_mode;
175} ; 175} ;
176 176
177struct SCfgAgc { 177struct s_cfg_agc {
178 enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ 178 enum agc_ctrl_mode ctrl_mode; /* off, user, auto */
179 u16 outputLevel; /* range dependent on AGC */ 179 u16 output_level; /* range dependent on AGC */
180 u16 minOutputLevel; /* range dependent on AGC */ 180 u16 min_output_level; /* range dependent on AGC */
181 u16 maxOutputLevel; /* range dependent on AGC */ 181 u16 max_output_level; /* range dependent on AGC */
182 u16 speed; /* range dependent on AGC */ 182 u16 speed; /* range dependent on AGC */
183 u16 top; /* rf-agc take over point */ 183 u16 top; /* rf-agc take over point */
184 u16 cutOffCurrent; /* rf-agc is accelerated if output current 184 u16 cut_off_current; /* rf-agc is accelerated if output current
185 is below cut-off current */ 185 is below cut-off current */
186 u16 IngainTgtMax; 186 u16 ingain_tgt_max;
187 u16 FastClipCtrlDelay; 187 u16 fast_clip_ctrl_delay;
188}; 188};
189 189
190struct SCfgPreSaw { 190struct s_cfg_pre_saw {
191 u16 reference; /* pre SAW reference value, range 0 .. 31 */ 191 u16 reference; /* pre SAW reference value, range 0 .. 31 */
192 bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ 192 bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
193}; 193};
194 194
195struct DRXKOfdmScCmd_t { 195struct drxk_ofdm_sc_cmd_t {
196 u16 cmd; /**< Command number */ 196 u16 cmd; /**< Command number */
197 u16 subcmd; /**< Sub-command parameter*/ 197 u16 subcmd; /**< Sub-command parameter*/
198 u16 param0; /**< General purpous param */ 198 u16 param0; /**< General purpous param */
@@ -213,121 +213,121 @@ struct drxk_state {
213 213
214 struct mutex mutex; 214 struct mutex mutex;
215 215
216 u32 m_Instance; /**< Channel 1,2,3 or 4 */ 216 u32 m_instance; /**< Channel 1,2,3 or 4 */
217 217
218 int m_ChunkSize; 218 int m_chunk_size;
219 u8 Chunk[256]; 219 u8 chunk[256];
220 220
221 bool m_hasLNA; 221 bool m_has_lna;
222 bool m_hasDVBT; 222 bool m_has_dvbt;
223 bool m_hasDVBC; 223 bool m_has_dvbc;
224 bool m_hasAudio; 224 bool m_has_audio;
225 bool m_hasATV; 225 bool m_has_atv;
226 bool m_hasOOB; 226 bool m_has_oob;
227 bool m_hasSAWSW; /**< TRUE if mat_tx is available */ 227 bool m_has_sawsw; /* TRUE if mat_tx is available */
228 bool m_hasGPIO1; /**< TRUE if mat_rx is available */ 228 bool m_has_gpio1; /* TRUE if mat_rx is available */
229 bool m_hasGPIO2; /**< TRUE if GPIO is available */ 229 bool m_has_gpio2; /* TRUE if GPIO is available */
230 bool m_hasIRQN; /**< TRUE if IRQN is available */ 230 bool m_has_irqn; /* TRUE if IRQN is available */
231 u16 m_oscClockFreq; 231 u16 m_osc_clock_freq;
232 u16 m_HICfgTimingDiv; 232 u16 m_hi_cfg_timing_div;
233 u16 m_HICfgBridgeDelay; 233 u16 m_hi_cfg_bridge_delay;
234 u16 m_HICfgWakeUpKey; 234 u16 m_hi_cfg_wake_up_key;
235 u16 m_HICfgTimeout; 235 u16 m_hi_cfg_timeout;
236 u16 m_HICfgCtrl; 236 u16 m_hi_cfg_ctrl;
237 s32 m_sysClockFreq; /**< system clock frequency in kHz */ 237 s32 m_sys_clock_freq; /**< system clock frequency in kHz */
238 238
239 enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */ 239 enum e_drxk_state m_drxk_state; /**< State of Drxk (init,stopped,started) */
240 enum OperationMode m_OperationMode; /**< digital standards */ 240 enum operation_mode m_operation_mode; /**< digital standards */
241 struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */ 241 struct s_cfg_agc m_vsb_rf_agc_cfg; /**< settings for VSB RF-AGC */
242 struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */ 242 struct s_cfg_agc m_vsb_if_agc_cfg; /**< settings for VSB IF-AGC */
243 u16 m_vsbPgaCfg; /**< settings for VSB PGA */ 243 u16 m_vsb_pga_cfg; /**< settings for VSB PGA */
244 struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */ 244 struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /**< settings for pre SAW sense */
245 s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */ 245 s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
246 s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */ 246 s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
247 bool m_smartAntInverted; 247 bool m_smart_ant_inverted;
248 bool m_bDebugEnableBridge; 248 bool m_b_debug_enable_bridge;
249 bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */ 249 bool m_b_p_down_open_bridge; /**< only open DRXK bridge before power-down once it has been accessed */
250 bool m_bPowerDown; /**< Power down when not used */ 250 bool m_b_power_down; /**< Power down when not used */
251 251
252 u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */ 252 u32 m_iqm_fs_rate_ofs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
253 253
254 bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ 254 bool m_enable_mpeg_output; /**< If TRUE, enable MPEG output */
255 bool m_insertRSByte; /**< If TRUE, insert RS byte */ 255 bool m_insert_rs_byte; /**< If TRUE, insert RS byte */
256 bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ 256 bool m_enable_parallel; /**< If TRUE, parallel out otherwise serial */
257 bool m_invertDATA; /**< If TRUE, invert DATA signals */ 257 bool m_invert_data; /**< If TRUE, invert DATA signals */
258 bool m_invertERR; /**< If TRUE, invert ERR signal */ 258 bool m_invert_err; /**< If TRUE, invert ERR signal */
259 bool m_invertSTR; /**< If TRUE, invert STR signals */ 259 bool m_invert_str; /**< If TRUE, invert STR signals */
260 bool m_invertVAL; /**< If TRUE, invert VAL signals */ 260 bool m_invert_val; /**< If TRUE, invert VAL signals */
261 bool m_invertCLK; /**< If TRUE, invert CLK signals */ 261 bool m_invert_clk; /**< If TRUE, invert CLK signals */
262 bool m_DVBCStaticCLK; 262 bool m_dvbc_static_clk;
263 bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will 263 bool m_dvbt_static_clk; /**< If TRUE, static MPEG clockrate will
264 be used, otherwise clockrate will 264 be used, otherwise clockrate will
265 adapt to the bitrate of the TS */ 265 adapt to the bitrate of the TS */
266 u32 m_DVBTBitrate; 266 u32 m_dvbt_bitrate;
267 u32 m_DVBCBitrate; 267 u32 m_dvbc_bitrate;
268 268
269 u8 m_TSDataStrength; 269 u8 m_ts_data_strength;
270 u8 m_TSClockkStrength; 270 u8 m_ts_clockk_strength;
271 271
272 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ 272 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
273 273
274 enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */ 274 enum drxmpeg_str_width_t m_width_str; /**< MPEG start width */
275 u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case 275 u32 m_mpeg_ts_static_bitrate; /**< Maximum bitrate in b/s in case
276 static clockrate is selected */ 276 static clockrate is selected */
277 277
278 /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */ 278 /* LARGE_INTEGER m_startTime; */ /**< Contains the time of the last demod start */
279 s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ 279 s32 m_mpeg_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */
280 s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ 280 s32 m_demod_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */
281 281
282 bool m_disableTEIhandling; 282 bool m_disable_te_ihandling;
283 283
284 bool m_RfAgcPol; 284 bool m_rf_agc_pol;
285 bool m_IfAgcPol; 285 bool m_if_agc_pol;
286 286
287 struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */ 287 struct s_cfg_agc m_atv_rf_agc_cfg; /**< settings for ATV RF-AGC */
288 struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */ 288 struct s_cfg_agc m_atv_if_agc_cfg; /**< settings for ATV IF-AGC */
289 struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */ 289 struct s_cfg_pre_saw m_atv_pre_saw_cfg; /**< settings for ATV pre SAW sense */
290 bool m_phaseCorrectionBypass; 290 bool m_phase_correction_bypass;
291 s16 m_atvTopVidPeak; 291 s16 m_atv_top_vid_peak;
292 u16 m_atvTopNoiseTh; 292 u16 m_atv_top_noise_th;
293 enum EDrxkSifAttenuation m_sifAttenuation; 293 enum e_drxk_sif_attenuation m_sif_attenuation;
294 bool m_enableCVBSOutput; 294 bool m_enable_cvbs_output;
295 bool m_enableSIFOutput; 295 bool m_enable_sif_output;
296 bool m_bMirrorFreqSpect; 296 bool m_b_mirror_freq_spect;
297 enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */ 297 enum e_drxk_constellation m_constellation; /**< constellation type of the channel */
298 u32 m_CurrSymbolRate; /**< Current QAM symbol rate */ 298 u32 m_curr_symbol_rate; /**< Current QAM symbol rate */
299 struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */ 299 struct s_cfg_agc m_qam_rf_agc_cfg; /**< settings for QAM RF-AGC */
300 struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */ 300 struct s_cfg_agc m_qam_if_agc_cfg; /**< settings for QAM IF-AGC */
301 u16 m_qamPgaCfg; /**< settings for QAM PGA */ 301 u16 m_qam_pga_cfg; /**< settings for QAM PGA */
302 struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */ 302 struct s_cfg_pre_saw m_qam_pre_saw_cfg; /**< settings for QAM pre SAW sense */
303 enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */ 303 enum e_drxk_interleave_mode m_qam_interleave_mode; /**< QAM Interleave mode */
304 u16 m_fecRsPlen; 304 u16 m_fec_rs_plen;
305 u16 m_fecRsPrescale; 305 u16 m_fec_rs_prescale;
306 306
307 enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; 307 enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
308 308
309 u16 m_GPIO; 309 u16 m_gpio;
310 u16 m_GPIOCfg; 310 u16 m_gpio_cfg;
311 311
312 struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */ 312 struct s_cfg_agc m_dvbt_rf_agc_cfg; /**< settings for QAM RF-AGC */
313 struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */ 313 struct s_cfg_agc m_dvbt_if_agc_cfg; /**< settings for QAM IF-AGC */
314 struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */ 314 struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /**< settings for QAM pre SAW sense */
315 315
316 u16 m_agcFastClipCtrlDelay; 316 u16 m_agcfast_clip_ctrl_delay;
317 bool m_adcCompPassed; 317 bool m_adc_comp_passed;
318 u16 m_adcCompCoef[64]; 318 u16 m_adcCompCoef[64];
319 u16 m_adcState; 319 u16 m_adc_state;
320 320
321 u8 *m_microcode; 321 u8 *m_microcode;
322 int m_microcode_length; 322 int m_microcode_length;
323 bool m_DRXK_A3_ROM_CODE; 323 bool m_drxk_a3_rom_code;
324 bool m_DRXK_A3_PATCH_CODE; 324 bool m_drxk_a3_patch_code;
325 325
326 bool m_rfmirror; 326 bool m_rfmirror;
327 u8 m_deviceSpin; 327 u8 m_device_spin;
328 u32 m_iqmRcRate; 328 u32 m_iqm_rc_rate;
329 329
330 enum DRXPowerMode m_currentPowerMode; 330 enum drx_power_mode m_current_power_mode;
331 331
332 /* when true, avoids other devices to use the I2C bus */ 332 /* when true, avoids other devices to use the I2C bus */
333 bool drxk_i2c_exclusive_lock; 333 bool drxk_i2c_exclusive_lock;
@@ -337,7 +337,7 @@ struct drxk_state {
337 * at struct drxk_config. 337 * at struct drxk_config.
338 */ 338 */
339 339
340 u16 UIO_mask; /* Bits used by UIO */ 340 u16 uio_mask; /* Bits used by UIO */
341 341
342 bool enable_merr_cfg; 342 bool enable_merr_cfg;
343 bool single_master; 343 bool single_master;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 12:37:50 -0500