diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-28 10:47:48 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-06-08 21:09:32 -0400 |
commit | 57b8b0035725db6b1a4f7bb815b3dc244942b04d (patch) | |
tree | b1f47c91012b76dd1a360342f7df83c2a476f808 /drivers/media/dvb-frontends/drxk_hard.h | |
parent | b72852baa0776f6ed416d54cd94b7804f0587f81 (diff) |
[media] drxk_hard.h: Remove some alien comment markups
X-Patchwork-Delegate: mchehab@redhat.com
The comments markup language used on Kernel is defined at:
Documentation/kernel-doc-nano-HOWTO.txt
Remove invalid markups from the header file.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb-frontends/drxk_hard.h')
-rw-r--r-- | drivers/media/dvb-frontends/drxk_hard.h | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/drivers/media/dvb-frontends/drxk_hard.h b/drivers/media/dvb-frontends/drxk_hard.h index db87a6d75720..e77d9f098c93 100644 --- a/drivers/media/dvb-frontends/drxk_hard.h +++ b/drivers/media/dvb-frontends/drxk_hard.h | |||
@@ -77,17 +77,17 @@ enum drx_power_mode { | |||
77 | }; | 77 | }; |
78 | 78 | ||
79 | 79 | ||
80 | /** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ | 80 | /* Intermediate power mode for DRXK, power down OFDM clock domain */ |
81 | #ifndef DRXK_POWER_DOWN_OFDM | 81 | #ifndef DRXK_POWER_DOWN_OFDM |
82 | #define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 | 82 | #define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 |
83 | #endif | 83 | #endif |
84 | 84 | ||
85 | /** /brief Intermediate power mode for DRXK, power down core (sysclk) */ | 85 | /* Intermediate power mode for DRXK, power down core (sysclk) */ |
86 | #ifndef DRXK_POWER_DOWN_CORE | 86 | #ifndef DRXK_POWER_DOWN_CORE |
87 | #define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 | 87 | #define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 |
88 | #endif | 88 | #endif |
89 | 89 | ||
90 | /** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ | 90 | /* Intermediate power mode for DRXK, power down pll (only osc runs) */ |
91 | #ifndef DRXK_POWER_DOWN_PLL | 91 | #ifndef DRXK_POWER_DOWN_PLL |
92 | #define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 | 92 | #define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 |
93 | #endif | 93 | #endif |
@@ -193,13 +193,13 @@ struct s_cfg_pre_saw { | |||
193 | }; | 193 | }; |
194 | 194 | ||
195 | struct drxk_ofdm_sc_cmd_t { | 195 | struct drxk_ofdm_sc_cmd_t { |
196 | u16 cmd; /**< Command number */ | 196 | u16 cmd; /* Command number */ |
197 | u16 subcmd; /**< Sub-command parameter*/ | 197 | u16 subcmd; /* Sub-command parameter*/ |
198 | u16 param0; /**< General purpous param */ | 198 | u16 param0; /* General purpous param */ |
199 | u16 param1; /**< General purpous param */ | 199 | u16 param1; /* General purpous param */ |
200 | u16 param2; /**< General purpous param */ | 200 | u16 param2; /* General purpous param */ |
201 | u16 param3; /**< General purpous param */ | 201 | u16 param3; /* General purpous param */ |
202 | u16 param4; /**< General purpous param */ | 202 | u16 param4; /* General purpous param */ |
203 | }; | 203 | }; |
204 | 204 | ||
205 | struct drxk_state { | 205 | struct drxk_state { |
@@ -213,7 +213,7 @@ struct drxk_state { | |||
213 | 213 | ||
214 | struct mutex mutex; | 214 | struct mutex mutex; |
215 | 215 | ||
216 | u32 m_instance; /**< Channel 1,2,3 or 4 */ | 216 | u32 m_instance; /* Channel 1,2,3 or 4 */ |
217 | 217 | ||
218 | int m_chunk_size; | 218 | int m_chunk_size; |
219 | u8 chunk[256]; | 219 | u8 chunk[256]; |
@@ -234,33 +234,33 @@ struct drxk_state { | |||
234 | u16 m_hi_cfg_wake_up_key; | 234 | u16 m_hi_cfg_wake_up_key; |
235 | u16 m_hi_cfg_timeout; | 235 | u16 m_hi_cfg_timeout; |
236 | u16 m_hi_cfg_ctrl; | 236 | u16 m_hi_cfg_ctrl; |
237 | s32 m_sys_clock_freq; /**< system clock frequency in kHz */ | 237 | s32 m_sys_clock_freq; /* system clock frequency in kHz */ |
238 | 238 | ||
239 | enum e_drxk_state m_drxk_state; /**< State of Drxk (init,stopped,started) */ | 239 | enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */ |
240 | enum operation_mode m_operation_mode; /**< digital standards */ | 240 | enum operation_mode m_operation_mode; /* digital standards */ |
241 | struct s_cfg_agc m_vsb_rf_agc_cfg; /**< settings for VSB RF-AGC */ | 241 | struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */ |
242 | struct s_cfg_agc m_vsb_if_agc_cfg; /**< settings for VSB IF-AGC */ | 242 | struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */ |
243 | u16 m_vsb_pga_cfg; /**< settings for VSB PGA */ | 243 | u16 m_vsb_pga_cfg; /* settings for VSB PGA */ |
244 | struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /**< settings for pre SAW sense */ | 244 | struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */ |
245 | s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */ | 245 | s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */ |
246 | s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */ | 246 | s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */ |
247 | bool m_smart_ant_inverted; | 247 | bool m_smart_ant_inverted; |
248 | bool m_b_debug_enable_bridge; | 248 | bool m_b_debug_enable_bridge; |
249 | bool m_b_p_down_open_bridge; /**< only open DRXK bridge before power-down once it has been accessed */ | 249 | bool m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */ |
250 | bool m_b_power_down; /**< Power down when not used */ | 250 | bool m_b_power_down; /* Power down when not used */ |
251 | 251 | ||
252 | u32 m_iqm_fs_rate_ofs; /**< frequency shift as written to DRXK register (28bit fixpoint) */ | 252 | u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */ |
253 | 253 | ||
254 | bool m_enable_mpeg_output; /**< If TRUE, enable MPEG output */ | 254 | bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */ |
255 | bool m_insert_rs_byte; /**< If TRUE, insert RS byte */ | 255 | bool m_insert_rs_byte; /* If TRUE, insert RS byte */ |
256 | bool m_enable_parallel; /**< If TRUE, parallel out otherwise serial */ | 256 | bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */ |
257 | bool m_invert_data; /**< If TRUE, invert DATA signals */ | 257 | bool m_invert_data; /* If TRUE, invert DATA signals */ |
258 | bool m_invert_err; /**< If TRUE, invert ERR signal */ | 258 | bool m_invert_err; /* If TRUE, invert ERR signal */ |
259 | bool m_invert_str; /**< If TRUE, invert STR signals */ | 259 | bool m_invert_str; /* If TRUE, invert STR signals */ |
260 | bool m_invert_val; /**< If TRUE, invert VAL signals */ | 260 | bool m_invert_val; /* If TRUE, invert VAL signals */ |
261 | bool m_invert_clk; /**< If TRUE, invert CLK signals */ | 261 | bool m_invert_clk; /* If TRUE, invert CLK signals */ |
262 | bool m_dvbc_static_clk; | 262 | bool m_dvbc_static_clk; |
263 | bool m_dvbt_static_clk; /**< If TRUE, static MPEG clockrate will | 263 | bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will |
264 | be used, otherwise clockrate will | 264 | be used, otherwise clockrate will |
265 | adapt to the bitrate of the TS */ | 265 | adapt to the bitrate of the TS */ |
266 | u32 m_dvbt_bitrate; | 266 | u32 m_dvbt_bitrate; |
@@ -271,22 +271,22 @@ struct drxk_state { | |||
271 | 271 | ||
272 | bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ | 272 | bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ |
273 | 273 | ||
274 | enum drxmpeg_str_width_t m_width_str; /**< MPEG start width */ | 274 | enum drxmpeg_str_width_t m_width_str; /* MPEG start width */ |
275 | u32 m_mpeg_ts_static_bitrate; /**< Maximum bitrate in b/s in case | 275 | u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case |
276 | static clockrate is selected */ | 276 | static clockrate is selected */ |
277 | 277 | ||
278 | /* LARGE_INTEGER m_startTime; */ /**< Contains the time of the last demod start */ | 278 | /* LARGE_INTEGER m_startTime; */ /* Contains the time of the last demod start */ |
279 | s32 m_mpeg_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */ | 279 | s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ |
280 | s32 m_demod_lock_time_out; /**< WaitForLockStatus Timeout (counts from start time) */ | 280 | s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ |
281 | 281 | ||
282 | bool m_disable_te_ihandling; | 282 | bool m_disable_te_ihandling; |
283 | 283 | ||
284 | bool m_rf_agc_pol; | 284 | bool m_rf_agc_pol; |
285 | bool m_if_agc_pol; | 285 | bool m_if_agc_pol; |
286 | 286 | ||
287 | struct s_cfg_agc m_atv_rf_agc_cfg; /**< settings for ATV RF-AGC */ | 287 | struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */ |
288 | struct s_cfg_agc m_atv_if_agc_cfg; /**< settings for ATV IF-AGC */ | 288 | struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */ |
289 | struct s_cfg_pre_saw m_atv_pre_saw_cfg; /**< settings for ATV pre SAW sense */ | 289 | struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */ |
290 | bool m_phase_correction_bypass; | 290 | bool m_phase_correction_bypass; |
291 | s16 m_atv_top_vid_peak; | 291 | s16 m_atv_top_vid_peak; |
292 | u16 m_atv_top_noise_th; | 292 | u16 m_atv_top_noise_th; |
@@ -294,13 +294,13 @@ struct drxk_state { | |||
294 | bool m_enable_cvbs_output; | 294 | bool m_enable_cvbs_output; |
295 | bool m_enable_sif_output; | 295 | bool m_enable_sif_output; |
296 | bool m_b_mirror_freq_spect; | 296 | bool m_b_mirror_freq_spect; |
297 | enum e_drxk_constellation m_constellation; /**< constellation type of the channel */ | 297 | enum e_drxk_constellation m_constellation; /* constellation type of the channel */ |
298 | u32 m_curr_symbol_rate; /**< Current QAM symbol rate */ | 298 | u32 m_curr_symbol_rate; /* Current QAM symbol rate */ |
299 | struct s_cfg_agc m_qam_rf_agc_cfg; /**< settings for QAM RF-AGC */ | 299 | struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */ |
300 | struct s_cfg_agc m_qam_if_agc_cfg; /**< settings for QAM IF-AGC */ | 300 | struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */ |
301 | u16 m_qam_pga_cfg; /**< settings for QAM PGA */ | 301 | u16 m_qam_pga_cfg; /* settings for QAM PGA */ |
302 | struct s_cfg_pre_saw m_qam_pre_saw_cfg; /**< settings for QAM pre SAW sense */ | 302 | struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */ |
303 | enum e_drxk_interleave_mode m_qam_interleave_mode; /**< QAM Interleave mode */ | 303 | enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */ |
304 | u16 m_fec_rs_plen; | 304 | u16 m_fec_rs_plen; |
305 | u16 m_fec_rs_prescale; | 305 | u16 m_fec_rs_prescale; |
306 | 306 | ||
@@ -309,9 +309,9 @@ struct drxk_state { | |||
309 | u16 m_gpio; | 309 | u16 m_gpio; |
310 | u16 m_gpio_cfg; | 310 | u16 m_gpio_cfg; |
311 | 311 | ||
312 | struct s_cfg_agc m_dvbt_rf_agc_cfg; /**< settings for QAM RF-AGC */ | 312 | struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */ |
313 | struct s_cfg_agc m_dvbt_if_agc_cfg; /**< settings for QAM IF-AGC */ | 313 | struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */ |
314 | struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /**< settings for QAM pre SAW sense */ | 314 | struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */ |
315 | 315 | ||
316 | u16 m_agcfast_clip_ctrl_delay; | 316 | u16 m_agcfast_clip_ctrl_delay; |
317 | bool m_adc_comp_passed; | 317 | bool m_adc_comp_passed; |