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authorSteven Toth <stoth@hauppauge.com>2008-05-01 05:35:48 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:38 -0400
commit8c66a19d45fb5b88abf10678db353f35179a2cde (patch)
treef97e9f45dd11df1e276aca89ab0e8b1601baa4f3 /drivers/media/common
parent85d220d03b70180b9958b29d43e99c7135f00654 (diff)
V4L/DVB (7868): mxl5005s: Cleanup #5
Cleanup #5 Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/common')
-rw-r--r--drivers/media/common/tuners/mxl5005s.c304
-rw-r--r--drivers/media/common/tuners/mxl5005s.h99
2 files changed, 181 insertions, 222 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 7e687171301b..aad88d5c0dc2 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -24,10 +24,10 @@
24 24
25#include "mxl5005s.h" 25#include "mxl5005s.h"
26 26
27static int debug; 27static int debug = 2;
28 28
29#define dprintk(level, arg...) do { \ 29#define dprintk(level, arg...) do { \
30 if (debug >= level) \ 30 if (level <= debug) \
31 printk(arg); \ 31 printk(arg); \
32 } while (0) 32 } while (0)
33 33
@@ -43,13 +43,6 @@ static int debug;
43#define MXLCTRL_NUM 189 43#define MXLCTRL_NUM 189
44#define MASTER_CONTROL_ADDR 9 44#define MASTER_CONTROL_ADDR 9
45 45
46/* Enumeration of AGC Mode */
47typedef enum
48{
49 MXL_DUAL_AGC = 0,
50 MXL_SINGLE_AGC
51} AGC_Mode;
52
53/* Enumeration of Master Control Register State */ 46/* Enumeration of Master Control Register State */
54typedef enum 47typedef enum
55{ 48{
@@ -59,51 +52,6 @@ typedef enum
59 MC_SEQ_OFF 52 MC_SEQ_OFF
60} Master_Control_State; 53} Master_Control_State;
61 54
62/* Enumeration of MXL5005 Tuner Mode */
63typedef enum
64{
65 MXL_ANALOG_MODE = 0,
66 MXL_DIGITAL_MODE
67} Tuner_Mode;
68
69/* Enumeration of MXL5005 Tuner IF Mode */
70typedef enum
71{
72 MXL_ZERO_IF = 0,
73 MXL_LOW_IF
74} Tuner_IF_Mode;
75
76/* Enumeration of MXL5005 Tuner Clock Out Mode */
77typedef enum
78{
79 MXL_CLOCK_OUT_DISABLE = 0,
80 MXL_CLOCK_OUT_ENABLE
81} Tuner_Clock_Out;
82
83/* Enumeration of MXL5005 Tuner Div Out Mode */
84typedef enum
85{
86 MXL_DIV_OUT_1 = 0,
87 MXL_DIV_OUT_4
88
89} Tuner_Div_Out;
90
91/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
92typedef enum
93{
94 MXL_CAP_SEL_DISABLE = 0,
95 MXL_CAP_SEL_ENABLE
96
97} Tuner_Cap_Select;
98
99/* Enumeration of MXL5005 Tuner RSSI Mode */
100typedef enum
101{
102 MXL_RSSI_DISABLE = 0,
103 MXL_RSSI_ENABLE
104
105} Tuner_RSSI;
106
107/* Enumeration of MXL5005 Tuner Modulation Type */ 55/* Enumeration of MXL5005 Tuner Modulation Type */
108typedef enum 56typedef enum
109{ 57{
@@ -115,22 +63,6 @@ typedef enum
115 MXL_ANALOG_OTA 63 MXL_ANALOG_OTA
116} Tuner_Modu_Type; 64} Tuner_Modu_Type;
117 65
118/* Enumeration of MXL5005 Tuner Tracking Filter Type */
119typedef enum
120{
121 MXL_TF_DEFAULT = 0,
122 MXL_TF_OFF,
123 MXL_TF_C,
124 MXL_TF_C_H,
125 MXL_TF_D,
126 MXL_TF_D_L,
127 MXL_TF_E,
128 MXL_TF_F,
129 MXL_TF_E_2,
130 MXL_TF_E_NA,
131 MXL_TF_G
132} Tuner_TF_Type;
133
134/* MXL5005 Tuner Register Struct */ 66/* MXL5005 Tuner Register Struct */
135typedef struct _TunerReg_struct 67typedef struct _TunerReg_struct
136{ 68{
@@ -261,33 +193,6 @@ enum
261}; 193};
262#define MXL5005S_BANDWIDTH_MODE_NUM 3 194#define MXL5005S_BANDWIDTH_MODE_NUM 3
263 195
264/* Top modes */
265enum
266{
267 MXL5005S_TOP_5P5 = 55,
268 MXL5005S_TOP_7P2 = 72,
269 MXL5005S_TOP_9P2 = 92,
270 MXL5005S_TOP_11P0 = 110,
271 MXL5005S_TOP_12P9 = 129,
272 MXL5005S_TOP_14P7 = 147,
273 MXL5005S_TOP_16P8 = 168,
274 MXL5005S_TOP_19P4 = 194,
275 MXL5005S_TOP_21P2 = 212,
276 MXL5005S_TOP_23P2 = 232,
277 MXL5005S_TOP_25P2 = 252,
278 MXL5005S_TOP_27P1 = 271,
279 MXL5005S_TOP_29P2 = 292,
280 MXL5005S_TOP_31P7 = 317,
281 MXL5005S_TOP_34P9 = 349,
282};
283
284/* IF output load */
285enum
286{
287 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
288 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
289};
290
291/* MXL5005 Tuner Control Struct */ 196/* MXL5005 Tuner Control Struct */
292typedef struct _TunerControl_struct { 197typedef struct _TunerControl_struct {
293 u16 Ctrl_Num; /* Control Number */ 198 u16 Ctrl_Num; /* Control Number */
@@ -342,8 +247,7 @@ struct mxl5005s_state
342 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ 247 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
343 248
344 /* Linux driver framework specific */ 249 /* Linux driver framework specific */
345 const struct mxl5005s_config *config; 250 struct mxl5005s_config *config;
346
347 struct dvb_frontend *frontend; 251 struct dvb_frontend *frontend;
348 struct i2c_adapter *i2c; 252 struct i2c_adapter *i2c;
349}; 253};
@@ -367,11 +271,11 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
367u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); 271u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
368int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); 272int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen);
369u16 MXL_IFSynthInit(struct dvb_frontend *fe); 273u16 MXL_IFSynthInit(struct dvb_frontend *fe);
274int mxl5005s_AssignTunerMode(struct dvb_frontend *fe);
370 275
371int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) 276int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
372{ 277{
373 struct mxl5005s_state *state = fe->tuner_priv; 278 struct mxl5005s_state *state = fe->tuner_priv;
374 u8 AgcMasterByte = state->config->AgcMasterByte;
375 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 279 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
376 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 280 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
377 int TableLen; 281 int TableLen;
@@ -402,13 +306,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
402 306
403 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 307 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
404 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 308 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
405 ByteTable[TableLen] = MasterControlByte | AgcMasterByte; 309 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte;
406 TableLen += 1; 310 TableLen += 1;
407 311
408 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); 312 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
409 313
410 // Wait 30 ms. 314 // Wait 30 ms.
411 msleep(30); 315 msleep(150);
412 316
413 // Tuner RF frequency setting stage 2 317 // Tuner RF frequency setting stage 2
414 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; 318 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
@@ -417,39 +321,56 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
417 321
418 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 322 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
419 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 323 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
420 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; 324 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ;
421 TableLen += 1; 325 TableLen += 1;
422 326
423 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); 327 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
424 328
329 msleep(100);
330
425 return 0; 331 return 0;
426} 332}
427 333
428/* Write a single byte to a single reg */ 334static int mxl5005s_reset(struct dvb_frontend *fe)
429static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val)
430{ 335{
431 struct mxl5005s_state *state = fe->tuner_priv; 336 struct mxl5005s_state *state = fe->tuner_priv;
432 u8 buf[2] = { reg, val }; 337 int ret = 0;
338
339 u8 buf[2] = { 0xff, 0x00 };
433 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, 340 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
434 .buf = buf, .len = 2 }; 341 .buf = buf, .len = 2 };
435 342
343 dprintk(2, "%s()\n", __func__);
344
345 if (fe->ops.i2c_gate_ctrl)
346 fe->ops.i2c_gate_ctrl(fe, 1);
347
436 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 348 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
437 printk(KERN_WARNING "mxl5005s I2C write failed\n"); 349 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
438 return -EREMOTEIO; 350 ret = -EREMOTEIO;
439 } 351 }
440 return 0; 352
353 if (fe->ops.i2c_gate_ctrl)
354 fe->ops.i2c_gate_ctrl(fe, 0);
355
356 return ret;
441} 357}
442 358
443/* Write a word to a single reg */ 359/* Write a single byte to a single reg */
444static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) 360static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
445{ 361{
446 struct mxl5005s_state *state = fe->tuner_priv; 362 struct mxl5005s_state *state = fe->tuner_priv;
447 u8 buf[3] = { reg, val >> 8 , val & 0xff }; 363 u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
448 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, 364 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
449 .buf = buf, .len = 3 }; 365 .buf = buf, .len = 3 };
450 366
367 if(latch == 0)
368 msg.len = 2;
369
370 dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr);
371
451 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 372 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
452 printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); 373 printk(KERN_WARNING "mxl5005s I2C write failed\n");
453 return -EREMOTEIO; 374 return -EREMOTEIO;
454 } 375 }
455 return 0; 376 return 0;
@@ -457,20 +378,22 @@ static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val)
457 378
458int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) 379int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen)
459{ 380{
460 int i, ret; 381 int i, ret = 0;
461 u8 end_two_bytes_buf[]={ 0 , 0 }; 382
383 if (fe->ops.i2c_gate_ctrl)
384 fe->ops.i2c_gate_ctrl(fe, 1);
462 385
463 for( i = 0 ; i < TableLen - 1 ; i++) 386 for( i = 0 ; i < TableLen - 1 ; i++)
464 { 387 {
465 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); 388 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0);
466 if (!ret) 389 if (ret < 0)
467 return ret; 390 break;
468 } 391 }
469 392
470 end_two_bytes_buf[0] = pByteTable[i]; 393 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1);
471 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
472 394
473 ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); 395 if (fe->ops.i2c_gate_ctrl)
396 fe->ops.i2c_gate_ctrl(fe, 0);
474 397
475 return ret; 398 return ret;
476} 399}
@@ -509,6 +432,7 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
509 return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); 432 return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1);
510} 433}
511 434
435
512// The following context is source code provided by MaxLinear. 436// The following context is source code provided by MaxLinear.
513// MaxLinear source code - MXL5005_Initialize.cpp 437// MaxLinear source code - MXL5005_Initialize.cpp
514// DONE 438// DONE
@@ -2034,6 +1958,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2034 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); 1958 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
2035 break; 1959 break;
2036 case 6000000: 1960 case 6000000:
1961 printk("%s() doing 6MHz digital\n", __func__);
2037 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); 1962 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
2038 break; 1963 break;
2039 } 1964 }
@@ -2064,7 +1989,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2064 else /* Single AGC Mode Dig Ana */ 1989 else /* Single AGC Mode Dig Ana */
2065 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); 1990 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
2066 1991
2067
2068 if (state->TOP == 55) /* TOP == 5.5 */ 1992 if (state->TOP == 55) /* TOP == 5.5 */
2069 status += MXL_ControlWrite(fe, AGC_IF, 0x0); 1993 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
2070 1994
@@ -2294,6 +2218,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2294 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2218 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2295 else /* High IF */ 2219 else /* High IF */
2296 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2220 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2221 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2222
2297 } 2223 }
2298 if (state->Mod_Type == MXL_ANALOG_CABLE) { 2224 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2299 /* Analog Cable Mode */ 2225 /* Analog Cable Mode */
@@ -2330,7 +2256,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2330 } 2256 }
2331 2257
2332 /* RSSI disable */ 2258 /* RSSI disable */
2333 if(state->EN_RSSI==0) { 2259 if(state->EN_RSSI == 0) {
2334 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2260 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2335 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2261 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2336 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2262 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
@@ -2539,6 +2465,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2539 Fref = 324000000UL ; 2465 Fref = 324000000UL ;
2540 } 2466 }
2541 if (state->IF_LO == 5380000UL) { 2467 if (state->IF_LO == 5380000UL) {
2468 printk("%s() doing 5.38\n", __func__);
2542 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2469 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2543 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2470 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2544 Fref = 322800000UL ; 2471 Fref = 322800000UL ;
@@ -3221,6 +3148,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3221 3148
3222 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only 3149 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
3223 { 3150 {
3151 printk("%s() CH filter\n", __func__);
3224 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 3152 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3225 3153
3226 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) 3154 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
@@ -4534,63 +4462,59 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
4534 4462
4535/* Linux driver related functions */ 4463/* Linux driver related functions */
4536 4464
4465int mxl5005s_init(struct dvb_frontend *fe)
4466{
4467 struct mxl5005s_state *state = fe->tuner_priv;
4468
4469 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4470 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4471 int TableLen;
4472
4473 dprintk(1, "%s()\n", __func__);
4474
4475 mxl5005s_reset(fe);
4476
4477 /* Tuner initialization stage 0 */
4478 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4479 AddrTable[0] = MASTER_CONTROL_ADDR;
4480 ByteTable[0] |= state->config->AgcMasterByte;
4537 4481
4538int mxl5005s_init2(struct dvb_frontend *fe) 4482 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
4483
4484 mxl5005s_AssignTunerMode(fe); // tunre_config
4485
4486 /* Tuner initialization stage 1 */
4487 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4488
4489 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
4490
4491 return 0;
4492}
4493
4494int mxl5005s_AssignTunerMode(struct dvb_frontend *fe)
4539{ 4495{
4540 int MxlModMode; 4496 struct mxl5005s_state *state = fe->tuner_priv;
4541 int MxlIfMode; 4497 struct mxl5005s_config *c = state->config;
4542 unsigned long MxlBandwitdh;
4543 unsigned long MxlIfFreqHz;
4544 unsigned long MxlCrystalFreqHz;
4545 int MxlAgcMode;
4546 unsigned short MxlTop;
4547 unsigned short MxlIfOutputLoad;
4548 int MxlClockOut;
4549 int MxlDivOut;
4550 int MxlCapSel;
4551 int MxlRssiOnOff;
4552 unsigned char MxlStandard;
4553 unsigned char MxlTfType;
4554 4498
4555 /* Set MxL5005S parameters. */ 4499 InitTunerControls(fe);
4556 MxlModMode = MXL_DIGITAL_MODE;
4557 MxlIfMode = MXL_ZERO_IF;
4558// steve
4559 //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
4560 //MxlIfFreqHz = IF_FREQ_4570000HZ;
4561 MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config
4562 MxlIfFreqHz = IF_FREQ_5380000HZ; // config
4563 MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config
4564 MxlAgcMode = MXL_SINGLE_AGC;
4565 MxlTop = MXL5005S_TOP_25P2;
4566 MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
4567 MxlClockOut = MXL_CLOCK_OUT_DISABLE;
4568 MxlDivOut = MXL_DIV_OUT_4;
4569 MxlCapSel = MXL_CAP_SEL_ENABLE;
4570 MxlRssiOnOff = MXL_RSSI_ENABLE; // config
4571 MxlTfType = MXL_TF_C_H; // config
4572
4573 MxlStandard = MXL_ATSC; // config
4574
4575 // TODO: this is bad, it trashes other configs
4576 // Set MxL5005S extra module.
4577 //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
4578 4500
4501 /* Set MxL5005S parameters. */
4579 MXL5005_TunerConfig( 4502 MXL5005_TunerConfig(
4580 fe, 4503 fe,
4581 (unsigned char)MxlModMode, 4504 c->mod_mode,
4582 (unsigned char)MxlIfMode, 4505 c->if_mode,
4583 MxlBandwitdh, 4506 MXL5005S_BANDWIDTH_6MHZ,
4584 MxlIfFreqHz, 4507 c->if_freq,
4585 MxlCrystalFreqHz, 4508 c->xtal_freq,
4586 (unsigned char)MxlAgcMode, 4509 c->agc_mode,
4587 MxlTop, 4510 c->top,
4588 MxlIfOutputLoad, 4511 c->output_load,
4589 (unsigned char)MxlClockOut, 4512 c->clock_out,
4590 (unsigned char)MxlDivOut, 4513 c->div_out,
4591 (unsigned char)MxlCapSel, 4514 c->cap_select,
4592 (unsigned char)MxlRssiOnOff, 4515 c->rssi_enable,
4593 MxlStandard, MxlTfType); 4516 MXL_QAM,
4517 c->tracking_filter);
4594 4518
4595 return 0; 4519 return 0;
4596} 4520}
@@ -4609,7 +4533,11 @@ static int mxl5005s_set_params(struct dvb_frontend *fe,
4609 freq = params->frequency; /* Hz */ 4533 freq = params->frequency; /* Hz */
4610 dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); 4534 dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw);
4611 4535
4612 return mxl5005s_SetRfFreqHz(fe, freq); 4536 mxl5005s_SetRfFreqHz(fe, freq);
4537
4538 msleep(350);
4539
4540 return 0;
4613} 4541}
4614 4542
4615static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) 4543static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
@@ -4642,32 +4570,6 @@ static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status)
4642 return 0; 4570 return 0;
4643} 4571}
4644 4572
4645static int mxl5005s_init(struct dvb_frontend *fe)
4646{
4647 struct mxl5005s_state *state = fe->tuner_priv;
4648 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4649 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4650 int TableLen;
4651
4652 dprintk(1, "%s()\n", __func__);
4653
4654 /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */
4655
4656 /* Tuner initialization stage 0 */
4657 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4658 AddrTable[0] = MASTER_CONTROL_ADDR;
4659 ByteTable[0] |= state->config->AgcMasterByte;
4660
4661 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
4662
4663 /* Tuner initialization stage 1 */
4664 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4665
4666 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
4667
4668 return mxl5005s_init2(fe);
4669}
4670
4671static int mxl5005s_release(struct dvb_frontend *fe) 4573static int mxl5005s_release(struct dvb_frontend *fe)
4672{ 4574{
4673 dprintk(1, "%s()\n", __func__); 4575 dprintk(1, "%s()\n", __func__);
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h
index 1c4d9da8e1fe..2777ecc20d19 100644
--- a/drivers/media/common/tuners/mxl5005s.h
+++ b/drivers/media/common/tuners/mxl5005s.h
@@ -26,31 +26,88 @@
26#ifndef __MXL5005S_H 26#ifndef __MXL5005S_H
27#define __MXL5005S_H 27#define __MXL5005S_H
28 28
29/* IF frequency */
30enum IF_FREQ_HZ
31{
32 IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz
33 IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz
34 IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz
35 IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz
36 IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz
37 IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz
38 IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz
39};
40
41/* Crystal frequency */
42enum CRYSTAL_FREQ_HZ
43{
44 CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz
45 CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz
46 CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz
47 CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz
48};
49
50struct mxl5005s_config 29struct mxl5005s_config
51{ 30{
31 /* 7 bit i2c address */
52 u8 i2c_address; 32 u8 i2c_address;
53 33
34#define IF_FREQ_4570000HZ 4570000
35#define IF_FREQ_4571429HZ 4571429
36#define IF_FREQ_5380000HZ 5380000
37#define IF_FREQ_36000000HZ 36000000
38#define IF_FREQ_36125000HZ 36125000
39#define IF_FREQ_36166667HZ 36166667
40#define IF_FREQ_44000000HZ 44000000
41 u32 if_freq;
42
43#define CRYSTAL_FREQ_4000000HZ 4000000
44#define CRYSTAL_FREQ_16000000HZ 16000000
45#define CRYSTAL_FREQ_25000000HZ 25000000
46#define CRYSTAL_FREQ_28800000HZ 28800000
47 u32 xtal_freq;
48
49#define MXL_DUAL_AGC 0
50#define MXL_SINGLE_AGC 1
51 u8 agc_mode;
52
53#define MXL_TF_DEFAULT 0
54#define MXL_TF_OFF 1
55#define MXL_TF_C 2
56#define MXL_TF_C_H 3
57#define MXL_TF_D 4
58#define MXL_TF_D_L 5
59#define MXL_TF_E 6
60#define MXL_TF_F 7
61#define MXL_TF_E_2 8
62#define MXL_TF_E_NA 9
63#define MXL_TF_G 10
64 u8 tracking_filter;
65
66#define MXL_RSSI_DISABLE 0
67#define MXL_RSSI_ENABLE 1
68 u8 rssi_enable;
69
70#define MXL_CAP_SEL_DISABLE 0
71#define MXL_CAP_SEL_ENABLE 1
72 u8 cap_select;
73
74#define MXL_DIV_OUT_1 0
75#define MXL_DIV_OUT_4 1
76 u8 div_out;
77
78#define MXL_CLOCK_OUT_DISABLE 0
79#define MXL_CLOCK_OUT_ENABLE 1
80 u8 clock_out;
81
82#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
83#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
84 u32 output_load;
85
86#define MXL5005S_TOP_5P5 55
87#define MXL5005S_TOP_7P2 72
88#define MXL5005S_TOP_9P2 92
89#define MXL5005S_TOP_11P0 110
90#define MXL5005S_TOP_12P9 129
91#define MXL5005S_TOP_14P7 147
92#define MXL5005S_TOP_16P8 168
93#define MXL5005S_TOP_19P4 194
94#define MXL5005S_TOP_21P2 212
95#define MXL5005S_TOP_23P2 232
96#define MXL5005S_TOP_25P2 252
97#define MXL5005S_TOP_27P1 271
98#define MXL5005S_TOP_29P2 292
99#define MXL5005S_TOP_31P7 317
100#define MXL5005S_TOP_34P9 349
101 u32 top;
102
103#define MXL_ANALOG_MODE 0
104#define MXL_DIGITAL_MODE 1
105 u8 mod_mode;
106
107#define MXL_ZERO_IF 0
108#define MXL_LOW_IF 1
109 u8 if_mode;
110
54 /* Stuff I don't know what to do with */ 111 /* Stuff I don't know what to do with */
55 u8 AgcMasterByte; 112 u8 AgcMasterByte;
56}; 113};
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-27 08:58:33 -0400