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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-20 21:55:25 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:18:59 -0500
commitfdf77a4f8ea4ac93128f4508cf305add80c36db1 (patch)
treed29bc8e8ba5fc2df06f4320163281159f10bea85 /drivers/media/common/tuners
parent065719a7689ff29debda9e8ce1c4891dcfc5ceb4 (diff)
[media] mt2063: Use Unix standard error handling
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common/tuners')
-rw-r--r--drivers/media/common/tuners/mt2063.c2359
1 files changed, 1139 insertions, 1220 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 98bc2e2ee41b..a1acfcc26bd0 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -16,64 +16,18 @@ module_param(verbose, int, 0644);
16#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100 16#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100
17#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101 17#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101
18 18
19#define MT2063_ERROR (1 << 31) 19/* FIXME: Those error codes need conversion*/
20#define MT2063_USER_ERROR (1 << 30)
21
22/* Macro to be used to check for errors */
23#define MT2063_IS_ERROR(s) (((s) >> 30) != 0)
24#define MT2063_NO_ERROR(s) (((s) >> 30) == 0)
25
26#define MT2063_OK (0x00000000)
27
28/* Unknown error */
29#define MT2063_UNKNOWN (0x80000001)
30
31/* Error: Upconverter PLL is not locked */ 20/* Error: Upconverter PLL is not locked */
32#define MT2063_UPC_UNLOCK (0x80000002) 21#define MT2063_UPC_UNLOCK (0x80000002)
33
34/* Error: Downconverter PLL is not locked */ 22/* Error: Downconverter PLL is not locked */
35#define MT2063_DNC_UNLOCK (0x80000004) 23#define MT2063_DNC_UNLOCK (0x80000004)
36 24/* Info: Unavoidable LO-related spur may be present in the output */
37/* Error: Two-wire serial bus communications error */ 25#define MT2063_SPUR_PRESENT_ERR (0x00800000)
38#define MT2063_COMM_ERR (0x80000008)
39
40/* Error: Tuner handle passed to function was invalid */
41#define MT2063_INV_HANDLE (0x80000010)
42
43/* Error: Function argument is invalid (out of range) */
44#define MT2063_ARG_RANGE (0x80000020)
45
46/* Error: Function argument (ptr to return value) was NULL */
47#define MT2063_ARG_NULL (0x80000040)
48
49/* Error: Attempt to open more than MT_TUNER_CNT tuners */
50#define MT2063_TUNER_CNT_ERR (0x80000080)
51
52/* Error: Tuner Part Code / Rev Code mismatches expected value */
53#define MT2063_TUNER_ID_ERR (0x80000100)
54
55/* Error: Tuner Initialization failure */
56#define MT2063_TUNER_INIT_ERR (0x80000200)
57
58#define MT2063_TUNER_OPEN_ERR (0x80000400)
59
60/* User-definable fields (see mt_userdef.h) */
61#define MT2063_USER_DEFINED1 (0x00001000)
62#define MT2063_USER_DEFINED2 (0x00002000)
63#define MT2063_USER_DEFINED3 (0x00004000)
64#define MT2063_USER_DEFINED4 (0x00008000)
65#define MT2063_USER_MASK (0x4000f000)
66#define MT2063_USER_SHIFT (12)
67 26
68/* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */ 27/* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
69#define MT2063_SPUR_CNT_MASK (0x001f0000) 28#define MT2063_SPUR_CNT_MASK (0x001f0000)
70#define MT2063_SPUR_SHIFT (16) 29#define MT2063_SPUR_SHIFT (16)
71 30
72/* Info: Tuner timeout waiting for condition */
73#define MT2063_TUNER_TIMEOUT (0x00400000)
74
75/* Info: Unavoidable LO-related spur may be present in the output */
76#define MT2063_SPUR_PRESENT_ERR (0x00800000)
77 31
78/* Info: Tuner input frequency is out of range */ 32/* Info: Tuner input frequency is out of range */
79#define MT2063_FIN_RANGE (0x01000000) 33#define MT2063_FIN_RANGE (0x01000000)
@@ -539,12 +493,12 @@ struct mt2063_state {
539/* Prototypes */ 493/* Prototypes */
540static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info, 494static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
541 u32 f_min, u32 f_max); 495 u32 f_min, u32 f_max);
542static u32 MT2063_ReInit(void *h); 496static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo);
543static u32 MT2063_Close(void *hMT2063); 497static u32 MT2063_Close(struct MT2063_Info_t *pInfo);
544static u32 MT2063_GetReg(void *h, u8 reg, u8 * val); 498static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val);
545static u32 MT2063_GetParam(void *h, enum MT2063_Param param, u32 * pValue); 499static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 * pValue);
546static u32 MT2063_SetReg(void *h, u8 reg, u8 val); 500static u32 MT2063_SetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 val);
547static u32 MT2063_SetParam(void *h, enum MT2063_Param param, u32 nValue); 501static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 nValue);
548 502
549/*****************/ 503/*****************/
550/* From drivers/media/common/tuners/mt2063_cfg.h */ 504/* From drivers/media/common/tuners/mt2063_cfg.h */
@@ -769,7 +723,7 @@ static u32 MT2063_WriteSub(void *hUserData,
769 u32 addr, 723 u32 addr,
770 u8 subAddress, u8 * pData, u32 cnt) 724 u8 subAddress, u8 * pData, u32 cnt)
771{ 725{
772 u32 status = MT2063_OK; /* Status to be returned */ 726 u32 status = 0; /* Status to be returned */
773 struct dvb_frontend *fe = hUserData; 727 struct dvb_frontend *fe = hUserData;
774 struct mt2063_state *state = fe->tuner_priv; 728 struct mt2063_state *state = fe->tuner_priv;
775 /* 729 /*
@@ -782,7 +736,7 @@ static u32 MT2063_WriteSub(void *hUserData,
782 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge 736 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge
783 737
784 if (mt2063_writeregs(state, subAddress, pData, cnt) < 0) { 738 if (mt2063_writeregs(state, subAddress, pData, cnt) < 0) {
785 status = MT2063_ERROR; 739 status = -EINVAL;
786 } 740 }
787 fe->ops.i2c_gate_ctrl(fe, 0); //I2C bypass drxk3926 close i2c bridge 741 fe->ops.i2c_gate_ctrl(fe, 0); //I2C bypass drxk3926 close i2c bridge
788 742
@@ -838,7 +792,7 @@ static u32 MT2063_ReadSub(void *hUserData,
838 ** return MT_OK. 792 ** return MT_OK.
839 */ 793 */
840/* return status; */ 794/* return status; */
841 u32 status = MT2063_OK; /* Status to be returned */ 795 u32 status = 0; /* Status to be returned */
842 struct dvb_frontend *fe = hUserData; 796 struct dvb_frontend *fe = hUserData;
843 struct mt2063_state *state = fe->tuner_priv; 797 struct mt2063_state *state = fe->tuner_priv;
844 u32 i = 0; 798 u32 i = 0;
@@ -846,7 +800,7 @@ static u32 MT2063_ReadSub(void *hUserData,
846 800
847 for (i = 0; i < cnt; i++) { 801 for (i = 0; i < cnt; i++) {
848 if (mt2063_read_regs(state, subAddress + i, pData + i, 1) < 0) { 802 if (mt2063_read_regs(state, subAddress + i, pData + i, 1) < 0) {
849 status = MT2063_ERROR; 803 status = -EINVAL;
850 break; 804 break;
851 } 805 }
852 } 806 }
@@ -962,7 +916,7 @@ static u32 MT2063_RegisterTuner(struct MT2063_AvoidSpursData_t *pAS_Info)
962{ 916{
963#if MT2063_TUNER_CNT == 1 917#if MT2063_TUNER_CNT == 1
964 pAS_Info->nAS_Algorithm = 1; 918 pAS_Info->nAS_Algorithm = 1;
965 return MT2063_OK; 919 return 0;
966#else 920#else
967 u32 index; 921 u32 index;
968 922
@@ -973,7 +927,7 @@ static u32 MT2063_RegisterTuner(struct MT2063_AvoidSpursData_t *pAS_Info)
973 */ 927 */
974 for (index = 0; index < TunerCount; index++) { 928 for (index = 0; index < TunerCount; index++) {
975 if (TunerList[index] == pAS_Info) { 929 if (TunerList[index] == pAS_Info) {
976 return MT2063_OK; /* Already here - no problem */ 930 return 0; /* Already here - no problem */
977 } 931 }
978 } 932 }
979 933
@@ -983,9 +937,9 @@ static u32 MT2063_RegisterTuner(struct MT2063_AvoidSpursData_t *pAS_Info)
983 if (TunerCount < MT2063_TUNER_CNT) { 937 if (TunerCount < MT2063_TUNER_CNT) {
984 TunerList[TunerCount] = pAS_Info; 938 TunerList[TunerCount] = pAS_Info;
985 TunerCount++; 939 TunerCount++;
986 return MT2063_OK; 940 return 0;
987 } else 941 } else
988 return MT2063_TUNER_CNT_ERR; 942 return -ENODEV;
989#endif 943#endif
990} 944}
991 945
@@ -1810,13 +1764,13 @@ static u32 IsSpurInBand(struct MT2063_AvoidSpursData_t *pAS_Info,
1810*****************************************************************************/ 1764*****************************************************************************/
1811static u32 MT2063_AvoidSpurs(void *h, struct MT2063_AvoidSpursData_t * pAS_Info) 1765static u32 MT2063_AvoidSpurs(void *h, struct MT2063_AvoidSpursData_t * pAS_Info)
1812{ 1766{
1813 u32 status = MT2063_OK; 1767 u32 status = 0;
1814 u32 fm, fp; /* restricted range on LO's */ 1768 u32 fm, fp; /* restricted range on LO's */
1815 pAS_Info->bSpurAvoided = 0; 1769 pAS_Info->bSpurAvoided = 0;
1816 pAS_Info->nSpursFound = 0; 1770 pAS_Info->nSpursFound = 0;
1817 1771
1818 if (pAS_Info->maxH1 == 0) 1772 if (pAS_Info->maxH1 == 0)
1819 return MT2063_OK; 1773 return 0;
1820 1774
1821 /* 1775 /*
1822 ** Avoid LO Generated Spurs 1776 ** Avoid LO Generated Spurs
@@ -2030,14 +1984,14 @@ static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num,
2030******************************************************************************/ 1984******************************************************************************/
2031static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hUserData) 1985static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hUserData)
2032{ 1986{
2033 u32 status = MT2063_OK; /* Status to be returned. */ 1987 u32 status = 0; /* Status to be returned. */
2034 struct MT2063_Info_t *pInfo = NULL; 1988 struct MT2063_Info_t *pInfo = NULL;
2035 struct dvb_frontend *fe = (struct dvb_frontend *)hUserData; 1989 struct dvb_frontend *fe = (struct dvb_frontend *)hUserData;
2036 struct mt2063_state *state = fe->tuner_priv; 1990 struct mt2063_state *state = fe->tuner_priv;
2037 1991
2038 /* Check the argument before using */ 1992 /* Check the argument before using */
2039 if (hMT2063 == NULL) { 1993 if (hMT2063 == NULL) {
2040 return MT2063_ARG_NULL; 1994 return -ENODEV;
2041 } 1995 }
2042 1996
2043 /* Default tuner handle to NULL. If successful, it will be reassigned */ 1997 /* Default tuner handle to NULL. If successful, it will be reassigned */
@@ -2045,7 +1999,7 @@ static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hU
2045 if (state->MT2063_init == false) { 1999 if (state->MT2063_init == false) {
2046 pInfo = kzalloc(sizeof(struct MT2063_Info_t), GFP_KERNEL); 2000 pInfo = kzalloc(sizeof(struct MT2063_Info_t), GFP_KERNEL);
2047 if (pInfo == NULL) { 2001 if (pInfo == NULL) {
2048 return MT2063_TUNER_OPEN_ERR; 2002 return -ENOMEM;
2049 } 2003 }
2050 pInfo->handle = NULL; 2004 pInfo->handle = NULL;
2051 pInfo->address = MAX_UDATA; 2005 pInfo->address = MAX_UDATA;
@@ -2055,11 +2009,11 @@ static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hU
2055 pInfo = *hMT2063; 2009 pInfo = *hMT2063;
2056 } 2010 }
2057 2011
2058 if (MT2063_NO_ERROR(status)) { 2012 if (status >= 0) {
2059 status |= MT2063_RegisterTuner(&pInfo->AS_Data); 2013 status |= MT2063_RegisterTuner(&pInfo->AS_Data);
2060 } 2014 }
2061 2015
2062 if (MT2063_NO_ERROR(status)) { 2016 if (status >= 0) {
2063 pInfo->handle = (void *) pInfo; 2017 pInfo->handle = (void *) pInfo;
2064 2018
2065 pInfo->hUserData = hUserData; 2019 pInfo->hUserData = hUserData;
@@ -2068,7 +2022,7 @@ static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hU
2068 status |= MT2063_ReInit((void *) pInfo); 2022 status |= MT2063_ReInit((void *) pInfo);
2069 } 2023 }
2070 2024
2071 if (MT2063_IS_ERROR(status)) 2025 if (status < 0)
2072 /* MT2063_Close handles the un-registration of the tuner */ 2026 /* MT2063_Close handles the un-registration of the tuner */
2073 MT2063_Close((void *) pInfo); 2027 MT2063_Close((void *) pInfo);
2074 else { 2028 else {
@@ -2106,12 +2060,10 @@ static u32 MT2063_IsValidHandle(struct MT2063_Info_t *handle)
2106** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 2060** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2107** 2061**
2108******************************************************************************/ 2062******************************************************************************/
2109static u32 MT2063_Close(void *hMT2063) 2063static u32 MT2063_Close(struct MT2063_Info_t *pInfo)
2110{ 2064{
2111 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)hMT2063;
2112
2113 if (!MT2063_IsValidHandle(pInfo)) 2065 if (!MT2063_IsValidHandle(pInfo))
2114 return MT2063_INV_HANDLE; 2066 return -ENODEV;
2115 2067
2116 /* Unregister tuner with SpurAvoidance routines (if needed) */ 2068 /* Unregister tuner with SpurAvoidance routines (if needed) */
2117 MT2063_UnRegisterTuner(&pInfo->AS_Data); 2069 MT2063_UnRegisterTuner(&pInfo->AS_Data);
@@ -2122,7 +2074,7 @@ static u32 MT2063_Close(void *hMT2063)
2122 //kfree(pInfo); 2074 //kfree(pInfo);
2123 //pInfo = NULL; 2075 //pInfo = NULL;
2124 2076
2125 return MT2063_OK; 2077 return 0;
2126} 2078}
2127 2079
2128/**************************************************************************** 2080/****************************************************************************
@@ -2150,19 +2102,18 @@ static u32 MT2063_Close(void *hMT2063)
2150** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 2102** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2151** 2103**
2152****************************************************************************/ 2104****************************************************************************/
2153static u32 MT2063_GetLocked(void *h) 2105static u32 MT2063_GetLocked(struct MT2063_Info_t *pInfo)
2154{ 2106{
2155 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */ 2107 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
2156 const u32 nPollRate = 2; /* poll status bits every 2 ms */ 2108 const u32 nPollRate = 2; /* poll status bits every 2 ms */
2157 const u32 nMaxLoops = nMaxWait / nPollRate; 2109 const u32 nMaxLoops = nMaxWait / nPollRate;
2158 const u8 LO1LK = 0x80; 2110 const u8 LO1LK = 0x80;
2159 u8 LO2LK = 0x08; 2111 u8 LO2LK = 0x08;
2160 u32 status = MT2063_OK; /* Status to be returned */ 2112 u32 status = 0; /* Status to be returned */
2161 u32 nDelays = 0; 2113 u32 nDelays = 0;
2162 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
2163 2114
2164 if (MT2063_IsValidHandle(pInfo) == 0) 2115 if (MT2063_IsValidHandle(pInfo) == 0)
2165 return MT2063_INV_HANDLE; 2116 return -ENODEV;
2166 2117
2167 /* LO2 Lock bit was in a different place for B0 version */ 2118 /* LO2 Lock bit was in a different place for B0 version */
2168 if (pInfo->tuner_id == MT2063_B0) 2119 if (pInfo->tuner_id == MT2063_B0)
@@ -2174,7 +2125,7 @@ static u32 MT2063_GetLocked(void *h)
2174 MT2063_REG_LO_STATUS, 2125 MT2063_REG_LO_STATUS,
2175 &pInfo->reg[MT2063_REG_LO_STATUS], 1); 2126 &pInfo->reg[MT2063_REG_LO_STATUS], 1);
2176 2127
2177 if (MT2063_IS_ERROR(status)) 2128 if (status < 0)
2178 return (status); 2129 return (status);
2179 2130
2180 if ((pInfo->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) == 2131 if ((pInfo->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
@@ -2285,378 +2236,375 @@ static u32 MT2063_GetLocked(void *h)
2285** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2236** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2286** 2237**
2287****************************************************************************/ 2238****************************************************************************/
2288static u32 MT2063_GetParam(void *h, enum MT2063_Param param, u32 * pValue) 2239static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 * pValue)
2289{ 2240{
2290 u32 status = MT2063_OK; /* Status to be returned */ 2241 u32 status = 0; /* Status to be returned */
2291 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
2292 u32 Div; 2242 u32 Div;
2293 u32 Num; 2243 u32 Num;
2294 2244
2295 if (pValue == NULL) 2245 if (pValue == NULL)
2296 status |= MT2063_ARG_NULL; 2246 return -EINVAL;
2297 2247
2298 /* Verify that the handle passed points to a valid tuner */ 2248 /* Verify that the handle passed points to a valid tuner */
2299 if (MT2063_IsValidHandle(pInfo) == 0) 2249 if (MT2063_IsValidHandle(pInfo) == 0)
2300 status |= MT2063_INV_HANDLE; 2250 return -ENODEV;
2301 2251
2302 if (MT2063_NO_ERROR(status)) { 2252 switch (param) {
2303 switch (param) { 2253 /* Serial Bus address of this tuner */
2304 /* Serial Bus address of this tuner */ 2254 case MT2063_IC_ADDR:
2305 case MT2063_IC_ADDR: 2255 *pValue = pInfo->address;
2306 *pValue = pInfo->address; 2256 break;
2307 break; 2257
2308 2258 /* Max # of MT2063's allowed to be open */
2309 /* Max # of MT2063's allowed to be open */ 2259 case MT2063_MAX_OPEN:
2310 case MT2063_MAX_OPEN: 2260 *pValue = nMT2063MaxTuners;
2311 *pValue = nMT2063MaxTuners; 2261 break;
2312 break; 2262
2313 2263 /* # of MT2063's open */
2314 /* # of MT2063's open */ 2264 case MT2063_NUM_OPEN:
2315 case MT2063_NUM_OPEN: 2265 *pValue = nMT2063OpenTuners;
2316 *pValue = nMT2063OpenTuners; 2266 break;
2317 break; 2267
2318 2268 /* crystal frequency */
2319 /* crystal frequency */ 2269 case MT2063_SRO_FREQ:
2320 case MT2063_SRO_FREQ: 2270 *pValue = pInfo->AS_Data.f_ref;
2321 *pValue = pInfo->AS_Data.f_ref; 2271 break;
2322 break; 2272
2323 2273 /* minimum tuning step size */
2324 /* minimum tuning step size */ 2274 case MT2063_STEPSIZE:
2325 case MT2063_STEPSIZE: 2275 *pValue = pInfo->AS_Data.f_LO2_Step;
2326 *pValue = pInfo->AS_Data.f_LO2_Step; 2276 break;
2327 break; 2277
2328 2278 /* input center frequency */
2329 /* input center frequency */ 2279 case MT2063_INPUT_FREQ:
2330 case MT2063_INPUT_FREQ: 2280 *pValue = pInfo->AS_Data.f_in;
2331 *pValue = pInfo->AS_Data.f_in; 2281 break;
2332 break; 2282
2333 2283 /* LO1 Frequency */
2334 /* LO1 Frequency */ 2284 case MT2063_LO1_FREQ:
2335 case MT2063_LO1_FREQ: 2285 {
2336 { 2286 /* read the actual tuner register values for LO1C_1 and LO1C_2 */
2337 /* read the actual tuner register values for LO1C_1 and LO1C_2 */ 2287 status |=
2338 status |= 2288 MT2063_ReadSub(pInfo->hUserData,
2339 MT2063_ReadSub(pInfo->hUserData, 2289 pInfo->address,
2340 pInfo->address, 2290 MT2063_REG_LO1C_1,
2341 MT2063_REG_LO1C_1, 2291 &pInfo->
2342 &pInfo-> 2292 reg[MT2063_REG_LO1C_1], 2);
2343 reg[MT2063_REG_LO1C_1], 2); 2293 Div = pInfo->reg[MT2063_REG_LO1C_1];
2344 Div = pInfo->reg[MT2063_REG_LO1C_1]; 2294 Num = pInfo->reg[MT2063_REG_LO1C_2] & 0x3F;
2345 Num = pInfo->reg[MT2063_REG_LO1C_2] & 0x3F; 2295 pInfo->AS_Data.f_LO1 =
2346 pInfo->AS_Data.f_LO1 = 2296 (pInfo->AS_Data.f_ref * Div) +
2347 (pInfo->AS_Data.f_ref * Div) + 2297 MT2063_fLO_FractionalTerm(pInfo->AS_Data.
2348 MT2063_fLO_FractionalTerm(pInfo->AS_Data. 2298 f_ref, Num, 64);
2349 f_ref, Num, 64); 2299 }
2350 } 2300 *pValue = pInfo->AS_Data.f_LO1;
2351 *pValue = pInfo->AS_Data.f_LO1; 2301 break;
2352 break; 2302
2353 2303 /* LO1 minimum step size */
2354 /* LO1 minimum step size */ 2304 case MT2063_LO1_STEPSIZE:
2355 case MT2063_LO1_STEPSIZE: 2305 *pValue = pInfo->AS_Data.f_LO1_Step;
2356 *pValue = pInfo->AS_Data.f_LO1_Step; 2306 break;
2357 break; 2307
2358 2308 /* LO1 FracN keep-out region */
2359 /* LO1 FracN keep-out region */ 2309 case MT2063_LO1_FRACN_AVOID_PARAM:
2360 case MT2063_LO1_FRACN_AVOID_PARAM: 2310 *pValue = pInfo->AS_Data.f_LO1_FracN_Avoid;
2361 *pValue = pInfo->AS_Data.f_LO1_FracN_Avoid; 2311 break;
2362 break; 2312
2363 2313 /* Current 1st IF in use */
2364 /* Current 1st IF in use */ 2314 case MT2063_IF1_ACTUAL:
2365 case MT2063_IF1_ACTUAL: 2315 *pValue = pInfo->f_IF1_actual;
2366 *pValue = pInfo->f_IF1_actual; 2316 break;
2367 break; 2317
2368 2318 /* Requested 1st IF */
2369 /* Requested 1st IF */ 2319 case MT2063_IF1_REQUEST:
2370 case MT2063_IF1_REQUEST: 2320 *pValue = pInfo->AS_Data.f_if1_Request;
2371 *pValue = pInfo->AS_Data.f_if1_Request; 2321 break;
2372 break; 2322
2373 2323 /* Center of 1st IF SAW filter */
2374 /* Center of 1st IF SAW filter */ 2324 case MT2063_IF1_CENTER:
2375 case MT2063_IF1_CENTER: 2325 *pValue = pInfo->AS_Data.f_if1_Center;
2376 *pValue = pInfo->AS_Data.f_if1_Center; 2326 break;
2377 break; 2327
2378 2328 /* Bandwidth of 1st IF SAW filter */
2379 /* Bandwidth of 1st IF SAW filter */ 2329 case MT2063_IF1_BW:
2380 case MT2063_IF1_BW: 2330 *pValue = pInfo->AS_Data.f_if1_bw;
2381 *pValue = pInfo->AS_Data.f_if1_bw; 2331 break;
2382 break; 2332
2383 2333 /* zero-IF bandwidth */
2384 /* zero-IF bandwidth */ 2334 case MT2063_ZIF_BW:
2385 case MT2063_ZIF_BW: 2335 *pValue = pInfo->AS_Data.f_zif_bw;
2386 *pValue = pInfo->AS_Data.f_zif_bw; 2336 break;
2387 break; 2337
2388 2338 /* LO2 Frequency */
2389 /* LO2 Frequency */ 2339 case MT2063_LO2_FREQ:
2390 case MT2063_LO2_FREQ: 2340 {
2391 { 2341 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */
2392 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */ 2342 status |=
2393 status |= 2343 MT2063_ReadSub(pInfo->hUserData,
2394 MT2063_ReadSub(pInfo->hUserData, 2344 pInfo->address,
2395 pInfo->address, 2345 MT2063_REG_LO2C_1,
2396 MT2063_REG_LO2C_1, 2346 &pInfo->
2397 &pInfo-> 2347 reg[MT2063_REG_LO2C_1], 3);
2398 reg[MT2063_REG_LO2C_1], 3); 2348 Div =
2399 Div = 2349 (pInfo->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1;
2400 (pInfo->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1; 2350 Num =
2401 Num = 2351 ((pInfo->
2402 ((pInfo-> 2352 reg[MT2063_REG_LO2C_1] & 0x01) << 12) |
2403 reg[MT2063_REG_LO2C_1] & 0x01) << 12) | 2353 (pInfo->
2404 (pInfo-> 2354 reg[MT2063_REG_LO2C_2] << 4) | (pInfo->
2405 reg[MT2063_REG_LO2C_2] << 4) | (pInfo-> 2355 reg
2406 reg 2356 [MT2063_REG_LO2C_3]
2407 [MT2063_REG_LO2C_3] 2357 & 0x00F);
2408 & 0x00F); 2358 pInfo->AS_Data.f_LO2 =
2409 pInfo->AS_Data.f_LO2 = 2359 (pInfo->AS_Data.f_ref * Div) +
2410 (pInfo->AS_Data.f_ref * Div) + 2360 MT2063_fLO_FractionalTerm(pInfo->AS_Data.
2411 MT2063_fLO_FractionalTerm(pInfo->AS_Data. 2361 f_ref, Num, 8191);
2412 f_ref, Num, 8191); 2362 }
2413 } 2363 *pValue = pInfo->AS_Data.f_LO2;
2414 *pValue = pInfo->AS_Data.f_LO2; 2364 break;
2415 break; 2365
2416 2366 /* LO2 minimum step size */
2417 /* LO2 minimum step size */ 2367 case MT2063_LO2_STEPSIZE:
2418 case MT2063_LO2_STEPSIZE: 2368 *pValue = pInfo->AS_Data.f_LO2_Step;
2419 *pValue = pInfo->AS_Data.f_LO2_Step; 2369 break;
2420 break; 2370
2421 2371 /* LO2 FracN keep-out region */
2422 /* LO2 FracN keep-out region */ 2372 case MT2063_LO2_FRACN_AVOID:
2423 case MT2063_LO2_FRACN_AVOID: 2373 *pValue = pInfo->AS_Data.f_LO2_FracN_Avoid;
2424 *pValue = pInfo->AS_Data.f_LO2_FracN_Avoid; 2374 break;
2425 break; 2375
2426 2376 /* output center frequency */
2427 /* output center frequency */ 2377 case MT2063_OUTPUT_FREQ:
2428 case MT2063_OUTPUT_FREQ: 2378 *pValue = pInfo->AS_Data.f_out;
2429 *pValue = pInfo->AS_Data.f_out; 2379 break;
2430 break; 2380
2431 2381 /* output bandwidth */
2432 /* output bandwidth */ 2382 case MT2063_OUTPUT_BW:
2433 case MT2063_OUTPUT_BW: 2383 *pValue = pInfo->AS_Data.f_out_bw - 750000;
2434 *pValue = pInfo->AS_Data.f_out_bw - 750000; 2384 break;
2435 break; 2385
2436 2386 /* min inter-tuner LO separation */
2437 /* min inter-tuner LO separation */ 2387 case MT2063_LO_SEPARATION:
2438 case MT2063_LO_SEPARATION: 2388 *pValue = pInfo->AS_Data.f_min_LO_Separation;
2439 *pValue = pInfo->AS_Data.f_min_LO_Separation; 2389 break;
2440 break; 2390
2441 2391 /* ID of avoid-spurs algorithm in use */
2442 /* ID of avoid-spurs algorithm in use */ 2392 case MT2063_AS_ALG:
2443 case MT2063_AS_ALG: 2393 *pValue = pInfo->AS_Data.nAS_Algorithm;
2444 *pValue = pInfo->AS_Data.nAS_Algorithm; 2394 break;
2445 break; 2395
2446 2396 /* max # of intra-tuner harmonics */
2447 /* max # of intra-tuner harmonics */ 2397 case MT2063_MAX_HARM1:
2448 case MT2063_MAX_HARM1: 2398 *pValue = pInfo->AS_Data.maxH1;
2449 *pValue = pInfo->AS_Data.maxH1; 2399 break;
2450 break; 2400
2451 2401 /* max # of inter-tuner harmonics */
2452 /* max # of inter-tuner harmonics */ 2402 case MT2063_MAX_HARM2:
2453 case MT2063_MAX_HARM2: 2403 *pValue = pInfo->AS_Data.maxH2;
2454 *pValue = pInfo->AS_Data.maxH2; 2404 break;
2455 break; 2405
2456 2406 /* # of 1st IF exclusion zones */
2457 /* # of 1st IF exclusion zones */ 2407 case MT2063_EXCL_ZONES:
2458 case MT2063_EXCL_ZONES: 2408 *pValue = pInfo->AS_Data.nZones;
2459 *pValue = pInfo->AS_Data.nZones; 2409 break;
2460 break; 2410
2461 2411 /* # of spurs found/avoided */
2462 /* # of spurs found/avoided */ 2412 case MT2063_NUM_SPURS:
2463 case MT2063_NUM_SPURS: 2413 *pValue = pInfo->AS_Data.nSpursFound;
2464 *pValue = pInfo->AS_Data.nSpursFound; 2414 break;
2465 break; 2415
2466 2416 /* >0 spurs avoided */
2467 /* >0 spurs avoided */ 2417 case MT2063_SPUR_AVOIDED:
2468 case MT2063_SPUR_AVOIDED: 2418 *pValue = pInfo->AS_Data.bSpurAvoided;
2469 *pValue = pInfo->AS_Data.bSpurAvoided; 2419 break;
2470 break; 2420
2471 2421 /* >0 spurs in output (mathematically) */
2472 /* >0 spurs in output (mathematically) */ 2422 case MT2063_SPUR_PRESENT:
2473 case MT2063_SPUR_PRESENT: 2423 *pValue = pInfo->AS_Data.bSpurPresent;
2474 *pValue = pInfo->AS_Data.bSpurPresent; 2424 break;
2475 break; 2425
2476 2426 /* Predefined receiver setup combination */
2477 /* Predefined receiver setup combination */ 2427 case MT2063_RCVR_MODE:
2478 case MT2063_RCVR_MODE: 2428 *pValue = pInfo->rcvr_mode;
2479 *pValue = pInfo->rcvr_mode; 2429 break;
2480 break; 2430
2481 2431 case MT2063_PD1:
2482 case MT2063_PD1: 2432 case MT2063_PD2:
2483 case MT2063_PD2: 2433 {
2484 { 2434 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */
2485 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */ 2435 u8 orig = (pInfo->reg[MT2063_REG_BYP_CTRL]);
2486 u8 orig = (pInfo->reg[MT2063_REG_BYP_CTRL]); 2436 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */
2487 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */ 2437 int i;
2488 int i; 2438
2489 2439 *pValue = 0;
2490 *pValue = 0; 2440
2491 2441 /* Initiate ADC output to reg 0x0A */
2492 /* Initiate ADC output to reg 0x0A */ 2442 if (reg != orig)
2493 if (reg != orig) 2443 status |=
2494 status |= 2444 MT2063_WriteSub(pInfo->hUserData,
2495 MT2063_WriteSub(pInfo->hUserData, 2445 pInfo->address,
2496 pInfo->address, 2446 MT2063_REG_BYP_CTRL,
2497 MT2063_REG_BYP_CTRL, 2447 &reg, 1);
2498 &reg, 1); 2448
2499 2449 if (status < 0)
2500 if (MT2063_IS_ERROR(status)) 2450 return (status);
2501 return (status); 2451
2502 2452 for (i = 0; i < 8; i++) {
2503 for (i = 0; i < 8; i++) { 2453 status |=
2504 status |= 2454 MT2063_ReadSub(pInfo->hUserData,
2505 MT2063_ReadSub(pInfo->hUserData, 2455 pInfo->address,
2506 pInfo->address, 2456 MT2063_REG_ADC_OUT,
2507 MT2063_REG_ADC_OUT, 2457 &pInfo->
2508 &pInfo-> 2458 reg
2509 reg 2459 [MT2063_REG_ADC_OUT],
2510 [MT2063_REG_ADC_OUT], 2460 1);
2511 1); 2461
2512 2462 if (status >= 0)
2513 if (MT2063_NO_ERROR(status)) 2463 *pValue +=
2514 *pValue += 2464 pInfo->
2515 pInfo-> 2465 reg[MT2063_REG_ADC_OUT];
2516 reg[MT2063_REG_ADC_OUT]; 2466 else {
2517 else { 2467 if (i)
2518 if (i) 2468 *pValue /= i;
2519 *pValue /= i; 2469 return (status);
2520 return (status); 2470 }
2521 } 2471 }
2522 } 2472 *pValue /= 8; /* divide by number of reads */
2523 *pValue /= 8; /* divide by number of reads */ 2473 *pValue >>= 2; /* only want 6 MSB's out of 8 */
2524 *pValue >>= 2; /* only want 6 MSB's out of 8 */ 2474
2525 2475 /* Restore value of Register BYP_CTRL */
2526 /* Restore value of Register BYP_CTRL */ 2476 if (reg != orig)
2527 if (reg != orig) 2477 status |=
2528 status |= 2478 MT2063_WriteSub(pInfo->hUserData,
2529 MT2063_WriteSub(pInfo->hUserData, 2479 pInfo->address,
2530 pInfo->address, 2480 MT2063_REG_BYP_CTRL,
2531 MT2063_REG_BYP_CTRL, 2481 &orig, 1);
2532 &orig, 1); 2482 }
2533 } 2483 break;
2534 break; 2484
2535 2485 /* Get LNA attenuator code */
2536 /* Get LNA attenuator code */ 2486 case MT2063_ACLNA:
2537 case MT2063_ACLNA: 2487 {
2538 { 2488 u8 val;
2539 u8 val; 2489 status |=
2540 status |= 2490 MT2063_GetReg(pInfo, MT2063_REG_XO_STATUS,
2541 MT2063_GetReg(pInfo, MT2063_REG_XO_STATUS, 2491 &val);
2542 &val); 2492 *pValue = val & 0x1f;
2543 *pValue = val & 0x1f; 2493 }
2544 } 2494 break;
2545 break; 2495
2546 2496 /* Get RF attenuator code */
2547 /* Get RF attenuator code */ 2497 case MT2063_ACRF:
2548 case MT2063_ACRF: 2498 {
2549 { 2499 u8 val;
2550 u8 val; 2500 status |=
2551 status |= 2501 MT2063_GetReg(pInfo, MT2063_REG_RF_STATUS,
2552 MT2063_GetReg(pInfo, MT2063_REG_RF_STATUS, 2502 &val);
2553 &val); 2503 *pValue = val & 0x1f;
2554 *pValue = val & 0x1f; 2504 }
2555 } 2505 break;
2556 break; 2506
2557 2507 /* Get FIF attenuator code */
2558 /* Get FIF attenuator code */ 2508 case MT2063_ACFIF:
2559 case MT2063_ACFIF: 2509 {
2560 { 2510 u8 val;
2561 u8 val; 2511 status |=
2562 status |= 2512 MT2063_GetReg(pInfo, MT2063_REG_FIF_STATUS,
2563 MT2063_GetReg(pInfo, MT2063_REG_FIF_STATUS, 2513 &val);
2564 &val); 2514 *pValue = val & 0x1f;
2565 *pValue = val & 0x1f; 2515 }
2566 } 2516 break;
2567 break; 2517
2568 2518 /* Get LNA attenuator limit */
2569 /* Get LNA attenuator limit */ 2519 case MT2063_ACLNA_MAX:
2570 case MT2063_ACLNA_MAX: 2520 {
2571 { 2521 u8 val;
2572 u8 val; 2522 status |=
2573 status |= 2523 MT2063_GetReg(pInfo, MT2063_REG_LNA_OV,
2574 MT2063_GetReg(pInfo, MT2063_REG_LNA_OV, 2524 &val);
2575 &val); 2525 *pValue = val & 0x1f;
2576 *pValue = val & 0x1f; 2526 }
2577 } 2527 break;
2578 break; 2528
2579 2529 /* Get RF attenuator limit */
2580 /* Get RF attenuator limit */ 2530 case MT2063_ACRF_MAX:
2581 case MT2063_ACRF_MAX: 2531 {
2582 { 2532 u8 val;
2583 u8 val; 2533 status |=
2584 status |= 2534 MT2063_GetReg(pInfo, MT2063_REG_RF_OV,
2585 MT2063_GetReg(pInfo, MT2063_REG_RF_OV, 2535 &val);
2586 &val); 2536 *pValue = val & 0x1f;
2587 *pValue = val & 0x1f; 2537 }
2588 } 2538 break;
2589 break; 2539
2590 2540 /* Get FIF attenuator limit */
2591 /* Get FIF attenuator limit */ 2541 case MT2063_ACFIF_MAX:
2592 case MT2063_ACFIF_MAX: 2542 {
2593 { 2543 u8 val;
2594 u8 val; 2544 status |=
2595 status |= 2545 MT2063_GetReg(pInfo, MT2063_REG_FIF_OV,
2596 MT2063_GetReg(pInfo, MT2063_REG_FIF_OV, 2546 &val);
2597 &val); 2547 *pValue = val & 0x1f;
2598 *pValue = val & 0x1f; 2548 }
2599 } 2549 break;
2600 break; 2550
2601 2551 /* Get current used DNC output */
2602 /* Get current used DNC output */ 2552 case MT2063_DNC_OUTPUT_ENABLE:
2603 case MT2063_DNC_OUTPUT_ENABLE: 2553 {
2604 { 2554 if ((pInfo->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
2605 if ((pInfo->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ 2555 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2606 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ 2556 *pValue =
2607 *pValue = 2557 (u32) MT2063_DNC_NONE;
2608 (u32) MT2063_DNC_NONE; 2558 else
2609 else 2559 *pValue =
2610 *pValue = 2560 (u32) MT2063_DNC_2;
2611 (u32) MT2063_DNC_2; 2561 } else { /* DNC1 is on */
2612 } else { /* DNC1 is on */ 2562
2613 2563 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2614 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ 2564 *pValue =
2615 *pValue = 2565 (u32) MT2063_DNC_1;
2616 (u32) MT2063_DNC_1; 2566 else
2617 else 2567 *pValue =
2618 *pValue = 2568 (u32) MT2063_DNC_BOTH;
2619 (u32) MT2063_DNC_BOTH; 2569 }
2620 } 2570 }
2621 } 2571 break;
2622 break; 2572
2623 2573 /* Get VGA Gain Code */
2624 /* Get VGA Gain Code */ 2574 case MT2063_VGAGC:
2625 case MT2063_VGAGC: 2575 *pValue =
2626 *pValue = 2576 ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2);
2627 ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2); 2577 break;
2628 break; 2578
2629 2579 /* Get VGA bias current */
2630 /* Get VGA bias current */ 2580 case MT2063_VGAOI:
2631 case MT2063_VGAOI: 2581 *pValue = (pInfo->reg[MT2063_REG_RSVD_31] & 0x07);
2632 *pValue = (pInfo->reg[MT2063_REG_RSVD_31] & 0x07); 2582 break;
2633 break; 2583
2634 2584 /* Get TAGC setting */
2635 /* Get TAGC setting */ 2585 case MT2063_TAGC:
2636 case MT2063_TAGC: 2586 *pValue = (pInfo->reg[MT2063_REG_RSVD_1E] & 0x03);
2637 *pValue = (pInfo->reg[MT2063_REG_RSVD_1E] & 0x03); 2587 break;
2638 break; 2588
2639 2589 /* Get AMP Gain Code */
2640 /* Get AMP Gain Code */ 2590 case MT2063_AMPGC:
2641 case MT2063_AMPGC: 2591 *pValue = (pInfo->reg[MT2063_REG_TEMP_SEL] & 0x03);
2642 *pValue = (pInfo->reg[MT2063_REG_TEMP_SEL] & 0x03); 2592 break;
2643 break; 2593
2644 2594 /* Avoid DECT Frequencies */
2645 /* Avoid DECT Frequencies */ 2595 case MT2063_AVOID_DECT:
2646 case MT2063_AVOID_DECT: 2596 *pValue = pInfo->AS_Data.avoidDECT;
2647 *pValue = pInfo->AS_Data.avoidDECT; 2597 break;
2648 break; 2598
2649 2599 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
2650 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */ 2600 case MT2063_CTFILT_SW:
2651 case MT2063_CTFILT_SW: 2601 *pValue = pInfo->ctfilt_sw;
2652 *pValue = pInfo->ctfilt_sw; 2602 break;
2653 break; 2603
2654 2604 case MT2063_EOP:
2655 case MT2063_EOP: 2605 default:
2656 default: 2606 status |= -ERANGE;
2657 status |= MT2063_ARG_RANGE; 2607 }
2658 }
2659 }
2660 return (status); 2608 return (status);
2661} 2609}
2662 2610
@@ -2689,28 +2637,22 @@ static u32 MT2063_GetParam(void *h, enum MT2063_Param param, u32 * pValue)
2689** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 2637** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2690** 2638**
2691****************************************************************************/ 2639****************************************************************************/
2692static u32 MT2063_GetReg(void *h, u8 reg, u8 * val) 2640static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val)
2693{ 2641{
2694 u32 status = MT2063_OK; /* Status to be returned */ 2642 u32 status = 0; /* Status to be returned */
2695 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
2696 2643
2697 /* Verify that the handle passed points to a valid tuner */ 2644 /* Verify that the handle passed points to a valid tuner */
2698 if (MT2063_IsValidHandle(pInfo) == 0) 2645 if (MT2063_IsValidHandle(pInfo) == 0)
2699 status |= MT2063_INV_HANDLE; 2646 return -ENODEV;
2700 2647
2701 if (val == NULL) 2648 if (val == NULL)
2702 status |= MT2063_ARG_NULL; 2649 return -EINVAL;
2703 2650
2704 if (reg >= MT2063_REG_END_REGS) 2651 if (reg >= MT2063_REG_END_REGS)
2705 status |= MT2063_ARG_RANGE; 2652 return -ERANGE;
2706 2653
2707 if (MT2063_NO_ERROR(status)) { 2654 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, reg,
2708 status |= 2655 &pInfo->reg[reg], 1);
2709 MT2063_ReadSub(pInfo->hUserData, pInfo->address, reg,
2710 &pInfo->reg[reg], 1);
2711 if (MT2063_NO_ERROR(status))
2712 *val = pInfo->reg[reg];
2713 }
2714 2656
2715 return (status); 2657 return (status);
2716} 2658}
@@ -2801,15 +2743,15 @@ static u32 MT2063_GetReg(void *h, u8 reg, u8 * val)
2801static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo, 2743static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2802 enum MT2063_RCVR_MODES Mode) 2744 enum MT2063_RCVR_MODES Mode)
2803{ 2745{
2804 u32 status = MT2063_OK; /* Status to be returned */ 2746 u32 status = 0; /* Status to be returned */
2805 u8 val; 2747 u8 val;
2806 u32 longval; 2748 u32 longval;
2807 2749
2808 if (Mode >= MT2063_NUM_RCVR_MODES) 2750 if (Mode >= MT2063_NUM_RCVR_MODES)
2809 status = MT2063_ARG_RANGE; 2751 status = -ERANGE;
2810 2752
2811 /* RFAGCen */ 2753 /* RFAGCen */
2812 if (MT2063_NO_ERROR(status)) { 2754 if (status >= 0) {
2813 val = 2755 val =
2814 (pInfo-> 2756 (pInfo->
2815 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x40) | (RFAGCEN[Mode] 2757 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x40) | (RFAGCEN[Mode]
@@ -2821,12 +2763,12 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2821 } 2763 }
2822 2764
2823 /* LNARin */ 2765 /* LNARin */
2824 if (MT2063_NO_ERROR(status)) { 2766 if (status >= 0) {
2825 status |= MT2063_SetParam(pInfo, MT2063_LNA_RIN, LNARIN[Mode]); 2767 status |= MT2063_SetParam(pInfo, MT2063_LNA_RIN, LNARIN[Mode]);
2826 } 2768 }
2827 2769
2828 /* FIFFQEN and FIFFQ */ 2770 /* FIFFQEN and FIFFQ */
2829 if (MT2063_NO_ERROR(status)) { 2771 if (status >= 0) {
2830 val = 2772 val =
2831 (pInfo-> 2773 (pInfo->
2832 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~ 0xF0) | 2774 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~ 0xF0) |
@@ -2852,40 +2794,40 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2852 status |= MT2063_SetParam(pInfo, MT2063_DNC_OUTPUT_ENABLE, longval); 2794 status |= MT2063_SetParam(pInfo, MT2063_DNC_OUTPUT_ENABLE, longval);
2853 2795
2854 /* acLNAmax */ 2796 /* acLNAmax */
2855 if (MT2063_NO_ERROR(status)) { 2797 if (status >= 0) {
2856 status |= 2798 status |=
2857 MT2063_SetParam(pInfo, MT2063_ACLNA_MAX, ACLNAMAX[Mode]); 2799 MT2063_SetParam(pInfo, MT2063_ACLNA_MAX, ACLNAMAX[Mode]);
2858 } 2800 }
2859 2801
2860 /* LNATGT */ 2802 /* LNATGT */
2861 if (MT2063_NO_ERROR(status)) { 2803 if (status >= 0) {
2862 status |= MT2063_SetParam(pInfo, MT2063_LNA_TGT, LNATGT[Mode]); 2804 status |= MT2063_SetParam(pInfo, MT2063_LNA_TGT, LNATGT[Mode]);
2863 } 2805 }
2864 2806
2865 /* ACRF */ 2807 /* ACRF */
2866 if (MT2063_NO_ERROR(status)) { 2808 if (status >= 0) {
2867 status |= 2809 status |=
2868 MT2063_SetParam(pInfo, MT2063_ACRF_MAX, ACRFMAX[Mode]); 2810 MT2063_SetParam(pInfo, MT2063_ACRF_MAX, ACRFMAX[Mode]);
2869 } 2811 }
2870 2812
2871 /* PD1TGT */ 2813 /* PD1TGT */
2872 if (MT2063_NO_ERROR(status)) { 2814 if (status >= 0) {
2873 status |= MT2063_SetParam(pInfo, MT2063_PD1_TGT, PD1TGT[Mode]); 2815 status |= MT2063_SetParam(pInfo, MT2063_PD1_TGT, PD1TGT[Mode]);
2874 } 2816 }
2875 2817
2876 /* FIFATN */ 2818 /* FIFATN */
2877 if (MT2063_NO_ERROR(status)) { 2819 if (status >= 0) {
2878 status |= 2820 status |=
2879 MT2063_SetParam(pInfo, MT2063_ACFIF_MAX, ACFIFMAX[Mode]); 2821 MT2063_SetParam(pInfo, MT2063_ACFIF_MAX, ACFIFMAX[Mode]);
2880 } 2822 }
2881 2823
2882 /* PD2TGT */ 2824 /* PD2TGT */
2883 if (MT2063_NO_ERROR(status)) { 2825 if (status >= 0) {
2884 status |= MT2063_SetParam(pInfo, MT2063_PD2_TGT, PD2TGT[Mode]); 2826 status |= MT2063_SetParam(pInfo, MT2063_PD2_TGT, PD2TGT[Mode]);
2885 } 2827 }
2886 2828
2887 /* Ignore ATN Overload */ 2829 /* Ignore ATN Overload */
2888 if (MT2063_NO_ERROR(status)) { 2830 if (status >= 0) {
2889 val = 2831 val =
2890 (pInfo-> 2832 (pInfo->
2891 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x80) | (RFOVDIS[Mode] 2833 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x80) | (RFOVDIS[Mode]
@@ -2897,7 +2839,7 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2897 } 2839 }
2898 2840
2899 /* Ignore FIF Overload */ 2841 /* Ignore FIF Overload */
2900 if (MT2063_NO_ERROR(status)) { 2842 if (status >= 0) {
2901 val = 2843 val =
2902 (pInfo-> 2844 (pInfo->
2903 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) | 2845 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) |
@@ -2907,7 +2849,7 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2907 } 2849 }
2908 } 2850 }
2909 2851
2910 if (MT2063_NO_ERROR(status)) 2852 if (status >= 0)
2911 pInfo->rcvr_mode = Mode; 2853 pInfo->rcvr_mode = Mode;
2912 2854
2913 return (status); 2855 return (status);
@@ -2947,13 +2889,15 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2947** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2889** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2948** 2890**
2949******************************************************************************/ 2891******************************************************************************/
2950static u32 MT2063_ReInit(void *h) 2892static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2951{ 2893{
2952 u8 all_resets = 0xF0; /* reset/load bits */ 2894 u8 all_resets = 0xF0; /* reset/load bits */
2953 u32 status = MT2063_OK; /* Status to be returned */ 2895 u32 status = 0; /* Status to be returned */
2954 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
2955 u8 *def = NULL; 2896 u8 *def = NULL;
2956 2897 u32 FCRUN;
2898 s32 maxReads;
2899 u32 fcu_osc;
2900 u32 i;
2957 u8 MT2063B0_defaults[] = { /* Reg, Value */ 2901 u8 MT2063B0_defaults[] = { /* Reg, Value */
2958 0x19, 0x05, 2902 0x19, 0x05,
2959 0x1B, 0x1D, 2903 0x1B, 0x1D,
@@ -2976,7 +2920,6 @@ static u32 MT2063_ReInit(void *h)
2976 0x28, 0xE0, /* Clear the FIFCrst bit here */ 2920 0x28, 0xE0, /* Clear the FIFCrst bit here */
2977 0x00 2921 0x00
2978 }; 2922 };
2979
2980 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */ 2923 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
2981 u8 MT2063B1_defaults[] = { /* Reg, Value */ 2924 u8 MT2063B1_defaults[] = { /* Reg, Value */
2982 0x05, 0xF0, 2925 0x05, 0xF0,
@@ -3002,7 +2945,6 @@ static u32 MT2063_ReInit(void *h)
3002 0x28, 0xE0, /* Clear the FIFCrst bit here */ 2945 0x28, 0xE0, /* Clear the FIFCrst bit here */
3003 0x00 2946 0x00
3004 }; 2947 };
3005
3006 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */ 2948 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
3007 u8 MT2063B3_defaults[] = { /* Reg, Value */ 2949 u8 MT2063B3_defaults[] = { /* Reg, Value */
3008 0x05, 0xF0, 2950 0x05, 0xF0,
@@ -3016,37 +2958,35 @@ static u32 MT2063_ReInit(void *h)
3016 2958
3017 /* Verify that the handle passed points to a valid tuner */ 2959 /* Verify that the handle passed points to a valid tuner */
3018 if (MT2063_IsValidHandle(pInfo) == 0) 2960 if (MT2063_IsValidHandle(pInfo) == 0)
3019 status |= MT2063_INV_HANDLE; 2961 return -ENODEV;
3020 2962
3021 /* Read the Part/Rev code from the tuner */ 2963 /* Read the Part/Rev code from the tuner */
3022 if (MT2063_NO_ERROR(status)) { 2964 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address,
3023 status |= 2965 MT2063_REG_PART_REV, pInfo->reg, 1);
3024 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2966 if (status < 0)
3025 MT2063_REG_PART_REV, pInfo->reg, 1); 2967 return status;
3026 } 2968
3027 2969 /* Check the part/rev code */
3028 if (MT2063_NO_ERROR(status) /* Check the part/rev code */ 2970 if (((pInfo->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */
3029 &&((pInfo->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */ 2971 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */
3030 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */ 2972 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */
3031 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */ 2973 return -ENODEV; /* Wrong tuner Part/Rev code */
3032 status |= MT2063_TUNER_ID_ERR; /* Wrong tuner Part/Rev code */ 2974
3033 2975 /* Check the 2nd byte of the Part/Rev code from the tuner */
3034 /* Read the Part/Rev code (2nd byte) from the tuner */ 2976 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address,
3035 if (MT2063_NO_ERROR(status)) 2977 MT2063_REG_RSVD_3B,
3036 status |= 2978 &pInfo->reg[MT2063_REG_RSVD_3B], 1);
3037 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2979
3038 MT2063_REG_RSVD_3B, 2980 if (status >= 0
3039 &pInfo->reg[MT2063_REG_RSVD_3B], 1);
3040
3041 if (MT2063_NO_ERROR(status) /* Check the 2nd part/rev code */
3042 &&((pInfo->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) /* b7 != 0 ==> NOT MT2063 */ 2981 &&((pInfo->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) /* b7 != 0 ==> NOT MT2063 */
3043 status |= MT2063_TUNER_ID_ERR; /* Wrong tuner Part/Rev code */ 2982 return -ENODEV; /* Wrong tuner Part/Rev code */
3044 2983
3045 /* Reset the tuner */ 2984 /* Reset the tuner */
3046 if (MT2063_NO_ERROR(status)) 2985 status = MT2063_WriteSub(pInfo->hUserData,
3047 status |= MT2063_WriteSub(pInfo->hUserData, 2986 pInfo->address,
3048 pInfo->address, 2987 MT2063_REG_LO2CQ_3, &all_resets, 1);
3049 MT2063_REG_LO2CQ_3, &all_resets, 1); 2988 if (status < 0)
2989 return status;
3050 2990
3051 /* change all of the default values that vary from the HW reset values */ 2991 /* change all of the default values that vary from the HW reset values */
3052 /* def = (pInfo->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */ 2992 /* def = (pInfo->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
@@ -3064,145 +3004,136 @@ static u32 MT2063_ReInit(void *h)
3064 break; 3004 break;
3065 3005
3066 default: 3006 default:
3067 status |= MT2063_TUNER_ID_ERR; 3007 return -ENODEV;
3068 break; 3008 break;
3069 } 3009 }
3070 3010
3071 while (MT2063_NO_ERROR(status) && *def) { 3011 while (status >= 0 && *def) {
3072 u8 reg = *def++; 3012 u8 reg = *def++;
3073 u8 val = *def++; 3013 u8 val = *def++;
3074 status |= 3014 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg,
3075 MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg, &val, 3015 &val, 1);
3076 1);
3077 } 3016 }
3017 if (status < 0)
3018 return status;
3078 3019
3079 /* Wait for FIFF location to complete. */ 3020 /* Wait for FIFF location to complete. */
3080 if (MT2063_NO_ERROR(status)) { 3021 FCRUN = 1;
3081 u32 FCRUN = 1; 3022 maxReads = 10;
3082 s32 maxReads = 10; 3023 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
3083 while (MT2063_NO_ERROR(status) && (FCRUN != 0) 3024 msleep(2);
3084 && (maxReads-- > 0)) { 3025 status = MT2063_ReadSub(pInfo->hUserData,
3085 msleep(2); 3026 pInfo->address,
3086 status |= MT2063_ReadSub(pInfo->hUserData, 3027 MT2063_REG_XO_STATUS,
3087 pInfo->address, 3028 &pInfo->
3088 MT2063_REG_XO_STATUS, 3029 reg[MT2063_REG_XO_STATUS], 1);
3089 &pInfo-> 3030 FCRUN = (pInfo->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
3090 reg[MT2063_REG_XO_STATUS], 1);
3091 FCRUN = (pInfo->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
3092 }
3093
3094 if (FCRUN != 0)
3095 status |= MT2063_TUNER_INIT_ERR | MT2063_TUNER_TIMEOUT;
3096
3097 if (MT2063_NO_ERROR(status)) /* Re-read FIFFC value */
3098 status |=
3099 MT2063_ReadSub(pInfo->hUserData, pInfo->address,
3100 MT2063_REG_FIFFC,
3101 &pInfo->reg[MT2063_REG_FIFFC], 1);
3102 } 3031 }
3103 3032
3104 /* Read back all the registers from the tuner */ 3033 if (FCRUN != 0)
3105 if (MT2063_NO_ERROR(status)) 3034 return -ENODEV;
3106 status |= MT2063_ReadSub(pInfo->hUserData,
3107 pInfo->address,
3108 MT2063_REG_PART_REV,
3109 pInfo->reg, MT2063_REG_END_REGS);
3110 3035
3111 if (MT2063_NO_ERROR(status)) { 3036 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address,
3112 /* Initialize the tuner state. */ 3037 MT2063_REG_FIFFC,
3113 pInfo->tuner_id = pInfo->reg[MT2063_REG_PART_REV]; 3038 &pInfo->reg[MT2063_REG_FIFFC], 1);
3114 pInfo->AS_Data.f_ref = MT2063_REF_FREQ; 3039 if (status < 0)
3115 pInfo->AS_Data.f_if1_Center = 3040 return status;
3116 (pInfo->AS_Data.f_ref / 8) *
3117 ((u32) pInfo->reg[MT2063_REG_FIFFC] + 640);
3118 pInfo->AS_Data.f_if1_bw = MT2063_IF1_BW;
3119 pInfo->AS_Data.f_out = 43750000UL;
3120 pInfo->AS_Data.f_out_bw = 6750000UL;
3121 pInfo->AS_Data.f_zif_bw = MT2063_ZIF_BW;
3122 pInfo->AS_Data.f_LO1_Step = pInfo->AS_Data.f_ref / 64;
3123 pInfo->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
3124 pInfo->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
3125 pInfo->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
3126 pInfo->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
3127 pInfo->AS_Data.f_if1_Request = pInfo->AS_Data.f_if1_Center;
3128 pInfo->AS_Data.f_LO1 = 2181000000UL;
3129 pInfo->AS_Data.f_LO2 = 1486249786UL;
3130 pInfo->f_IF1_actual = pInfo->AS_Data.f_if1_Center;
3131 pInfo->AS_Data.f_in =
3132 pInfo->AS_Data.f_LO1 - pInfo->f_IF1_actual;
3133 pInfo->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
3134 pInfo->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
3135 pInfo->num_regs = MT2063_REG_END_REGS;
3136 pInfo->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
3137 pInfo->ctfilt_sw = 0;
3138 }
3139 3041
3140 if (MT2063_NO_ERROR(status)) { 3042 /* Read back all the registers from the tuner */
3141 pInfo->CTFiltMax[0] = 69230000; 3043 status = MT2063_ReadSub(pInfo->hUserData,
3142 pInfo->CTFiltMax[1] = 105770000; 3044 pInfo->address,
3143 pInfo->CTFiltMax[2] = 140350000; 3045 MT2063_REG_PART_REV,
3144 pInfo->CTFiltMax[3] = 177110000; 3046 pInfo->reg, MT2063_REG_END_REGS);
3145 pInfo->CTFiltMax[4] = 212860000; 3047 if (status < 0)
3146 pInfo->CTFiltMax[5] = 241130000; 3048 return status;
3147 pInfo->CTFiltMax[6] = 274370000; 3049
3148 pInfo->CTFiltMax[7] = 309820000; 3050 /* Initialize the tuner state. */
3149 pInfo->CTFiltMax[8] = 342450000; 3051 pInfo->tuner_id = pInfo->reg[MT2063_REG_PART_REV];
3150 pInfo->CTFiltMax[9] = 378870000; 3052 pInfo->AS_Data.f_ref = MT2063_REF_FREQ;
3151 pInfo->CTFiltMax[10] = 416210000; 3053 pInfo->AS_Data.f_if1_Center = (pInfo->AS_Data.f_ref / 8) *
3152 pInfo->CTFiltMax[11] = 456500000; 3054 ((u32) pInfo->reg[MT2063_REG_FIFFC] + 640);
3153 pInfo->CTFiltMax[12] = 495790000; 3055 pInfo->AS_Data.f_if1_bw = MT2063_IF1_BW;
3154 pInfo->CTFiltMax[13] = 534530000; 3056 pInfo->AS_Data.f_out = 43750000UL;
3155 pInfo->CTFiltMax[14] = 572610000; 3057 pInfo->AS_Data.f_out_bw = 6750000UL;
3156 pInfo->CTFiltMax[15] = 598970000; 3058 pInfo->AS_Data.f_zif_bw = MT2063_ZIF_BW;
3157 pInfo->CTFiltMax[16] = 635910000; 3059 pInfo->AS_Data.f_LO1_Step = pInfo->AS_Data.f_ref / 64;
3158 pInfo->CTFiltMax[17] = 672130000; 3060 pInfo->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
3159 pInfo->CTFiltMax[18] = 714840000; 3061 pInfo->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
3160 pInfo->CTFiltMax[19] = 739660000; 3062 pInfo->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
3161 pInfo->CTFiltMax[20] = 770410000; 3063 pInfo->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
3162 pInfo->CTFiltMax[21] = 814660000; 3064 pInfo->AS_Data.f_if1_Request = pInfo->AS_Data.f_if1_Center;
3163 pInfo->CTFiltMax[22] = 846950000; 3065 pInfo->AS_Data.f_LO1 = 2181000000UL;
3164 pInfo->CTFiltMax[23] = 867820000; 3066 pInfo->AS_Data.f_LO2 = 1486249786UL;
3165 pInfo->CTFiltMax[24] = 915980000; 3067 pInfo->f_IF1_actual = pInfo->AS_Data.f_if1_Center;
3166 pInfo->CTFiltMax[25] = 947450000; 3068 pInfo->AS_Data.f_in = pInfo->AS_Data.f_LO1 - pInfo->f_IF1_actual;
3167 pInfo->CTFiltMax[26] = 983110000; 3069 pInfo->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
3168 pInfo->CTFiltMax[27] = 1021630000; 3070 pInfo->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
3169 pInfo->CTFiltMax[28] = 1061870000; 3071 pInfo->num_regs = MT2063_REG_END_REGS;
3170 pInfo->CTFiltMax[29] = 1098330000; 3072 pInfo->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
3171 pInfo->CTFiltMax[30] = 1138990000; 3073 pInfo->ctfilt_sw = 0;
3172 } 3074
3075 pInfo->CTFiltMax[0] = 69230000;
3076 pInfo->CTFiltMax[1] = 105770000;
3077 pInfo->CTFiltMax[2] = 140350000;
3078 pInfo->CTFiltMax[3] = 177110000;
3079 pInfo->CTFiltMax[4] = 212860000;
3080 pInfo->CTFiltMax[5] = 241130000;
3081 pInfo->CTFiltMax[6] = 274370000;
3082 pInfo->CTFiltMax[7] = 309820000;
3083 pInfo->CTFiltMax[8] = 342450000;
3084 pInfo->CTFiltMax[9] = 378870000;
3085 pInfo->CTFiltMax[10] = 416210000;
3086 pInfo->CTFiltMax[11] = 456500000;
3087 pInfo->CTFiltMax[12] = 495790000;
3088 pInfo->CTFiltMax[13] = 534530000;
3089 pInfo->CTFiltMax[14] = 572610000;
3090 pInfo->CTFiltMax[15] = 598970000;
3091 pInfo->CTFiltMax[16] = 635910000;
3092 pInfo->CTFiltMax[17] = 672130000;
3093 pInfo->CTFiltMax[18] = 714840000;
3094 pInfo->CTFiltMax[19] = 739660000;
3095 pInfo->CTFiltMax[20] = 770410000;
3096 pInfo->CTFiltMax[21] = 814660000;
3097 pInfo->CTFiltMax[22] = 846950000;
3098 pInfo->CTFiltMax[23] = 867820000;
3099 pInfo->CTFiltMax[24] = 915980000;
3100 pInfo->CTFiltMax[25] = 947450000;
3101 pInfo->CTFiltMax[26] = 983110000;
3102 pInfo->CTFiltMax[27] = 1021630000;
3103 pInfo->CTFiltMax[28] = 1061870000;
3104 pInfo->CTFiltMax[29] = 1098330000;
3105 pInfo->CTFiltMax[30] = 1138990000;
3173 3106
3174 /* 3107 /*
3175 ** Fetch the FCU osc value and use it and the fRef value to 3108 ** Fetch the FCU osc value and use it and the fRef value to
3176 ** scale all of the Band Max values 3109 ** scale all of the Band Max values
3177 */ 3110 */
3178 if (MT2063_NO_ERROR(status)) {
3179 u32 fcu_osc;
3180 u32 i;
3181 3111
3182 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; 3112 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
3183 status |= 3113 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3184 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3114 MT2063_REG_CTUNE_CTRL,
3185 MT2063_REG_CTUNE_CTRL, 3115 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1);
3186 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 3116 if (status < 0)
3187 /* Read the ClearTune filter calibration value */ 3117 return status;
3188 status |= 3118 /* Read the ClearTune filter calibration value */
3189 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 3119 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address,
3190 MT2063_REG_FIFFC, 3120 MT2063_REG_FIFFC,
3191 &pInfo->reg[MT2063_REG_FIFFC], 1); 3121 &pInfo->reg[MT2063_REG_FIFFC], 1);
3192 fcu_osc = pInfo->reg[MT2063_REG_FIFFC]; 3122 if (status < 0)
3193 3123 return status;
3194 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x00; 3124
3195 status |= 3125 fcu_osc = pInfo->reg[MT2063_REG_FIFFC];
3196 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3126
3197 MT2063_REG_CTUNE_CTRL, 3127 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
3198 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 3128 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3199 3129 MT2063_REG_CTUNE_CTRL,
3200 /* Adjust each of the values in the ClearTune filter cross-over table */ 3130 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1);
3201 for (i = 0; i < 31; i++) { 3131 if (status < 0)
3202 pInfo->CTFiltMax[i] = 3132 return status;
3203 (pInfo->CTFiltMax[i] / 768) * (fcu_osc + 640); 3133
3204 } 3134 /* Adjust each of the values in the ClearTune filter cross-over table */
3205 } 3135 for (i = 0; i < 31; i++)
3136 pInfo->CTFiltMax[i] =(pInfo->CTFiltMax[i] / 768) * (fcu_osc + 640);
3206 3137
3207 return (status); 3138 return (status);
3208} 3139}
@@ -3290,595 +3221,592 @@ static u32 MT2063_ReInit(void *h)
3290** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 3221** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
3291** 3222**
3292****************************************************************************/ 3223****************************************************************************/
3293static u32 MT2063_SetParam(void *h, enum MT2063_Param param, u32 nValue) 3224static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 nValue)
3294{ 3225{
3295 u32 status = MT2063_OK; /* Status to be returned */ 3226 u32 status = 0; /* Status to be returned */
3296 u8 val = 0; 3227 u8 val = 0;
3297 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
3298 3228
3299 /* Verify that the handle passed points to a valid tuner */ 3229 /* Verify that the handle passed points to a valid tuner */
3300 if (MT2063_IsValidHandle(pInfo) == 0) 3230 if (MT2063_IsValidHandle(pInfo) == 0)
3301 status |= MT2063_INV_HANDLE; 3231 return -ENODEV;
3302
3303 if (MT2063_NO_ERROR(status)) {
3304 switch (param) {
3305 /* crystal frequency */
3306 case MT2063_SRO_FREQ:
3307 pInfo->AS_Data.f_ref = nValue;
3308 pInfo->AS_Data.f_LO1_FracN_Avoid = 0;
3309 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue / 80 - 1;
3310 pInfo->AS_Data.f_LO1_Step = nValue / 64;
3311 pInfo->AS_Data.f_if1_Center =
3312 (pInfo->AS_Data.f_ref / 8) *
3313 (pInfo->reg[MT2063_REG_FIFFC] + 640);
3314 break;
3315
3316 /* minimum tuning step size */
3317 case MT2063_STEPSIZE:
3318 pInfo->AS_Data.f_LO2_Step = nValue;
3319 break;
3320 3232
3321 /* LO1 frequency */ 3233 switch (param) {
3322 case MT2063_LO1_FREQ: 3234 /* crystal frequency */
3323 { 3235 case MT2063_SRO_FREQ:
3324 /* Note: LO1 and LO2 are BOTH written at toggle of LDLOos */ 3236 pInfo->AS_Data.f_ref = nValue;
3325 /* Capture the Divider and Numerator portions of other LO */ 3237 pInfo->AS_Data.f_LO1_FracN_Avoid = 0;
3326 u8 tempLO2CQ[3]; 3238 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue / 80 - 1;
3327 u8 tempLO2C[3]; 3239 pInfo->AS_Data.f_LO1_Step = nValue / 64;
3328 u8 tmpOneShot; 3240 pInfo->AS_Data.f_if1_Center =
3329 u32 Div, FracN; 3241 (pInfo->AS_Data.f_ref / 8) *
3330 u8 restore = 0; 3242 (pInfo->reg[MT2063_REG_FIFFC] + 640);
3331 3243 break;
3332 /* Buffer the queue for restoration later and get actual LO2 values. */
3333 status |=
3334 MT2063_ReadSub(pInfo->hUserData,
3335 pInfo->address,
3336 MT2063_REG_LO2CQ_1,
3337 &(tempLO2CQ[0]), 3);
3338 status |=
3339 MT2063_ReadSub(pInfo->hUserData,
3340 pInfo->address,
3341 MT2063_REG_LO2C_1,
3342 &(tempLO2C[0]), 3);
3343
3344 /* clear the one-shot bits */
3345 tempLO2CQ[2] = tempLO2CQ[2] & 0x0F;
3346 tempLO2C[2] = tempLO2C[2] & 0x0F;
3347
3348 /* only write the queue values if they are different from the actual. */
3349 if ((tempLO2CQ[0] != tempLO2C[0]) ||
3350 (tempLO2CQ[1] != tempLO2C[1]) ||
3351 (tempLO2CQ[2] != tempLO2C[2])) {
3352 /* put actual LO2 value into queue (with 0 in one-shot bits) */
3353 status |=
3354 MT2063_WriteSub(pInfo->hUserData,
3355 pInfo->address,
3356 MT2063_REG_LO2CQ_1,
3357 &(tempLO2C[0]), 3);
3358
3359 if (status == MT2063_OK) {
3360 /* cache the bytes just written. */
3361 pInfo->reg[MT2063_REG_LO2CQ_1] =
3362 tempLO2C[0];
3363 pInfo->reg[MT2063_REG_LO2CQ_2] =
3364 tempLO2C[1];
3365 pInfo->reg[MT2063_REG_LO2CQ_3] =
3366 tempLO2C[2];
3367 }
3368 restore = 1;
3369 }
3370 3244
3371 /* Calculate the Divider and Numberator components of LO1 */ 3245 /* minimum tuning step size */
3372 status = 3246 case MT2063_STEPSIZE:
3373 MT2063_CalcLO1Mult(&Div, &FracN, nValue, 3247 pInfo->AS_Data.f_LO2_Step = nValue;
3374 pInfo->AS_Data.f_ref / 3248 break;
3375 64,
3376 pInfo->AS_Data.f_ref);
3377 pInfo->reg[MT2063_REG_LO1CQ_1] =
3378 (u8) (Div & 0x00FF);
3379 pInfo->reg[MT2063_REG_LO1CQ_2] =
3380 (u8) (FracN);
3381 status |=
3382 MT2063_WriteSub(pInfo->hUserData,
3383 pInfo->address,
3384 MT2063_REG_LO1CQ_1,
3385 &pInfo->
3386 reg[MT2063_REG_LO1CQ_1], 2);
3387 3249
3388 /* set the one-shot bit to load the pair of LO values */ 3250 /* LO1 frequency */
3389 tmpOneShot = tempLO2CQ[2] | 0xE0; 3251 case MT2063_LO1_FREQ:
3252 {
3253 /* Note: LO1 and LO2 are BOTH written at toggle of LDLOos */
3254 /* Capture the Divider and Numerator portions of other LO */
3255 u8 tempLO2CQ[3];
3256 u8 tempLO2C[3];
3257 u8 tmpOneShot;
3258 u32 Div, FracN;
3259 u8 restore = 0;
3260
3261 /* Buffer the queue for restoration later and get actual LO2 values. */
3262 status |=
3263 MT2063_ReadSub(pInfo->hUserData,
3264 pInfo->address,
3265 MT2063_REG_LO2CQ_1,
3266 &(tempLO2CQ[0]), 3);
3267 status |=
3268 MT2063_ReadSub(pInfo->hUserData,
3269 pInfo->address,
3270 MT2063_REG_LO2C_1,
3271 &(tempLO2C[0]), 3);
3272
3273 /* clear the one-shot bits */
3274 tempLO2CQ[2] = tempLO2CQ[2] & 0x0F;
3275 tempLO2C[2] = tempLO2C[2] & 0x0F;
3276
3277 /* only write the queue values if they are different from the actual. */
3278 if ((tempLO2CQ[0] != tempLO2C[0]) ||
3279 (tempLO2CQ[1] != tempLO2C[1]) ||
3280 (tempLO2CQ[2] != tempLO2C[2])) {
3281 /* put actual LO2 value into queue (with 0 in one-shot bits) */
3390 status |= 3282 status |=
3391 MT2063_WriteSub(pInfo->hUserData, 3283 MT2063_WriteSub(pInfo->hUserData,
3392 pInfo->address, 3284 pInfo->address,
3393 MT2063_REG_LO2CQ_3, 3285 MT2063_REG_LO2CQ_1,
3394 &tmpOneShot, 1); 3286 &(tempLO2C[0]), 3);
3395
3396 /* only restore the queue values if they were different from the actual. */
3397 if (restore) {
3398 /* put actual LO2 value into queue (0 in one-shot bits) */
3399 status |=
3400 MT2063_WriteSub(pInfo->hUserData,
3401 pInfo->address,
3402 MT2063_REG_LO2CQ_1,
3403 &(tempLO2CQ[0]), 3);
3404 3287
3288 if (status == 0) {
3405 /* cache the bytes just written. */ 3289 /* cache the bytes just written. */
3406 pInfo->reg[MT2063_REG_LO2CQ_1] = 3290 pInfo->reg[MT2063_REG_LO2CQ_1] =
3407 tempLO2CQ[0]; 3291 tempLO2C[0];
3408 pInfo->reg[MT2063_REG_LO2CQ_2] = 3292 pInfo->reg[MT2063_REG_LO2CQ_2] =
3409 tempLO2CQ[1]; 3293 tempLO2C[1];
3410 pInfo->reg[MT2063_REG_LO2CQ_3] = 3294 pInfo->reg[MT2063_REG_LO2CQ_3] =
3411 tempLO2CQ[2]; 3295 tempLO2C[2];
3412 } 3296 }
3413 3297 restore = 1;
3414 MT2063_GetParam(pInfo->hUserData,
3415 MT2063_LO1_FREQ,
3416 &pInfo->AS_Data.f_LO1);
3417 } 3298 }
3418 break;
3419 3299
3420 /* LO1 minimum step size */ 3300 /* Calculate the Divider and Numberator components of LO1 */
3421 case MT2063_LO1_STEPSIZE: 3301 status =
3422 pInfo->AS_Data.f_LO1_Step = nValue; 3302 MT2063_CalcLO1Mult(&Div, &FracN, nValue,
3423 break; 3303 pInfo->AS_Data.f_ref /
3304 64,
3305 pInfo->AS_Data.f_ref);
3306 pInfo->reg[MT2063_REG_LO1CQ_1] =
3307 (u8) (Div & 0x00FF);
3308 pInfo->reg[MT2063_REG_LO1CQ_2] =
3309 (u8) (FracN);
3310 status |=
3311 MT2063_WriteSub(pInfo->hUserData,
3312 pInfo->address,
3313 MT2063_REG_LO1CQ_1,
3314 &pInfo->
3315 reg[MT2063_REG_LO1CQ_1], 2);
3316
3317 /* set the one-shot bit to load the pair of LO values */
3318 tmpOneShot = tempLO2CQ[2] | 0xE0;
3319 status |=
3320 MT2063_WriteSub(pInfo->hUserData,
3321 pInfo->address,
3322 MT2063_REG_LO2CQ_3,
3323 &tmpOneShot, 1);
3324
3325 /* only restore the queue values if they were different from the actual. */
3326 if (restore) {
3327 /* put actual LO2 value into queue (0 in one-shot bits) */
3328 status |=
3329 MT2063_WriteSub(pInfo->hUserData,
3330 pInfo->address,
3331 MT2063_REG_LO2CQ_1,
3332 &(tempLO2CQ[0]), 3);
3424 3333
3425 /* LO1 FracN keep-out region */ 3334 /* cache the bytes just written. */
3426 case MT2063_LO1_FRACN_AVOID_PARAM: 3335 pInfo->reg[MT2063_REG_LO2CQ_1] =
3427 pInfo->AS_Data.f_LO1_FracN_Avoid = nValue; 3336 tempLO2CQ[0];
3428 break; 3337 pInfo->reg[MT2063_REG_LO2CQ_2] =
3338 tempLO2CQ[1];
3339 pInfo->reg[MT2063_REG_LO2CQ_3] =
3340 tempLO2CQ[2];
3341 }
3429 3342
3430 /* Requested 1st IF */ 3343 MT2063_GetParam(pInfo->hUserData,
3431 case MT2063_IF1_REQUEST: 3344 MT2063_LO1_FREQ,
3432 pInfo->AS_Data.f_if1_Request = nValue; 3345 &pInfo->AS_Data.f_LO1);
3433 break; 3346 }
3347 break;
3434 3348
3435 /* zero-IF bandwidth */ 3349 /* LO1 minimum step size */
3436 case MT2063_ZIF_BW: 3350 case MT2063_LO1_STEPSIZE:
3437 pInfo->AS_Data.f_zif_bw = nValue; 3351 pInfo->AS_Data.f_LO1_Step = nValue;
3438 break; 3352 break;
3439 3353
3440 /* LO2 frequency */ 3354 /* LO1 FracN keep-out region */
3441 case MT2063_LO2_FREQ: 3355 case MT2063_LO1_FRACN_AVOID_PARAM:
3442 { 3356 pInfo->AS_Data.f_LO1_FracN_Avoid = nValue;
3443 /* Note: LO1 and LO2 are BOTH written at toggle of LDLOos */ 3357 break;
3444 /* Capture the Divider and Numerator portions of other LO */
3445 u8 tempLO1CQ[2];
3446 u8 tempLO1C[2];
3447 u32 Div2;
3448 u32 FracN2;
3449 u8 tmpOneShot;
3450 u8 restore = 0;
3451
3452 /* Buffer the queue for restoration later and get actual LO2 values. */
3453 status |=
3454 MT2063_ReadSub(pInfo->hUserData,
3455 pInfo->address,
3456 MT2063_REG_LO1CQ_1,
3457 &(tempLO1CQ[0]), 2);
3458 status |=
3459 MT2063_ReadSub(pInfo->hUserData,
3460 pInfo->address,
3461 MT2063_REG_LO1C_1,
3462 &(tempLO1C[0]), 2);
3463
3464 /* only write the queue values if they are different from the actual. */
3465 if ((tempLO1CQ[0] != tempLO1C[0])
3466 || (tempLO1CQ[1] != tempLO1C[1])) {
3467 /* put actual LO1 value into queue */
3468 status |=
3469 MT2063_WriteSub(pInfo->hUserData,
3470 pInfo->address,
3471 MT2063_REG_LO1CQ_1,
3472 &(tempLO1C[0]), 2);
3473 3358
3474 /* cache the bytes just written. */ 3359 /* Requested 1st IF */
3475 pInfo->reg[MT2063_REG_LO1CQ_1] = 3360 case MT2063_IF1_REQUEST:
3476 tempLO1C[0]; 3361 pInfo->AS_Data.f_if1_Request = nValue;
3477 pInfo->reg[MT2063_REG_LO1CQ_2] = 3362 break;
3478 tempLO1C[1];
3479 restore = 1;
3480 }
3481 3363
3482 /* Calculate the Divider and Numberator components of LO2 */ 3364 /* zero-IF bandwidth */
3483 status = 3365 case MT2063_ZIF_BW:
3484 MT2063_CalcLO2Mult(&Div2, &FracN2, nValue, 3366 pInfo->AS_Data.f_zif_bw = nValue;
3485 pInfo->AS_Data.f_ref / 3367 break;
3486 8191, 3368
3487 pInfo->AS_Data.f_ref); 3369 /* LO2 frequency */
3488 pInfo->reg[MT2063_REG_LO2CQ_1] = 3370 case MT2063_LO2_FREQ:
3489 (u8) ((Div2 << 1) | 3371 {
3490 ((FracN2 >> 12) & 0x01)) & 0xFF; 3372 /* Note: LO1 and LO2 are BOTH written at toggle of LDLOos */
3491 pInfo->reg[MT2063_REG_LO2CQ_2] = 3373 /* Capture the Divider and Numerator portions of other LO */
3492 (u8) ((FracN2 >> 4) & 0xFF); 3374 u8 tempLO1CQ[2];
3493 pInfo->reg[MT2063_REG_LO2CQ_3] = 3375 u8 tempLO1C[2];
3494 (u8) ((FracN2 & 0x0F)); 3376 u32 Div2;
3377 u32 FracN2;
3378 u8 tmpOneShot;
3379 u8 restore = 0;
3380
3381 /* Buffer the queue for restoration later and get actual LO2 values. */
3382 status |=
3383 MT2063_ReadSub(pInfo->hUserData,
3384 pInfo->address,
3385 MT2063_REG_LO1CQ_1,
3386 &(tempLO1CQ[0]), 2);
3387 status |=
3388 MT2063_ReadSub(pInfo->hUserData,
3389 pInfo->address,
3390 MT2063_REG_LO1C_1,
3391 &(tempLO1C[0]), 2);
3392
3393 /* only write the queue values if they are different from the actual. */
3394 if ((tempLO1CQ[0] != tempLO1C[0])
3395 || (tempLO1CQ[1] != tempLO1C[1])) {
3396 /* put actual LO1 value into queue */
3495 status |= 3397 status |=
3496 MT2063_WriteSub(pInfo->hUserData, 3398 MT2063_WriteSub(pInfo->hUserData,
3497 pInfo->address, 3399 pInfo->address,
3498 MT2063_REG_LO1CQ_1, 3400 MT2063_REG_LO1CQ_1,
3499 &pInfo-> 3401 &(tempLO1C[0]), 2);
3500 reg[MT2063_REG_LO1CQ_1], 3); 3402
3403 /* cache the bytes just written. */
3404 pInfo->reg[MT2063_REG_LO1CQ_1] =
3405 tempLO1C[0];
3406 pInfo->reg[MT2063_REG_LO1CQ_2] =
3407 tempLO1C[1];
3408 restore = 1;
3409 }
3501 3410
3502 /* set the one-shot bit to load the LO values */ 3411 /* Calculate the Divider and Numberator components of LO2 */
3503 tmpOneShot = 3412 status =
3504 pInfo->reg[MT2063_REG_LO2CQ_3] | 0xE0; 3413 MT2063_CalcLO2Mult(&Div2, &FracN2, nValue,
3414 pInfo->AS_Data.f_ref /
3415 8191,
3416 pInfo->AS_Data.f_ref);
3417 pInfo->reg[MT2063_REG_LO2CQ_1] =
3418 (u8) ((Div2 << 1) |
3419 ((FracN2 >> 12) & 0x01)) & 0xFF;
3420 pInfo->reg[MT2063_REG_LO2CQ_2] =
3421 (u8) ((FracN2 >> 4) & 0xFF);
3422 pInfo->reg[MT2063_REG_LO2CQ_3] =
3423 (u8) ((FracN2 & 0x0F));
3424 status |=
3425 MT2063_WriteSub(pInfo->hUserData,
3426 pInfo->address,
3427 MT2063_REG_LO1CQ_1,
3428 &pInfo->
3429 reg[MT2063_REG_LO1CQ_1], 3);
3430
3431 /* set the one-shot bit to load the LO values */
3432 tmpOneShot =
3433 pInfo->reg[MT2063_REG_LO2CQ_3] | 0xE0;
3434 status |=
3435 MT2063_WriteSub(pInfo->hUserData,
3436 pInfo->address,
3437 MT2063_REG_LO2CQ_3,
3438 &tmpOneShot, 1);
3439
3440 /* only restore LO1 queue value if they were different from the actual. */
3441 if (restore) {
3442 /* put previous LO1 queue value back into queue */
3505 status |= 3443 status |=
3506 MT2063_WriteSub(pInfo->hUserData, 3444 MT2063_WriteSub(pInfo->hUserData,
3507 pInfo->address, 3445 pInfo->address,
3508 MT2063_REG_LO2CQ_3, 3446 MT2063_REG_LO1CQ_1,
3509 &tmpOneShot, 1); 3447 &(tempLO1CQ[0]), 2);
3510 3448
3511 /* only restore LO1 queue value if they were different from the actual. */ 3449 /* cache the bytes just written. */
3512 if (restore) { 3450 pInfo->reg[MT2063_REG_LO1CQ_1] =
3513 /* put previous LO1 queue value back into queue */ 3451 tempLO1CQ[0];
3514 status |= 3452 pInfo->reg[MT2063_REG_LO1CQ_2] =
3515 MT2063_WriteSub(pInfo->hUserData, 3453 tempLO1CQ[1];
3516 pInfo->address, 3454 }
3517 MT2063_REG_LO1CQ_1,
3518 &(tempLO1CQ[0]), 2);
3519 3455
3520 /* cache the bytes just written. */ 3456 MT2063_GetParam(pInfo->hUserData,
3521 pInfo->reg[MT2063_REG_LO1CQ_1] = 3457 MT2063_LO2_FREQ,
3522 tempLO1CQ[0]; 3458 &pInfo->AS_Data.f_LO2);
3523 pInfo->reg[MT2063_REG_LO1CQ_2] = 3459 }
3524 tempLO1CQ[1]; 3460 break;
3525 }
3526 3461
3527 MT2063_GetParam(pInfo->hUserData, 3462 /* LO2 minimum step size */
3528 MT2063_LO2_FREQ, 3463 case MT2063_LO2_STEPSIZE:
3529 &pInfo->AS_Data.f_LO2); 3464 pInfo->AS_Data.f_LO2_Step = nValue;
3530 } 3465 break;
3531 break;
3532 3466
3533 /* LO2 minimum step size */ 3467 /* LO2 FracN keep-out region */
3534 case MT2063_LO2_STEPSIZE: 3468 case MT2063_LO2_FRACN_AVOID:
3535 pInfo->AS_Data.f_LO2_Step = nValue; 3469 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue;
3536 break; 3470 break;
3537 3471
3538 /* LO2 FracN keep-out region */ 3472 /* output center frequency */
3539 case MT2063_LO2_FRACN_AVOID: 3473 case MT2063_OUTPUT_FREQ:
3540 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue; 3474 pInfo->AS_Data.f_out = nValue;
3541 break; 3475 break;
3542 3476
3543 /* output center frequency */ 3477 /* output bandwidth */
3544 case MT2063_OUTPUT_FREQ: 3478 case MT2063_OUTPUT_BW:
3545 pInfo->AS_Data.f_out = nValue; 3479 pInfo->AS_Data.f_out_bw = nValue + 750000;
3546 break; 3480 break;
3547 3481
3548 /* output bandwidth */ 3482 /* min inter-tuner LO separation */
3549 case MT2063_OUTPUT_BW: 3483 case MT2063_LO_SEPARATION:
3550 pInfo->AS_Data.f_out_bw = nValue + 750000; 3484 pInfo->AS_Data.f_min_LO_Separation = nValue;
3551 break; 3485 break;
3552 3486
3553 /* min inter-tuner LO separation */ 3487 /* max # of intra-tuner harmonics */
3554 case MT2063_LO_SEPARATION: 3488 case MT2063_MAX_HARM1:
3555 pInfo->AS_Data.f_min_LO_Separation = nValue; 3489 pInfo->AS_Data.maxH1 = nValue;
3556 break; 3490 break;
3557 3491
3558 /* max # of intra-tuner harmonics */ 3492 /* max # of inter-tuner harmonics */
3559 case MT2063_MAX_HARM1: 3493 case MT2063_MAX_HARM2:
3560 pInfo->AS_Data.maxH1 = nValue; 3494 pInfo->AS_Data.maxH2 = nValue;
3561 break; 3495 break;
3562 3496
3563 /* max # of inter-tuner harmonics */ 3497 case MT2063_RCVR_MODE:
3564 case MT2063_MAX_HARM2: 3498 status |=
3565 pInfo->AS_Data.maxH2 = nValue; 3499 MT2063_SetReceiverMode(pInfo,
3566 break; 3500 (enum MT2063_RCVR_MODES)
3501 nValue);
3502 break;
3567 3503
3568 case MT2063_RCVR_MODE: 3504 /* Set LNA Rin -- nValue is desired value */
3505 case MT2063_LNA_RIN:
3506 val =
3507 (pInfo->
3508 reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) |
3509 (nValue & 0x03);
3510 if (pInfo->reg[MT2063_REG_CTRL_2C] != val) {
3569 status |= 3511 status |=
3570 MT2063_SetReceiverMode(pInfo, 3512 MT2063_SetReg(pInfo, MT2063_REG_CTRL_2C,
3571 (enum MT2063_RCVR_MODES) 3513 val);
3572 nValue); 3514 }
3573 break; 3515 break;
3574 3516
3575 /* Set LNA Rin -- nValue is desired value */ 3517 /* Set target power level at LNA -- nValue is desired value */
3576 case MT2063_LNA_RIN: 3518 case MT2063_LNA_TGT:
3577 val = 3519 val =
3578 (pInfo-> 3520 (pInfo->
3579 reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) | 3521 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) |
3580 (nValue & 0x03); 3522 (nValue & 0x3F);
3581 if (pInfo->reg[MT2063_REG_CTRL_2C] != val) { 3523 if (pInfo->reg[MT2063_REG_LNA_TGT] != val) {
3582 status |= 3524 status |=
3583 MT2063_SetReg(pInfo, MT2063_REG_CTRL_2C, 3525 MT2063_SetReg(pInfo, MT2063_REG_LNA_TGT,
3584 val); 3526 val);
3585 } 3527 }
3586 break; 3528 break;
3587 3529
3588 /* Set target power level at LNA -- nValue is desired value */ 3530 /* Set target power level at PD1 -- nValue is desired value */
3589 case MT2063_LNA_TGT: 3531 case MT2063_PD1_TGT:
3590 val = 3532 val =
3591 (pInfo-> 3533 (pInfo->
3592 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) | 3534 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) |
3593 (nValue & 0x3F); 3535 (nValue & 0x3F);
3594 if (pInfo->reg[MT2063_REG_LNA_TGT] != val) { 3536 if (pInfo->reg[MT2063_REG_PD1_TGT] != val) {
3595 status |= 3537 status |=
3596 MT2063_SetReg(pInfo, MT2063_REG_LNA_TGT, 3538 MT2063_SetReg(pInfo, MT2063_REG_PD1_TGT,
3597 val); 3539 val);
3598 } 3540 }
3599 break; 3541 break;
3600 3542
3601 /* Set target power level at PD1 -- nValue is desired value */ 3543 /* Set target power level at PD2 -- nValue is desired value */
3602 case MT2063_PD1_TGT: 3544 case MT2063_PD2_TGT:
3603 val = 3545 val =
3604 (pInfo-> 3546 (pInfo->
3605 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) | 3547 reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) |
3606 (nValue & 0x3F); 3548 (nValue & 0x3F);
3607 if (pInfo->reg[MT2063_REG_PD1_TGT] != val) { 3549 if (pInfo->reg[MT2063_REG_PD2_TGT] != val) {
3608 status |= 3550 status |=
3609 MT2063_SetReg(pInfo, MT2063_REG_PD1_TGT, 3551 MT2063_SetReg(pInfo, MT2063_REG_PD2_TGT,
3610 val); 3552 val);
3611 } 3553 }
3612 break; 3554 break;
3613 3555
3614 /* Set target power level at PD2 -- nValue is desired value */ 3556 /* Set LNA atten limit -- nValue is desired value */
3615 case MT2063_PD2_TGT: 3557 case MT2063_ACLNA_MAX:
3616 val = 3558 val =
3617 (pInfo-> 3559 (pInfo->
3618 reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) | 3560 reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) | (nValue
3619 (nValue & 0x3F); 3561 &
3620 if (pInfo->reg[MT2063_REG_PD2_TGT] != val) { 3562 0x1F);
3621 status |= 3563 if (pInfo->reg[MT2063_REG_LNA_OV] != val) {
3622 MT2063_SetReg(pInfo, MT2063_REG_PD2_TGT, 3564 status |=
3623 val); 3565 MT2063_SetReg(pInfo, MT2063_REG_LNA_OV,
3624 } 3566 val);
3625 break; 3567 }
3568 break;
3626 3569
3627 /* Set LNA atten limit -- nValue is desired value */ 3570 /* Set RF atten limit -- nValue is desired value */
3628 case MT2063_ACLNA_MAX: 3571 case MT2063_ACRF_MAX:
3629 val = 3572 val =
3630 (pInfo-> 3573 (pInfo->
3631 reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) | (nValue 3574 reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) | (nValue
3632 & 3575 &
3633 0x1F); 3576 0x1F);
3634 if (pInfo->reg[MT2063_REG_LNA_OV] != val) { 3577 if (pInfo->reg[MT2063_REG_RF_OV] != val) {
3635 status |= 3578 status |=
3636 MT2063_SetReg(pInfo, MT2063_REG_LNA_OV, 3579 MT2063_SetReg(pInfo, MT2063_REG_RF_OV, val);
3637 val); 3580 }
3638 } 3581 break;
3639 break;
3640 3582
3641 /* Set RF atten limit -- nValue is desired value */ 3583 /* Set FIF atten limit -- nValue is desired value, max. 5 if no B3 */
3642 case MT2063_ACRF_MAX: 3584 case MT2063_ACFIF_MAX:
3643 val = 3585 if (pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3
3644 (pInfo-> 3586 && nValue > 5)
3645 reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) | (nValue 3587 nValue = 5;
3646 & 3588 val =
3647 0x1F); 3589 (pInfo->
3648 if (pInfo->reg[MT2063_REG_RF_OV] != val) { 3590 reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) | (nValue
3649 status |= 3591 &
3650 MT2063_SetReg(pInfo, MT2063_REG_RF_OV, val); 3592 0x1F);
3651 } 3593 if (pInfo->reg[MT2063_REG_FIF_OV] != val) {
3652 break; 3594 status |=
3595 MT2063_SetReg(pInfo, MT2063_REG_FIF_OV,
3596 val);
3597 }
3598 break;
3653 3599
3654 /* Set FIF atten limit -- nValue is desired value, max. 5 if no B3 */ 3600 case MT2063_DNC_OUTPUT_ENABLE:
3655 case MT2063_ACFIF_MAX: 3601 /* selects, which DNC output is used */
3656 if (pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3 3602 switch ((enum MT2063_DNC_Output_Enable)nValue) {
3657 && nValue > 5) 3603 case MT2063_DNC_NONE:
3658 nValue = 5; 3604 {
3659 val = 3605 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3660 (pInfo-> 3606 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3661 reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) | (nValue 3607 val)
3662 & 3608 status |=
3663 0x1F); 3609 MT2063_SetReg(pInfo,
3664 if (pInfo->reg[MT2063_REG_FIF_OV] != val) { 3610 MT2063_REG_DNC_GAIN,
3665 status |= 3611 val);
3666 MT2063_SetReg(pInfo, MT2063_REG_FIF_OV, 3612
3667 val); 3613 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3668 } 3614 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3669 break; 3615 val)
3616 status |=
3617 MT2063_SetReg(pInfo,
3618 MT2063_REG_VGA_GAIN,
3619 val);
3620
3621 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3622 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3623 val)
3624 status |=
3625 MT2063_SetReg(pInfo,
3626 MT2063_REG_RSVD_20,
3627 val);
3670 3628
3671 case MT2063_DNC_OUTPUT_ENABLE:
3672 /* selects, which DNC output is used */
3673 switch ((enum MT2063_DNC_Output_Enable)nValue) {
3674 case MT2063_DNC_NONE:
3675 {
3676 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3677 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3678 val)
3679 status |=
3680 MT2063_SetReg(h,
3681 MT2063_REG_DNC_GAIN,
3682 val);
3683
3684 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3685 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3686 val)
3687 status |=
3688 MT2063_SetReg(h,
3689 MT2063_REG_VGA_GAIN,
3690 val);
3691
3692 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3693 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3694 val)
3695 status |=
3696 MT2063_SetReg(h,
3697 MT2063_REG_RSVD_20,
3698 val);
3699
3700 break;
3701 }
3702 case MT2063_DNC_1:
3703 {
3704 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3705 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3706 val)
3707 status |=
3708 MT2063_SetReg(h,
3709 MT2063_REG_DNC_GAIN,
3710 val);
3711
3712 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3713 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3714 val)
3715 status |=
3716 MT2063_SetReg(h,
3717 MT2063_REG_VGA_GAIN,
3718 val);
3719
3720 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3721 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3722 val)
3723 status |=
3724 MT2063_SetReg(h,
3725 MT2063_REG_RSVD_20,
3726 val);
3727
3728 break;
3729 }
3730 case MT2063_DNC_2:
3731 {
3732 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3733 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3734 val)
3735 status |=
3736 MT2063_SetReg(h,
3737 MT2063_REG_DNC_GAIN,
3738 val);
3739
3740 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3741 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3742 val)
3743 status |=
3744 MT2063_SetReg(h,
3745 MT2063_REG_VGA_GAIN,
3746 val);
3747
3748 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3749 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3750 val)
3751 status |=
3752 MT2063_SetReg(h,
3753 MT2063_REG_RSVD_20,
3754 val);
3755
3756 break;
3757 }
3758 case MT2063_DNC_BOTH:
3759 {
3760 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3761 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3762 val)
3763 status |=
3764 MT2063_SetReg(h,
3765 MT2063_REG_DNC_GAIN,
3766 val);
3767
3768 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3769 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3770 val)
3771 status |=
3772 MT2063_SetReg(h,
3773 MT2063_REG_VGA_GAIN,
3774 val);
3775
3776 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3777 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3778 val)
3779 status |=
3780 MT2063_SetReg(h,
3781 MT2063_REG_RSVD_20,
3782 val);
3783
3784 break;
3785 }
3786 default:
3787 break; 3629 break;
3788 } 3630 }
3789 break; 3631 case MT2063_DNC_1:
3632 {
3633 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3634 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3635 val)
3636 status |=
3637 MT2063_SetReg(pInfo,
3638 MT2063_REG_DNC_GAIN,
3639 val);
3790 3640
3791 case MT2063_VGAGC: 3641 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3792 /* Set VGA gain code */ 3642 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3793 val = 3643 val)
3794 (pInfo-> 3644 status |=
3795 reg[MT2063_REG_VGA_GAIN] & (u8) ~ 0x0C) | 3645 MT2063_SetReg(pInfo,
3796 ((nValue & 0x03) << 2); 3646 MT2063_REG_VGA_GAIN,
3797 if (pInfo->reg[MT2063_REG_VGA_GAIN] != val) { 3647 val);
3798 status |=
3799 MT2063_SetReg(pInfo, MT2063_REG_VGA_GAIN,
3800 val);
3801 }
3802 break;
3803 3648
3804 case MT2063_VGAOI: 3649 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3805 /* Set VGA bias current */ 3650 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3806 val = 3651 val)
3807 (pInfo-> 3652 status |=
3808 reg[MT2063_REG_RSVD_31] & (u8) ~ 0x07) | 3653 MT2063_SetReg(pInfo,
3809 (nValue & 0x07); 3654 MT2063_REG_RSVD_20,
3810 if (pInfo->reg[MT2063_REG_RSVD_31] != val) { 3655 val);
3811 status |=
3812 MT2063_SetReg(pInfo, MT2063_REG_RSVD_31,
3813 val);
3814 }
3815 break;
3816 3656
3817 case MT2063_TAGC: 3657 break;
3818 /* Set TAGC */
3819 val =
3820 (pInfo->
3821 reg[MT2063_REG_RSVD_1E] & (u8) ~ 0x03) |
3822 (nValue & 0x03);
3823 if (pInfo->reg[MT2063_REG_RSVD_1E] != val) {
3824 status |=
3825 MT2063_SetReg(pInfo, MT2063_REG_RSVD_1E,
3826 val);
3827 } 3658 }
3828 break; 3659 case MT2063_DNC_2:
3660 {
3661 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3662 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3663 val)
3664 status |=
3665 MT2063_SetReg(pInfo,
3666 MT2063_REG_DNC_GAIN,
3667 val);
3829 3668
3830 case MT2063_AMPGC: 3669 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3831 /* Set Amp gain code */ 3670 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3832 val = 3671 val)
3833 (pInfo-> 3672 status |=
3834 reg[MT2063_REG_TEMP_SEL] & (u8) ~ 0x03) | 3673 MT2063_SetReg(pInfo,
3835 (nValue & 0x03); 3674 MT2063_REG_VGA_GAIN,
3836 if (pInfo->reg[MT2063_REG_TEMP_SEL] != val) { 3675 val);
3837 status |= 3676
3838 MT2063_SetReg(pInfo, MT2063_REG_TEMP_SEL, 3677 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3839 val); 3678 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3840 } 3679 val)
3841 break; 3680 status |=
3681 MT2063_SetReg(pInfo,
3682 MT2063_REG_RSVD_20,
3683 val);
3842 3684
3843 /* Avoid DECT Frequencies */ 3685 break;
3844 case MT2063_AVOID_DECT: 3686 }
3687 case MT2063_DNC_BOTH:
3845 { 3688 {
3846 enum MT2063_DECT_Avoid_Type newAvoidSetting = 3689 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3847 (enum MT2063_DECT_Avoid_Type)nValue; 3690 if (pInfo->reg[MT2063_REG_DNC_GAIN] !=
3848 if ((newAvoidSetting >= 3691 val)
3849 MT2063_NO_DECT_AVOIDANCE) 3692 status |=
3850 && (newAvoidSetting <= MT2063_AVOID_BOTH)) { 3693 MT2063_SetReg(pInfo,
3851 pInfo->AS_Data.avoidDECT = 3694 MT2063_REG_DNC_GAIN,
3852 newAvoidSetting; 3695 val);
3853 } 3696
3697 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3698 if (pInfo->reg[MT2063_REG_VGA_GAIN] !=
3699 val)
3700 status |=
3701 MT2063_SetReg(pInfo,
3702 MT2063_REG_VGA_GAIN,
3703 val);
3704
3705 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3706 if (pInfo->reg[MT2063_REG_RSVD_20] !=
3707 val)
3708 status |=
3709 MT2063_SetReg(pInfo,
3710 MT2063_REG_RSVD_20,
3711 val);
3712
3713 break;
3854 } 3714 }
3715 default:
3855 break; 3716 break;
3717 }
3718 break;
3856 3719
3857 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */ 3720 case MT2063_VGAGC:
3858 case MT2063_CTFILT_SW: 3721 /* Set VGA gain code */
3859 pInfo->ctfilt_sw = (nValue & 0x01); 3722 val =
3860 break; 3723 (pInfo->
3724 reg[MT2063_REG_VGA_GAIN] & (u8) ~ 0x0C) |
3725 ((nValue & 0x03) << 2);
3726 if (pInfo->reg[MT2063_REG_VGA_GAIN] != val) {
3727 status |=
3728 MT2063_SetReg(pInfo, MT2063_REG_VGA_GAIN,
3729 val);
3730 }
3731 break;
3861 3732
3862 /* These parameters are read-only */ 3733 case MT2063_VGAOI:
3863 case MT2063_IC_ADDR: 3734 /* Set VGA bias current */
3864 case MT2063_MAX_OPEN: 3735 val =
3865 case MT2063_NUM_OPEN: 3736 (pInfo->
3866 case MT2063_INPUT_FREQ: 3737 reg[MT2063_REG_RSVD_31] & (u8) ~ 0x07) |
3867 case MT2063_IF1_ACTUAL: 3738 (nValue & 0x07);
3868 case MT2063_IF1_CENTER: 3739 if (pInfo->reg[MT2063_REG_RSVD_31] != val) {
3869 case MT2063_IF1_BW: 3740 status |=
3870 case MT2063_AS_ALG: 3741 MT2063_SetReg(pInfo, MT2063_REG_RSVD_31,
3871 case MT2063_EXCL_ZONES: 3742 val);
3872 case MT2063_SPUR_AVOIDED:
3873 case MT2063_NUM_SPURS:
3874 case MT2063_SPUR_PRESENT:
3875 case MT2063_ACLNA:
3876 case MT2063_ACRF:
3877 case MT2063_ACFIF:
3878 case MT2063_EOP:
3879 default:
3880 status |= MT2063_ARG_RANGE;
3881 } 3743 }
3744 break;
3745
3746 case MT2063_TAGC:
3747 /* Set TAGC */
3748 val =
3749 (pInfo->
3750 reg[MT2063_REG_RSVD_1E] & (u8) ~ 0x03) |
3751 (nValue & 0x03);
3752 if (pInfo->reg[MT2063_REG_RSVD_1E] != val) {
3753 status |=
3754 MT2063_SetReg(pInfo, MT2063_REG_RSVD_1E,
3755 val);
3756 }
3757 break;
3758
3759 case MT2063_AMPGC:
3760 /* Set Amp gain code */
3761 val =
3762 (pInfo->
3763 reg[MT2063_REG_TEMP_SEL] & (u8) ~ 0x03) |
3764 (nValue & 0x03);
3765 if (pInfo->reg[MT2063_REG_TEMP_SEL] != val) {
3766 status |=
3767 MT2063_SetReg(pInfo, MT2063_REG_TEMP_SEL,
3768 val);
3769 }
3770 break;
3771
3772 /* Avoid DECT Frequencies */
3773 case MT2063_AVOID_DECT:
3774 {
3775 enum MT2063_DECT_Avoid_Type newAvoidSetting =
3776 (enum MT2063_DECT_Avoid_Type)nValue;
3777 if ((newAvoidSetting >=
3778 MT2063_NO_DECT_AVOIDANCE)
3779 && (newAvoidSetting <= MT2063_AVOID_BOTH)) {
3780 pInfo->AS_Data.avoidDECT =
3781 newAvoidSetting;
3782 }
3783 }
3784 break;
3785
3786 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
3787 case MT2063_CTFILT_SW:
3788 pInfo->ctfilt_sw = (nValue & 0x01);
3789 break;
3790
3791 /* These parameters are read-only */
3792 case MT2063_IC_ADDR:
3793 case MT2063_MAX_OPEN:
3794 case MT2063_NUM_OPEN:
3795 case MT2063_INPUT_FREQ:
3796 case MT2063_IF1_ACTUAL:
3797 case MT2063_IF1_CENTER:
3798 case MT2063_IF1_BW:
3799 case MT2063_AS_ALG:
3800 case MT2063_EXCL_ZONES:
3801 case MT2063_SPUR_AVOIDED:
3802 case MT2063_NUM_SPURS:
3803 case MT2063_SPUR_PRESENT:
3804 case MT2063_ACLNA:
3805 case MT2063_ACRF:
3806 case MT2063_ACFIF:
3807 case MT2063_EOP:
3808 default:
3809 status |= -ERANGE;
3882 } 3810 }
3883 return (status); 3811 return (status);
3884} 3812}
@@ -3912,27 +3840,25 @@ static u32 MT2063_SetParam(void *h, enum MT2063_Param param, u32 nValue)
3912****************************************************************************/ 3840****************************************************************************/
3913static u32 MT2063_ClearPowerMaskBits(struct MT2063_Info_t *pInfo, enum MT2063_Mask_Bits Bits) 3841static u32 MT2063_ClearPowerMaskBits(struct MT2063_Info_t *pInfo, enum MT2063_Mask_Bits Bits)
3914{ 3842{
3915 u32 status = MT2063_OK; /* Status to be returned */ 3843 u32 status = 0; /* Status to be returned */
3916 3844
3917 /* Verify that the handle passed points to a valid tuner */ 3845 /* Verify that the handle passed points to a valid tuner */
3918 if (MT2063_IsValidHandle(pInfo) == 0) 3846 if (MT2063_IsValidHandle(pInfo) == 0)
3919 status = MT2063_INV_HANDLE; 3847 return -ENODEV;
3920 else { 3848 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
3921 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */ 3849 if ((Bits & 0xFF00) != 0) {
3922 if ((Bits & 0xFF00) != 0) { 3850 pInfo->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
3923 pInfo->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); 3851 status |=
3924 status |= 3852 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3925 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3853 MT2063_REG_PWR_2,
3926 MT2063_REG_PWR_2, 3854 &pInfo->reg[MT2063_REG_PWR_2], 1);
3927 &pInfo->reg[MT2063_REG_PWR_2], 1); 3855 }
3928 } 3856 if ((Bits & 0xFF) != 0) {
3929 if ((Bits & 0xFF) != 0) { 3857 pInfo->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
3930 pInfo->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); 3858 status |=
3931 status |= 3859 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3932 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3860 MT2063_REG_PWR_1,
3933 MT2063_REG_PWR_1, 3861 &pInfo->reg[MT2063_REG_PWR_1], 1);
3934 &pInfo->reg[MT2063_REG_PWR_1], 1);
3935 }
3936 } 3862 }
3937 3863
3938 return (status); 3864 return (status);
@@ -3968,38 +3894,36 @@ static u32 MT2063_ClearPowerMaskBits(struct MT2063_Info_t *pInfo, enum MT2063_Ma
3968****************************************************************************/ 3894****************************************************************************/
3969static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown) 3895static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown)
3970{ 3896{
3971 u32 status = MT2063_OK; /* Status to be returned */ 3897 u32 status = 0; /* Status to be returned */
3972 3898
3973 /* Verify that the handle passed points to a valid tuner */ 3899 /* Verify that the handle passed points to a valid tuner */
3974 if (MT2063_IsValidHandle(pInfo) == 0) { 3900 if (MT2063_IsValidHandle(pInfo) == 0)
3975 status = MT2063_INV_HANDLE; 3901 return -ENODEV;
3976 } else { 3902 if (Shutdown == 1)
3977 if (Shutdown == 1) 3903 pInfo->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */
3978 pInfo->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */ 3904 else
3979 else 3905 pInfo->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */
3980 pInfo->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */
3981 3906
3907 status |=
3908 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3909 MT2063_REG_PWR_1,
3910 &pInfo->reg[MT2063_REG_PWR_1], 1);
3911
3912 if (Shutdown != 1) {
3913 pInfo->reg[MT2063_REG_BYP_CTRL] =
3914 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
3982 status |= 3915 status |=
3983 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3916 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3984 MT2063_REG_PWR_1, 3917 MT2063_REG_BYP_CTRL,
3985 &pInfo->reg[MT2063_REG_PWR_1], 1); 3918 &pInfo->reg[MT2063_REG_BYP_CTRL],
3986 3919 1);
3987 if (Shutdown != 1) { 3920 pInfo->reg[MT2063_REG_BYP_CTRL] =
3988 pInfo->reg[MT2063_REG_BYP_CTRL] = 3921 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F);
3989 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; 3922 status |=
3990 status |= 3923 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3991 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3924 MT2063_REG_BYP_CTRL,
3992 MT2063_REG_BYP_CTRL, 3925 &pInfo->reg[MT2063_REG_BYP_CTRL],
3993 &pInfo->reg[MT2063_REG_BYP_CTRL], 3926 1);
3994 1);
3995 pInfo->reg[MT2063_REG_BYP_CTRL] =
3996 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F);
3997 status |=
3998 MT2063_WriteSub(pInfo->hUserData, pInfo->address,
3999 MT2063_REG_BYP_CTRL,
4000 &pInfo->reg[MT2063_REG_BYP_CTRL],
4001 1);
4002 }
4003 } 3927 }
4004 3928
4005 return (status); 3929 return (status);
@@ -4033,25 +3957,21 @@ static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown)
4033** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 3957** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
4034** 3958**
4035****************************************************************************/ 3959****************************************************************************/
4036static u32 MT2063_SetReg(void *h, u8 reg, u8 val) 3960static u32 MT2063_SetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 val)
4037{ 3961{
4038 u32 status = MT2063_OK; /* Status to be returned */ 3962 u32 status = 0; /* Status to be returned */
4039 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
4040 3963
4041 /* Verify that the handle passed points to a valid tuner */ 3964 /* Verify that the handle passed points to a valid tuner */
4042 if (MT2063_IsValidHandle(pInfo) == 0) 3965 if (MT2063_IsValidHandle(pInfo) == 0)
4043 status |= MT2063_INV_HANDLE; 3966 return -ENODEV;
4044 3967
4045 if (reg >= MT2063_REG_END_REGS) 3968 if (reg >= MT2063_REG_END_REGS)
4046 status |= MT2063_ARG_RANGE; 3969 status |= -ERANGE;
4047 3970
4048 if (MT2063_NO_ERROR(status)) { 3971 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg, &val,
4049 status |= 3972 1);
4050 MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg, &val, 3973 if (status >= 0)
4051 1); 3974 pInfo->reg[reg] = val;
4052 if (MT2063_NO_ERROR(status))
4053 pInfo->reg[reg] = val;
4054 }
4055 3975
4056 return (status); 3976 return (status);
4057} 3977}
@@ -4271,11 +4191,10 @@ static u32 FindClearTuneFilter(struct MT2063_Info_t *pInfo, u32 f_in)
4271** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 4191** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
4272** 4192**
4273****************************************************************************/ 4193****************************************************************************/
4274static u32 MT2063_Tune(void *h, u32 f_in) 4194static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4275{ /* RF input center frequency */ 4195{ /* RF input center frequency */
4276 struct MT2063_Info_t *pInfo = (struct MT2063_Info_t *)h;
4277 4196
4278 u32 status = MT2063_OK; /* status of operation */ 4197 u32 status = 0; /* status of operation */
4279 u32 LO1; /* 1st LO register value */ 4198 u32 LO1; /* 1st LO register value */
4280 u32 Num1; /* Numerator for LO1 reg. value */ 4199 u32 Num1; /* Numerator for LO1 reg. value */
4281 u32 f_IF1; /* 1st IF requested */ 4200 u32 f_IF1; /* 1st IF requested */
@@ -4292,15 +4211,15 @@ static u32 MT2063_Tune(void *h, u32 f_in)
4292 4211
4293 /* Verify that the handle passed points to a valid tuner */ 4212 /* Verify that the handle passed points to a valid tuner */
4294 if (MT2063_IsValidHandle(pInfo) == 0) 4213 if (MT2063_IsValidHandle(pInfo) == 0)
4295 return MT2063_INV_HANDLE; 4214 return -ENODEV;
4296 4215
4297 /* Check the input and output frequency ranges */ 4216 /* Check the input and output frequency ranges */
4298 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ)) 4217 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
4299 status |= MT2063_FIN_RANGE; 4218 return -EINVAL;
4300 4219
4301 if ((pInfo->AS_Data.f_out < MT2063_MIN_FOUT_FREQ) 4220 if ((pInfo->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
4302 || (pInfo->AS_Data.f_out > MT2063_MAX_FOUT_FREQ)) 4221 || (pInfo->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
4303 status |= MT2063_FOUT_RANGE; 4222 return -EINVAL;
4304 4223
4305 /* 4224 /*
4306 ** Save original LO1 and LO2 register values 4225 ** Save original LO1 and LO2 register values
@@ -4333,7 +4252,7 @@ static u32 MT2063_Tune(void *h, u32 f_in)
4333 /* 4252 /*
4334 ** Read the FIFF Center Frequency from the tuner 4253 ** Read the FIFF Center Frequency from the tuner
4335 */ 4254 */
4336 if (MT2063_NO_ERROR(status)) { 4255 if (status >= 0) {
4337 status |= 4256 status |=
4338 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 4257 MT2063_ReadSub(pInfo->hUserData, pInfo->address,
4339 MT2063_REG_FIFFC, 4258 MT2063_REG_FIFFC,
@@ -4370,7 +4289,7 @@ static u32 MT2063_Tune(void *h, u32 f_in)
4370 ** Check for any LO spurs in the output bandwidth and adjust 4289 ** Check for any LO spurs in the output bandwidth and adjust
4371 ** the LO settings to avoid them if needed 4290 ** the LO settings to avoid them if needed
4372 */ 4291 */
4373 status |= MT2063_AvoidSpurs(h, &pInfo->AS_Data); 4292 status |= MT2063_AvoidSpurs(pInfo, &pInfo->AS_Data);
4374 /* 4293 /*
4375 ** MT_AvoidSpurs spurs may have changed the LO1 & LO2 values. 4294 ** MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
4376 ** Recalculate the LO frequencies and the values to be placed 4295 ** Recalculate the LO frequencies and the values to be placed
@@ -4425,7 +4344,7 @@ static u32 MT2063_Tune(void *h, u32 f_in)
4425 ** Place all of the calculated values into the local tuner 4344 ** Place all of the calculated values into the local tuner
4426 ** register fields. 4345 ** register fields.
4427 */ 4346 */
4428 if (MT2063_NO_ERROR(status)) { 4347 if (status >= 0) {
4429 pInfo->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ 4348 pInfo->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
4430 pInfo->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ 4349 pInfo->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
4431 pInfo->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ 4350 pInfo->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
@@ -4462,13 +4381,13 @@ static u32 MT2063_Tune(void *h, u32 f_in)
4462 ** Check for LO's locking 4381 ** Check for LO's locking
4463 */ 4382 */
4464 4383
4465 if (MT2063_NO_ERROR(status)) { 4384 if (status >= 0) {
4466 status |= MT2063_GetLocked(h); 4385 status |= MT2063_GetLocked(pInfo);
4467 } 4386 }
4468 /* 4387 /*
4469 ** If we locked OK, assign calculated data to MT2063_Info_t structure 4388 ** If we locked OK, assign calculated data to MT2063_Info_t structure
4470 */ 4389 */
4471 if (MT2063_NO_ERROR(status)) { 4390 if (status >= 0) {
4472 pInfo->f_IF1_actual = pInfo->AS_Data.f_LO1 - f_in; 4391 pInfo->f_IF1_actual = pInfo->AS_Data.f_LO1 - f_in;
4473 } 4392 }
4474 } 4393 }
@@ -4480,7 +4399,7 @@ static u32 MT_Tune_atv(void *h, u32 f_in, u32 bw_in,
4480 enum MTTune_atv_standard tv_type) 4399 enum MTTune_atv_standard tv_type)
4481{ 4400{
4482 4401
4483 u32 status = MT2063_OK; 4402 u32 status = 0;
4484 4403
4485 s32 pict_car = 0; 4404 s32 pict_car = 0;
4486 s32 pict2chanb_vsb = 0; 4405 s32 pict2chanb_vsb = 0;
@@ -4608,14 +4527,14 @@ static u32 MT_Tune_atv(void *h, u32 f_in, u32 bw_in,
4608 4527
4609static int mt2063_init(struct dvb_frontend *fe) 4528static int mt2063_init(struct dvb_frontend *fe)
4610{ 4529{
4611 u32 status = MT2063_ERROR; 4530 u32 status = -EINVAL;
4612 struct mt2063_state *state = fe->tuner_priv; 4531 struct mt2063_state *state = fe->tuner_priv;
4613 4532
4614 status = MT2063_Open(0xC0, &(state->MT2063_ht), fe); 4533 status = MT2063_Open(0xC0, &(state->MT2063_ht), fe);
4615 status |= MT2063_SoftwareShutdown(state->MT2063_ht, 1); 4534 status |= MT2063_SoftwareShutdown(state->MT2063_ht, 1);
4616 status |= MT2063_ClearPowerMaskBits(state->MT2063_ht, MT2063_ALL_SD); 4535 status |= MT2063_ClearPowerMaskBits(state->MT2063_ht, MT2063_ALL_SD);
4617 4536
4618 if (MT2063_OK != status) { 4537 if (0 != status) {
4619 printk("%s %d error status = 0x%x!!\n", __func__, __LINE__, 4538 printk("%s %d error status = 0x%x!!\n", __func__, __LINE__,
4620 status); 4539 status);
4621 return -1; 4540 return -1;
@@ -4665,7 +4584,7 @@ static int mt2063_set_state(struct dvb_frontend *fe,
4665 enum tuner_param param, struct tuner_state *state) 4584 enum tuner_param param, struct tuner_state *state)
4666{ 4585{
4667 struct mt2063_state *mt2063State = fe->tuner_priv; 4586 struct mt2063_state *mt2063State = fe->tuner_priv;
4668 u32 status = MT2063_OK; 4587 u32 status = 0;
4669 4588
4670 switch (param) { 4589 switch (param) {
4671 case DVBFE_TUNER_FREQUENCY: 4590 case DVBFE_TUNER_FREQUENCY:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 15:02:28 -0500