litmus-rt.git - The LITMUS^RT kernel.

The LITMUS^RT kernel.

Bjoern Brandenburg

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author	Linus Torvalds <torvalds@linux-foundation.org>	2010-02-24 13:52:17 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2010-02-24 13:52:17 -0500
commit	60b341b778cc2929df16c0a504c91621b3c6a4ad (patch)
tree	b76a619a82e7f3a95c08cc0894e19d3c47c68fe5 /drivers/macintosh/nvram.c
parent	1e6c5c4e4c98af5f9e905b860f4536dcc8e92402 (diff)

Linux 2.6.33v2.6.33

Diffstat (limited to 'drivers/macintosh/nvram.c')

0 files changed, 0 insertions, 0 deletions

04 #define DMASCR_SEM_EN 0x00010 #define DMASCR_DMA_COMP_EN 0x00020 #define DMASCR_CHAIN_COMP_EN 0x00040 #define DMASCR_ERR_INT_EN 0x00080 #define DMASCR_PARITY_INT_EN 0x00100 #define DMASCR_ANY_ERR 0x00800 #define DMASCR_MBE_ERR 0x01000 #define DMASCR_PARITY_ERR_REP 0x02000 #define DMASCR_PARITY_ERR_DET 0x04000 #define DMASCR_SYSTEM_ERR_SIG 0x08000 #define DMASCR_TARGET_ABT 0x10000 #define DMASCR_MASTER_ABT 0x20000 #define DMASCR_DMA_COMPLETE 0x40000 #define DMASCR_CHAIN_COMPLETE 0x80000 /* 3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING DMA READ OPERATIONS. */ #define DMASCR_READ 0x60000000 #define DMASCR_READLINE 0xE0000000 #define DMASCR_READMULTI 0xC0000000 #define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) #define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) #define WINDOWMAP_WINNUM 0x7B #define DMA_READ_FROM_HOST 0 #define DMA_WRITE_TO_HOST 1 struct mm_dma_desc { __le64 pci_addr; __le64 local_addr; __le32 transfer_size; u32 zero1; __le64 next_desc_addr; __le64 sem_addr; __le32 control_bits; u32 zero2; dma_addr_t data_dma_handle; /* Copy of the bits */ __le64 sem_control_bits; } __attribute__((aligned(8))); /* bits for card->flags */ #define UM_FLAG_DMA_IN_REGS 1 #define UM_FLAG_NO_BYTE_STATUS 2 #define UM_FLAG_NO_BATTREG 4 #define UM_FLAG_NO_BATT 8 #endif


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