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authorAvi Kivity <avi@qumranet.com>2007-05-31 11:20:14 -0400
committerAvi Kivity <avi@qumranet.com>2007-07-16 05:05:44 -0400
commitfd97dc516c372982f9c3637e20b131e1f55ac2f6 (patch)
tree40c86e7691de599286daeebaa942d0392e54e1dd /drivers/kvm
parent4436d466219a6a7874ebc19eb6523c3a9a280dcc (diff)
KVM: MMU: Simpify accessed/dirty/present/nx bit handling
Always set the accessed and dirty bit (since having them cleared causes a read-modify-write cycle), always set the present bit, and copy the nx bit from the guest. Signed-off-by: Avi Kivity <avi@qumranet.com>
Diffstat (limited to 'drivers/kvm')
-rw-r--r--drivers/kvm/mmu.c5
-rw-r--r--drivers/kvm/paging_tmpl.h7
2 files changed, 2 insertions, 10 deletions
diff --git a/drivers/kvm/mmu.c b/drivers/kvm/mmu.c
index f24b540148aa..b47391ffe549 100644
--- a/drivers/kvm/mmu.c
+++ b/drivers/kvm/mmu.c
@@ -91,11 +91,6 @@ static int dbg = 1;
91#define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 91#define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
92 92
93 93
94#define PT32_PTE_COPY_MASK \
95 (PT_PRESENT_MASK | PT_ACCESSED_MASK | PT_DIRTY_MASK | PT_GLOBAL_MASK)
96
97#define PT64_PTE_COPY_MASK (PT64_NX_MASK | PT32_PTE_COPY_MASK)
98
99#define PT_FIRST_AVAIL_BITS_SHIFT 9 94#define PT_FIRST_AVAIL_BITS_SHIFT 9
100#define PT64_SECOND_AVAIL_BITS_SHIFT 52 95#define PT64_SECOND_AVAIL_BITS_SHIFT 52
101 96
diff --git a/drivers/kvm/paging_tmpl.h b/drivers/kvm/paging_tmpl.h
index 59b4cb29e0f7..b17a4b783cd4 100644
--- a/drivers/kvm/paging_tmpl.h
+++ b/drivers/kvm/paging_tmpl.h
@@ -31,7 +31,6 @@
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level) 31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) 32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) 33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
35 #ifdef CONFIG_X86_64 34 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4 35 #define PT_MAX_FULL_LEVELS 4
37 #else 36 #else
@@ -46,7 +45,6 @@
46 #define PT_INDEX(addr, level) PT32_INDEX(addr, level) 45 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
47 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) 46 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
48 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) 47 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
49 #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
50 #define PT_MAX_FULL_LEVELS 2 48 #define PT_MAX_FULL_LEVELS 2
51#else 49#else
52 #error Invalid PTTYPE value 50 #error Invalid PTTYPE value
@@ -219,7 +217,8 @@ static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
219 FNAME(mark_pagetable_dirty)(vcpu->kvm, walker); 217 FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
220 } 218 }
221 219
222 spte |= *gpte & PT_PTE_COPY_MASK; 220 spte |= PT_PRESENT_MASK | PT_ACCESSED_MASK | PT_DIRTY_MASK;
221 spte |= *gpte & PT64_NX_MASK;
223 spte |= access_bits << PT_SHADOW_BITS_OFFSET; 222 spte |= access_bits << PT_SHADOW_BITS_OFFSET;
224 if (!dirty) 223 if (!dirty)
225 access_bits &= ~PT_WRITABLE_MASK; 224 access_bits &= ~PT_WRITABLE_MASK;
@@ -495,7 +494,5 @@ static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
495#undef PT_INDEX 494#undef PT_INDEX
496#undef SHADOW_PT_INDEX 495#undef SHADOW_PT_INDEX
497#undef PT_LEVEL_MASK 496#undef PT_LEVEL_MASK
498#undef PT_PTE_COPY_MASK
499#undef PT_NON_PTE_COPY_MASK
500#undef PT_DIR_BASE_ADDR_MASK 497#undef PT_DIR_BASE_ADDR_MASK
501#undef PT_MAX_FULL_LEVELS 498#undef PT_MAX_FULL_LEVELS