diff options
author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2013-12-13 19:09:31 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-12-22 19:27:17 -0500 |
commit | ce70af18801fd8dac6e9f85308294948916e84d6 (patch) | |
tree | 8e2ddd6fd6cebb04cd93bff3030245be75c1a313 /drivers/irqchip | |
parent | 6a7e3b3007b5396a9e812ca0ceddc7915f8768dd (diff) |
irq-renesas-irqc: simplify irq_set_type() method
Value 0 of the sense selection field of CONFIG_n register means "disable event
detection" and serves in irqc_sense[] for marking the invalid values of the IRQ
type (by just omitting initializers). There is no need for INTC_IRQ_SENSE_VALID
and hence INTC_IRQ_SENSE() as all field values matching to the valid IRQ types
are non-zero anyway.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/irqchip')
-rw-r--r-- | drivers/irqchip/irq-renesas-irqc.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c index 082d95cb5528..8777065012a5 100644 --- a/drivers/irqchip/irq-renesas-irqc.c +++ b/drivers/irqchip/irq-renesas-irqc.c | |||
@@ -81,15 +81,12 @@ static void irqc_irq_disable(struct irq_data *d) | |||
81 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); | 81 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); |
82 | } | 82 | } |
83 | 83 | ||
84 | #define INTC_IRQ_SENSE_VALID 0x10 | ||
85 | #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) | ||
86 | |||
87 | static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { | 84 | static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { |
88 | [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), | 85 | [IRQ_TYPE_LEVEL_LOW] = 0x01, |
89 | [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), | 86 | [IRQ_TYPE_LEVEL_HIGH] = 0x02, |
90 | [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ | 87 | [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */ |
91 | [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ | 88 | [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */ |
92 | [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ | 89 | [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */ |
93 | }; | 90 | }; |
94 | 91 | ||
95 | static int irqc_irq_set_type(struct irq_data *d, unsigned int type) | 92 | static int irqc_irq_set_type(struct irq_data *d, unsigned int type) |
@@ -101,12 +98,12 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type) | |||
101 | 98 | ||
102 | irqc_dbg(&p->irq[hw_irq], "sense"); | 99 | irqc_dbg(&p->irq[hw_irq], "sense"); |
103 | 100 | ||
104 | if (!(value & INTC_IRQ_SENSE_VALID)) | 101 | if (!value) |
105 | return -EINVAL; | 102 | return -EINVAL; |
106 | 103 | ||
107 | tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); | 104 | tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); |
108 | tmp &= ~0x3f; | 105 | tmp &= ~0x3f; |
109 | tmp |= value ^ INTC_IRQ_SENSE_VALID; | 106 | tmp |= value; |
110 | iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); | 107 | iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); |
111 | return 0; | 108 | return 0; |
112 | } | 109 | } |