Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull core irq changes from Ingo Molnar:
 "The main changes:

  - generic-irqchip driver additions, cleanups and fixes

  - 3 new irqchip drivers: ARMv7-M NVIC, TB10x and Marvell Orion SoCs

  - irq_get_trigger_type() simplification and cross-arch cleanup

  - various cleanups, simplifications

  - documentation updates"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  softirq: Use _RET_IP_
  genirq: Add the generic chip to the genirq docbook
  genirq: generic-chip: Export some irq_gc_ functions
  genirq: Fix can_request_irq() for IRQs without an action
  irqchip: exynos-combiner: Staticize combiner_init
  irqchip: Add support for ARMv7-M NVIC
  irqchip: Add TB10x interrupt controller driver
  irqdomain: Use irq_get_trigger_type() to get IRQ flags
  MIPS: octeon: Use irq_get_trigger_type() to get IRQ flags
  arm: orion: Use irq_get_trigger_type() to get IRQ flags
  mfd: stmpe: use irq_get_trigger_type() to get IRQ flags
  mfd: twl4030-irq: Use irq_get_trigger_type() to get IRQ flags
  gpio: mvebu: Use irq_get_trigger_type() to get IRQ flags
  genirq: Add irq_get_trigger_type() to get IRQ flags
  genirq: Irqchip: document gcflags arg of irq_alloc_domain_generic_chips
  genirq: Set irq thread to RT priority on creation
  irqchip: Add support for Marvell Orion SoCs
  genirq: Add kerneldoc for irq_disable.
  genirq: irqchip: Add mask to block out invalid irqs
  genirq: Generic chip: Add linear irq domain support
  ...

6 files changed, 526 insertions, 4 deletions

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4a33351c25dc..1fea003ed33f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -10,6 +10,11 @@ config ARM_GIC
 config GIC_NON_BANKED
         bool
 
+config ARM_NVIC
+        bool
+        select IRQ_DOMAIN
+        select GENERIC_IRQ_CHIP
+
 config ARM_VIC
         bool
         select IRQ_DOMAIN
@@ -25,6 +30,11 @@ config ARM_VIC_NR
           The maximum number of VICs available in the system, for
           power management.
 
+config ORION_IRQCHIP
+        bool
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+
 config RENESAS_INTC_IRQPIN
         bool
         select IRQ_DOMAIN
@@ -33,6 +43,11 @@ config RENESAS_IRQC
         bool
         select IRQ_DOMAIN
 
+config TB10X_IRQC
+        bool
+        select IRQ_DOMAIN
+        select GENERIC_IRQ_CHIP
+
 config VERSATILE_FPGA_IRQ
         bool
         select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index cda4cb5f7327..2065ef6a949c 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -7,12 +7,15 @@ obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)              += irq-s3c24xx.o
 obj-$(CONFIG_METAG)                     += irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)    += irq-metag.o
+obj-$(CONFIG_ORION_IRQCHIP)             += irq-orion.o
 obj-$(CONFIG_ARCH_SUNXI)                += irq-sun4i.o
 obj-$(CONFIG_ARCH_SPEAR3XX)             += spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                   += irq-gic.o
+obj-$(CONFIG_ARM_NVIC)                  += irq-nvic.o
 obj-$(CONFIG_ARM_VIC)                   += irq-vic.o
 obj-$(CONFIG_SIRF_IRQ)                  += irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)       += irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)              += irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)        += irq-versatile-fpga.o
 obj-$(CONFIG_ARCH_VT8500)               += irq-vt8500.o
+obj-$(CONFIG_TB10X_IRQC)                += irq-tb10x.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index a9d2b2fa4afd..4c6826513901 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -204,10 +204,10 @@ static unsigned int combiner_lookup_irq(int group)
         return 0;
 }
 
-void __init combiner_init(void __iomem *combiner_base,
-                          struct device_node *np,
-                          unsigned int max_nr,
-                          int irq_base)
+static void __init combiner_init(void __iomem *combiner_base,
+                                 struct device_node *np,
+                                 unsigned int max_nr,
+                                 int irq_base)
 {
         int i, irq;
         unsigned int nr_irq;
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
new file mode 100644
index 000000000000..8d0c8b3181c5
--- /dev/null
+++ b/drivers/irqchip/irq-nvic.c
@@ -0,0 +1,117 @@
+/*
+ * drivers/irq/irq-nvic.c
+ *
+ * Copyright (C) 2008 ARM Limited, All Rights Reserved.
+ * Copyright (C) 2013 Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Support for the Nested Vectored Interrupt Controller found on the
+ * ARMv7-M CPUs (Cortex-M3/M4)
+ */
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+
+#include <asm/v7m.h>
+#include <asm/exception.h>
+
+#include "irqchip.h"
+
+#define NVIC_ISER               0x000
+#define NVIC_ICER               0x080
+#define NVIC_IPR                0x300
+
+#define NVIC_MAX_BANKS          16
+/*
+ * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
+ * 16 irqs.
+ */
+#define NVIC_MAX_IRQ            ((NVIC_MAX_BANKS - 1) * 32 + 16)
+
+static struct irq_domain *nvic_irq_domain;
+
+asmlinkage void __exception_irq_entry
+nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
+{
+        unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
+
+        handle_IRQ(irq, regs);
+}
+
+static void nvic_eoi(struct irq_data *d)
+{
+        /*
+         * This is a no-op as end of interrupt is signaled by the exception
+         * return sequence.
+         */
+}
+
+static int __init nvic_of_init(struct device_node *node,
+                               struct device_node *parent)
+{
+        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        unsigned int irqs, i, ret, numbanks;
+        void __iomem *nvic_base;
+
+        numbanks = (readl_relaxed(V7M_SCS_ICTR) &
+                    V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
+
+        nvic_base = of_iomap(node, 0);
+        if (!nvic_base) {
+                pr_warn("unable to map nvic registers\n");
+                return -ENOMEM;
+        }
+
+        irqs = numbanks * 32;
+        if (irqs > NVIC_MAX_IRQ)
+                irqs = NVIC_MAX_IRQ;
+
+        nvic_irq_domain =
+                irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
+        if (!nvic_irq_domain) {
+                pr_warn("Failed to allocate irq domain\n");
+                return -ENOMEM;
+        }
+
+        ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, numbanks,
+                                             "nvic_irq", handle_fasteoi_irq,
+                                             clr, 0, IRQ_GC_INIT_MASK_CACHE);
+        if (ret) {
+                pr_warn("Failed to allocate irq chips\n");
+                irq_domain_remove(nvic_irq_domain);
+                return ret;
+        }
+
+        for (i = 0; i < numbanks; ++i) {
+                struct irq_chip_generic *gc;
+
+                gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
+                gc->reg_base = nvic_base + 4 * i;
+                gc->chip_types[0].regs.enable = NVIC_ISER;
+                gc->chip_types[0].regs.disable = NVIC_ICER;
+                gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
+                gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
+                gc->chip_types[0].chip.irq_eoi = nvic_eoi;
+
+                /* disable interrupts */
+                writel_relaxed(~0, gc->reg_base + NVIC_ICER);
+        }
+
+        /* Set priority on all interrupts */
+        for (i = 0; i < irqs; i += 4)
+                writel_relaxed(0, nvic_base + NVIC_IPR + i);
+
+        return 0;
+}
+IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
new file mode 100644
index 000000000000..e51d40031884
--- /dev/null
+++ b/drivers/irqchip/irq-orion.c
@@ -0,0 +1,192 @@
+/*
+ * Marvell Orion SoCs IRQ chip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
+
+/*
+ * Orion SoC main interrupt controller
+ */
+#define ORION_IRQS_PER_CHIP             32
+
+#define ORION_IRQ_CAUSE                 0x00
+#define ORION_IRQ_MASK                  0x04
+#define ORION_IRQ_FIQ_MASK              0x08
+#define ORION_IRQ_ENDP_MASK             0x0c
+
+static struct irq_domain *orion_irq_domain;
+
+static asmlinkage void
+__exception_irq_entry orion_handle_irq(struct pt_regs *regs)
+{
+        struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;
+        int n, base = 0;
+
+        for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) {
+                struct irq_chip_generic *gc =
+                        irq_get_domain_generic_chip(orion_irq_domain, base);
+                u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
+                        gc->mask_cache;
+                while (stat) {
+                        u32 hwirq = ffs(stat) - 1;
+                        u32 irq = irq_find_mapping(orion_irq_domain,
+                                                   gc->irq_base + hwirq);
+                        handle_IRQ(irq, regs);
+                        stat &= ~(1 << hwirq);
+                }
+        }
+}
+
+static int __init orion_irq_init(struct device_node *np,
+                                 struct device_node *parent)
+{
+        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        int n, ret, base, num_chips = 0;
+        struct resource r;
+
+        /* count number of irq chips by valid reg addresses */
+        while (of_address_to_resource(np, num_chips, &r) == 0)
+                num_chips++;
+
+        orion_irq_domain = irq_domain_add_linear(np,
+                                num_chips * ORION_IRQS_PER_CHIP,
+                                &irq_generic_chip_ops, NULL);
+        if (!orion_irq_domain)
+                panic("%s: unable to add irq domain\n", np->name);
+
+        ret = irq_alloc_domain_generic_chips(orion_irq_domain,
+                                ORION_IRQS_PER_CHIP, 1, np->name,
+                                handle_level_irq, clr, 0,
+                                IRQ_GC_INIT_MASK_CACHE);
+        if (ret)
+                panic("%s: unable to alloc irq domain gc\n", np->name);
+
+        for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
+                struct irq_chip_generic *gc =
+                        irq_get_domain_generic_chip(orion_irq_domain, base);
+
+                of_address_to_resource(np, n, &r);
+
+                if (!request_mem_region(r.start, resource_size(&r), np->name))
+                        panic("%s: unable to request mem region %d",
+                              np->name, n);
+
+                gc->reg_base = ioremap(r.start, resource_size(&r));
+                if (!gc->reg_base)
+                        panic("%s: unable to map resource %d", np->name, n);
+
+                gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
+                gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+                gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
+
+                /* mask all interrupts */
+                writel(0, gc->reg_base + ORION_IRQ_MASK);
+        }
+
+        set_handle_irq(orion_handle_irq);
+        return 0;
+}
+IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
+
+/*
+ * Orion SoC bridge interrupt controller
+ */
+#define ORION_BRIDGE_IRQ_CAUSE  0x00
+#define ORION_BRIDGE_IRQ_MASK   0x04
+
+static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_domain *d = irq_get_handler_data(irq);
+        struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq);
+        u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
+                   gc->mask_cache;
+
+        while (stat) {
+                u32 hwirq = ffs(stat) - 1;
+
+                generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq));
+                stat &= ~(1 << hwirq);
+        }
+}
+
+static int __init orion_bridge_irq_init(struct device_node *np,
+                                        struct device_node *parent)
+{
+        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        struct resource r;
+        struct irq_domain *domain;
+        struct irq_chip_generic *gc;
+        int ret, irq, nrirqs = 32;
+
+        /* get optional number of interrupts provided */
+        of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
+
+        domain = irq_domain_add_linear(np, nrirqs,
+                                       &irq_generic_chip_ops, NULL);
+        if (!domain) {
+                pr_err("%s: unable to add irq domain\n", np->name);
+                return -ENOMEM;
+        }
+
+        ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
+                             handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
+        if (ret) {
+                pr_err("%s: unable to alloc irq domain gc\n", np->name);
+                return ret;
+        }
+
+        ret = of_address_to_resource(np, 0, &r);
+        if (ret) {
+                pr_err("%s: unable to get resource\n", np->name);
+                return ret;
+        }
+
+        if (!request_mem_region(r.start, resource_size(&r), np->name)) {
+                pr_err("%s: unable to request mem region\n", np->name);
+                return -ENOMEM;
+        }
+
+        /* Map the parent interrupt for the chained handler */
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("%s: unable to parse irq\n", np->name);
+                return -EINVAL;
+        }
+
+        gc = irq_get_domain_generic_chip(domain, 0);
+        gc->reg_base = ioremap(r.start, resource_size(&r));
+        if (!gc->reg_base) {
+                pr_err("%s: unable to map resource\n", np->name);
+                return -ENOMEM;
+        }
+
+        gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
+        gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
+        gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
+        gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+        gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
+
+        /* mask all interrupts */
+        writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
+
+        irq_set_handler_data(irq, domain);
+        irq_set_chained_handler(irq, orion_bridge_irq_handler);
+
+        return 0;
+}
+IRQCHIP_DECLARE(orion_bridge_intc,
+                "marvell,orion-bridge-intc", orion_bridge_irq_init);
diff --git a/drivers/irqchip/irq-tb10x.c b/drivers/irqchip/irq-tb10x.c
new file mode 100644
index 000000000000..7c44c99bf1f2
--- /dev/null
+++ b/drivers/irqchip/irq-tb10x.c
@@ -0,0 +1,195 @@
+/*
+ * Abilis Systems interrupt controller driver
+ *
+ * Copyright (C) Abilis Systems 2012
+ *
+ * Author: Christian Ruppert <christian.ruppert@abilis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include "irqchip.h"
+
+#define AB_IRQCTL_INT_ENABLE   0x00
+#define AB_IRQCTL_INT_STATUS   0x04
+#define AB_IRQCTL_SRC_MODE     0x08
+#define AB_IRQCTL_SRC_POLARITY 0x0C
+#define AB_IRQCTL_INT_MODE     0x10
+#define AB_IRQCTL_INT_POLARITY 0x14
+#define AB_IRQCTL_INT_FORCE    0x18
+
+#define AB_IRQCTL_MAXIRQ       32
+
+static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
+        u32 val)
+{
+        irq_reg_writel(val, gc->reg_base + reg);
+}
+
+static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
+{
+        return irq_reg_readl(gc->reg_base + reg);
+}
+
+static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+        uint32_t im, mod, pol;
+
+        im = data->mask;
+
+        irq_gc_lock(gc);
+
+        mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
+        pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
+
+        switch (flow_type & IRQF_TRIGGER_MASK) {
+        case IRQ_TYPE_EDGE_FALLING:
+                pol ^= im;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                mod ^= im;
+                break;
+        case IRQ_TYPE_NONE:
+                flow_type = IRQ_TYPE_LEVEL_LOW;
+        case IRQ_TYPE_LEVEL_LOW:
+                mod ^= im;
+                pol ^= im;
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                break;
+        default:
+                irq_gc_unlock(gc);
+                pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
+                        __func__, data->irq);
+                return -EBADR;
+        }
+
+        irqd_set_trigger_type(data, flow_type);
+        irq_setup_alt_chip(data, flow_type);
+
+        ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
+        ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
+        ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
+
+        irq_gc_unlock(gc);
+
+        return IRQ_SET_MASK_OK;
+}
+
+static void tb10x_irq_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_domain *domain = irq_desc_get_handler_data(desc);
+
+        generic_handle_irq(irq_find_mapping(domain, irq));
+}
+
+static int __init of_tb10x_init_irq(struct device_node *ictl,
+                                        struct device_node *parent)
+{
+        int i, ret, nrirqs = of_irq_count(ictl);
+        struct resource mem;
+        struct irq_chip_generic *gc;
+        struct irq_domain *domain;
+        void __iomem *reg_base;
+
+        if (of_address_to_resource(ictl, 0, &mem)) {
+                pr_err("%s: No registers declared in DeviceTree.\n",
+                        ictl->name);
+                return -EINVAL;
+        }
+
+        if (!request_mem_region(mem.start, resource_size(&mem),
+                ictl->name)) {
+                pr_err("%s: Request mem region failed.\n", ictl->name);
+                return -EBUSY;
+        }
+
+        reg_base = ioremap(mem.start, resource_size(&mem));
+        if (!reg_base) {
+                ret = -EBUSY;
+                pr_err("%s: ioremap failed.\n", ictl->name);
+                goto ioremap_fail;
+        }
+
+        domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
+                                        &irq_generic_chip_ops, NULL);
+        if (!domain) {
+                ret = -ENOMEM;
+                pr_err("%s: Could not register interrupt domain.\n",
+                        ictl->name);
+                goto irq_domain_add_fail;
+        }
+
+        ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
+                                2, ictl->name, handle_level_irq,
+                                IRQ_NOREQUEST, IRQ_NOPROBE,
+                                IRQ_GC_INIT_MASK_CACHE);
+        if (ret) {
+                pr_err("%s: Could not allocate generic interrupt chip.\n",
+                        ictl->name);
+                goto gc_alloc_fail;
+        }
+
+        gc = domain->gc->gc[0];
+        gc->reg_base                         = reg_base;
+
+        gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;
+        gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
+        gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
+        gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;
+        gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;
+
+        gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;
+        gc->chip_types[1].chip.name          = gc->chip_types[0].chip.name;
+        gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;
+        gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;
+        gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;
+        gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;
+        gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;
+        gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;
+        gc->chip_types[1].handler            = handle_edge_irq;
+
+        for (i = 0; i < nrirqs; i++) {
+                unsigned int irq = irq_of_parse_and_map(ictl, i);
+
+                irq_set_handler_data(irq, domain);
+                irq_set_chained_handler(irq, tb10x_irq_cascade);
+        }
+
+        ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
+        ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
+        ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
+        ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
+
+        return 0;
+
+gc_alloc_fail:
+        irq_domain_remove(domain);
+irq_domain_add_fail:
+        iounmap(reg_base);
+ioremap_fail:
+        release_mem_region(mem.start, resource_size(&mem));
+        return ret;
+}
+IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);