diff options
| author | Joe Perches <joe@perches.com> | 2010-11-30 02:33:07 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2010-12-01 02:10:20 -0500 |
| commit | 4eb3c30b2e034b673df3e8f21b497e39f3911a02 (patch) | |
| tree | 013e473ebaee813ccbc7e5dfeed19cd6fe8fa3de /drivers/input | |
| parent | b029ffafe89cf4b97cf39e0225a5205cbbf9e02f (diff) | |
Input: i8042 - use pr_<level>, pr_fmt, fix dbg and __FILE__ use
Standardized message logging prefixes.
Removed \n from dbg macro, added \n to each dbg call site.
Removed direct use of __FILE__ from dbg, converted to pr_fmt(fmt)
Added non-debug printf argument verification of dbg calls
Removed "i8042.c" from printks, converted to pr_<level>
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
Diffstat (limited to 'drivers/input')
| -rw-r--r-- | drivers/input/serio/i8042-x86ia64io.h | 30 | ||||
| -rw-r--r-- | drivers/input/serio/i8042.c | 92 | ||||
| -rw-r--r-- | drivers/input/serio/i8042.h | 14 |
3 files changed, 63 insertions, 73 deletions
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index a5475b577086..cd9ff808bd23 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h | |||
| @@ -752,7 +752,7 @@ static int __init i8042_pnp_init(void) | |||
| 752 | #endif | 752 | #endif |
| 753 | 753 | ||
| 754 | if (i8042_nopnp) { | 754 | if (i8042_nopnp) { |
| 755 | printk(KERN_INFO "i8042: PNP detection disabled\n"); | 755 | pr_info("PNP detection disabled\n"); |
| 756 | return 0; | 756 | return 0; |
| 757 | } | 757 | } |
| 758 | 758 | ||
| @@ -769,7 +769,7 @@ static int __init i8042_pnp_init(void) | |||
| 769 | #if defined(__ia64__) | 769 | #if defined(__ia64__) |
| 770 | return -ENODEV; | 770 | return -ENODEV; |
| 771 | #else | 771 | #else |
| 772 | printk(KERN_INFO "PNP: No PS/2 controller found. Probing ports directly.\n"); | 772 | pr_info("PNP: No PS/2 controller found. Probing ports directly.\n"); |
| 773 | return 0; | 773 | return 0; |
| 774 | #endif | 774 | #endif |
| 775 | } | 775 | } |
| @@ -781,7 +781,7 @@ static int __init i8042_pnp_init(void) | |||
| 781 | snprintf(aux_irq_str, sizeof(aux_irq_str), | 781 | snprintf(aux_irq_str, sizeof(aux_irq_str), |
| 782 | "%d", i8042_pnp_aux_irq); | 782 | "%d", i8042_pnp_aux_irq); |
| 783 | 783 | ||
| 784 | printk(KERN_INFO "PNP: PS/2 Controller [%s%s%s] at %#x,%#x irq %s%s%s\n", | 784 | pr_info("PNP: PS/2 Controller [%s%s%s] at %#x,%#x irq %s%s%s\n", |
| 785 | i8042_pnp_kbd_name, (i8042_pnp_kbd_devices && i8042_pnp_aux_devices) ? "," : "", | 785 | i8042_pnp_kbd_name, (i8042_pnp_kbd_devices && i8042_pnp_aux_devices) ? "," : "", |
| 786 | i8042_pnp_aux_name, | 786 | i8042_pnp_aux_name, |
| 787 | i8042_pnp_data_reg, i8042_pnp_command_reg, | 787 | i8042_pnp_data_reg, i8042_pnp_command_reg, |
| @@ -798,9 +798,7 @@ static int __init i8042_pnp_init(void) | |||
| 798 | if (((i8042_pnp_data_reg & ~0xf) == (i8042_data_reg & ~0xf) && | 798 | if (((i8042_pnp_data_reg & ~0xf) == (i8042_data_reg & ~0xf) && |
| 799 | i8042_pnp_data_reg != i8042_data_reg) || | 799 | i8042_pnp_data_reg != i8042_data_reg) || |
| 800 | !i8042_pnp_data_reg) { | 800 | !i8042_pnp_data_reg) { |
| 801 | printk(KERN_WARNING | 801 | pr_warn("PNP: PS/2 controller has invalid data port %#x; using default %#x\n", |
| 802 | "PNP: PS/2 controller has invalid data port %#x; " | ||
| 803 | "using default %#x\n", | ||
| 804 | i8042_pnp_data_reg, i8042_data_reg); | 802 | i8042_pnp_data_reg, i8042_data_reg); |
| 805 | i8042_pnp_data_reg = i8042_data_reg; | 803 | i8042_pnp_data_reg = i8042_data_reg; |
| 806 | pnp_data_busted = true; | 804 | pnp_data_busted = true; |
| @@ -809,33 +807,27 @@ static int __init i8042_pnp_init(void) | |||
| 809 | if (((i8042_pnp_command_reg & ~0xf) == (i8042_command_reg & ~0xf) && | 807 | if (((i8042_pnp_command_reg & ~0xf) == (i8042_command_reg & ~0xf) && |
| 810 | i8042_pnp_command_reg != i8042_command_reg) || | 808 | i8042_pnp_command_reg != i8042_command_reg) || |
| 811 | !i8042_pnp_command_reg) { | 809 | !i8042_pnp_command_reg) { |
| 812 | printk(KERN_WARNING | 810 | pr_warn("PNP: PS/2 controller has invalid command port %#x; using default %#x\n", |
| 813 | "PNP: PS/2 controller has invalid command port %#x; " | ||
| 814 | "using default %#x\n", | ||
| 815 | i8042_pnp_command_reg, i8042_command_reg); | 811 | i8042_pnp_command_reg, i8042_command_reg); |
| 816 | i8042_pnp_command_reg = i8042_command_reg; | 812 | i8042_pnp_command_reg = i8042_command_reg; |
| 817 | pnp_data_busted = true; | 813 | pnp_data_busted = true; |
| 818 | } | 814 | } |
| 819 | 815 | ||
| 820 | if (!i8042_nokbd && !i8042_pnp_kbd_irq) { | 816 | if (!i8042_nokbd && !i8042_pnp_kbd_irq) { |
| 821 | printk(KERN_WARNING | 817 | pr_warn("PNP: PS/2 controller doesn't have KBD irq; using default %d\n", |
| 822 | "PNP: PS/2 controller doesn't have KBD irq; " | 818 | i8042_kbd_irq); |
| 823 | "using default %d\n", i8042_kbd_irq); | ||
| 824 | i8042_pnp_kbd_irq = i8042_kbd_irq; | 819 | i8042_pnp_kbd_irq = i8042_kbd_irq; |
| 825 | pnp_data_busted = true; | 820 | pnp_data_busted = true; |
| 826 | } | 821 | } |
| 827 | 822 | ||
| 828 | if (!i8042_noaux && !i8042_pnp_aux_irq) { | 823 | if (!i8042_noaux && !i8042_pnp_aux_irq) { |
| 829 | if (!pnp_data_busted && i8042_pnp_kbd_irq) { | 824 | if (!pnp_data_busted && i8042_pnp_kbd_irq) { |
| 830 | printk(KERN_WARNING | 825 | pr_warn("PNP: PS/2 appears to have AUX port disabled, " |
| 831 | "PNP: PS/2 appears to have AUX port disabled, " | 826 | "if this is incorrect please boot with i8042.nopnp\n"); |
| 832 | "if this is incorrect please boot with " | ||
| 833 | "i8042.nopnp\n"); | ||
| 834 | i8042_noaux = true; | 827 | i8042_noaux = true; |
| 835 | } else { | 828 | } else { |
| 836 | printk(KERN_WARNING | 829 | pr_warn("PNP: PS/2 controller doesn't have AUX irq; using default %d\n", |
| 837 | "PNP: PS/2 controller doesn't have AUX irq; " | 830 | i8042_aux_irq); |
| 838 | "using default %d\n", i8042_aux_irq); | ||
| 839 | i8042_pnp_aux_irq = i8042_aux_irq; | 831 | i8042_pnp_aux_irq = i8042_aux_irq; |
| 840 | } | 832 | } |
| 841 | } | 833 | } |
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index 18db5a8c7478..c04ff00a3663 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | * the Free Software Foundation. | 10 | * the Free Software Foundation. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
| 14 | |||
| 13 | #include <linux/types.h> | 15 | #include <linux/types.h> |
| 14 | #include <linux/delay.h> | 16 | #include <linux/delay.h> |
| 15 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| @@ -225,8 +227,8 @@ static int i8042_flush(void) | |||
| 225 | udelay(50); | 227 | udelay(50); |
| 226 | data = i8042_read_data(); | 228 | data = i8042_read_data(); |
| 227 | i++; | 229 | i++; |
| 228 | dbg("%02x <- i8042 (flush, %s)", data, | 230 | dbg("%02x <- i8042 (flush, %s)\n", |
| 229 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | 231 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); |
| 230 | } | 232 | } |
| 231 | 233 | ||
| 232 | spin_unlock_irqrestore(&i8042_lock, flags); | 234 | spin_unlock_irqrestore(&i8042_lock, flags); |
| @@ -253,32 +255,32 @@ static int __i8042_command(unsigned char *param, int command) | |||
| 253 | if (error) | 255 | if (error) |
| 254 | return error; | 256 | return error; |
| 255 | 257 | ||
| 256 | dbg("%02x -> i8042 (command)", command & 0xff); | 258 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
| 257 | i8042_write_command(command & 0xff); | 259 | i8042_write_command(command & 0xff); |
| 258 | 260 | ||
| 259 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | 261 | for (i = 0; i < ((command >> 12) & 0xf); i++) { |
| 260 | error = i8042_wait_write(); | 262 | error = i8042_wait_write(); |
| 261 | if (error) | 263 | if (error) |
| 262 | return error; | 264 | return error; |
| 263 | dbg("%02x -> i8042 (parameter)", param[i]); | 265 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
| 264 | i8042_write_data(param[i]); | 266 | i8042_write_data(param[i]); |
| 265 | } | 267 | } |
| 266 | 268 | ||
| 267 | for (i = 0; i < ((command >> 8) & 0xf); i++) { | 269 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
| 268 | error = i8042_wait_read(); | 270 | error = i8042_wait_read(); |
| 269 | if (error) { | 271 | if (error) { |
| 270 | dbg(" -- i8042 (timeout)"); | 272 | dbg(" -- i8042 (timeout)\n"); |
| 271 | return error; | 273 | return error; |
| 272 | } | 274 | } |
| 273 | 275 | ||
| 274 | if (command == I8042_CMD_AUX_LOOP && | 276 | if (command == I8042_CMD_AUX_LOOP && |
| 275 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | 277 | !(i8042_read_status() & I8042_STR_AUXDATA)) { |
| 276 | dbg(" -- i8042 (auxerr)"); | 278 | dbg(" -- i8042 (auxerr)\n"); |
| 277 | return -1; | 279 | return -1; |
| 278 | } | 280 | } |
| 279 | 281 | ||
| 280 | param[i] = i8042_read_data(); | 282 | param[i] = i8042_read_data(); |
| 281 | dbg("%02x <- i8042 (return)", param[i]); | 283 | dbg("%02x <- i8042 (return)\n", param[i]); |
| 282 | } | 284 | } |
| 283 | 285 | ||
| 284 | return 0; | 286 | return 0; |
| @@ -309,7 +311,7 @@ static int i8042_kbd_write(struct serio *port, unsigned char c) | |||
| 309 | spin_lock_irqsave(&i8042_lock, flags); | 311 | spin_lock_irqsave(&i8042_lock, flags); |
| 310 | 312 | ||
| 311 | if (!(retval = i8042_wait_write())) { | 313 | if (!(retval = i8042_wait_write())) { |
| 312 | dbg("%02x -> i8042 (kbd-data)", c); | 314 | dbg("%02x -> i8042 (kbd-data)\n", c); |
| 313 | i8042_write_data(c); | 315 | i8042_write_data(c); |
| 314 | } | 316 | } |
| 315 | 317 | ||
| @@ -355,17 +357,14 @@ static void i8042_port_close(struct serio *serio) | |||
| 355 | 357 | ||
| 356 | i8042_ctr &= ~irq_bit; | 358 | i8042_ctr &= ~irq_bit; |
| 357 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 359 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
| 358 | printk(KERN_WARNING | 360 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
| 359 | "i8042.c: Can't write CTR while closing %s port.\n", | ||
| 360 | port_name); | ||
| 361 | 361 | ||
| 362 | udelay(50); | 362 | udelay(50); |
| 363 | 363 | ||
| 364 | i8042_ctr &= ~disable_bit; | 364 | i8042_ctr &= ~disable_bit; |
| 365 | i8042_ctr |= irq_bit; | 365 | i8042_ctr |= irq_bit; |
| 366 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 366 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
| 367 | printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", | 367 | pr_err("Can't reactivate %s port\n", port_name); |
| 368 | port_name); | ||
| 369 | 368 | ||
| 370 | /* | 369 | /* |
| 371 | * See if there is any data appeared while we were messing with | 370 | * See if there is any data appeared while we were messing with |
| @@ -456,7 +455,8 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
| 456 | str = i8042_read_status(); | 455 | str = i8042_read_status(); |
| 457 | if (unlikely(~str & I8042_STR_OBF)) { | 456 | if (unlikely(~str & I8042_STR_OBF)) { |
| 458 | spin_unlock_irqrestore(&i8042_lock, flags); | 457 | spin_unlock_irqrestore(&i8042_lock, flags); |
| 459 | if (irq) dbg("Interrupt %d, without any data", irq); | 458 | if (irq) |
| 459 | dbg("Interrupt %d, without any data\n", irq); | ||
| 460 | ret = 0; | 460 | ret = 0; |
| 461 | goto out; | 461 | goto out; |
| 462 | } | 462 | } |
| @@ -469,7 +469,8 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
| 469 | 469 | ||
| 470 | dfl = 0; | 470 | dfl = 0; |
| 471 | if (str & I8042_STR_MUXERR) { | 471 | if (str & I8042_STR_MUXERR) { |
| 472 | dbg("MUX error, status is %02x, data is %02x", str, data); | 472 | dbg("MUX error, status is %02x, data is %02x\n", |
| 473 | str, data); | ||
| 473 | /* | 474 | /* |
| 474 | * When MUXERR condition is signalled the data register can only contain | 475 | * When MUXERR condition is signalled the data register can only contain |
| 475 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | 476 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately |
| @@ -512,7 +513,7 @@ static irqreturn_t i8042_interrupt(int irq, void *dev_id) | |||
| 512 | port = &i8042_ports[port_no]; | 513 | port = &i8042_ports[port_no]; |
| 513 | serio = port->exists ? port->serio : NULL; | 514 | serio = port->exists ? port->serio : NULL; |
| 514 | 515 | ||
| 515 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", | 516 | dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", |
| 516 | data, port_no, irq, | 517 | data, port_no, irq, |
| 517 | dfl & SERIO_PARITY ? ", bad parity" : "", | 518 | dfl & SERIO_PARITY ? ", bad parity" : "", |
| 518 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | 519 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); |
| @@ -540,7 +541,7 @@ static int i8042_enable_kbd_port(void) | |||
| 540 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 541 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 541 | i8042_ctr &= ~I8042_CTR_KBDINT; | 542 | i8042_ctr &= ~I8042_CTR_KBDINT; |
| 542 | i8042_ctr |= I8042_CTR_KBDDIS; | 543 | i8042_ctr |= I8042_CTR_KBDDIS; |
| 543 | printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); | 544 | pr_err("Failed to enable KBD port\n"); |
| 544 | return -EIO; | 545 | return -EIO; |
| 545 | } | 546 | } |
| 546 | 547 | ||
| @@ -559,7 +560,7 @@ static int i8042_enable_aux_port(void) | |||
| 559 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 560 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 560 | i8042_ctr &= ~I8042_CTR_AUXINT; | 561 | i8042_ctr &= ~I8042_CTR_AUXINT; |
| 561 | i8042_ctr |= I8042_CTR_AUXDIS; | 562 | i8042_ctr |= I8042_CTR_AUXDIS; |
| 562 | printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); | 563 | pr_err("Failed to enable AUX port\n"); |
| 563 | return -EIO; | 564 | return -EIO; |
| 564 | } | 565 | } |
| 565 | 566 | ||
| @@ -641,7 +642,7 @@ static int __init i8042_check_mux(void) | |||
| 641 | if (i8042_set_mux_mode(true, &mux_version)) | 642 | if (i8042_set_mux_mode(true, &mux_version)) |
| 642 | return -1; | 643 | return -1; |
| 643 | 644 | ||
| 644 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | 645 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
| 645 | (mux_version >> 4) & 0xf, mux_version & 0xf); | 646 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
| 646 | 647 | ||
| 647 | /* | 648 | /* |
| @@ -651,7 +652,7 @@ static int __init i8042_check_mux(void) | |||
| 651 | i8042_ctr &= ~I8042_CTR_AUXINT; | 652 | i8042_ctr &= ~I8042_CTR_AUXINT; |
| 652 | 653 | ||
| 653 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 654 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 654 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | 655 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
| 655 | return -EIO; | 656 | return -EIO; |
| 656 | } | 657 | } |
| 657 | 658 | ||
| @@ -676,8 +677,8 @@ static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) | |||
| 676 | str = i8042_read_status(); | 677 | str = i8042_read_status(); |
| 677 | if (str & I8042_STR_OBF) { | 678 | if (str & I8042_STR_OBF) { |
| 678 | data = i8042_read_data(); | 679 | data = i8042_read_data(); |
| 679 | dbg("%02x <- i8042 (aux_test_irq, %s)", | 680 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
| 680 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | 681 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); |
| 681 | if (i8042_irq_being_tested && | 682 | if (i8042_irq_being_tested && |
| 682 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | 683 | data == 0xa5 && (str & I8042_STR_AUXDATA)) |
| 683 | complete(&i8042_aux_irq_delivered); | 684 | complete(&i8042_aux_irq_delivered); |
| @@ -770,8 +771,8 @@ static int __init i8042_check_aux(void) | |||
| 770 | */ | 771 | */ |
| 771 | 772 | ||
| 772 | if (i8042_toggle_aux(false)) { | 773 | if (i8042_toggle_aux(false)) { |
| 773 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | 774 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
| 774 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | 775 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); |
| 775 | } | 776 | } |
| 776 | 777 | ||
| 777 | if (i8042_toggle_aux(true)) | 778 | if (i8042_toggle_aux(true)) |
| @@ -819,7 +820,7 @@ static int __init i8042_check_aux(void) | |||
| 819 | * AUX IRQ was never delivered so we need to flush the controller to | 820 | * AUX IRQ was never delivered so we need to flush the controller to |
| 820 | * get rid of the byte we put there; otherwise keyboard may not work. | 821 | * get rid of the byte we put there; otherwise keyboard may not work. |
| 821 | */ | 822 | */ |
| 822 | dbg(" -- i8042 (aux irq test timeout)"); | 823 | dbg(" -- i8042 (aux irq test timeout)\n"); |
| 823 | i8042_flush(); | 824 | i8042_flush(); |
| 824 | retval = -1; | 825 | retval = -1; |
| 825 | } | 826 | } |
| @@ -845,7 +846,7 @@ static int __init i8042_check_aux(void) | |||
| 845 | static int i8042_controller_check(void) | 846 | static int i8042_controller_check(void) |
| 846 | { | 847 | { |
| 847 | if (i8042_flush() == I8042_BUFFER_SIZE) { | 848 | if (i8042_flush() == I8042_BUFFER_SIZE) { |
| 848 | printk(KERN_ERR "i8042.c: No controller found.\n"); | 849 | pr_err("No controller found\n"); |
| 849 | return -ENODEV; | 850 | return -ENODEV; |
| 850 | } | 851 | } |
| 851 | 852 | ||
| @@ -864,15 +865,15 @@ static int i8042_controller_selftest(void) | |||
| 864 | do { | 865 | do { |
| 865 | 866 | ||
| 866 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | 867 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { |
| 867 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | 868 | pr_err("i8042 controller self test timeout\n"); |
| 868 | return -ENODEV; | 869 | return -ENODEV; |
| 869 | } | 870 | } |
| 870 | 871 | ||
| 871 | if (param == I8042_RET_CTL_TEST) | 872 | if (param == I8042_RET_CTL_TEST) |
| 872 | return 0; | 873 | return 0; |
| 873 | 874 | ||
| 874 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | 875 | pr_err("i8042 controller selftest failed. (%#x != %#x)\n", |
| 875 | param, I8042_RET_CTL_TEST); | 876 | param, I8042_RET_CTL_TEST); |
| 876 | msleep(50); | 877 | msleep(50); |
| 877 | } while (i++ < 5); | 878 | } while (i++ < 5); |
| 878 | 879 | ||
| @@ -883,8 +884,7 @@ static int i8042_controller_selftest(void) | |||
| 883 | * and user will still get a working keyboard. This is especially | 884 | * and user will still get a working keyboard. This is especially |
| 884 | * important on netbooks. On other arches we trust hardware more. | 885 | * important on netbooks. On other arches we trust hardware more. |
| 885 | */ | 886 | */ |
| 886 | printk(KERN_INFO | 887 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
| 887 | "i8042: giving up on controller selftest, continuing anyway...\n"); | ||
| 888 | return 0; | 888 | return 0; |
| 889 | #else | 889 | #else |
| 890 | return -EIO; | 890 | return -EIO; |
| @@ -909,8 +909,7 @@ static int i8042_controller_init(void) | |||
| 909 | 909 | ||
| 910 | do { | 910 | do { |
| 911 | if (n >= 10) { | 911 | if (n >= 10) { |
| 912 | printk(KERN_ERR | 912 | pr_err("Unable to get stable CTR read\n"); |
| 913 | "i8042.c: Unable to get stable CTR read.\n"); | ||
| 914 | return -EIO; | 913 | return -EIO; |
| 915 | } | 914 | } |
| 916 | 915 | ||
| @@ -918,8 +917,7 @@ static int i8042_controller_init(void) | |||
| 918 | udelay(50); | 917 | udelay(50); |
| 919 | 918 | ||
| 920 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | 919 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { |
| 921 | printk(KERN_ERR | 920 | pr_err("Can't read CTR while initializing i8042\n"); |
| 922 | "i8042.c: Can't read CTR while initializing i8042.\n"); | ||
| 923 | return -EIO; | 921 | return -EIO; |
| 924 | } | 922 | } |
| 925 | 923 | ||
| @@ -943,7 +941,7 @@ static int i8042_controller_init(void) | |||
| 943 | if (i8042_unlock) | 941 | if (i8042_unlock) |
| 944 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | 942 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; |
| 945 | else | 943 | else |
| 946 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | 944 | pr_warn("Warning: Keylock active\n"); |
| 947 | } | 945 | } |
| 948 | spin_unlock_irqrestore(&i8042_lock, flags); | 946 | spin_unlock_irqrestore(&i8042_lock, flags); |
| 949 | 947 | ||
| @@ -970,7 +968,7 @@ static int i8042_controller_init(void) | |||
| 970 | */ | 968 | */ |
| 971 | 969 | ||
| 972 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 970 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 973 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | 971 | pr_err("Can't write CTR while initializing i8042\n"); |
| 974 | return -EIO; | 972 | return -EIO; |
| 975 | } | 973 | } |
| 976 | 974 | ||
| @@ -1000,7 +998,7 @@ static void i8042_controller_reset(void) | |||
| 1000 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | 998 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); |
| 1001 | 999 | ||
| 1002 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | 1000 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
| 1003 | printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); | 1001 | pr_warn("Can't write CTR while resetting\n"); |
| 1004 | 1002 | ||
| 1005 | /* | 1003 | /* |
| 1006 | * Disable MUX mode if present. | 1004 | * Disable MUX mode if present. |
| @@ -1021,7 +1019,7 @@ static void i8042_controller_reset(void) | |||
| 1021 | */ | 1019 | */ |
| 1022 | 1020 | ||
| 1023 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | 1021 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) |
| 1024 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); | 1022 | pr_warn("Can't restore CTR\n"); |
| 1025 | } | 1023 | } |
| 1026 | 1024 | ||
| 1027 | 1025 | ||
| @@ -1045,14 +1043,14 @@ static long i8042_panic_blink(int state) | |||
| 1045 | led = (state) ? 0x01 | 0x04 : 0; | 1043 | led = (state) ? 0x01 | 0x04 : 0; |
| 1046 | while (i8042_read_status() & I8042_STR_IBF) | 1044 | while (i8042_read_status() & I8042_STR_IBF) |
| 1047 | DELAY; | 1045 | DELAY; |
| 1048 | dbg("%02x -> i8042 (panic blink)", 0xed); | 1046 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
| 1049 | i8042_suppress_kbd_ack = 2; | 1047 | i8042_suppress_kbd_ack = 2; |
| 1050 | i8042_write_data(0xed); /* set leds */ | 1048 | i8042_write_data(0xed); /* set leds */ |
| 1051 | DELAY; | 1049 | DELAY; |
| 1052 | while (i8042_read_status() & I8042_STR_IBF) | 1050 | while (i8042_read_status() & I8042_STR_IBF) |
| 1053 | DELAY; | 1051 | DELAY; |
| 1054 | DELAY; | 1052 | DELAY; |
| 1055 | dbg("%02x -> i8042 (panic blink)", led); | 1053 | dbg("%02x -> i8042 (panic blink)\n", led); |
| 1056 | i8042_write_data(led); | 1054 | i8042_write_data(led); |
| 1057 | DELAY; | 1055 | DELAY; |
| 1058 | return delay; | 1056 | return delay; |
| @@ -1068,9 +1066,7 @@ static void i8042_dritek_enable(void) | |||
| 1068 | 1066 | ||
| 1069 | error = i8042_command(¶m, 0x1059); | 1067 | error = i8042_command(¶m, 0x1059); |
| 1070 | if (error) | 1068 | if (error) |
| 1071 | printk(KERN_WARNING | 1069 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
| 1072 | "Failed to enable DRITEK extension: %d\n", | ||
| 1073 | error); | ||
| 1074 | } | 1070 | } |
| 1075 | #endif | 1071 | #endif |
| 1076 | 1072 | ||
| @@ -1105,10 +1101,10 @@ static int i8042_controller_resume(bool force_reset) | |||
| 1105 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; | 1101 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
| 1106 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | 1102 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); |
| 1107 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 1103 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 1108 | printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); | 1104 | pr_warn("Can't write CTR to resume, retrying...\n"); |
| 1109 | msleep(50); | 1105 | msleep(50); |
| 1110 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 1106 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
| 1111 | printk(KERN_ERR "i8042: CTR write retry failed\n"); | 1107 | pr_err("CTR write retry failed\n"); |
| 1112 | return -EIO; | 1108 | return -EIO; |
| 1113 | } | 1109 | } |
| 1114 | } | 1110 | } |
| @@ -1121,9 +1117,7 @@ static int i8042_controller_resume(bool force_reset) | |||
| 1121 | 1117 | ||
| 1122 | if (i8042_mux_present) { | 1118 | if (i8042_mux_present) { |
| 1123 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) | 1119 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
| 1124 | printk(KERN_WARNING | 1120 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
| 1125 | "i8042: failed to resume active multiplexor, " | ||
| 1126 | "mouse won't work.\n"); | ||
| 1127 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) | 1121 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
| 1128 | i8042_enable_aux_port(); | 1122 | i8042_enable_aux_port(); |
| 1129 | 1123 | ||
diff --git a/drivers/input/serio/i8042.h b/drivers/input/serio/i8042.h index cbc1beb66574..ac1d759d0f55 100644 --- a/drivers/input/serio/i8042.h +++ b/drivers/input/serio/i8042.h | |||
| @@ -89,15 +89,19 @@ | |||
| 89 | #ifdef DEBUG | 89 | #ifdef DEBUG |
| 90 | static unsigned long i8042_start_time; | 90 | static unsigned long i8042_start_time; |
| 91 | #define dbg_init() do { i8042_start_time = jiffies; } while (0) | 91 | #define dbg_init() do { i8042_start_time = jiffies; } while (0) |
| 92 | #define dbg(format, arg...) \ | 92 | #define dbg(format, arg...) \ |
| 93 | do { \ | 93 | do { \ |
| 94 | if (i8042_debug) \ | 94 | if (i8042_debug) \ |
| 95 | printk(KERN_DEBUG __FILE__ ": " format " [%d]\n" , \ | 95 | printk(KERN_DEBUG KBUILD_MODNAME ": [%d] " format, \ |
| 96 | ## arg, (int) (jiffies - i8042_start_time)); \ | 96 | (int) (jiffies - i8042_start_time), ##arg); \ |
| 97 | } while (0) | 97 | } while (0) |
| 98 | #else | 98 | #else |
| 99 | #define dbg_init() do { } while (0) | 99 | #define dbg_init() do { } while (0) |
| 100 | #define dbg(format, arg...) do {} while (0) | 100 | #define dbg(format, arg...) \ |
| 101 | do { \ | ||
| 102 | if (0) \ | ||
| 103 | printk(KERN_DEBUG pr_fmt(format), ##arg); \ | ||
| 104 | } while (0) | ||
| 101 | #endif | 105 | #endif |
| 102 | 106 | ||
| 103 | #endif /* _I8042_H */ | 107 | #endif /* _I8042_H */ |
