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authorIngo Molnar <mingo@elte.hu>2009-05-11 08:44:27 -0400
committerIngo Molnar <mingo@elte.hu>2009-05-11 08:44:31 -0400
commit41fb454ebe6024f5c1e3b3cbc0abc0da762e7b51 (patch)
tree51c50bcb67a5039448ddfa1869d7948cab1217e9 /drivers/infiniband/hw
parent19c1a6f5764d787113fa323ffb18be7991208f82 (diff)
parent091bf7624d1c90cec9e578a18529f615213ff847 (diff)
Merge commit 'v2.6.30-rc5' into core/iommu
Merge reason: core/iommu was on an .30-rc1 base, update it to .30-rc5 to refresh. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/infiniband/hw')
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_hal.c10
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_hal.h6
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch.c11
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch.h5
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_cm.c124
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_cm.h3
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_qp.c5
-rw-r--r--drivers/infiniband/hw/mlx4/main.c3
-rw-r--r--drivers/infiniband/hw/mthca/mthca_cmd.c16
-rw-r--r--drivers/infiniband/hw/nes/nes.h8
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.c106
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.h2
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c395
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.h2
-rw-r--r--drivers/infiniband/hw/nes/nes_nic.c52
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.c67
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.h1
17 files changed, 460 insertions, 356 deletions
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c
index a4a82bff7100..8d71086f5a1c 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c
@@ -152,7 +152,7 @@ static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
152 sge_cmd = qpid << 8 | 3; 152 sge_cmd = qpid << 8 | 3;
153 wqe->sge_cmd = cpu_to_be64(sge_cmd); 153 wqe->sge_cmd = cpu_to_be64(sge_cmd);
154 skb->priority = CPL_PRIORITY_CONTROL; 154 skb->priority = CPL_PRIORITY_CONTROL;
155 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 155 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
156} 156}
157 157
158int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) 158int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
@@ -571,7 +571,7 @@ static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
571 (unsigned long long) rdev_p->ctrl_qp.dma_addr, 571 (unsigned long long) rdev_p->ctrl_qp.dma_addr,
572 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2); 572 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
573 skb->priority = CPL_PRIORITY_CONTROL; 573 skb->priority = CPL_PRIORITY_CONTROL;
574 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 574 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
575err: 575err:
576 kfree_skb(skb); 576 kfree_skb(skb);
577 return err; 577 return err;
@@ -701,7 +701,7 @@ static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
701 u32 stag_idx; 701 u32 stag_idx;
702 u32 wptr; 702 u32 wptr;
703 703
704 if (rdev_p->flags) 704 if (cxio_fatal_error(rdev_p))
705 return -EIO; 705 return -EIO;
706 706
707 stag_state = stag_state > 0; 707 stag_state = stag_state > 0;
@@ -858,7 +858,7 @@ int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
858 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size); 858 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
859 wqe->irs = cpu_to_be32(attr->irs); 859 wqe->irs = cpu_to_be32(attr->irs);
860 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */ 860 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
861 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 861 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
862} 862}
863 863
864void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb) 864void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
@@ -1041,9 +1041,9 @@ void cxio_rdev_close(struct cxio_rdev *rdev_p)
1041 cxio_hal_pblpool_destroy(rdev_p); 1041 cxio_hal_pblpool_destroy(rdev_p);
1042 cxio_hal_rqtpool_destroy(rdev_p); 1042 cxio_hal_rqtpool_destroy(rdev_p);
1043 list_del(&rdev_p->entry); 1043 list_del(&rdev_p->entry);
1044 rdev_p->t3cdev_p->ulp = NULL;
1045 cxio_hal_destroy_ctrl_qp(rdev_p); 1044 cxio_hal_destroy_ctrl_qp(rdev_p);
1046 cxio_hal_destroy_resource(rdev_p->rscp); 1045 cxio_hal_destroy_resource(rdev_p->rscp);
1046 rdev_p->t3cdev_p->ulp = NULL;
1047 } 1047 }
1048} 1048}
1049 1049
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.h b/drivers/infiniband/hw/cxgb3/cxio_hal.h
index 094a66d1480c..bfd03bf8be54 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.h
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.h
@@ -115,6 +115,11 @@ struct cxio_rdev {
115#define CXIO_ERROR_FATAL 1 115#define CXIO_ERROR_FATAL 1
116}; 116};
117 117
118static inline int cxio_fatal_error(struct cxio_rdev *rdev_p)
119{
120 return rdev_p->flags & CXIO_ERROR_FATAL;
121}
122
118static inline int cxio_num_stags(struct cxio_rdev *rdev_p) 123static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
119{ 124{
120 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5)); 125 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
@@ -188,6 +193,7 @@ void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
188void cxio_flush_hw_cq(struct t3_cq *cq); 193void cxio_flush_hw_cq(struct t3_cq *cq);
189int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe, 194int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
190 u8 *cqe_flushed, u64 *cookie, u32 *credit); 195 u8 *cqe_flushed, u64 *cookie, u32 *credit);
196int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb);
191 197
192#define MOD "iw_cxgb3: " 198#define MOD "iw_cxgb3: "
193#define PDBG(fmt, args...) pr_debug(MOD fmt, ## args) 199#define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
diff --git a/drivers/infiniband/hw/cxgb3/iwch.c b/drivers/infiniband/hw/cxgb3/iwch.c
index 37a4fc264a07..26fc0a4eaa74 100644
--- a/drivers/infiniband/hw/cxgb3/iwch.c
+++ b/drivers/infiniband/hw/cxgb3/iwch.c
@@ -165,12 +165,19 @@ static void close_rnic_dev(struct t3cdev *tdev)
165static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error) 165static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error)
166{ 166{
167 struct cxio_rdev *rdev = tdev->ulp; 167 struct cxio_rdev *rdev = tdev->ulp;
168 struct iwch_dev *rnicp = rdev_to_iwch_dev(rdev);
169 struct ib_event event;
168 170
169 if (status == OFFLOAD_STATUS_DOWN) 171 if (status == OFFLOAD_STATUS_DOWN) {
170 rdev->flags = CXIO_ERROR_FATAL; 172 rdev->flags = CXIO_ERROR_FATAL;
171 173
172 return; 174 event.device = &rnicp->ibdev;
175 event.event = IB_EVENT_DEVICE_FATAL;
176 event.element.port_num = 0;
177 ib_dispatch_event(&event);
178 }
173 179
180 return;
174} 181}
175 182
176static int __init iwch_init_module(void) 183static int __init iwch_init_module(void)
diff --git a/drivers/infiniband/hw/cxgb3/iwch.h b/drivers/infiniband/hw/cxgb3/iwch.h
index 3773453b2cf0..84735506333f 100644
--- a/drivers/infiniband/hw/cxgb3/iwch.h
+++ b/drivers/infiniband/hw/cxgb3/iwch.h
@@ -117,6 +117,11 @@ static inline struct iwch_dev *to_iwch_dev(struct ib_device *ibdev)
117 return container_of(ibdev, struct iwch_dev, ibdev); 117 return container_of(ibdev, struct iwch_dev, ibdev);
118} 118}
119 119
120static inline struct iwch_dev *rdev_to_iwch_dev(struct cxio_rdev *rdev)
121{
122 return container_of(rdev, struct iwch_dev, rdev);
123}
124
120static inline int t3b_device(const struct iwch_dev *rhp) 125static inline int t3b_device(const struct iwch_dev *rhp)
121{ 126{
122 return rhp->rdev.t3cdev_p->type == T3B; 127 return rhp->rdev.t3cdev_p->type == T3B;
diff --git a/drivers/infiniband/hw/cxgb3/iwch_cm.c b/drivers/infiniband/hw/cxgb3/iwch_cm.c
index 8699947aaf6c..52d7bb0c2a12 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_cm.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_cm.c
@@ -139,6 +139,38 @@ static void stop_ep_timer(struct iwch_ep *ep)
139 put_ep(&ep->com); 139 put_ep(&ep->com);
140} 140}
141 141
142int iwch_l2t_send(struct t3cdev *tdev, struct sk_buff *skb, struct l2t_entry *l2e)
143{
144 int error = 0;
145 struct cxio_rdev *rdev;
146
147 rdev = (struct cxio_rdev *)tdev->ulp;
148 if (cxio_fatal_error(rdev)) {
149 kfree_skb(skb);
150 return -EIO;
151 }
152 error = l2t_send(tdev, skb, l2e);
153 if (error)
154 kfree_skb(skb);
155 return error;
156}
157
158int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb)
159{
160 int error = 0;
161 struct cxio_rdev *rdev;
162
163 rdev = (struct cxio_rdev *)tdev->ulp;
164 if (cxio_fatal_error(rdev)) {
165 kfree_skb(skb);
166 return -EIO;
167 }
168 error = cxgb3_ofld_send(tdev, skb);
169 if (error)
170 kfree_skb(skb);
171 return error;
172}
173
142static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb) 174static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb)
143{ 175{
144 struct cpl_tid_release *req; 176 struct cpl_tid_release *req;
@@ -150,7 +182,7 @@ static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb)
150 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 182 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
151 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, hwtid)); 183 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, hwtid));
152 skb->priority = CPL_PRIORITY_SETUP; 184 skb->priority = CPL_PRIORITY_SETUP;
153 cxgb3_ofld_send(tdev, skb); 185 iwch_cxgb3_ofld_send(tdev, skb);
154 return; 186 return;
155} 187}
156 188
@@ -172,8 +204,7 @@ int iwch_quiesce_tid(struct iwch_ep *ep)
172 req->val = cpu_to_be64(1 << S_TCB_RX_QUIESCE); 204 req->val = cpu_to_be64(1 << S_TCB_RX_QUIESCE);
173 205
174 skb->priority = CPL_PRIORITY_DATA; 206 skb->priority = CPL_PRIORITY_DATA;
175 cxgb3_ofld_send(ep->com.tdev, skb); 207 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
176 return 0;
177} 208}
178 209
179int iwch_resume_tid(struct iwch_ep *ep) 210int iwch_resume_tid(struct iwch_ep *ep)
@@ -194,8 +225,7 @@ int iwch_resume_tid(struct iwch_ep *ep)
194 req->val = 0; 225 req->val = 0;
195 226
196 skb->priority = CPL_PRIORITY_DATA; 227 skb->priority = CPL_PRIORITY_DATA;
197 cxgb3_ofld_send(ep->com.tdev, skb); 228 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
198 return 0;
199} 229}
200 230
201static void set_emss(struct iwch_ep *ep, u16 opt) 231static void set_emss(struct iwch_ep *ep, u16 opt)
@@ -252,18 +282,22 @@ static void *alloc_ep(int size, gfp_t gfp)
252 282
253void __free_ep(struct kref *kref) 283void __free_ep(struct kref *kref)
254{ 284{
255 struct iwch_ep_common *epc; 285 struct iwch_ep *ep;
256 epc = container_of(kref, struct iwch_ep_common, kref); 286 ep = container_of(container_of(kref, struct iwch_ep_common, kref),
257 PDBG("%s ep %p state %s\n", __func__, epc, states[state_read(epc)]); 287 struct iwch_ep, com);
258 kfree(epc); 288 PDBG("%s ep %p state %s\n", __func__, ep, states[state_read(&ep->com)]);
289 if (ep->com.flags & RELEASE_RESOURCES) {
290 cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid);
291 dst_release(ep->dst);
292 l2t_release(L2DATA(ep->com.tdev), ep->l2t);
293 }
294 kfree(ep);
259} 295}
260 296
261static void release_ep_resources(struct iwch_ep *ep) 297static void release_ep_resources(struct iwch_ep *ep)
262{ 298{
263 PDBG("%s ep %p tid %d\n", __func__, ep, ep->hwtid); 299 PDBG("%s ep %p tid %d\n", __func__, ep, ep->hwtid);
264 cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid); 300 ep->com.flags |= RELEASE_RESOURCES;
265 dst_release(ep->dst);
266 l2t_release(L2DATA(ep->com.tdev), ep->l2t);
267 put_ep(&ep->com); 301 put_ep(&ep->com);
268} 302}
269 303
@@ -382,7 +416,7 @@ static void abort_arp_failure(struct t3cdev *dev, struct sk_buff *skb)
382 416
383 PDBG("%s t3cdev %p\n", __func__, dev); 417 PDBG("%s t3cdev %p\n", __func__, dev);
384 req->cmd = CPL_ABORT_NO_RST; 418 req->cmd = CPL_ABORT_NO_RST;
385 cxgb3_ofld_send(dev, skb); 419 iwch_cxgb3_ofld_send(dev, skb);
386} 420}
387 421
388static int send_halfclose(struct iwch_ep *ep, gfp_t gfp) 422static int send_halfclose(struct iwch_ep *ep, gfp_t gfp)
@@ -402,8 +436,7 @@ static int send_halfclose(struct iwch_ep *ep, gfp_t gfp)
402 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_OFLD_CLOSE_CON)); 436 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_OFLD_CLOSE_CON));
403 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 437 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
404 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_CON_REQ, ep->hwtid)); 438 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_CON_REQ, ep->hwtid));
405 l2t_send(ep->com.tdev, skb, ep->l2t); 439 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
406 return 0;
407} 440}
408 441
409static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp) 442static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp)
@@ -424,8 +457,7 @@ static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp)
424 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 457 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
425 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ABORT_REQ, ep->hwtid)); 458 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ABORT_REQ, ep->hwtid));
426 req->cmd = CPL_ABORT_SEND_RST; 459 req->cmd = CPL_ABORT_SEND_RST;
427 l2t_send(ep->com.tdev, skb, ep->l2t); 460 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
428 return 0;
429} 461}
430 462
431static int send_connect(struct iwch_ep *ep) 463static int send_connect(struct iwch_ep *ep)
@@ -469,8 +501,7 @@ static int send_connect(struct iwch_ep *ep)
469 req->opt0l = htonl(opt0l); 501 req->opt0l = htonl(opt0l);
470 req->params = 0; 502 req->params = 0;
471 req->opt2 = htonl(opt2); 503 req->opt2 = htonl(opt2);
472 l2t_send(ep->com.tdev, skb, ep->l2t); 504 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
473 return 0;
474} 505}
475 506
476static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb) 507static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb)
@@ -527,7 +558,7 @@ static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb)
527 req->sndseq = htonl(ep->snd_seq); 558 req->sndseq = htonl(ep->snd_seq);
528 BUG_ON(ep->mpa_skb); 559 BUG_ON(ep->mpa_skb);
529 ep->mpa_skb = skb; 560 ep->mpa_skb = skb;
530 l2t_send(ep->com.tdev, skb, ep->l2t); 561 iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
531 start_ep_timer(ep); 562 start_ep_timer(ep);
532 state_set(&ep->com, MPA_REQ_SENT); 563 state_set(&ep->com, MPA_REQ_SENT);
533 return; 564 return;
@@ -578,8 +609,7 @@ static int send_mpa_reject(struct iwch_ep *ep, const void *pdata, u8 plen)
578 req->sndseq = htonl(ep->snd_seq); 609 req->sndseq = htonl(ep->snd_seq);
579 BUG_ON(ep->mpa_skb); 610 BUG_ON(ep->mpa_skb);
580 ep->mpa_skb = skb; 611 ep->mpa_skb = skb;
581 l2t_send(ep->com.tdev, skb, ep->l2t); 612 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
582 return 0;
583} 613}
584 614
585static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen) 615static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen)
@@ -630,8 +660,7 @@ static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen)
630 req->sndseq = htonl(ep->snd_seq); 660 req->sndseq = htonl(ep->snd_seq);
631 ep->mpa_skb = skb; 661 ep->mpa_skb = skb;
632 state_set(&ep->com, MPA_REP_SENT); 662 state_set(&ep->com, MPA_REP_SENT);
633 l2t_send(ep->com.tdev, skb, ep->l2t); 663 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
634 return 0;
635} 664}
636 665
637static int act_establish(struct t3cdev *tdev, struct sk_buff *skb, void *ctx) 666static int act_establish(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
@@ -795,7 +824,7 @@ static int update_rx_credits(struct iwch_ep *ep, u32 credits)
795 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RX_DATA_ACK, ep->hwtid)); 824 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RX_DATA_ACK, ep->hwtid));
796 req->credit_dack = htonl(V_RX_CREDITS(credits) | V_RX_FORCE_ACK(1)); 825 req->credit_dack = htonl(V_RX_CREDITS(credits) | V_RX_FORCE_ACK(1));
797 skb->priority = CPL_PRIORITY_ACK; 826 skb->priority = CPL_PRIORITY_ACK;
798 cxgb3_ofld_send(ep->com.tdev, skb); 827 iwch_cxgb3_ofld_send(ep->com.tdev, skb);
799 return credits; 828 return credits;
800} 829}
801 830
@@ -1127,8 +1156,8 @@ static int abort_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1127 * We get 2 abort replies from the HW. The first one must 1156 * We get 2 abort replies from the HW. The first one must
1128 * be ignored except for scribbling that we need one more. 1157 * be ignored except for scribbling that we need one more.
1129 */ 1158 */
1130 if (!(ep->flags & ABORT_REQ_IN_PROGRESS)) { 1159 if (!(ep->com.flags & ABORT_REQ_IN_PROGRESS)) {
1131 ep->flags |= ABORT_REQ_IN_PROGRESS; 1160 ep->com.flags |= ABORT_REQ_IN_PROGRESS;
1132 return CPL_RET_BUF_DONE; 1161 return CPL_RET_BUF_DONE;
1133 } 1162 }
1134 1163
@@ -1203,8 +1232,7 @@ static int listen_start(struct iwch_listen_ep *ep)
1203 req->opt1 = htonl(V_CONN_POLICY(CPL_CONN_POLICY_ASK)); 1232 req->opt1 = htonl(V_CONN_POLICY(CPL_CONN_POLICY_ASK));
1204 1233
1205 skb->priority = 1; 1234 skb->priority = 1;
1206 cxgb3_ofld_send(ep->com.tdev, skb); 1235 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
1207 return 0;
1208} 1236}
1209 1237
1210static int pass_open_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx) 1238static int pass_open_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
@@ -1237,8 +1265,7 @@ static int listen_stop(struct iwch_listen_ep *ep)
1237 req->cpu_idx = 0; 1265 req->cpu_idx = 0;
1238 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, ep->stid)); 1266 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, ep->stid));
1239 skb->priority = 1; 1267 skb->priority = 1;
1240 cxgb3_ofld_send(ep->com.tdev, skb); 1268 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
1241 return 0;
1242} 1269}
1243 1270
1244static int close_listsrv_rpl(struct t3cdev *tdev, struct sk_buff *skb, 1271static int close_listsrv_rpl(struct t3cdev *tdev, struct sk_buff *skb,
@@ -1286,7 +1313,7 @@ static void accept_cr(struct iwch_ep *ep, __be32 peer_ip, struct sk_buff *skb)
1286 rpl->opt2 = htonl(opt2); 1313 rpl->opt2 = htonl(opt2);
1287 rpl->rsvd = rpl->opt2; /* workaround for HW bug */ 1314 rpl->rsvd = rpl->opt2; /* workaround for HW bug */
1288 skb->priority = CPL_PRIORITY_SETUP; 1315 skb->priority = CPL_PRIORITY_SETUP;
1289 l2t_send(ep->com.tdev, skb, ep->l2t); 1316 iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
1290 1317
1291 return; 1318 return;
1292} 1319}
@@ -1315,7 +1342,7 @@ static void reject_cr(struct t3cdev *tdev, u32 hwtid, __be32 peer_ip,
1315 rpl->opt0l_status = htonl(CPL_PASS_OPEN_REJECT); 1342 rpl->opt0l_status = htonl(CPL_PASS_OPEN_REJECT);
1316 rpl->opt2 = 0; 1343 rpl->opt2 = 0;
1317 rpl->rsvd = rpl->opt2; 1344 rpl->rsvd = rpl->opt2;
1318 cxgb3_ofld_send(tdev, skb); 1345 iwch_cxgb3_ofld_send(tdev, skb);
1319 } 1346 }
1320} 1347}
1321 1348
@@ -1534,8 +1561,8 @@ static int peer_abort(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1534 * We get 2 peer aborts from the HW. The first one must 1561 * We get 2 peer aborts from the HW. The first one must
1535 * be ignored except for scribbling that we need one more. 1562 * be ignored except for scribbling that we need one more.
1536 */ 1563 */
1537 if (!(ep->flags & PEER_ABORT_IN_PROGRESS)) { 1564 if (!(ep->com.flags & PEER_ABORT_IN_PROGRESS)) {
1538 ep->flags |= PEER_ABORT_IN_PROGRESS; 1565 ep->com.flags |= PEER_ABORT_IN_PROGRESS;
1539 return CPL_RET_BUF_DONE; 1566 return CPL_RET_BUF_DONE;
1540 } 1567 }
1541 1568
@@ -1613,7 +1640,7 @@ static int peer_abort(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1613 rpl->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 1640 rpl->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
1614 OPCODE_TID(rpl) = htonl(MK_OPCODE_TID(CPL_ABORT_RPL, ep->hwtid)); 1641 OPCODE_TID(rpl) = htonl(MK_OPCODE_TID(CPL_ABORT_RPL, ep->hwtid));
1615 rpl->cmd = CPL_ABORT_NO_RST; 1642 rpl->cmd = CPL_ABORT_NO_RST;
1616 cxgb3_ofld_send(ep->com.tdev, rpl_skb); 1643 iwch_cxgb3_ofld_send(ep->com.tdev, rpl_skb);
1617out: 1644out:
1618 if (release) 1645 if (release)
1619 release_ep_resources(ep); 1646 release_ep_resources(ep);
@@ -1803,6 +1830,10 @@ int iwch_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
1803 ep->com.rpl_err = 0; 1830 ep->com.rpl_err = 0;
1804 ep->ird = conn_param->ird; 1831 ep->ird = conn_param->ird;
1805 ep->ord = conn_param->ord; 1832 ep->ord = conn_param->ord;
1833
1834 if (peer2peer && ep->ird == 0)
1835 ep->ird = 1;
1836
1806 PDBG("%s %d ird %d ord %d\n", __func__, __LINE__, ep->ird, ep->ord); 1837 PDBG("%s %d ird %d ord %d\n", __func__, __LINE__, ep->ird, ep->ord);
1807 1838
1808 get_ep(&ep->com); 1839 get_ep(&ep->com);
@@ -1888,6 +1919,10 @@ int iwch_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
1888 conn_param->private_data, ep->plen); 1919 conn_param->private_data, ep->plen);
1889 ep->ird = conn_param->ird; 1920 ep->ird = conn_param->ird;
1890 ep->ord = conn_param->ord; 1921 ep->ord = conn_param->ord;
1922
1923 if (peer2peer && ep->ord == 0)
1924 ep->ord = 1;
1925
1891 ep->com.tdev = h->rdev.t3cdev_p; 1926 ep->com.tdev = h->rdev.t3cdev_p;
1892 1927
1893 cm_id->add_ref(cm_id); 1928 cm_id->add_ref(cm_id);
@@ -2017,8 +2052,11 @@ int iwch_destroy_listen(struct iw_cm_id *cm_id)
2017 ep->com.rpl_done = 0; 2052 ep->com.rpl_done = 0;
2018 ep->com.rpl_err = 0; 2053 ep->com.rpl_err = 0;
2019 err = listen_stop(ep); 2054 err = listen_stop(ep);
2055 if (err)
2056 goto done;
2020 wait_event(ep->com.waitq, ep->com.rpl_done); 2057 wait_event(ep->com.waitq, ep->com.rpl_done);
2021 cxgb3_free_stid(ep->com.tdev, ep->stid); 2058 cxgb3_free_stid(ep->com.tdev, ep->stid);
2059done:
2022 err = ep->com.rpl_err; 2060 err = ep->com.rpl_err;
2023 cm_id->rem_ref(cm_id); 2061 cm_id->rem_ref(cm_id);
2024 put_ep(&ep->com); 2062 put_ep(&ep->com);
@@ -2030,12 +2068,22 @@ int iwch_ep_disconnect(struct iwch_ep *ep, int abrupt, gfp_t gfp)
2030 int ret=0; 2068 int ret=0;
2031 unsigned long flags; 2069 unsigned long flags;
2032 int close = 0; 2070 int close = 0;
2071 int fatal = 0;
2072 struct t3cdev *tdev;
2073 struct cxio_rdev *rdev;
2033 2074
2034 spin_lock_irqsave(&ep->com.lock, flags); 2075 spin_lock_irqsave(&ep->com.lock, flags);
2035 2076
2036 PDBG("%s ep %p state %s, abrupt %d\n", __func__, ep, 2077 PDBG("%s ep %p state %s, abrupt %d\n", __func__, ep,
2037 states[ep->com.state], abrupt); 2078 states[ep->com.state], abrupt);
2038 2079
2080 tdev = (struct t3cdev *)ep->com.tdev;
2081 rdev = (struct cxio_rdev *)tdev->ulp;
2082 if (cxio_fatal_error(rdev)) {
2083 fatal = 1;
2084 close_complete_upcall(ep);
2085 ep->com.state = DEAD;
2086 }
2039 switch (ep->com.state) { 2087 switch (ep->com.state) {
2040 case MPA_REQ_WAIT: 2088 case MPA_REQ_WAIT:
2041 case MPA_REQ_SENT: 2089 case MPA_REQ_SENT:
@@ -2075,7 +2123,11 @@ int iwch_ep_disconnect(struct iwch_ep *ep, int abrupt, gfp_t gfp)
2075 ret = send_abort(ep, NULL, gfp); 2123 ret = send_abort(ep, NULL, gfp);
2076 else 2124 else
2077 ret = send_halfclose(ep, gfp); 2125 ret = send_halfclose(ep, gfp);
2126 if (ret)
2127 fatal = 1;
2078 } 2128 }
2129 if (fatal)
2130 release_ep_resources(ep);
2079 return ret; 2131 return ret;
2080} 2132}
2081 2133
diff --git a/drivers/infiniband/hw/cxgb3/iwch_cm.h b/drivers/infiniband/hw/cxgb3/iwch_cm.h
index d7c7e09f0996..43c0aea7eadc 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_cm.h
+++ b/drivers/infiniband/hw/cxgb3/iwch_cm.h
@@ -147,6 +147,7 @@ enum iwch_ep_state {
147enum iwch_ep_flags { 147enum iwch_ep_flags {
148 PEER_ABORT_IN_PROGRESS = (1 << 0), 148 PEER_ABORT_IN_PROGRESS = (1 << 0),
149 ABORT_REQ_IN_PROGRESS = (1 << 1), 149 ABORT_REQ_IN_PROGRESS = (1 << 1),
150 RELEASE_RESOURCES = (1 << 2),
150}; 151};
151 152
152struct iwch_ep_common { 153struct iwch_ep_common {
@@ -161,6 +162,7 @@ struct iwch_ep_common {
161 wait_queue_head_t waitq; 162 wait_queue_head_t waitq;
162 int rpl_done; 163 int rpl_done;
163 int rpl_err; 164 int rpl_err;
165 u32 flags;
164}; 166};
165 167
166struct iwch_listen_ep { 168struct iwch_listen_ep {
@@ -188,7 +190,6 @@ struct iwch_ep {
188 u16 plen; 190 u16 plen;
189 u32 ird; 191 u32 ird;
190 u32 ord; 192 u32 ord;
191 u32 flags;
192}; 193};
193 194
194static inline struct iwch_ep *to_ep(struct iw_cm_id *cm_id) 195static inline struct iwch_ep *to_ep(struct iw_cm_id *cm_id)
diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c
index c758fbd58478..27bbdc8e773a 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_qp.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -751,7 +751,7 @@ int iwch_post_zb_read(struct iwch_qp *qhp)
751 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)| 751 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
752 V_FW_RIWR_LEN(flit_cnt)); 752 V_FW_RIWR_LEN(flit_cnt));
753 skb->priority = CPL_PRIORITY_DATA; 753 skb->priority = CPL_PRIORITY_DATA;
754 return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb); 754 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
755} 755}
756 756
757/* 757/*
@@ -783,7 +783,7 @@ int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
783 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG)); 783 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
784 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)); 784 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
785 skb->priority = CPL_PRIORITY_DATA; 785 skb->priority = CPL_PRIORITY_DATA;
786 return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb); 786 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
787} 787}
788 788
789/* 789/*
@@ -1069,7 +1069,6 @@ int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
1069 goto out; 1069 goto out;
1070 } 1070 }
1071 qhp->attr.state = IWCH_QP_STATE_IDLE; 1071 qhp->attr.state = IWCH_QP_STATE_IDLE;
1072 memset(&qhp->attr, 0, sizeof(qhp->attr));
1073 break; 1072 break;
1074 case IWCH_QP_STATE_TERMINATE: 1073 case IWCH_QP_STATE_TERMINATE:
1075 if (!internal) { 1074 if (!internal) {
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index 2ccb9d31771f..ae3d7590346e 100644
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -394,8 +394,7 @@ static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
394 PAGE_SIZE, vma->vm_page_prot)) 394 PAGE_SIZE, vma->vm_page_prot))
395 return -EAGAIN; 395 return -EAGAIN;
396 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 396 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
397 /* FIXME want pgprot_writecombine() for BlueFlame pages */ 397 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
398 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
399 398
400 if (io_remap_pfn_range(vma, vma->vm_start, 399 if (io_remap_pfn_range(vma, vma->vm_start,
401 to_mucontext(context)->uar.pfn + 400 to_mucontext(context)->uar.pfn +
diff --git a/drivers/infiniband/hw/mthca/mthca_cmd.c b/drivers/infiniband/hw/mthca/mthca_cmd.c
index c33e1c53c799..6d55f9d748f6 100644
--- a/drivers/infiniband/hw/mthca/mthca_cmd.c
+++ b/drivers/infiniband/hw/mthca/mthca_cmd.c
@@ -157,13 +157,15 @@ enum {
157enum { 157enum {
158 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, 158 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
159 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, 159 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
160 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1 160 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
161 CMD_TIME_CLASS_D = 60 * HZ
161}; 162};
162#else 163#else
163enum { 164enum {
164 CMD_TIME_CLASS_A = 60 * HZ, 165 CMD_TIME_CLASS_A = 60 * HZ,
165 CMD_TIME_CLASS_B = 60 * HZ, 166 CMD_TIME_CLASS_B = 60 * HZ,
166 CMD_TIME_CLASS_C = 60 * HZ 167 CMD_TIME_CLASS_C = 60 * HZ,
168 CMD_TIME_CLASS_D = 60 * HZ
167}; 169};
168#endif 170#endif
169 171
@@ -598,7 +600,7 @@ int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
598 u64 out; 600 u64 out;
599 int ret; 601 int ret;
600 602
601 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status); 603 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status);
602 604
603 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) 605 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
604 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " 606 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
@@ -611,7 +613,7 @@ int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
611 613
612int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) 614int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
613{ 615{
614 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status); 616 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
615} 617}
616 618
617static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, 619static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
@@ -1390,7 +1392,7 @@ int mthca_INIT_HCA(struct mthca_dev *dev,
1390 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); 1392 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1391 } 1393 }
1392 1394
1393 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status); 1395 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status);
1394 1396
1395 mthca_free_mailbox(dev, mailbox); 1397 mthca_free_mailbox(dev, mailbox);
1396 return err; 1398 return err;
@@ -1450,12 +1452,12 @@ int mthca_INIT_IB(struct mthca_dev *dev,
1450 1452
1451int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) 1453int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1452{ 1454{
1453 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status); 1455 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status);
1454} 1456}
1455 1457
1456int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) 1458int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1457{ 1459{
1458 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status); 1460 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status);
1459} 1461}
1460 1462
1461int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, 1463int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h
index 04b12ad23390..bf1720f7f35f 100644
--- a/drivers/infiniband/hw/nes/nes.h
+++ b/drivers/infiniband/hw/nes/nes.h
@@ -56,10 +56,8 @@
56 56
57#define QUEUE_DISCONNECTS 57#define QUEUE_DISCONNECTS
58 58
59#define DRV_BUILD "1"
60
61#define DRV_NAME "iw_nes" 59#define DRV_NAME "iw_nes"
62#define DRV_VERSION "1.0 KO Build " DRV_BUILD 60#define DRV_VERSION "1.5.0.0"
63#define PFX DRV_NAME ": " 61#define PFX DRV_NAME ": "
64 62
65/* 63/*
@@ -289,8 +287,8 @@ static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
289static inline void 287static inline void
290set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value) 288set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
291{ 289{
292 wqe_words[index] = cpu_to_le32((u32) ((unsigned long)value)); 290 wqe_words[index] = cpu_to_le32((u32) value);
293 wqe_words[index + 1] = cpu_to_le32((u32)(upper_32_bits((unsigned long)value))); 291 wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
294} 292}
295 293
296static inline void 294static inline void
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c
index 52425154acd4..11c7d6642014 100644
--- a/drivers/infiniband/hw/nes/nes_cm.c
+++ b/drivers/infiniband/hw/nes/nes_cm.c
@@ -56,6 +56,7 @@
56#include <net/neighbour.h> 56#include <net/neighbour.h>
57#include <net/route.h> 57#include <net/route.h>
58#include <net/ip_fib.h> 58#include <net/ip_fib.h>
59#include <net/tcp.h>
59 60
60#include "nes.h" 61#include "nes.h"
61 62
@@ -426,6 +427,7 @@ int schedule_nes_timer(struct nes_cm_node *cm_node, struct sk_buff *skb,
426 if (type == NES_TIMER_TYPE_CLOSE) { 427 if (type == NES_TIMER_TYPE_CLOSE) {
427 new_send->timetosend += (HZ/10); 428 new_send->timetosend += (HZ/10);
428 if (cm_node->recv_entry) { 429 if (cm_node->recv_entry) {
430 kfree(new_send);
429 WARN_ON(1); 431 WARN_ON(1);
430 return -EINVAL; 432 return -EINVAL;
431 } 433 }
@@ -445,8 +447,8 @@ int schedule_nes_timer(struct nes_cm_node *cm_node, struct sk_buff *skb,
445 if (ret != NETDEV_TX_OK) { 447 if (ret != NETDEV_TX_OK) {
446 nes_debug(NES_DBG_CM, "Error sending packet %p " 448 nes_debug(NES_DBG_CM, "Error sending packet %p "
447 "(jiffies = %lu)\n", new_send, jiffies); 449 "(jiffies = %lu)\n", new_send, jiffies);
448 atomic_dec(&new_send->skb->users);
449 new_send->timetosend = jiffies; 450 new_send->timetosend = jiffies;
451 ret = NETDEV_TX_OK;
450 } else { 452 } else {
451 cm_packets_sent++; 453 cm_packets_sent++;
452 if (!send_retrans) { 454 if (!send_retrans) {
@@ -539,6 +541,7 @@ static void nes_cm_timer_tick(unsigned long pass)
539 struct list_head *list_node; 541 struct list_head *list_node;
540 struct nes_cm_core *cm_core = g_cm_core; 542 struct nes_cm_core *cm_core = g_cm_core;
541 u32 settimer = 0; 543 u32 settimer = 0;
544 unsigned long timetosend;
542 int ret = NETDEV_TX_OK; 545 int ret = NETDEV_TX_OK;
543 546
544 struct list_head timer_list; 547 struct list_head timer_list;
@@ -630,7 +633,6 @@ static void nes_cm_timer_tick(unsigned long pass)
630 nes_debug(NES_DBG_CM, "rexmit failed for " 633 nes_debug(NES_DBG_CM, "rexmit failed for "
631 "node=%p\n", cm_node); 634 "node=%p\n", cm_node);
632 cm_packets_bounced++; 635 cm_packets_bounced++;
633 atomic_dec(&send_entry->skb->users);
634 send_entry->retrycount--; 636 send_entry->retrycount--;
635 nexttimeout = jiffies + NES_SHORT_TIME; 637 nexttimeout = jiffies + NES_SHORT_TIME;
636 settimer = 1; 638 settimer = 1;
@@ -644,8 +646,11 @@ static void nes_cm_timer_tick(unsigned long pass)
644 send_entry->retrycount); 646 send_entry->retrycount);
645 if (send_entry->send_retrans) { 647 if (send_entry->send_retrans) {
646 send_entry->retranscount--; 648 send_entry->retranscount--;
649 timetosend = (NES_RETRY_TIMEOUT <<
650 (NES_DEFAULT_RETRANS - send_entry->retranscount));
651
647 send_entry->timetosend = jiffies + 652 send_entry->timetosend = jiffies +
648 NES_RETRY_TIMEOUT; 653 min(timetosend, NES_MAX_TIMEOUT);
649 if (nexttimeout > send_entry->timetosend || 654 if (nexttimeout > send_entry->timetosend ||
650 !settimer) { 655 !settimer) {
651 nexttimeout = send_entry->timetosend; 656 nexttimeout = send_entry->timetosend;
@@ -666,11 +671,6 @@ static void nes_cm_timer_tick(unsigned long pass)
666 671
667 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); 672 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags);
668 rem_ref_cm_node(cm_node->cm_core, cm_node); 673 rem_ref_cm_node(cm_node->cm_core, cm_node);
669 if (ret != NETDEV_TX_OK) {
670 nes_debug(NES_DBG_CM, "rexmit failed for cm_node=%p\n",
671 cm_node);
672 break;
673 }
674 } 674 }
675 675
676 if (settimer) { 676 if (settimer) {
@@ -859,7 +859,6 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core,
859{ 859{
860 unsigned long flags; 860 unsigned long flags;
861 struct nes_cm_listener *listen_node; 861 struct nes_cm_listener *listen_node;
862 __be32 tmp_addr = cpu_to_be32(dst_addr);
863 862
864 /* walk list and find cm_node associated with this session ID */ 863 /* walk list and find cm_node associated with this session ID */
865 spin_lock_irqsave(&cm_core->listen_list_lock, flags); 864 spin_lock_irqsave(&cm_core->listen_list_lock, flags);
@@ -876,9 +875,6 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core,
876 } 875 }
877 spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); 876 spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);
878 877
879 nes_debug(NES_DBG_CM, "Unable to find listener for %pI4:%x\n",
880 &tmp_addr, dst_port);
881
882 /* no listener */ 878 /* no listener */
883 return NULL; 879 return NULL;
884} 880}
@@ -1262,7 +1258,6 @@ static int rem_ref_cm_node(struct nes_cm_core *cm_core,
1262 cm_node->nesqp = NULL; 1258 cm_node->nesqp = NULL;
1263 } 1259 }
1264 1260
1265 cm_node->freed = 1;
1266 kfree(cm_node); 1261 kfree(cm_node);
1267 return 0; 1262 return 0;
1268} 1263}
@@ -1331,18 +1326,20 @@ static void handle_fin_pkt(struct nes_cm_node *cm_node)
1331 nes_debug(NES_DBG_CM, "Received FIN, cm_node = %p, state = %u. " 1326 nes_debug(NES_DBG_CM, "Received FIN, cm_node = %p, state = %u. "
1332 "refcnt=%d\n", cm_node, cm_node->state, 1327 "refcnt=%d\n", cm_node, cm_node->state,
1333 atomic_read(&cm_node->ref_count)); 1328 atomic_read(&cm_node->ref_count));
1334 cm_node->tcp_cntxt.rcv_nxt++;
1335 cleanup_retrans_entry(cm_node);
1336 switch (cm_node->state) { 1329 switch (cm_node->state) {
1337 case NES_CM_STATE_SYN_RCVD: 1330 case NES_CM_STATE_SYN_RCVD:
1338 case NES_CM_STATE_SYN_SENT: 1331 case NES_CM_STATE_SYN_SENT:
1339 case NES_CM_STATE_ESTABLISHED: 1332 case NES_CM_STATE_ESTABLISHED:
1340 case NES_CM_STATE_MPAREQ_SENT: 1333 case NES_CM_STATE_MPAREQ_SENT:
1341 case NES_CM_STATE_MPAREJ_RCVD: 1334 case NES_CM_STATE_MPAREJ_RCVD:
1335 cm_node->tcp_cntxt.rcv_nxt++;
1336 cleanup_retrans_entry(cm_node);
1342 cm_node->state = NES_CM_STATE_LAST_ACK; 1337 cm_node->state = NES_CM_STATE_LAST_ACK;
1343 send_fin(cm_node, NULL); 1338 send_fin(cm_node, NULL);
1344 break; 1339 break;
1345 case NES_CM_STATE_FIN_WAIT1: 1340 case NES_CM_STATE_FIN_WAIT1:
1341 cm_node->tcp_cntxt.rcv_nxt++;
1342 cleanup_retrans_entry(cm_node);
1346 cm_node->state = NES_CM_STATE_CLOSING; 1343 cm_node->state = NES_CM_STATE_CLOSING;
1347 send_ack(cm_node, NULL); 1344 send_ack(cm_node, NULL);
1348 /* Wait for ACK as this is simultanous close.. 1345 /* Wait for ACK as this is simultanous close..
@@ -1350,11 +1347,15 @@ static void handle_fin_pkt(struct nes_cm_node *cm_node)
1350 * Just rm the node.. Done.. */ 1347 * Just rm the node.. Done.. */
1351 break; 1348 break;
1352 case NES_CM_STATE_FIN_WAIT2: 1349 case NES_CM_STATE_FIN_WAIT2:
1350 cm_node->tcp_cntxt.rcv_nxt++;
1351 cleanup_retrans_entry(cm_node);
1353 cm_node->state = NES_CM_STATE_TIME_WAIT; 1352 cm_node->state = NES_CM_STATE_TIME_WAIT;
1354 send_ack(cm_node, NULL); 1353 send_ack(cm_node, NULL);
1355 schedule_nes_timer(cm_node, NULL, NES_TIMER_TYPE_CLOSE, 1, 0); 1354 schedule_nes_timer(cm_node, NULL, NES_TIMER_TYPE_CLOSE, 1, 0);
1356 break; 1355 break;
1357 case NES_CM_STATE_TIME_WAIT: 1356 case NES_CM_STATE_TIME_WAIT:
1357 cm_node->tcp_cntxt.rcv_nxt++;
1358 cleanup_retrans_entry(cm_node);
1358 cm_node->state = NES_CM_STATE_CLOSED; 1359 cm_node->state = NES_CM_STATE_CLOSED;
1359 rem_ref_cm_node(cm_node->cm_core, cm_node); 1360 rem_ref_cm_node(cm_node->cm_core, cm_node);
1360 break; 1361 break;
@@ -1390,7 +1391,6 @@ static void handle_rst_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1390 passive_state = atomic_add_return(1, &cm_node->passive_state); 1391 passive_state = atomic_add_return(1, &cm_node->passive_state);
1391 if (passive_state == NES_SEND_RESET_EVENT) 1392 if (passive_state == NES_SEND_RESET_EVENT)
1392 create_event(cm_node, NES_CM_EVENT_RESET); 1393 create_event(cm_node, NES_CM_EVENT_RESET);
1393 cleanup_retrans_entry(cm_node);
1394 cm_node->state = NES_CM_STATE_CLOSED; 1394 cm_node->state = NES_CM_STATE_CLOSED;
1395 dev_kfree_skb_any(skb); 1395 dev_kfree_skb_any(skb);
1396 break; 1396 break;
@@ -1404,17 +1404,16 @@ static void handle_rst_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1404 active_open_err(cm_node, skb, reset); 1404 active_open_err(cm_node, skb, reset);
1405 break; 1405 break;
1406 case NES_CM_STATE_CLOSED: 1406 case NES_CM_STATE_CLOSED:
1407 cleanup_retrans_entry(cm_node);
1408 drop_packet(skb); 1407 drop_packet(skb);
1409 break; 1408 break;
1409 case NES_CM_STATE_LAST_ACK:
1410 cm_node->cm_id->rem_ref(cm_node->cm_id);
1410 case NES_CM_STATE_TIME_WAIT: 1411 case NES_CM_STATE_TIME_WAIT:
1411 cleanup_retrans_entry(cm_node);
1412 cm_node->state = NES_CM_STATE_CLOSED; 1412 cm_node->state = NES_CM_STATE_CLOSED;
1413 rem_ref_cm_node(cm_node->cm_core, cm_node); 1413 rem_ref_cm_node(cm_node->cm_core, cm_node);
1414 drop_packet(skb); 1414 drop_packet(skb);
1415 break; 1415 break;
1416 case NES_CM_STATE_FIN_WAIT1: 1416 case NES_CM_STATE_FIN_WAIT1:
1417 cleanup_retrans_entry(cm_node);
1418 nes_debug(NES_DBG_CM, "Bad state %s[%u]\n", __func__, __LINE__); 1417 nes_debug(NES_DBG_CM, "Bad state %s[%u]\n", __func__, __LINE__);
1419 default: 1418 default:
1420 drop_packet(skb); 1419 drop_packet(skb);
@@ -1461,6 +1460,7 @@ static void handle_rcv_mpa(struct nes_cm_node *cm_node, struct sk_buff *skb)
1461 NES_PASSIVE_STATE_INDICATED); 1460 NES_PASSIVE_STATE_INDICATED);
1462 break; 1461 break;
1463 case NES_CM_STATE_MPAREQ_SENT: 1462 case NES_CM_STATE_MPAREQ_SENT:
1463 cleanup_retrans_entry(cm_node);
1464 if (res_type == NES_MPA_REQUEST_REJECT) { 1464 if (res_type == NES_MPA_REQUEST_REJECT) {
1465 type = NES_CM_EVENT_MPA_REJECT; 1465 type = NES_CM_EVENT_MPA_REJECT;
1466 cm_node->state = NES_CM_STATE_MPAREJ_RCVD; 1466 cm_node->state = NES_CM_STATE_MPAREJ_RCVD;
@@ -1524,7 +1524,7 @@ static int check_seq(struct nes_cm_node *cm_node, struct tcphdr *tcph,
1524 rcv_wnd = cm_node->tcp_cntxt.rcv_wnd; 1524 rcv_wnd = cm_node->tcp_cntxt.rcv_wnd;
1525 if (ack_seq != loc_seq_num) 1525 if (ack_seq != loc_seq_num)
1526 err = 1; 1526 err = 1;
1527 else if ((seq + rcv_wnd) < rcv_nxt) 1527 else if (!between(seq, rcv_nxt, (rcv_nxt+rcv_wnd)))
1528 err = 1; 1528 err = 1;
1529 if (err) { 1529 if (err) {
1530 nes_debug(NES_DBG_CM, "%s[%u] create abort for cm_node=%p " 1530 nes_debug(NES_DBG_CM, "%s[%u] create abort for cm_node=%p "
@@ -1658,49 +1658,39 @@ static void handle_synack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1658 } 1658 }
1659} 1659}
1660 1660
1661static void handle_ack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb, 1661static int handle_ack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1662 struct tcphdr *tcph) 1662 struct tcphdr *tcph)
1663{ 1663{
1664 int datasize = 0; 1664 int datasize = 0;
1665 u32 inc_sequence; 1665 u32 inc_sequence;
1666 u32 rem_seq_ack; 1666 u32 rem_seq_ack;
1667 u32 rem_seq; 1667 u32 rem_seq;
1668 int ret; 1668 int ret = 0;
1669 int optionsize; 1669 int optionsize;
1670 optionsize = (tcph->doff << 2) - sizeof(struct tcphdr); 1670 optionsize = (tcph->doff << 2) - sizeof(struct tcphdr);
1671 1671
1672 if (check_seq(cm_node, tcph, skb)) 1672 if (check_seq(cm_node, tcph, skb))
1673 return; 1673 return -EINVAL;
1674 1674
1675 skb_pull(skb, tcph->doff << 2); 1675 skb_pull(skb, tcph->doff << 2);
1676 inc_sequence = ntohl(tcph->seq); 1676 inc_sequence = ntohl(tcph->seq);
1677 rem_seq = ntohl(tcph->seq); 1677 rem_seq = ntohl(tcph->seq);
1678 rem_seq_ack = ntohl(tcph->ack_seq); 1678 rem_seq_ack = ntohl(tcph->ack_seq);
1679 datasize = skb->len; 1679 datasize = skb->len;
1680 cleanup_retrans_entry(cm_node);
1681 switch (cm_node->state) { 1680 switch (cm_node->state) {
1682 case NES_CM_STATE_SYN_RCVD: 1681 case NES_CM_STATE_SYN_RCVD:
1683 /* Passive OPEN */ 1682 /* Passive OPEN */
1683 cleanup_retrans_entry(cm_node);
1684 ret = handle_tcp_options(cm_node, tcph, skb, optionsize, 1); 1684 ret = handle_tcp_options(cm_node, tcph, skb, optionsize, 1);
1685 if (ret) 1685 if (ret)
1686 break; 1686 break;
1687 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); 1687 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq);
1688 if (cm_node->tcp_cntxt.rem_ack_num !=
1689 cm_node->tcp_cntxt.loc_seq_num) {
1690 nes_debug(NES_DBG_CM, "rem_ack_num != loc_seq_num\n");
1691 cleanup_retrans_entry(cm_node);
1692 send_reset(cm_node, skb);
1693 return;
1694 }
1695 cm_node->state = NES_CM_STATE_ESTABLISHED; 1688 cm_node->state = NES_CM_STATE_ESTABLISHED;
1696 cleanup_retrans_entry(cm_node);
1697 if (datasize) { 1689 if (datasize) {
1698 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; 1690 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize;
1699 handle_rcv_mpa(cm_node, skb); 1691 handle_rcv_mpa(cm_node, skb);
1700 } else { /* rcvd ACK only */ 1692 } else /* rcvd ACK only */
1701 dev_kfree_skb_any(skb); 1693 dev_kfree_skb_any(skb);
1702 cleanup_retrans_entry(cm_node);
1703 }
1704 break; 1694 break;
1705 case NES_CM_STATE_ESTABLISHED: 1695 case NES_CM_STATE_ESTABLISHED:
1706 /* Passive OPEN */ 1696 /* Passive OPEN */
@@ -1712,15 +1702,12 @@ static void handle_ack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1712 drop_packet(skb); 1702 drop_packet(skb);
1713 break; 1703 break;
1714 case NES_CM_STATE_MPAREQ_SENT: 1704 case NES_CM_STATE_MPAREQ_SENT:
1715 cleanup_retrans_entry(cm_node);
1716 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); 1705 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq);
1717 if (datasize) { 1706 if (datasize) {
1718 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; 1707 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize;
1719 handle_rcv_mpa(cm_node, skb); 1708 handle_rcv_mpa(cm_node, skb);
1720 } else { /* Could be just an ack pkt.. */ 1709 } else /* Could be just an ack pkt.. */
1721 cleanup_retrans_entry(cm_node);
1722 dev_kfree_skb_any(skb); 1710 dev_kfree_skb_any(skb);
1723 }
1724 break; 1711 break;
1725 case NES_CM_STATE_LISTENING: 1712 case NES_CM_STATE_LISTENING:
1726 case NES_CM_STATE_CLOSED: 1713 case NES_CM_STATE_CLOSED:
@@ -1728,11 +1715,10 @@ static void handle_ack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1728 send_reset(cm_node, skb); 1715 send_reset(cm_node, skb);
1729 break; 1716 break;
1730 case NES_CM_STATE_LAST_ACK: 1717 case NES_CM_STATE_LAST_ACK:
1718 case NES_CM_STATE_CLOSING:
1731 cleanup_retrans_entry(cm_node); 1719 cleanup_retrans_entry(cm_node);
1732 cm_node->state = NES_CM_STATE_CLOSED; 1720 cm_node->state = NES_CM_STATE_CLOSED;
1733 cm_node->cm_id->rem_ref(cm_node->cm_id); 1721 cm_node->cm_id->rem_ref(cm_node->cm_id);
1734 case NES_CM_STATE_CLOSING:
1735 cleanup_retrans_entry(cm_node);
1736 rem_ref_cm_node(cm_node->cm_core, cm_node); 1722 rem_ref_cm_node(cm_node->cm_core, cm_node);
1737 drop_packet(skb); 1723 drop_packet(skb);
1738 break; 1724 break;
@@ -1747,9 +1733,11 @@ static void handle_ack_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1747 case NES_CM_STATE_MPAREQ_RCVD: 1733 case NES_CM_STATE_MPAREQ_RCVD:
1748 case NES_CM_STATE_UNKNOWN: 1734 case NES_CM_STATE_UNKNOWN:
1749 default: 1735 default:
1736 cleanup_retrans_entry(cm_node);
1750 drop_packet(skb); 1737 drop_packet(skb);
1751 break; 1738 break;
1752 } 1739 }
1740 return ret;
1753} 1741}
1754 1742
1755 1743
@@ -1855,6 +1843,7 @@ static void process_packet(struct nes_cm_node *cm_node, struct sk_buff *skb,
1855 enum nes_tcpip_pkt_type pkt_type = NES_PKT_TYPE_UNKNOWN; 1843 enum nes_tcpip_pkt_type pkt_type = NES_PKT_TYPE_UNKNOWN;
1856 struct tcphdr *tcph = tcp_hdr(skb); 1844 struct tcphdr *tcph = tcp_hdr(skb);
1857 u32 fin_set = 0; 1845 u32 fin_set = 0;
1846 int ret = 0;
1858 skb_pull(skb, ip_hdr(skb)->ihl << 2); 1847 skb_pull(skb, ip_hdr(skb)->ihl << 2);
1859 1848
1860 nes_debug(NES_DBG_CM, "process_packet: cm_node=%p state =%d syn=%d " 1849 nes_debug(NES_DBG_CM, "process_packet: cm_node=%p state =%d syn=%d "
@@ -1880,17 +1869,17 @@ static void process_packet(struct nes_cm_node *cm_node, struct sk_buff *skb,
1880 handle_synack_pkt(cm_node, skb, tcph); 1869 handle_synack_pkt(cm_node, skb, tcph);
1881 break; 1870 break;
1882 case NES_PKT_TYPE_ACK: 1871 case NES_PKT_TYPE_ACK:
1883 handle_ack_pkt(cm_node, skb, tcph); 1872 ret = handle_ack_pkt(cm_node, skb, tcph);
1884 if (fin_set) 1873 if (fin_set && !ret)
1885 handle_fin_pkt(cm_node); 1874 handle_fin_pkt(cm_node);
1886 break; 1875 break;
1887 case NES_PKT_TYPE_RST: 1876 case NES_PKT_TYPE_RST:
1888 handle_rst_pkt(cm_node, skb, tcph); 1877 handle_rst_pkt(cm_node, skb, tcph);
1889 break; 1878 break;
1890 default: 1879 default:
1891 drop_packet(skb); 1880 if ((fin_set) && (!check_seq(cm_node, tcph, skb)))
1892 if (fin_set)
1893 handle_fin_pkt(cm_node); 1881 handle_fin_pkt(cm_node);
1882 drop_packet(skb);
1894 break; 1883 break;
1895 } 1884 }
1896} 1885}
@@ -1999,13 +1988,17 @@ static struct nes_cm_node *mini_cm_connect(struct nes_cm_core *cm_core,
1999 if (loopbackremotelistener == NULL) { 1988 if (loopbackremotelistener == NULL) {
2000 create_event(cm_node, NES_CM_EVENT_ABORTED); 1989 create_event(cm_node, NES_CM_EVENT_ABORTED);
2001 } else { 1990 } else {
2002 atomic_inc(&cm_loopbacks);
2003 loopback_cm_info = *cm_info; 1991 loopback_cm_info = *cm_info;
2004 loopback_cm_info.loc_port = cm_info->rem_port; 1992 loopback_cm_info.loc_port = cm_info->rem_port;
2005 loopback_cm_info.rem_port = cm_info->loc_port; 1993 loopback_cm_info.rem_port = cm_info->loc_port;
2006 loopback_cm_info.cm_id = loopbackremotelistener->cm_id; 1994 loopback_cm_info.cm_id = loopbackremotelistener->cm_id;
2007 loopbackremotenode = make_cm_node(cm_core, nesvnic, 1995 loopbackremotenode = make_cm_node(cm_core, nesvnic,
2008 &loopback_cm_info, loopbackremotelistener); 1996 &loopback_cm_info, loopbackremotelistener);
1997 if (!loopbackremotenode) {
1998 rem_ref_cm_node(cm_node->cm_core, cm_node);
1999 return NULL;
2000 }
2001 atomic_inc(&cm_loopbacks);
2009 loopbackremotenode->loopbackpartner = cm_node; 2002 loopbackremotenode->loopbackpartner = cm_node;
2010 loopbackremotenode->tcp_cntxt.rcv_wscale = 2003 loopbackremotenode->tcp_cntxt.rcv_wscale =
2011 NES_CM_DEFAULT_RCV_WND_SCALE; 2004 NES_CM_DEFAULT_RCV_WND_SCALE;
@@ -2690,6 +2683,7 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2690 struct ib_mr *ibmr = NULL; 2683 struct ib_mr *ibmr = NULL;
2691 struct ib_phys_buf ibphysbuf; 2684 struct ib_phys_buf ibphysbuf;
2692 struct nes_pd *nespd; 2685 struct nes_pd *nespd;
2686 u64 tagged_offset;
2693 2687
2694 2688
2695 2689
@@ -2711,7 +2705,6 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2711 /* associate the node with the QP */ 2705 /* associate the node with the QP */
2712 nesqp->cm_node = (void *)cm_node; 2706 nesqp->cm_node = (void *)cm_node;
2713 cm_node->nesqp = nesqp; 2707 cm_node->nesqp = nesqp;
2714 nes_add_ref(&nesqp->ibqp);
2715 2708
2716 nes_debug(NES_DBG_CM, "QP%u, cm_node=%p, jiffies = %lu listener = %p\n", 2709 nes_debug(NES_DBG_CM, "QP%u, cm_node=%p, jiffies = %lu listener = %p\n",
2717 nesqp->hwqp.qp_id, cm_node, jiffies, cm_node->listener); 2710 nesqp->hwqp.qp_id, cm_node, jiffies, cm_node->listener);
@@ -2755,14 +2748,18 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2755 ibphysbuf.addr = nesqp->ietf_frame_pbase; 2748 ibphysbuf.addr = nesqp->ietf_frame_pbase;
2756 ibphysbuf.size = conn_param->private_data_len + 2749 ibphysbuf.size = conn_param->private_data_len +
2757 sizeof(struct ietf_mpa_frame); 2750 sizeof(struct ietf_mpa_frame);
2751 tagged_offset = (u64)(unsigned long)nesqp->ietf_frame;
2758 ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd, 2752 ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd,
2759 &ibphysbuf, 1, 2753 &ibphysbuf, 1,
2760 IB_ACCESS_LOCAL_WRITE, 2754 IB_ACCESS_LOCAL_WRITE,
2761 (u64 *)&nesqp->ietf_frame); 2755 &tagged_offset);
2762 if (!ibmr) { 2756 if (!ibmr) {
2763 nes_debug(NES_DBG_CM, "Unable to register memory region" 2757 nes_debug(NES_DBG_CM, "Unable to register memory region"
2764 "for lSMM for cm_node = %p \n", 2758 "for lSMM for cm_node = %p \n",
2765 cm_node); 2759 cm_node);
2760 pci_free_consistent(nesdev->pcidev,
2761 nesqp->private_data_len+sizeof(struct ietf_mpa_frame),
2762 nesqp->ietf_frame, nesqp->ietf_frame_pbase);
2766 return -ENOMEM; 2763 return -ENOMEM;
2767 } 2764 }
2768 2765
@@ -2782,7 +2779,7 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2782 sizeof(struct ietf_mpa_frame)); 2779 sizeof(struct ietf_mpa_frame));
2783 set_wqe_64bit_value(wqe->wqe_words, 2780 set_wqe_64bit_value(wqe->wqe_words,
2784 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX, 2781 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX,
2785 (u64)nesqp->ietf_frame); 2782 (u64)(unsigned long)nesqp->ietf_frame);
2786 wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] = 2783 wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] =
2787 cpu_to_le32(conn_param->private_data_len + 2784 cpu_to_le32(conn_param->private_data_len +
2788 sizeof(struct ietf_mpa_frame)); 2785 sizeof(struct ietf_mpa_frame));
@@ -2879,6 +2876,7 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2879 2876
2880 /* notify OF layer that accept event was successful */ 2877 /* notify OF layer that accept event was successful */
2881 cm_id->add_ref(cm_id); 2878 cm_id->add_ref(cm_id);
2879 nes_add_ref(&nesqp->ibqp);
2882 2880
2883 cm_event.event = IW_CM_EVENT_ESTABLISHED; 2881 cm_event.event = IW_CM_EVENT_ESTABLISHED;
2884 cm_event.status = IW_CM_EVENT_STATUS_ACCEPTED; 2882 cm_event.status = IW_CM_EVENT_STATUS_ACCEPTED;
@@ -2959,6 +2957,7 @@ int nes_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2959 struct nes_device *nesdev; 2957 struct nes_device *nesdev;
2960 struct nes_cm_node *cm_node; 2958 struct nes_cm_node *cm_node;
2961 struct nes_cm_info cm_info; 2959 struct nes_cm_info cm_info;
2960 int apbvt_set = 0;
2962 2961
2963 ibqp = nes_get_qp(cm_id->device, conn_param->qpn); 2962 ibqp = nes_get_qp(cm_id->device, conn_param->qpn);
2964 if (!ibqp) 2963 if (!ibqp)
@@ -2996,9 +2995,11 @@ int nes_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2996 conn_param->private_data_len); 2995 conn_param->private_data_len);
2997 2996
2998 if (cm_id->local_addr.sin_addr.s_addr != 2997 if (cm_id->local_addr.sin_addr.s_addr !=
2999 cm_id->remote_addr.sin_addr.s_addr) 2998 cm_id->remote_addr.sin_addr.s_addr) {
3000 nes_manage_apbvt(nesvnic, ntohs(cm_id->local_addr.sin_port), 2999 nes_manage_apbvt(nesvnic, ntohs(cm_id->local_addr.sin_port),
3001 PCI_FUNC(nesdev->pcidev->devfn), NES_MANAGE_APBVT_ADD); 3000 PCI_FUNC(nesdev->pcidev->devfn), NES_MANAGE_APBVT_ADD);
3001 apbvt_set = 1;
3002 }
3002 3003
3003 /* set up the connection params for the node */ 3004 /* set up the connection params for the node */
3004 cm_info.loc_addr = htonl(cm_id->local_addr.sin_addr.s_addr); 3005 cm_info.loc_addr = htonl(cm_id->local_addr.sin_addr.s_addr);
@@ -3015,8 +3016,7 @@ int nes_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3015 conn_param->private_data_len, (void *)conn_param->private_data, 3016 conn_param->private_data_len, (void *)conn_param->private_data,
3016 &cm_info); 3017 &cm_info);
3017 if (!cm_node) { 3018 if (!cm_node) {
3018 if (cm_id->local_addr.sin_addr.s_addr != 3019 if (apbvt_set)
3019 cm_id->remote_addr.sin_addr.s_addr)
3020 nes_manage_apbvt(nesvnic, ntohs(cm_id->local_addr.sin_port), 3020 nes_manage_apbvt(nesvnic, ntohs(cm_id->local_addr.sin_port),
3021 PCI_FUNC(nesdev->pcidev->devfn), 3021 PCI_FUNC(nesdev->pcidev->devfn),
3022 NES_MANAGE_APBVT_DEL); 3022 NES_MANAGE_APBVT_DEL);
@@ -3025,7 +3025,7 @@ int nes_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3025 return -ENOMEM; 3025 return -ENOMEM;
3026 } 3026 }
3027 3027
3028 cm_node->apbvt_set = 1; 3028 cm_node->apbvt_set = apbvt_set;
3029 nesqp->cm_node = cm_node; 3029 nesqp->cm_node = cm_node;
3030 cm_node->nesqp = nesqp; 3030 cm_node->nesqp = nesqp;
3031 nes_add_ref(&nesqp->ibqp); 3031 nes_add_ref(&nesqp->ibqp);
diff --git a/drivers/infiniband/hw/nes/nes_cm.h b/drivers/infiniband/hw/nes/nes_cm.h
index d5f778202eb7..8b7e7c0e496e 100644
--- a/drivers/infiniband/hw/nes/nes_cm.h
+++ b/drivers/infiniband/hw/nes/nes_cm.h
@@ -149,6 +149,7 @@ struct nes_timer_entry {
149#endif 149#endif
150#define NES_SHORT_TIME (10) 150#define NES_SHORT_TIME (10)
151#define NES_LONG_TIME (2000*HZ/1000) 151#define NES_LONG_TIME (2000*HZ/1000)
152#define NES_MAX_TIMEOUT ((unsigned long) (12*HZ))
152 153
153#define NES_CM_HASHTABLE_SIZE 1024 154#define NES_CM_HASHTABLE_SIZE 1024
154#define NES_CM_TCP_TIMER_INTERVAL 3000 155#define NES_CM_TCP_TIMER_INTERVAL 3000
@@ -298,7 +299,6 @@ struct nes_cm_node {
298 struct nes_vnic *nesvnic; 299 struct nes_vnic *nesvnic;
299 int apbvt_set; 300 int apbvt_set;
300 int accept_pend; 301 int accept_pend;
301 int freed;
302 struct list_head timer_entry; 302 struct list_head timer_entry;
303 struct list_head reset_entry; 303 struct list_head reset_entry;
304 struct nes_qp *nesqp; 304 struct nes_qp *nesqp;
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index 52e734042b8e..b832a7b814a2 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -46,6 +46,10 @@ static unsigned int nes_lro_max_aggr = NES_LRO_MAX_AGGR;
46module_param(nes_lro_max_aggr, uint, 0444); 46module_param(nes_lro_max_aggr, uint, 0444);
47MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation"); 47MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation");
48 48
49static int wide_ppm_offset;
50module_param(wide_ppm_offset, int, 0644);
51MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
52
49static u32 crit_err_count; 53static u32 crit_err_count;
50u32 int_mod_timer_init; 54u32 int_mod_timer_init;
51u32 int_mod_cq_depth_256; 55u32 int_mod_cq_depth_256;
@@ -547,7 +551,7 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
547 } 551 }
548 if (int_cnt > 1) { 552 if (int_cnt > 1) {
549 spin_lock_irqsave(&nesadapter->phy_lock, flags); 553 spin_lock_irqsave(&nesadapter->phy_lock, flags);
550 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088); 554 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
551 mh_detected++; 555 mh_detected++;
552 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET); 556 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
553 reset_value |= 0x0000003d; 557 reset_value |= 0x0000003d;
@@ -572,7 +576,7 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
572 if (++ext_cnt > int_cnt) { 576 if (++ext_cnt > int_cnt) {
573 spin_lock_irqsave(&nesadapter->phy_lock, flags); 577 spin_lock_irqsave(&nesadapter->phy_lock, flags);
574 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 578 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
575 0x0000F0C8); 579 0x0000F088);
576 mh_detected++; 580 mh_detected++;
577 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET); 581 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
578 reset_value |= 0x0000003d; 582 reset_value |= 0x0000003d;
@@ -736,38 +740,50 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
736{ 740{
737 int i; 741 int i;
738 u32 u32temp; 742 u32 u32temp;
739 u32 serdes_common_control; 743 u32 sds;
740 744
741 if (hw_rev != NE020_REV) { 745 if (hw_rev != NE020_REV) {
742 /* init serdes 0 */ 746 /* init serdes 0 */
747 if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4))
748 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
749 else
750 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
743 751
744 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
745 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { 752 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
746 serdes_common_control = nes_read_indexed(nesdev, 753 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
747 NES_IDX_ETH_SERDES_COMMON_CONTROL0); 754 sds |= 0x00000100;
748 serdes_common_control |= 0x000000100; 755 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
749 nes_write_indexed(nesdev,
750 NES_IDX_ETH_SERDES_COMMON_CONTROL0,
751 serdes_common_control);
752 } else if (!OneG_Mode) {
753 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
754 } 756 }
755 if (((port_count > 1) && 757 if (!OneG_Mode)
756 (nesadapter->phy_type[0] != NES_PHY_TYPE_PUMA_1G)) || 758 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
757 ((port_count > 2) && 759
758 (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) { 760 if (port_count < 2)
759 /* init serdes 1 */ 761 return 0;
762
763 /* init serdes 1 */
764 if (!(OneG_Mode && (nesadapter->phy_type[1] != NES_PHY_TYPE_PUMA_1G)))
760 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF); 765 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
761 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { 766
762 serdes_common_control = nes_read_indexed(nesdev, 767 switch (nesadapter->phy_type[1]) {
763 NES_IDX_ETH_SERDES_COMMON_CONTROL1); 768 case NES_PHY_TYPE_ARGUS:
764 serdes_common_control |= 0x000000100; 769 case NES_PHY_TYPE_SFP_D:
765 nes_write_indexed(nesdev, 770 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
766 NES_IDX_ETH_SERDES_COMMON_CONTROL1, 771 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
767 serdes_common_control); 772 break;
768 } else if (!OneG_Mode) { 773 case NES_PHY_TYPE_CX4:
769 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000); 774 if (wide_ppm_offset)
770 } 775 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
776 break;
777 case NES_PHY_TYPE_PUMA_1G:
778 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
779 sds |= 0x000000100;
780 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
781 }
782 if (!OneG_Mode) {
783 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
784 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
785 sds &= 0xFFFFFFBF;
786 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
771 } 787 }
772 } else { 788 } else {
773 /* init serdes 0 */ 789 /* init serdes 0 */
@@ -896,6 +912,12 @@ static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_cou
896 u32temp &= 0x7fffffff; 912 u32temp &= 0x7fffffff;
897 u32temp |= 0x7fff0010; 913 u32temp |= 0x7fff0010;
898 nes_write_indexed(nesdev, 0x000021f8, u32temp); 914 nes_write_indexed(nesdev, 0x000021f8, u32temp);
915 if (port_count > 1) {
916 u32temp = nes_read_indexed(nesdev, 0x000023f8);
917 u32temp &= 0x7fffffff;
918 u32temp |= 0x7fff0010;
919 nes_write_indexed(nesdev, 0x000023f8, u32temp);
920 }
899 } 921 }
900} 922}
901 923
@@ -1259,203 +1281,163 @@ int nes_init_phy(struct nes_device *nesdev)
1259{ 1281{
1260 struct nes_adapter *nesadapter = nesdev->nesadapter; 1282 struct nes_adapter *nesadapter = nesdev->nesadapter;
1261 u32 counter = 0; 1283 u32 counter = 0;
1262 u32 sds_common_control0; 1284 u32 sds;
1263 u32 mac_index = nesdev->mac_index; 1285 u32 mac_index = nesdev->mac_index;
1264 u32 tx_config = 0; 1286 u32 tx_config = 0;
1265 u16 phy_data; 1287 u16 phy_data;
1266 u32 temp_phy_data = 0; 1288 u32 temp_phy_data = 0;
1267 u32 temp_phy_data2 = 0; 1289 u32 temp_phy_data2 = 0;
1268 u32 i = 0; 1290 u8 phy_type = nesadapter->phy_type[mac_index];
1291 u8 phy_index = nesadapter->phy_index[mac_index];
1269 1292
1270 if ((nesadapter->OneG_Mode) && 1293 if ((nesadapter->OneG_Mode) &&
1271 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) { 1294 (phy_type != NES_PHY_TYPE_PUMA_1G)) {
1272 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); 1295 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
1273 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) { 1296 if (phy_type == NES_PHY_TYPE_1G) {
1274 printk(PFX "%s: Programming mdc config for 1G\n", __func__);
1275 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); 1297 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1276 tx_config &= 0xFFFFFFE3; 1298 tx_config &= 0xFFFFFFE3;
1277 tx_config |= 0x04; 1299 tx_config |= 0x04;
1278 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); 1300 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1279 } 1301 }
1280 1302
1281 nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data); 1303 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1282 nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n", 1304 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
1283 nesadapter->phy_index[mac_index], phy_data);
1284 nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
1285 1305
1286 /* Reset the PHY */ 1306 /* Reset the PHY */
1287 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], 0x8000); 1307 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1288 udelay(100); 1308 udelay(100);
1289 counter = 0; 1309 counter = 0;
1290 do { 1310 do {
1291 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1311 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1292 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1312 if (counter++ > 100)
1293 if (counter++ > 100) break; 1313 break;
1294 } while (phy_data & 0x8000); 1314 } while (phy_data & 0x8000);
1295 1315
1296 /* Setting no phy loopback */ 1316 /* Setting no phy loopback */
1297 phy_data &= 0xbfff; 1317 phy_data &= 0xbfff;
1298 phy_data |= 0x1140; 1318 phy_data |= 0x1140;
1299 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data); 1319 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1300 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1320 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1301 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1321 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1302 1322 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1303 nes_read_1G_phy_reg(nesdev, 0x17, nesadapter->phy_index[mac_index], &phy_data);
1304 nes_debug(NES_DBG_PHY, "Phy data from register 0x17 = 0x%X.\n", phy_data);
1305
1306 nes_read_1G_phy_reg(nesdev, 0x1e, nesadapter->phy_index[mac_index], &phy_data);
1307 nes_debug(NES_DBG_PHY, "Phy data from register 0x1e = 0x%X.\n", phy_data);
1308 1323
1309 /* Setting the interrupt mask */ 1324 /* Setting the interrupt mask */
1310 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data); 1325 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1311 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data); 1326 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1312 nes_write_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], 0xffee); 1327 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1313
1314 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
1315 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
1316 1328
1317 /* turning on flow control */ 1329 /* turning on flow control */
1318 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data); 1330 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1319 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data); 1331 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1320 nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], 1332 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1321 (phy_data & ~(0x03E0)) | 0xc00);
1322 /* nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
1323 phy_data | 0xc00); */
1324 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
1325 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
1326
1327 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1328 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1329 /* Clear Half duplex */
1330 nes_write_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index],
1331 phy_data & ~(0x0100));
1332 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1333 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1334 1333
1335 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1334 /* Clear Half duplex */
1336 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300); 1335 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1337 } else { 1336 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1338 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) || 1337 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1339 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1340 /* setup 10G MDIO operation */
1341 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1342 tx_config &= 0xFFFFFFE3;
1343 tx_config |= 0x15;
1344 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1345 }
1346 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1347 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1348
1349 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1350 mdelay(10);
1351 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1352 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1353 1338
1354 /* 1339 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1355 * if firmware is already running (like from a 1340 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1356 * driver un-load/load, don't do anything.
1357 */
1358 if (temp_phy_data == temp_phy_data2) {
1359 /* configure QT2505 AMCC PHY */
1360 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0x0000, 0x8000);
1361 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0000);
1362 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc302, 0x0044);
1363 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc318, 0x0052);
1364 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc319, 0x0008);
1365 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc31a, 0x0098);
1366 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0026, 0x0E00);
1367 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0027, 0x0001);
1368 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0028, 0xA528);
1369 1341
1370 /* 1342 return 0;
1371 * remove micro from reset; chip boots from ROM, 1343 }
1372 * uploads EEPROM f/w image, uC executes f/w
1373 */
1374 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0002);
1375 1344
1376 /* 1345 if ((phy_type == NES_PHY_TYPE_IRIS) ||
1377 * wait for heart beat to start to 1346 (phy_type == NES_PHY_TYPE_ARGUS) ||
1378 * know loading is done 1347 (phy_type == NES_PHY_TYPE_SFP_D)) {
1379 */ 1348 /* setup 10G MDIO operation */
1380 counter = 0; 1349 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1381 do { 1350 tx_config &= 0xFFFFFFE3;
1382 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee); 1351 tx_config |= 0x15;
1383 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1352 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1384 if (counter++ > 1000) { 1353 }
1385 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from heartbeat check <this is bad!!!> \n"); 1354 if ((phy_type == NES_PHY_TYPE_ARGUS) ||
1386 break; 1355 (phy_type == NES_PHY_TYPE_SFP_D)) {
1387 } 1356 /* Check firmware heartbeat */
1388 mdelay(100); 1357 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1389 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee); 1358 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1390 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1359 udelay(1500);
1391 } while ((temp_phy_data2 == temp_phy_data)); 1360 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1361 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1362
1363 if (temp_phy_data != temp_phy_data2)
1364 return 0;
1392 1365
1393 /* 1366 /* no heartbeat, configure the PHY */
1394 * wait for tracking to start to know 1367 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1395 * f/w is good to go 1368 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1396 */ 1369 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1397 counter = 0; 1370 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1398 do { 1371 if (phy_type == NES_PHY_TYPE_ARGUS) {
1399 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7fd); 1372 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1400 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1373 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1401 if (counter++ > 1000) { 1374 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1402 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from status check <this is bad!!!> \n"); 1375 } else {
1403 break; 1376 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1404 } 1377 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1405 mdelay(1000); 1378 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1406 /* 1379 }
1407 * nes_debug(NES_DBG_PHY, "AMCC PHY- phy_status not ready yet = 0x%02X\n", 1380 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1408 * temp_phy_data); 1381 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1409 */
1410 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1411
1412 /* set LOS Control invert RXLOSB_I_PADINV */
1413 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd003, 0x0000);
1414 /* set LOS Control to mask of RXLOSB_I */
1415 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc314, 0x0042);
1416 /* set LED1 to input mode (LED1 and LED2 share same LED) */
1417 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd006, 0x0007);
1418 /* set LED2 to RX link_status and activity */
1419 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd007, 0x000A);
1420 /* set LED3 to RX link_status */
1421 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd008, 0x0009);
1422 1382
1423 /* 1383 /* setup LEDs */
1424 * reset the res-calibration on t2 1384 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1425 * serdes; ensures it is stable after 1385 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1426 * the amcc phy is stable 1386 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1427 */
1428 1387
1429 sds_common_control0 = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); 1388 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
1430 sds_common_control0 |= 0x1;
1431 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1432 1389
1433 /* release the res-calibration reset */ 1390 /* Bring PHY out of reset */
1434 sds_common_control0 &= 0xfffffffe; 1391 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
1435 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1436 1392
1437 i = 0; 1393 /* Check for heartbeat */
1438 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) 1394 counter = 0;
1439 && (i++ < 5000)) { 1395 mdelay(690);
1440 /* mdelay(1); */ 1396 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1441 } 1397 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1398 do {
1399 if (counter++ > 150) {
1400 nes_debug(NES_DBG_PHY, "No PHY heartbeat\n");
1401 break;
1402 }
1403 mdelay(1);
1404 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1405 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1406 } while ((temp_phy_data2 == temp_phy_data));
1442 1407
1443 /* 1408 /* wait for tracking */
1444 * wait for link train done before moving on, 1409 counter = 0;
1445 * or will get an interupt storm 1410 do {
1446 */ 1411 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1447 counter = 0; 1412 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1448 do { 1413 if (counter++ > 300) {
1449 temp_phy_data = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 1414 nes_debug(NES_DBG_PHY, "PHY did not track\n");
1450 (0x200 * (nesdev->mac_index & 1))); 1415 break;
1451 if (counter++ > 1000) {
1452 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from link train wait <this is bad, link didnt train!!!>\n");
1453 break;
1454 }
1455 mdelay(1);
1456 } while (((temp_phy_data & 0x0f1f0000) != 0x0f0f0000));
1457 } 1416 }
1458 } 1417 mdelay(10);
1418 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1419
1420 /* setup signal integrity */
1421 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1422 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1423 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1424 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1425 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
1426
1427 /* reset serdes */
1428 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1429 mac_index * 0x200);
1430 sds |= 0x1;
1431 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1432 mac_index * 0x200, sds);
1433 sds &= 0xfffffffe;
1434 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1435 mac_index * 0x200, sds);
1436
1437 counter = 0;
1438 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1439 && (counter++ < 5000))
1440 ;
1459 } 1441 }
1460 return 0; 1442 return 0;
1461} 1443}
@@ -2359,6 +2341,7 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2359 u16 temp_phy_data; 2341 u16 temp_phy_data;
2360 u32 pcs_val = 0x0f0f0000; 2342 u32 pcs_val = 0x0f0f0000;
2361 u32 pcs_mask = 0x0f1f0000; 2343 u32 pcs_mask = 0x0f1f0000;
2344 u32 cdr_ctrl;
2362 2345
2363 spin_lock_irqsave(&nesadapter->phy_lock, flags); 2346 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2364 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) { 2347 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
@@ -2473,6 +2456,7 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2473 break; 2456 break;
2474 2457
2475 case NES_PHY_TYPE_ARGUS: 2458 case NES_PHY_TYPE_ARGUS:
2459 case NES_PHY_TYPE_SFP_D:
2476 /* clear the alarms */ 2460 /* clear the alarms */
2477 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); 2461 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008);
2478 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); 2462 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001);
@@ -2483,19 +2467,18 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2483 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004); 2467 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2484 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005); 2468 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2485 /* check link status */ 2469 /* check link status */
2486 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); 2470 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2487 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2471 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2488 u32temp = 100;
2489 do {
2490 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1);
2491 2472
2492 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2473 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2493 if ((phy_data == temp_phy_data) || (!(--u32temp))) 2474 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2494 break; 2475 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2495 temp_phy_data = phy_data; 2476 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2496 } while (1); 2477
2478 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2479
2497 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n", 2480 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2498 __func__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP"); 2481 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2499 break; 2482 break;
2500 2483
2501 case NES_PHY_TYPE_PUMA_1G: 2484 case NES_PHY_TYPE_PUMA_1G:
@@ -2511,6 +2494,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2511 } 2494 }
2512 2495
2513 if (phy_data & 0x0004) { 2496 if (phy_data & 0x0004) {
2497 if (wide_ppm_offset &&
2498 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2499 (nesadapter->hw_rev != NE020_REV)) {
2500 cdr_ctrl = nes_read_indexed(nesdev,
2501 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2502 mac_index * 0x200);
2503 nes_write_indexed(nesdev,
2504 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2505 mac_index * 0x200,
2506 cdr_ctrl | 0x000F0000);
2507 }
2514 nesadapter->mac_link_down[mac_index] = 0; 2508 nesadapter->mac_link_down[mac_index] = 0;
2515 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) { 2509 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2516 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n", 2510 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
@@ -2525,6 +2519,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2525 } 2519 }
2526 } 2520 }
2527 } else { 2521 } else {
2522 if (wide_ppm_offset &&
2523 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2524 (nesadapter->hw_rev != NE020_REV)) {
2525 cdr_ctrl = nes_read_indexed(nesdev,
2526 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2527 mac_index * 0x200);
2528 nes_write_indexed(nesdev,
2529 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2530 mac_index * 0x200,
2531 cdr_ctrl & 0xFFF0FFFF);
2532 }
2528 nesadapter->mac_link_down[mac_index] = 1; 2533 nesadapter->mac_link_down[mac_index] = 1;
2529 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) { 2534 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2530 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n", 2535 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index f41a8710d2a8..c3654c6383fe 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -35,12 +35,14 @@
35 35
36#include <linux/inet_lro.h> 36#include <linux/inet_lro.h>
37 37
38#define NES_PHY_TYPE_CX4 1
38#define NES_PHY_TYPE_1G 2 39#define NES_PHY_TYPE_1G 2
39#define NES_PHY_TYPE_IRIS 3 40#define NES_PHY_TYPE_IRIS 3
40#define NES_PHY_TYPE_ARGUS 4 41#define NES_PHY_TYPE_ARGUS 4
41#define NES_PHY_TYPE_PUMA_1G 5 42#define NES_PHY_TYPE_PUMA_1G 5
42#define NES_PHY_TYPE_PUMA_10G 6 43#define NES_PHY_TYPE_PUMA_10G 6
43#define NES_PHY_TYPE_GLADIUS 7 44#define NES_PHY_TYPE_GLADIUS 7
45#define NES_PHY_TYPE_SFP_D 8
44 46
45#define NES_MULTICAST_PF_MAX 8 47#define NES_MULTICAST_PF_MAX 8
46 48
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c
index ecb1f6fd6276..c6e6611d3016 100644
--- a/drivers/infiniband/hw/nes/nes_nic.c
+++ b/drivers/infiniband/hw/nes/nes_nic.c
@@ -1426,49 +1426,55 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd
1426 struct nes_vnic *nesvnic = netdev_priv(netdev); 1426 struct nes_vnic *nesvnic = netdev_priv(netdev);
1427 struct nes_device *nesdev = nesvnic->nesdev; 1427 struct nes_device *nesdev = nesvnic->nesdev;
1428 struct nes_adapter *nesadapter = nesdev->nesadapter; 1428 struct nes_adapter *nesadapter = nesdev->nesadapter;
1429 u32 mac_index = nesdev->mac_index;
1430 u8 phy_type = nesadapter->phy_type[mac_index];
1431 u8 phy_index = nesadapter->phy_index[mac_index];
1429 u16 phy_data; 1432 u16 phy_data;
1430 1433
1431 et_cmd->duplex = DUPLEX_FULL; 1434 et_cmd->duplex = DUPLEX_FULL;
1432 et_cmd->port = PORT_MII; 1435 et_cmd->port = PORT_MII;
1436 et_cmd->maxtxpkt = 511;
1437 et_cmd->maxrxpkt = 511;
1433 1438
1434 if (nesadapter->OneG_Mode) { 1439 if (nesadapter->OneG_Mode) {
1435 et_cmd->speed = SPEED_1000; 1440 et_cmd->speed = SPEED_1000;
1436 if (nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) { 1441 if (phy_type == NES_PHY_TYPE_PUMA_1G) {
1437 et_cmd->supported = SUPPORTED_1000baseT_Full; 1442 et_cmd->supported = SUPPORTED_1000baseT_Full;
1438 et_cmd->advertising = ADVERTISED_1000baseT_Full; 1443 et_cmd->advertising = ADVERTISED_1000baseT_Full;
1439 et_cmd->autoneg = AUTONEG_DISABLE; 1444 et_cmd->autoneg = AUTONEG_DISABLE;
1440 et_cmd->transceiver = XCVR_INTERNAL; 1445 et_cmd->transceiver = XCVR_INTERNAL;
1441 et_cmd->phy_address = nesdev->mac_index; 1446 et_cmd->phy_address = mac_index;
1442 } else { 1447 } else {
1443 et_cmd->supported = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg; 1448 et_cmd->supported = SUPPORTED_1000baseT_Full
1444 et_cmd->advertising = ADVERTISED_1000baseT_Full | ADVERTISED_Autoneg; 1449 | SUPPORTED_Autoneg;
1445 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[nesdev->mac_index], &phy_data); 1450 et_cmd->advertising = ADVERTISED_1000baseT_Full
1451 | ADVERTISED_Autoneg;
1452 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1446 if (phy_data & 0x1000) 1453 if (phy_data & 0x1000)
1447 et_cmd->autoneg = AUTONEG_ENABLE; 1454 et_cmd->autoneg = AUTONEG_ENABLE;
1448 else 1455 else
1449 et_cmd->autoneg = AUTONEG_DISABLE; 1456 et_cmd->autoneg = AUTONEG_DISABLE;
1450 et_cmd->transceiver = XCVR_EXTERNAL; 1457 et_cmd->transceiver = XCVR_EXTERNAL;
1451 et_cmd->phy_address = nesadapter->phy_index[nesdev->mac_index]; 1458 et_cmd->phy_address = phy_index;
1452 } 1459 }
1460 return 0;
1461 }
1462 if ((phy_type == NES_PHY_TYPE_IRIS) ||
1463 (phy_type == NES_PHY_TYPE_ARGUS) ||
1464 (phy_type == NES_PHY_TYPE_SFP_D)) {
1465 et_cmd->transceiver = XCVR_EXTERNAL;
1466 et_cmd->port = PORT_FIBRE;
1467 et_cmd->supported = SUPPORTED_FIBRE;
1468 et_cmd->advertising = ADVERTISED_FIBRE;
1469 et_cmd->phy_address = phy_index;
1453 } else { 1470 } else {
1454 if ((nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_IRIS) || 1471 et_cmd->transceiver = XCVR_INTERNAL;
1455 (nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_ARGUS)) { 1472 et_cmd->supported = SUPPORTED_10000baseT_Full;
1456 et_cmd->transceiver = XCVR_EXTERNAL; 1473 et_cmd->advertising = ADVERTISED_10000baseT_Full;
1457 et_cmd->port = PORT_FIBRE; 1474 et_cmd->phy_address = mac_index;
1458 et_cmd->supported = SUPPORTED_FIBRE;
1459 et_cmd->advertising = ADVERTISED_FIBRE;
1460 et_cmd->phy_address = nesadapter->phy_index[nesdev->mac_index];
1461 } else {
1462 et_cmd->transceiver = XCVR_INTERNAL;
1463 et_cmd->supported = SUPPORTED_10000baseT_Full;
1464 et_cmd->advertising = ADVERTISED_10000baseT_Full;
1465 et_cmd->phy_address = nesdev->mac_index;
1466 }
1467 et_cmd->speed = SPEED_10000;
1468 et_cmd->autoneg = AUTONEG_DISABLE;
1469 } 1475 }
1470 et_cmd->maxtxpkt = 511; 1476 et_cmd->speed = SPEED_10000;
1471 et_cmd->maxrxpkt = 511; 1477 et_cmd->autoneg = AUTONEG_DISABLE;
1472 return 0; 1478 return 0;
1473} 1479}
1474 1480
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c
index 7e5b5ba13a74..64d5cfd8f380 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.c
+++ b/drivers/infiniband/hw/nes/nes_verbs.c
@@ -1627,6 +1627,7 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries,
1627 nescq->hw_cq.cq_number = nes_ucontext->mcrqf & 0xffff; 1627 nescq->hw_cq.cq_number = nes_ucontext->mcrqf & 0xffff;
1628 else 1628 else
1629 nescq->hw_cq.cq_number = nesvnic->mcrq_qp_id + nes_ucontext->mcrqf-1; 1629 nescq->hw_cq.cq_number = nesvnic->mcrq_qp_id + nes_ucontext->mcrqf-1;
1630 nescq->mcrqf = nes_ucontext->mcrqf;
1630 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1631 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1631 } 1632 }
1632 nes_debug(NES_DBG_CQ, "CQ Virtual Address = %08lX, size = %u.\n", 1633 nes_debug(NES_DBG_CQ, "CQ Virtual Address = %08lX, size = %u.\n",
@@ -1682,6 +1683,12 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries,
1682 if (!context) 1683 if (!context)
1683 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem, 1684 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem,
1684 nescq->hw_cq.cq_pbase); 1685 nescq->hw_cq.cq_pbase);
1686 else {
1687 pci_free_consistent(nesdev->pcidev, nespbl->pbl_size,
1688 nespbl->pbl_vbase, nespbl->pbl_pbase);
1689 kfree(nespbl);
1690 }
1691
1685 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1692 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1686 kfree(nescq); 1693 kfree(nescq);
1687 return ERR_PTR(-ENOMEM); 1694 return ERR_PTR(-ENOMEM);
@@ -1705,6 +1712,11 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries,
1705 if (!context) 1712 if (!context)
1706 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem, 1713 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem,
1707 nescq->hw_cq.cq_pbase); 1714 nescq->hw_cq.cq_pbase);
1715 else {
1716 pci_free_consistent(nesdev->pcidev, nespbl->pbl_size,
1717 nespbl->pbl_vbase, nespbl->pbl_pbase);
1718 kfree(nespbl);
1719 }
1708 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1720 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1709 kfree(nescq); 1721 kfree(nescq);
1710 return ERR_PTR(-ENOMEM); 1722 return ERR_PTR(-ENOMEM);
@@ -1722,6 +1734,11 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries,
1722 if (!context) 1734 if (!context)
1723 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem, 1735 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem,
1724 nescq->hw_cq.cq_pbase); 1736 nescq->hw_cq.cq_pbase);
1737 else {
1738 pci_free_consistent(nesdev->pcidev, nespbl->pbl_size,
1739 nespbl->pbl_vbase, nespbl->pbl_pbase);
1740 kfree(nespbl);
1741 }
1725 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1742 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1726 kfree(nescq); 1743 kfree(nescq);
1727 return ERR_PTR(-ENOMEM); 1744 return ERR_PTR(-ENOMEM);
@@ -1774,6 +1791,11 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev, int entries,
1774 if (!context) 1791 if (!context)
1775 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem, 1792 pci_free_consistent(nesdev->pcidev, nescq->cq_mem_size, mem,
1776 nescq->hw_cq.cq_pbase); 1793 nescq->hw_cq.cq_pbase);
1794 else {
1795 pci_free_consistent(nesdev->pcidev, nespbl->pbl_size,
1796 nespbl->pbl_vbase, nespbl->pbl_pbase);
1797 kfree(nespbl);
1798 }
1777 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1799 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1778 kfree(nescq); 1800 kfree(nescq);
1779 return ERR_PTR(-EIO); 1801 return ERR_PTR(-EIO);
@@ -1855,7 +1877,9 @@ static int nes_destroy_cq(struct ib_cq *ib_cq)
1855 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, opcode); 1877 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, opcode);
1856 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX, 1878 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1857 (nescq->hw_cq.cq_number | ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 16))); 1879 (nescq->hw_cq.cq_number | ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 16)));
1858 nes_free_resource(nesadapter, nesadapter->allocated_cqs, nescq->hw_cq.cq_number); 1880 if (!nescq->mcrqf)
1881 nes_free_resource(nesadapter, nesadapter->allocated_cqs, nescq->hw_cq.cq_number);
1882
1859 atomic_set(&cqp_request->refcount, 2); 1883 atomic_set(&cqp_request->refcount, 2);
1860 nes_post_cqp_request(nesdev, cqp_request); 1884 nes_post_cqp_request(nesdev, cqp_request);
1861 1885
@@ -1895,8 +1919,7 @@ static int nes_destroy_cq(struct ib_cq *ib_cq)
1895static u32 root_256(struct nes_device *nesdev, 1919static u32 root_256(struct nes_device *nesdev,
1896 struct nes_root_vpbl *root_vpbl, 1920 struct nes_root_vpbl *root_vpbl,
1897 struct nes_root_vpbl *new_root, 1921 struct nes_root_vpbl *new_root,
1898 u16 pbl_count_4k, 1922 u16 pbl_count_4k)
1899 u16 pbl_count_256)
1900{ 1923{
1901 u64 leaf_pbl; 1924 u64 leaf_pbl;
1902 int i, j, k; 1925 int i, j, k;
@@ -1952,7 +1975,7 @@ static int nes_reg_mr(struct nes_device *nesdev, struct nes_pd *nespd,
1952 int ret; 1975 int ret;
1953 struct nes_adapter *nesadapter = nesdev->nesadapter; 1976 struct nes_adapter *nesadapter = nesdev->nesadapter;
1954 uint pg_cnt = 0; 1977 uint pg_cnt = 0;
1955 u16 pbl_count_256; 1978 u16 pbl_count_256 = 0;
1956 u16 pbl_count = 0; 1979 u16 pbl_count = 0;
1957 u8 use_256_pbls = 0; 1980 u8 use_256_pbls = 0;
1958 u8 use_4k_pbls = 0; 1981 u8 use_4k_pbls = 0;
@@ -2012,7 +2035,7 @@ static int nes_reg_mr(struct nes_device *nesdev, struct nes_pd *nespd,
2012 } 2035 }
2013 2036
2014 if (use_256_pbls && use_two_level) { 2037 if (use_256_pbls && use_two_level) {
2015 if (root_256(nesdev, root_vpbl, &new_root, pbl_count_4k, pbl_count_256) == 1) { 2038 if (root_256(nesdev, root_vpbl, &new_root, pbl_count_4k) == 1) {
2016 if (new_root.pbl_pbase != 0) 2039 if (new_root.pbl_pbase != 0)
2017 root_vpbl = &new_root; 2040 root_vpbl = &new_root;
2018 } else { 2041 } else {
@@ -2122,6 +2145,7 @@ static struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
2122 struct nes_root_vpbl root_vpbl; 2145 struct nes_root_vpbl root_vpbl;
2123 u32 stag; 2146 u32 stag;
2124 u32 i; 2147 u32 i;
2148 unsigned long mask;
2125 u32 stag_index = 0; 2149 u32 stag_index = 0;
2126 u32 next_stag_index = 0; 2150 u32 next_stag_index = 0;
2127 u32 driver_key = 0; 2151 u32 driver_key = 0;
@@ -2150,6 +2174,9 @@ static struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
2150 return ERR_PTR(-E2BIG); 2174 return ERR_PTR(-E2BIG);
2151 } 2175 }
2152 2176
2177 if ((buffer_list[0].addr ^ *iova_start) & ~PAGE_MASK)
2178 return ERR_PTR(-EINVAL);
2179
2153 err = nes_alloc_resource(nesadapter, nesadapter->allocated_mrs, nesadapter->max_mr, 2180 err = nes_alloc_resource(nesadapter, nesadapter->allocated_mrs, nesadapter->max_mr,
2154 &stag_index, &next_stag_index); 2181 &stag_index, &next_stag_index);
2155 if (err) { 2182 if (err) {
@@ -2215,19 +2242,16 @@ static struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
2215 root_pbl_index++; 2242 root_pbl_index++;
2216 cur_pbl_index = 0; 2243 cur_pbl_index = 0;
2217 } 2244 }
2218 if (buffer_list[i].addr & ~PAGE_MASK) {
2219 /* TODO: Unwind allocated buffers */
2220 nes_free_resource(nesadapter, nesadapter->allocated_mrs, stag_index);
2221 nes_debug(NES_DBG_MR, "Unaligned Memory Buffer: 0x%x\n",
2222 (unsigned int) buffer_list[i].addr);
2223 ibmr = ERR_PTR(-EINVAL);
2224 kfree(nesmr);
2225 goto reg_phys_err;
2226 }
2227 2245
2228 if (!buffer_list[i].size) { 2246 mask = !buffer_list[i].size;
2247 if (i != 0)
2248 mask |= buffer_list[i].addr;
2249 if (i != num_phys_buf - 1)
2250 mask |= buffer_list[i].addr + buffer_list[i].size;
2251
2252 if (mask & ~PAGE_MASK) {
2229 nes_free_resource(nesadapter, nesadapter->allocated_mrs, stag_index); 2253 nes_free_resource(nesadapter, nesadapter->allocated_mrs, stag_index);
2230 nes_debug(NES_DBG_MR, "Invalid Buffer Size\n"); 2254 nes_debug(NES_DBG_MR, "Invalid buffer addr or size\n");
2231 ibmr = ERR_PTR(-EINVAL); 2255 ibmr = ERR_PTR(-EINVAL);
2232 kfree(nesmr); 2256 kfree(nesmr);
2233 goto reg_phys_err; 2257 goto reg_phys_err;
@@ -2238,7 +2262,7 @@ static struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
2238 if ((buffer_list[i-1].addr+PAGE_SIZE) != buffer_list[i].addr) 2262 if ((buffer_list[i-1].addr+PAGE_SIZE) != buffer_list[i].addr)
2239 single_page = 0; 2263 single_page = 0;
2240 } 2264 }
2241 vpbl.pbl_vbase[cur_pbl_index].pa_low = cpu_to_le32((u32)buffer_list[i].addr); 2265 vpbl.pbl_vbase[cur_pbl_index].pa_low = cpu_to_le32((u32)buffer_list[i].addr & PAGE_MASK);
2242 vpbl.pbl_vbase[cur_pbl_index++].pa_high = 2266 vpbl.pbl_vbase[cur_pbl_index++].pa_high =
2243 cpu_to_le32((u32)((((u64)buffer_list[i].addr) >> 32))); 2267 cpu_to_le32((u32)((((u64)buffer_list[i].addr) >> 32)));
2244 } 2268 }
@@ -2251,8 +2275,6 @@ static struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
2251 " length = 0x%016lX, index = 0x%08X\n", 2275 " length = 0x%016lX, index = 0x%08X\n",
2252 stag, (unsigned long)*iova_start, (unsigned long)region_length, stag_index); 2276 stag, (unsigned long)*iova_start, (unsigned long)region_length, stag_index);
2253 2277
2254 region_length -= (*iova_start)&PAGE_MASK;
2255
2256 /* Make the leaf PBL the root if only one PBL */ 2278 /* Make the leaf PBL the root if only one PBL */
2257 if (root_pbl_index == 1) { 2279 if (root_pbl_index == 1) {
2258 root_vpbl.pbl_pbase = vpbl.pbl_pbase; 2280 root_vpbl.pbl_pbase = vpbl.pbl_pbase;
@@ -2786,10 +2808,9 @@ static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr,
2786 struct nes_vnic *nesvnic = nesibdev->nesvnic; 2808 struct nes_vnic *nesvnic = nesibdev->nesvnic;
2787 2809
2788 nes_debug(NES_DBG_INIT, "\n"); 2810 nes_debug(NES_DBG_INIT, "\n");
2789 return sprintf(buf, "%x.%x.%x\n", 2811 return sprintf(buf, "%u.%u\n",
2790 (int)(nesvnic->nesdev->nesadapter->fw_ver >> 32), 2812 (nesvnic->nesdev->nesadapter->firmware_version >> 16),
2791 (int)(nesvnic->nesdev->nesadapter->fw_ver >> 16) & 0xffff, 2813 (nesvnic->nesdev->nesadapter->firmware_version & 0x000000ff));
2792 (int)(nesvnic->nesdev->nesadapter->fw_ver & 0xffff));
2793} 2814}
2794 2815
2795 2816
diff --git a/drivers/infiniband/hw/nes/nes_verbs.h b/drivers/infiniband/hw/nes/nes_verbs.h
index 5e48f67fbe8d..41c07f29f7c9 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.h
+++ b/drivers/infiniband/hw/nes/nes_verbs.h
@@ -112,6 +112,7 @@ struct nes_cq {
112 spinlock_t lock; 112 spinlock_t lock;
113 u8 virtual_cq; 113 u8 virtual_cq;
114 u8 pad[3]; 114 u8 pad[3];
115 u32 mcrqf;
115}; 116};
116 117
117struct nes_wq { 118struct nes_wq {
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 12:12:27 -0400