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authorDave Olson <dave.olson@qlogic.com>2008-04-17 00:09:30 -0400
committerRoland Dreier <rolandd@cisco.com>2008-04-17 00:09:30 -0400
commit1d7c2e529fb6d4143d294ade7d99e29cb6b3775f (patch)
tree15bb2a68280fbefeca12ef1db4c47e9f0d386e86 /drivers/infiniband/hw/ipath/ipath_init_chip.c
parent0ab6b2b9abb692919902edb6606c3b898f2dac17 (diff)
IB/ipath: Enable reduced PIO update for HCAs that support it.
Newer HCAs have a threshold counter to reduce the number of DMAs the chip makes to update the PIO buffer availability status bits. This patch enables the feature. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_init_chip.c')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_init_chip.c22
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_init_chip.c b/drivers/infiniband/hw/ipath/ipath_init_chip.c
index 720ff4df84eb..1adafa97e082 100644
--- a/drivers/infiniband/hw/ipath/ipath_init_chip.c
+++ b/drivers/infiniband/hw/ipath/ipath_init_chip.c
@@ -341,6 +341,7 @@ static int init_chip_reset(struct ipath_devdata *dd)
341{ 341{
342 u32 rtmp; 342 u32 rtmp;
343 int i; 343 int i;
344 unsigned long flags;
344 345
345 /* 346 /*
346 * ensure chip does no sends or receives, tail updates, or 347 * ensure chip does no sends or receives, tail updates, or
@@ -356,8 +357,13 @@ static int init_chip_reset(struct ipath_devdata *dd)
356 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 357 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
357 dd->ipath_rcvctrl); 358 dd->ipath_rcvctrl);
358 359
360 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
361 dd->ipath_sendctrl = 0U; /* no sdma, etc */
359 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); 362 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
360 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control); 363 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
364 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
365
366 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
361 367
362 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); 368 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
363 if (rtmp != dd->ipath_rcvtidcnt) 369 if (rtmp != dd->ipath_rcvtidcnt)
@@ -478,6 +484,14 @@ static void enable_chip(struct ipath_devdata *dd, int reinit)
478 /* Enable PIO send, and update of PIOavail regs to memory. */ 484 /* Enable PIO send, and update of PIOavail regs to memory. */
479 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE | 485 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
480 INFINIPATH_S_PIOBUFAVAILUPD; 486 INFINIPATH_S_PIOBUFAVAILUPD;
487
488 /*
489 * Set the PIO avail update threshold to host memory
490 * on chips that support it.
491 */
492 if (dd->ipath_pioupd_thresh)
493 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
494 << INFINIPATH_S_UPDTHRESH_SHIFT;
481 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl); 495 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
482 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 496 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
483 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); 497 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
@@ -757,6 +771,12 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
757 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u " 771 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
758 "each for %u user ports\n", kpiobufs, 772 "each for %u user ports\n", kpiobufs,
759 piobufs, dd->ipath_pbufsport, uports); 773 piobufs, dd->ipath_pbufsport, uports);
774 if (dd->ipath_pioupd_thresh) {
775 if (dd->ipath_pbufsport < dd->ipath_pioupd_thresh)
776 dd->ipath_pioupd_thresh = dd->ipath_pbufsport;
777 if (kpiobufs < dd->ipath_pioupd_thresh)
778 dd->ipath_pioupd_thresh = kpiobufs;
779 }
760 780
761 dd->ipath_f_early_init(dd); 781 dd->ipath_f_early_init(dd);
762 /* 782 /*