diff options
author | Joachim Fenkes <fenkes@de.ibm.com> | 2007-07-09 09:23:15 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2007-07-09 23:12:27 -0400 |
commit | 9a79fc0a1b815cbd05a8e37ea838acfccb7235cc (patch) | |
tree | ed94fc291a5017f94e2b9d57f6909a84e1eb40db /drivers/infiniband/hw/ehca/hcp_if.c | |
parent | 91f13aa3fc22e357b494c5b8270e94543870928d (diff) |
IB/ehca: QP code restructuring in preparation for SRQ
- Replace init_qp_queues() by a shorter init_qp_queue(), eliminating
duplicate code.
- hipz_h_alloc_resource_qp() doesn't need a pointer to struct ehca_qp any
longer. All input and output data is transferred through the parms
parameter.
- Change the interface to also support SRQ.
Signed-off-by: Joachim Fenkes <fenkes@de.ibm.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ehca/hcp_if.c')
-rw-r--r-- | drivers/infiniband/hw/ehca/hcp_if.c | 35 |
1 files changed, 13 insertions, 22 deletions
diff --git a/drivers/infiniband/hw/ehca/hcp_if.c b/drivers/infiniband/hw/ehca/hcp_if.c index 5766ae3a2029..7efc4a2ad2b9 100644 --- a/drivers/infiniband/hw/ehca/hcp_if.c +++ b/drivers/infiniband/hw/ehca/hcp_if.c | |||
@@ -74,11 +74,6 @@ | |||
74 | #define H_MP_SHUTDOWN EHCA_BMASK_IBM(48, 48) | 74 | #define H_MP_SHUTDOWN EHCA_BMASK_IBM(48, 48) |
75 | #define H_MP_RESET_QKEY_CTR EHCA_BMASK_IBM(49, 49) | 75 | #define H_MP_RESET_QKEY_CTR EHCA_BMASK_IBM(49, 49) |
76 | 76 | ||
77 | /* direct access qp controls */ | ||
78 | #define DAQP_CTRL_ENABLE 0x01 | ||
79 | #define DAQP_CTRL_SEND_COMP 0x20 | ||
80 | #define DAQP_CTRL_RECV_COMP 0x40 | ||
81 | |||
82 | static u32 get_longbusy_msecs(int longbusy_rc) | 77 | static u32 get_longbusy_msecs(int longbusy_rc) |
83 | { | 78 | { |
84 | switch (longbusy_rc) { | 79 | switch (longbusy_rc) { |
@@ -284,36 +279,31 @@ u64 hipz_h_alloc_resource_cq(const struct ipz_adapter_handle adapter_handle, | |||
284 | } | 279 | } |
285 | 280 | ||
286 | u64 hipz_h_alloc_resource_qp(const struct ipz_adapter_handle adapter_handle, | 281 | u64 hipz_h_alloc_resource_qp(const struct ipz_adapter_handle adapter_handle, |
287 | struct ehca_qp *qp, | ||
288 | struct ehca_alloc_qp_parms *parms) | 282 | struct ehca_alloc_qp_parms *parms) |
289 | { | 283 | { |
290 | u64 ret; | 284 | u64 ret; |
291 | u64 allocate_controls; | 285 | u64 allocate_controls; |
292 | u64 max_r10_reg; | 286 | u64 max_r10_reg; |
293 | u64 outs[PLPAR_HCALL9_BUFSIZE]; | 287 | u64 outs[PLPAR_HCALL9_BUFSIZE]; |
294 | u16 max_nr_receive_wqes = qp->init_attr.cap.max_recv_wr + 1; | ||
295 | u16 max_nr_send_wqes = qp->init_attr.cap.max_send_wr + 1; | ||
296 | int daqp_ctrl = parms->daqp_ctrl; | ||
297 | 288 | ||
298 | allocate_controls = | 289 | allocate_controls = |
299 | EHCA_BMASK_SET(H_ALL_RES_QP_ENHANCED_OPS, | 290 | EHCA_BMASK_SET(H_ALL_RES_QP_ENHANCED_OPS, parms->ext_type) |
300 | (daqp_ctrl & DAQP_CTRL_ENABLE) ? 1 : 0) | ||
301 | | EHCA_BMASK_SET(H_ALL_RES_QP_PTE_PIN, 0) | 291 | | EHCA_BMASK_SET(H_ALL_RES_QP_PTE_PIN, 0) |
302 | | EHCA_BMASK_SET(H_ALL_RES_QP_SERVICE_TYPE, parms->servicetype) | 292 | | EHCA_BMASK_SET(H_ALL_RES_QP_SERVICE_TYPE, parms->servicetype) |
303 | | EHCA_BMASK_SET(H_ALL_RES_QP_SIGNALING_TYPE, parms->sigtype) | 293 | | EHCA_BMASK_SET(H_ALL_RES_QP_SIGNALING_TYPE, parms->sigtype) |
304 | | EHCA_BMASK_SET(H_ALL_RES_QP_LL_RQ_CQE_POSTING, | 294 | | EHCA_BMASK_SET(H_ALL_RES_QP_LL_RQ_CQE_POSTING, |
305 | (daqp_ctrl & DAQP_CTRL_RECV_COMP) ? 1 : 0) | 295 | !!(parms->ll_comp_flags & LLQP_RECV_COMP)) |
306 | | EHCA_BMASK_SET(H_ALL_RES_QP_LL_SQ_CQE_POSTING, | 296 | | EHCA_BMASK_SET(H_ALL_RES_QP_LL_SQ_CQE_POSTING, |
307 | (daqp_ctrl & DAQP_CTRL_SEND_COMP) ? 1 : 0) | 297 | !!(parms->ll_comp_flags & LLQP_SEND_COMP)) |
308 | | EHCA_BMASK_SET(H_ALL_RES_QP_UD_AV_LKEY_CTRL, | 298 | | EHCA_BMASK_SET(H_ALL_RES_QP_UD_AV_LKEY_CTRL, |
309 | parms->ud_av_l_key_ctl) | 299 | parms->ud_av_l_key_ctl) |
310 | | EHCA_BMASK_SET(H_ALL_RES_QP_RESOURCE_TYPE, 1); | 300 | | EHCA_BMASK_SET(H_ALL_RES_QP_RESOURCE_TYPE, 1); |
311 | 301 | ||
312 | max_r10_reg = | 302 | max_r10_reg = |
313 | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_SEND_WR, | 303 | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_SEND_WR, |
314 | max_nr_send_wqes) | 304 | parms->max_send_wr + 1) |
315 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_RECV_WR, | 305 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_RECV_WR, |
316 | max_nr_receive_wqes) | 306 | parms->max_recv_wr + 1) |
317 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_SEND_SGE, | 307 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_SEND_SGE, |
318 | parms->max_send_sge) | 308 | parms->max_send_sge) |
319 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_RECV_SGE, | 309 | | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_RECV_SGE, |
@@ -322,15 +312,16 @@ u64 hipz_h_alloc_resource_qp(const struct ipz_adapter_handle adapter_handle, | |||
322 | ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs, | 312 | ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs, |
323 | adapter_handle.handle, /* r4 */ | 313 | adapter_handle.handle, /* r4 */ |
324 | allocate_controls, /* r5 */ | 314 | allocate_controls, /* r5 */ |
325 | qp->send_cq->ipz_cq_handle.handle, | 315 | parms->send_cq_handle.handle, |
326 | qp->recv_cq->ipz_cq_handle.handle, | 316 | parms->recv_cq_handle.handle, |
327 | parms->ipz_eq_handle.handle, | 317 | parms->eq_handle.handle, |
328 | ((u64)qp->token << 32) | parms->pd.value, | 318 | ((u64)parms->token << 32) | parms->pd.value, |
329 | max_r10_reg, /* r10 */ | 319 | max_r10_reg, /* r10 */ |
330 | parms->ud_av_l_key_ctl, /* r11 */ | 320 | parms->ud_av_l_key_ctl, /* r11 */ |
331 | 0); | 321 | 0); |
332 | qp->ipz_qp_handle.handle = outs[0]; | 322 | |
333 | qp->real_qp_num = (u32)outs[1]; | 323 | parms->qp_handle.handle = outs[0]; |
324 | parms->real_qp_num = (u32)outs[1]; | ||
334 | parms->act_nr_send_wqes = | 325 | parms->act_nr_send_wqes = |
335 | (u16)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_OUTST_SEND_WR, outs[2]); | 326 | (u16)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_OUTST_SEND_WR, outs[2]); |
336 | parms->act_nr_recv_wqes = | 327 | parms->act_nr_recv_wqes = |
@@ -345,7 +336,7 @@ u64 hipz_h_alloc_resource_qp(const struct ipz_adapter_handle adapter_handle, | |||
345 | (u32)EHCA_BMASK_GET(H_ALL_RES_QP_RQUEUE_SIZE_PAGES, outs[4]); | 336 | (u32)EHCA_BMASK_GET(H_ALL_RES_QP_RQUEUE_SIZE_PAGES, outs[4]); |
346 | 337 | ||
347 | if (ret == H_SUCCESS) | 338 | if (ret == H_SUCCESS) |
348 | hcp_galpas_ctor(&qp->galpas, outs[6], outs[6]); | 339 | hcp_galpas_ctor(&parms->galpas, outs[6], outs[6]); |
349 | 340 | ||
350 | if (ret == H_NOT_ENOUGH_RESOURCES) | 341 | if (ret == H_NOT_ENOUGH_RESOURCES) |
351 | ehca_gen_err("Not enough resources. ret=%lx", ret); | 342 | ehca_gen_err("Not enough resources. ret=%lx", ret); |