diff options
| author | Hoang-Nam Nguyen <hnguyen@de.ibm.com> | 2007-07-12 11:53:47 -0400 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2007-07-17 21:37:40 -0400 |
| commit | 2b94397adc68c2f0f851539884cc426e03444a26 (patch) | |
| tree | f510f23f62efea31f1de472c6a384d55f593b6be /drivers/infiniband/hw/ehca/ehca_classes_pSeries.h | |
| parent | 187c72e31f92791ec70395b80aa9883f2edad97f (diff) | |
IB/ehca: Fix warnings issued by checkpatch.pl
Run the existing ehca code through checkpatch.pl and clean up the
worst of the coding style violations.
Signed-off-by: Joachim Fenkes <fenkes@de.ibm.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ehca/ehca_classes_pSeries.h')
| -rw-r--r-- | drivers/infiniband/hw/ehca/ehca_classes_pSeries.h | 156 |
1 files changed, 78 insertions, 78 deletions
diff --git a/drivers/infiniband/hw/ehca/ehca_classes_pSeries.h b/drivers/infiniband/hw/ehca/ehca_classes_pSeries.h index fb3df5c271e7..1798e6466bd0 100644 --- a/drivers/infiniband/hw/ehca/ehca_classes_pSeries.h +++ b/drivers/infiniband/hw/ehca/ehca_classes_pSeries.h | |||
| @@ -154,83 +154,83 @@ struct hcp_modify_qp_control_block { | |||
| 154 | u32 reserved_70_127[58]; /* 70 */ | 154 | u32 reserved_70_127[58]; /* 70 */ |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | #define MQPCB_MASK_QKEY EHCA_BMASK_IBM(0,0) | 157 | #define MQPCB_MASK_QKEY EHCA_BMASK_IBM( 0, 0) |
| 158 | #define MQPCB_MASK_SEND_PSN EHCA_BMASK_IBM(2,2) | 158 | #define MQPCB_MASK_SEND_PSN EHCA_BMASK_IBM( 2, 2) |
| 159 | #define MQPCB_MASK_RECEIVE_PSN EHCA_BMASK_IBM(3,3) | 159 | #define MQPCB_MASK_RECEIVE_PSN EHCA_BMASK_IBM( 3, 3) |
| 160 | #define MQPCB_MASK_PRIM_PHYS_PORT EHCA_BMASK_IBM(4,4) | 160 | #define MQPCB_MASK_PRIM_PHYS_PORT EHCA_BMASK_IBM( 4, 4) |
| 161 | #define MQPCB_PRIM_PHYS_PORT EHCA_BMASK_IBM(24,31) | 161 | #define MQPCB_PRIM_PHYS_PORT EHCA_BMASK_IBM(24, 31) |
| 162 | #define MQPCB_MASK_ALT_PHYS_PORT EHCA_BMASK_IBM(5,5) | 162 | #define MQPCB_MASK_ALT_PHYS_PORT EHCA_BMASK_IBM( 5, 5) |
| 163 | #define MQPCB_MASK_PRIM_P_KEY_IDX EHCA_BMASK_IBM(6,6) | 163 | #define MQPCB_MASK_PRIM_P_KEY_IDX EHCA_BMASK_IBM( 6, 6) |
| 164 | #define MQPCB_PRIM_P_KEY_IDX EHCA_BMASK_IBM(24,31) | 164 | #define MQPCB_PRIM_P_KEY_IDX EHCA_BMASK_IBM(24, 31) |
| 165 | #define MQPCB_MASK_ALT_P_KEY_IDX EHCA_BMASK_IBM(7,7) | 165 | #define MQPCB_MASK_ALT_P_KEY_IDX EHCA_BMASK_IBM( 7, 7) |
| 166 | #define MQPCB_MASK_RDMA_ATOMIC_CTRL EHCA_BMASK_IBM(8,8) | 166 | #define MQPCB_MASK_RDMA_ATOMIC_CTRL EHCA_BMASK_IBM( 8, 8) |
| 167 | #define MQPCB_MASK_QP_STATE EHCA_BMASK_IBM(9,9) | 167 | #define MQPCB_MASK_QP_STATE EHCA_BMASK_IBM( 9, 9) |
| 168 | #define MQPCB_QP_STATE EHCA_BMASK_IBM(24,31) | 168 | #define MQPCB_QP_STATE EHCA_BMASK_IBM(24, 31) |
| 169 | #define MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES EHCA_BMASK_IBM(11,11) | 169 | #define MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES EHCA_BMASK_IBM(11, 11) |
| 170 | #define MQPCB_MASK_PATH_MIGRATION_STATE EHCA_BMASK_IBM(12,12) | 170 | #define MQPCB_MASK_PATH_MIGRATION_STATE EHCA_BMASK_IBM(12, 12) |
| 171 | #define MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP EHCA_BMASK_IBM(13,13) | 171 | #define MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP EHCA_BMASK_IBM(13, 13) |
| 172 | #define MQPCB_MASK_DEST_QP_NR EHCA_BMASK_IBM(14,14) | 172 | #define MQPCB_MASK_DEST_QP_NR EHCA_BMASK_IBM(14, 14) |
| 173 | #define MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD EHCA_BMASK_IBM(15,15) | 173 | #define MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD EHCA_BMASK_IBM(15, 15) |
| 174 | #define MQPCB_MASK_SERVICE_LEVEL EHCA_BMASK_IBM(16,16) | 174 | #define MQPCB_MASK_SERVICE_LEVEL EHCA_BMASK_IBM(16, 16) |
| 175 | #define MQPCB_MASK_SEND_GRH_FLAG EHCA_BMASK_IBM(17,17) | 175 | #define MQPCB_MASK_SEND_GRH_FLAG EHCA_BMASK_IBM(17, 17) |
| 176 | #define MQPCB_MASK_RETRY_COUNT EHCA_BMASK_IBM(18,18) | 176 | #define MQPCB_MASK_RETRY_COUNT EHCA_BMASK_IBM(18, 18) |
| 177 | #define MQPCB_MASK_TIMEOUT EHCA_BMASK_IBM(19,19) | 177 | #define MQPCB_MASK_TIMEOUT EHCA_BMASK_IBM(19, 19) |
| 178 | #define MQPCB_MASK_PATH_MTU EHCA_BMASK_IBM(20,20) | 178 | #define MQPCB_MASK_PATH_MTU EHCA_BMASK_IBM(20, 20) |
| 179 | #define MQPCB_PATH_MTU EHCA_BMASK_IBM(24,31) | 179 | #define MQPCB_PATH_MTU EHCA_BMASK_IBM(24, 31) |
| 180 | #define MQPCB_MASK_MAX_STATIC_RATE EHCA_BMASK_IBM(21,21) | 180 | #define MQPCB_MASK_MAX_STATIC_RATE EHCA_BMASK_IBM(21, 21) |
| 181 | #define MQPCB_MAX_STATIC_RATE EHCA_BMASK_IBM(24,31) | 181 | #define MQPCB_MAX_STATIC_RATE EHCA_BMASK_IBM(24, 31) |
| 182 | #define MQPCB_MASK_DLID EHCA_BMASK_IBM(22,22) | 182 | #define MQPCB_MASK_DLID EHCA_BMASK_IBM(22, 22) |
| 183 | #define MQPCB_DLID EHCA_BMASK_IBM(16,31) | 183 | #define MQPCB_DLID EHCA_BMASK_IBM(16, 31) |
| 184 | #define MQPCB_MASK_RNR_RETRY_COUNT EHCA_BMASK_IBM(23,23) | 184 | #define MQPCB_MASK_RNR_RETRY_COUNT EHCA_BMASK_IBM(23, 23) |
| 185 | #define MQPCB_RNR_RETRY_COUNT EHCA_BMASK_IBM(29,31) | 185 | #define MQPCB_RNR_RETRY_COUNT EHCA_BMASK_IBM(29, 31) |
| 186 | #define MQPCB_MASK_SOURCE_PATH_BITS EHCA_BMASK_IBM(24,24) | 186 | #define MQPCB_MASK_SOURCE_PATH_BITS EHCA_BMASK_IBM(24, 24) |
| 187 | #define MQPCB_SOURCE_PATH_BITS EHCA_BMASK_IBM(25,31) | 187 | #define MQPCB_SOURCE_PATH_BITS EHCA_BMASK_IBM(25, 31) |
| 188 | #define MQPCB_MASK_TRAFFIC_CLASS EHCA_BMASK_IBM(25,25) | 188 | #define MQPCB_MASK_TRAFFIC_CLASS EHCA_BMASK_IBM(25, 25) |
| 189 | #define MQPCB_TRAFFIC_CLASS EHCA_BMASK_IBM(24,31) | 189 | #define MQPCB_TRAFFIC_CLASS EHCA_BMASK_IBM(24, 31) |
| 190 | #define MQPCB_MASK_HOP_LIMIT EHCA_BMASK_IBM(26,26) | 190 | #define MQPCB_MASK_HOP_LIMIT EHCA_BMASK_IBM(26, 26) |
| 191 | #define MQPCB_HOP_LIMIT EHCA_BMASK_IBM(24,31) | 191 | #define MQPCB_HOP_LIMIT EHCA_BMASK_IBM(24, 31) |
| 192 | #define MQPCB_MASK_SOURCE_GID_IDX EHCA_BMASK_IBM(27,27) | 192 | #define MQPCB_MASK_SOURCE_GID_IDX EHCA_BMASK_IBM(27, 27) |
| 193 | #define MQPCB_SOURCE_GID_IDX EHCA_BMASK_IBM(24,31) | 193 | #define MQPCB_SOURCE_GID_IDX EHCA_BMASK_IBM(24, 31) |
| 194 | #define MQPCB_MASK_FLOW_LABEL EHCA_BMASK_IBM(28,28) | 194 | #define MQPCB_MASK_FLOW_LABEL EHCA_BMASK_IBM(28, 28) |
| 195 | #define MQPCB_FLOW_LABEL EHCA_BMASK_IBM(12,31) | 195 | #define MQPCB_FLOW_LABEL EHCA_BMASK_IBM(12, 31) |
| 196 | #define MQPCB_MASK_DEST_GID EHCA_BMASK_IBM(30,30) | 196 | #define MQPCB_MASK_DEST_GID EHCA_BMASK_IBM(30, 30) |
| 197 | #define MQPCB_MASK_SERVICE_LEVEL_AL EHCA_BMASK_IBM(31,31) | 197 | #define MQPCB_MASK_SERVICE_LEVEL_AL EHCA_BMASK_IBM(31, 31) |
| 198 | #define MQPCB_SERVICE_LEVEL_AL EHCA_BMASK_IBM(28,31) | 198 | #define MQPCB_SERVICE_LEVEL_AL EHCA_BMASK_IBM(28, 31) |
| 199 | #define MQPCB_MASK_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(32,32) | 199 | #define MQPCB_MASK_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(32, 32) |
| 200 | #define MQPCB_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(31,31) | 200 | #define MQPCB_SEND_GRH_FLAG_AL EHCA_BMASK_IBM(31, 31) |
| 201 | #define MQPCB_MASK_RETRY_COUNT_AL EHCA_BMASK_IBM(33,33) | 201 | #define MQPCB_MASK_RETRY_COUNT_AL EHCA_BMASK_IBM(33, 33) |
| 202 | #define MQPCB_RETRY_COUNT_AL EHCA_BMASK_IBM(29,31) | 202 | #define MQPCB_RETRY_COUNT_AL EHCA_BMASK_IBM(29, 31) |
| 203 | #define MQPCB_MASK_TIMEOUT_AL EHCA_BMASK_IBM(34,34) | 203 | #define MQPCB_MASK_TIMEOUT_AL EHCA_BMASK_IBM(34, 34) |
| 204 | #define MQPCB_TIMEOUT_AL EHCA_BMASK_IBM(27,31) | 204 | #define MQPCB_TIMEOUT_AL EHCA_BMASK_IBM(27, 31) |
| 205 | #define MQPCB_MASK_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(35,35) | 205 | #define MQPCB_MASK_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(35, 35) |
| 206 | #define MQPCB_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(24,31) | 206 | #define MQPCB_MAX_STATIC_RATE_AL EHCA_BMASK_IBM(24, 31) |
| 207 | #define MQPCB_MASK_DLID_AL EHCA_BMASK_IBM(36,36) | 207 | #define MQPCB_MASK_DLID_AL EHCA_BMASK_IBM(36, 36) |
| 208 | #define MQPCB_DLID_AL EHCA_BMASK_IBM(16,31) | 208 | #define MQPCB_DLID_AL EHCA_BMASK_IBM(16, 31) |
| 209 | #define MQPCB_MASK_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(37,37) | 209 | #define MQPCB_MASK_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(37, 37) |
| 210 | #define MQPCB_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(29,31) | 210 | #define MQPCB_RNR_RETRY_COUNT_AL EHCA_BMASK_IBM(29, 31) |
| 211 | #define MQPCB_MASK_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(38,38) | 211 | #define MQPCB_MASK_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(38, 38) |
| 212 | #define MQPCB_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(25,31) | 212 | #define MQPCB_SOURCE_PATH_BITS_AL EHCA_BMASK_IBM(25, 31) |
| 213 | #define MQPCB_MASK_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(39,39) | 213 | #define MQPCB_MASK_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(39, 39) |
| 214 | #define MQPCB_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(24,31) | 214 | #define MQPCB_TRAFFIC_CLASS_AL EHCA_BMASK_IBM(24, 31) |
| 215 | #define MQPCB_MASK_HOP_LIMIT_AL EHCA_BMASK_IBM(40,40) | 215 | #define MQPCB_MASK_HOP_LIMIT_AL EHCA_BMASK_IBM(40, 40) |
| 216 | #define MQPCB_HOP_LIMIT_AL EHCA_BMASK_IBM(24,31) | 216 | #define MQPCB_HOP_LIMIT_AL EHCA_BMASK_IBM(24, 31) |
| 217 | #define MQPCB_MASK_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(41,41) | 217 | #define MQPCB_MASK_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(41, 41) |
| 218 | #define MQPCB_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(24,31) | 218 | #define MQPCB_SOURCE_GID_IDX_AL EHCA_BMASK_IBM(24, 31) |
| 219 | #define MQPCB_MASK_FLOW_LABEL_AL EHCA_BMASK_IBM(42,42) | 219 | #define MQPCB_MASK_FLOW_LABEL_AL EHCA_BMASK_IBM(42, 42) |
| 220 | #define MQPCB_FLOW_LABEL_AL EHCA_BMASK_IBM(12,31) | 220 | #define MQPCB_FLOW_LABEL_AL EHCA_BMASK_IBM(12, 31) |
| 221 | #define MQPCB_MASK_DEST_GID_AL EHCA_BMASK_IBM(44,44) | 221 | #define MQPCB_MASK_DEST_GID_AL EHCA_BMASK_IBM(44, 44) |
| 222 | #define MQPCB_MASK_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(45,45) | 222 | #define MQPCB_MASK_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(45, 45) |
| 223 | #define MQPCB_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(16,31) | 223 | #define MQPCB_MAX_NR_OUTST_SEND_WR EHCA_BMASK_IBM(16, 31) |
| 224 | #define MQPCB_MASK_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(46,46) | 224 | #define MQPCB_MASK_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(46, 46) |
| 225 | #define MQPCB_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(16,31) | 225 | #define MQPCB_MAX_NR_OUTST_RECV_WR EHCA_BMASK_IBM(16, 31) |
| 226 | #define MQPCB_MASK_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(47,47) | 226 | #define MQPCB_MASK_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(47, 47) |
| 227 | #define MQPCB_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(31,31) | 227 | #define MQPCB_DISABLE_ETE_CREDIT_CHECK EHCA_BMASK_IBM(31, 31) |
| 228 | #define MQPCB_QP_NUMBER EHCA_BMASK_IBM(8,31) | 228 | #define MQPCB_QP_NUMBER EHCA_BMASK_IBM( 8, 31) |
| 229 | #define MQPCB_MASK_QP_ENABLE EHCA_BMASK_IBM(48,48) | 229 | #define MQPCB_MASK_QP_ENABLE EHCA_BMASK_IBM(48, 48) |
| 230 | #define MQPCB_QP_ENABLE EHCA_BMASK_IBM(31,31) | 230 | #define MQPCB_QP_ENABLE EHCA_BMASK_IBM(31, 31) |
| 231 | #define MQPCB_MASK_CURR_SRQ_LIMIT EHCA_BMASK_IBM(49,49) | 231 | #define MQPCB_MASK_CURR_SRQ_LIMIT EHCA_BMASK_IBM(49, 49) |
| 232 | #define MQPCB_CURR_SRQ_LIMIT EHCA_BMASK_IBM(16,31) | 232 | #define MQPCB_CURR_SRQ_LIMIT EHCA_BMASK_IBM(16, 31) |
| 233 | #define MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG EHCA_BMASK_IBM(50,50) | 233 | #define MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG EHCA_BMASK_IBM(50, 50) |
| 234 | #define MQPCB_MASK_SHARED_RQ_HNDL EHCA_BMASK_IBM(51,51) | 234 | #define MQPCB_MASK_SHARED_RQ_HNDL EHCA_BMASK_IBM(51, 51) |
| 235 | 235 | ||
| 236 | #endif /* __EHCA_CLASSES_PSERIES_H__ */ | 236 | #endif /* __EHCA_CLASSES_PSERIES_H__ */ |