intel_idle: Update support for Silvermont Core in Baytrail SOC

On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.

Under some conditions, the latency of the C6N-BYT and C6S-BYT states
may exceed the specified values of 40 and 140 usec, respectively.
Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set
by the Linux PM_QOS sub-system.

Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.

Signed-off-by: Len Brown <len.brown@intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: <stable@vger.kernel.org>

1 files changed, 3 insertions, 11 deletions

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index b0e58522780d..44d1d7920202 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -218,18 +218,10 @@ static struct cpuidle_state byt_cstates[] = {
                 .enter = &intel_idle,
                 .enter_freeze = intel_idle_freeze, },
         {
-                .name = "C1E-BYT",
-                .desc = "MWAIT 0x01",
-                .flags = MWAIT2flg(0x01),
-                .exit_latency = 15,
-                .target_residency = 30,
-                .enter = &intel_idle,
-                .enter_freeze = intel_idle_freeze, },
-        {
                 .name = "C6N-BYT",
                 .desc = "MWAIT 0x58",
                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
-                .exit_latency = 40,
+                .exit_latency = 300,
                 .target_residency = 275,
                 .enter = &intel_idle,
                 .enter_freeze = intel_idle_freeze, },
@@ -237,7 +229,7 @@ static struct cpuidle_state byt_cstates[] = {
                 .name = "C6S-BYT",
                 .desc = "MWAIT 0x52",
                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
-                .exit_latency = 140,
+                .exit_latency = 500,
                 .target_residency = 560,
                 .enter = &intel_idle,
                 .enter_freeze = intel_idle_freeze, },
@@ -246,7 +238,7 @@ static struct cpuidle_state byt_cstates[] = {
                 .desc = "MWAIT 0x60",
                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
                 .exit_latency = 1200,
-                .target_residency = 1500,
+                .target_residency = 4000,
                 .enter = &intel_idle,
                 .enter_freeze = intel_idle_freeze, },
         {