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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-07-16 14:33:36 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-07-16 14:33:36 -0400
commitf0ffc9872e972e9d9fe8f7ae577ff046dbdba51b (patch)
treee2de0658c7a2fba2eb40a58c1bae1a0322453194 /drivers/ide/ide-timing.h
parente4e8d02f56f5c0cefc6713384629e068193d706a (diff)
ide: remove unused XFER_UDMA_SLOW
Remove unused XFER_UDMA_SLOW from ide_timing[]. While at it: - fix re-defining XFER_PIO_5 (no need to define it in ide-timing.h as it is defined in <linux/ata.h> which is included by <linux/hdreg.h>) - fix whitespace damage There should be no functional changes caused by this patch. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/ide-timing.h')
-rw-r--r--drivers/ide/ide-timing.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/ide/ide-timing.h b/drivers/ide/ide-timing.h
index 2e91c5870b4c..a20c4cbbfcdb 100644
--- a/drivers/ide/ide-timing.h
+++ b/drivers/ide/ide-timing.h
@@ -28,9 +28,6 @@
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/hdreg.h> 29#include <linux/hdreg.h>
30 30
31#define XFER_PIO_5 0x0d
32#define XFER_UDMA_SLOW 0x4f
33
34struct ide_timing { 31struct ide_timing {
35 short mode; 32 short mode;
36 short setup; /* t1 */ 33 short setup; /* t1 */
@@ -61,12 +58,10 @@ static struct ide_timing ide_timing[] = {
61 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, 58 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
62 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, 59 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
63 60
64 { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 },
65
66 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, 61 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
67 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, 62 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
68 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, 63 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
69 64
70 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, 65 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
71 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, 66 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
72 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, 67 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },