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authorMarek Vasut <marex@denx.de>2012-07-09 12:22:53 -0400
committerWolfram Sang <w.sang@pengutronix.de>2012-07-13 04:33:42 -0400
commitcd4f2d4aa79ccbb2713f33f9c9f24ed21b5fc8fa (patch)
treef18425262e5ab482c4b6b12dbbf5ca8759ad33b3 /drivers/i2c/busses/i2c-mxs.c
parent90c16bbf57412d69fb29ca61a3942c8f433aa381 (diff)
i2c: mxs: Set I2C timing registers for mxs-i2c
This patch configures the I2C bus timing registers according to information passed via DT. Currently, 100kHz and 400kHz modes are supported. The TIMING2 register value is wrong in the documentation for i.MX28! This was found and fixed by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'drivers/i2c/busses/i2c-mxs.c')
-rw-r--r--drivers/i2c/busses/i2c-mxs.c66
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 02ce1faeeeef..088c5c1ed17d 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -46,6 +46,10 @@
46#define MXS_I2C_CTRL0_DIRECTION 0x00010000 46#define MXS_I2C_CTRL0_DIRECTION 0x00010000
47#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) 47#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
48 48
49#define MXS_I2C_TIMING0 (0x10)
50#define MXS_I2C_TIMING1 (0x20)
51#define MXS_I2C_TIMING2 (0x30)
52
49#define MXS_I2C_CTRL1 (0x40) 53#define MXS_I2C_CTRL1 (0x40)
50#define MXS_I2C_CTRL1_SET (0x44) 54#define MXS_I2C_CTRL1_SET (0x44)
51#define MXS_I2C_CTRL1_CLR (0x48) 55#define MXS_I2C_CTRL1_CLR (0x48)
@@ -97,6 +101,35 @@
97#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ 101#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
98 MXS_I2C_CTRL0_MASTER_MODE) 102 MXS_I2C_CTRL0_MASTER_MODE)
99 103
104struct mxs_i2c_speed_config {
105 uint32_t timing0;
106 uint32_t timing1;
107 uint32_t timing2;
108};
109
110/*
111 * Timing values for the default 24MHz clock supplied into the i2c block.
112 *
113 * The bus can operate at 95kHz or at 400kHz with the following timing
114 * register configurations. The 100kHz mode isn't present because it's
115 * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
116 * shall be close enough replacement. Therefore when the bus is configured
117 * for 100kHz operation, 95kHz timing settings are actually loaded.
118 *
119 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
120 */
121static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
122 .timing0 = 0x00780030,
123 .timing1 = 0x00800030,
124 .timing2 = 0x00300030,
125};
126
127static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
128 .timing0 = 0x000f0007,
129 .timing1 = 0x001f000f,
130 .timing2 = 0x00300030,
131};
132
100/** 133/**
101 * struct mxs_i2c_dev - per device, private MXS-I2C data 134 * struct mxs_i2c_dev - per device, private MXS-I2C data
102 * 135 *
@@ -112,11 +145,17 @@ struct mxs_i2c_dev {
112 struct completion cmd_complete; 145 struct completion cmd_complete;
113 u32 cmd_err; 146 u32 cmd_err;
114 struct i2c_adapter adapter; 147 struct i2c_adapter adapter;
148 const struct mxs_i2c_speed_config *speed;
115}; 149};
116 150
117static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) 151static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
118{ 152{
119 stmp_reset_block(i2c->regs); 153 stmp_reset_block(i2c->regs);
154
155 writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
156 writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
157 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
158
120 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 159 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
121 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 160 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
122 i2c->regs + MXS_I2C_QUEUECTRL_SET); 161 i2c->regs + MXS_I2C_QUEUECTRL_SET);
@@ -319,6 +358,28 @@ static const struct i2c_algorithm mxs_i2c_algo = {
319 .functionality = mxs_i2c_func, 358 .functionality = mxs_i2c_func,
320}; 359};
321 360
361static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
362{
363 uint32_t speed;
364 struct device *dev = i2c->dev;
365 struct device_node *node = dev->of_node;
366 int ret;
367
368 if (!node)
369 return -EINVAL;
370
371 i2c->speed = &mxs_i2c_95kHz_config;
372 ret = of_property_read_u32(node, "clock-frequency", &speed);
373 if (ret)
374 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
375 else if (speed == 400000)
376 i2c->speed = &mxs_i2c_400kHz_config;
377 else if (speed != 100000)
378 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
379
380 return 0;
381}
382
322static int __devinit mxs_i2c_probe(struct platform_device *pdev) 383static int __devinit mxs_i2c_probe(struct platform_device *pdev)
323{ 384{
324 struct device *dev = &pdev->dev; 385 struct device *dev = &pdev->dev;
@@ -358,6 +419,11 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
358 return err; 419 return err;
359 420
360 i2c->dev = dev; 421 i2c->dev = dev;
422
423 err = mxs_i2c_get_ofdata(i2c);
424 if (err)
425 return err;
426
361 platform_set_drvdata(pdev, i2c); 427 platform_set_drvdata(pdev, i2c);
362 428
363 /* Do reset to enforce correct startup after pinmuxing */ 429 /* Do reset to enforce correct startup after pinmuxing */