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authorGuenter Roeck <linux@roeck-us.net>2012-03-23 05:02:18 -0400
committerJean Delvare <khali@endymion.delvare>2012-03-23 05:02:18 -0400
commitc10b3ee8aa7b26875a8ec0afb6f6323810b35043 (patch)
treefd171acc133d5781fd442d3c015b24a1eec75fd9 /drivers/hwmon
parent72fea694c4208d7ee1704a7dbccddd54af352cde (diff)
hwmon: (w83795) Fix multi-line comments
Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Jean Delvare <khali@linux-fr.org>
Diffstat (limited to 'drivers/hwmon')
-rw-r--r--drivers/hwmon/w83795.c94
1 files changed, 62 insertions, 32 deletions
diff --git a/drivers/hwmon/w83795.c b/drivers/hwmon/w83795.c
index 5478dd136233..d887cb3b72e8 100644
--- a/drivers/hwmon/w83795.c
+++ b/drivers/hwmon/w83795.c
@@ -72,8 +72,10 @@ MODULE_PARM_DESC(reset, "Set to 1 to reset chip, not recommended");
72#define TEMP_CRIT_HYST 2 72#define TEMP_CRIT_HYST 2
73#define TEMP_WARN 3 73#define TEMP_WARN 3
74#define TEMP_WARN_HYST 4 74#define TEMP_WARN_HYST 4
75/* only crit and crit_hyst affect real-time alarm status 75/*
76 * current crit crit_hyst warn warn_hyst */ 76 * only crit and crit_hyst affect real-time alarm status
77 * current crit crit_hyst warn warn_hyst
78 */
77static const u16 W83795_REG_TEMP[][5] = { 79static const u16 W83795_REG_TEMP[][5] = {
78 {0x21, 0x96, 0x97, 0x98, 0x99}, /* TD1/TR1 */ 80 {0x21, 0x96, 0x97, 0x98, 0x99}, /* TD1/TR1 */
79 {0x22, 0x9a, 0x9b, 0x9c, 0x9d}, /* TD2/TR2 */ 81 {0x22, 0x9a, 0x9b, 0x9c, 0x9d}, /* TD2/TR2 */
@@ -354,26 +356,34 @@ struct w83795_data {
354 u8 temp_mode; /* Bit vector, 0 = TR, 1 = TD */ 356 u8 temp_mode; /* Bit vector, 0 = TR, 1 = TD */
355 u8 temp_src[3]; /* Register value */ 357 u8 temp_src[3]; /* Register value */
356 358
357 u8 enable_dts; /* Enable PECI and SB-TSI, 359 u8 enable_dts; /*
360 * Enable PECI and SB-TSI,
358 * bit 0: =1 enable, =0 disable, 361 * bit 0: =1 enable, =0 disable,
359 * bit 1: =1 AMD SB-TSI, =0 Intel PECI */ 362 * bit 1: =1 AMD SB-TSI, =0 Intel PECI
363 */
360 u8 has_dts; /* Enable monitor DTS temp */ 364 u8 has_dts; /* Enable monitor DTS temp */
361 s8 dts[8]; /* Register value */ 365 s8 dts[8]; /* Register value */
362 u8 dts_read_vrlsb[8]; /* Register value */ 366 u8 dts_read_vrlsb[8]; /* Register value */
363 s8 dts_ext[4]; /* Register value */ 367 s8 dts_ext[4]; /* Register value */
364 368
365 u8 has_pwm; /* 795g supports 8 pwm, 795adg only supports 2, 369 u8 has_pwm; /*
370 * 795g supports 8 pwm, 795adg only supports 2,
366 * no config register, only affected by chip 371 * no config register, only affected by chip
367 * type */ 372 * type
368 u8 pwm[8][5]; /* Register value, output, freq, start, 373 */
369 * non stop, stop time */ 374 u8 pwm[8][5]; /*
375 * Register value, output, freq, start,
376 * non stop, stop time
377 */
370 u16 clkin; /* CLKIN frequency in kHz */ 378 u16 clkin; /* CLKIN frequency in kHz */
371 u8 pwm_fcms[2]; /* Register value */ 379 u8 pwm_fcms[2]; /* Register value */
372 u8 pwm_tfmr[6]; /* Register value */ 380 u8 pwm_tfmr[6]; /* Register value */
373 u8 pwm_fomc; /* Register value */ 381 u8 pwm_fomc; /* Register value */
374 382
375 u16 target_speed[8]; /* Register value, target speed for speed 383 u16 target_speed[8]; /*
376 * cruise */ 384 * Register value, target speed for speed
385 * cruise
386 */
377 u8 tol_speed; /* tolerance of target speed */ 387 u8 tol_speed; /* tolerance of target speed */
378 u8 pwm_temp[6][4]; /* TTTI, CTFS, HCT, HOT */ 388 u8 pwm_temp[6][4]; /* TTTI, CTFS, HCT, HOT */
379 u8 sf4_reg[6][2][7]; /* 6 temp, temp/dcpwm, 7 registers */ 389 u8 sf4_reg[6][2][7]; /* 6 temp, temp/dcpwm, 7 registers */
@@ -482,8 +492,10 @@ static void w83795_update_limits(struct i2c_client *client)
482 /* Read the fan limits */ 492 /* Read the fan limits */
483 lsb = 0; /* Silent false gcc warning */ 493 lsb = 0; /* Silent false gcc warning */
484 for (i = 0; i < ARRAY_SIZE(data->fan); i++) { 494 for (i = 0; i < ARRAY_SIZE(data->fan); i++) {
485 /* Each register contains LSB for 2 fans, but we want to 495 /*
486 * read it only once to save time */ 496 * Each register contains LSB for 2 fans, but we want to
497 * read it only once to save time
498 */
487 if ((i & 1) == 0 && (data->has_fan & (3 << i))) 499 if ((i & 1) == 0 && (data->has_fan & (3 << i)))
488 lsb = w83795_read(client, W83795_REG_FAN_MIN_LSB(i)); 500 lsb = w83795_read(client, W83795_REG_FAN_MIN_LSB(i));
489 501
@@ -665,9 +677,11 @@ static struct w83795_data *w83795_update_device(struct device *dev)
665 w83795_read(client, W83795_REG_PWM(i, PWM_OUTPUT)); 677 w83795_read(client, W83795_REG_PWM(i, PWM_OUTPUT));
666 } 678 }
667 679
668 /* Update intrusion and alarms 680 /*
681 * Update intrusion and alarms
669 * It is important to read intrusion first, because reading from 682 * It is important to read intrusion first, because reading from
670 * register SMI STS6 clears the interrupt status temporarily. */ 683 * register SMI STS6 clears the interrupt status temporarily.
684 */
671 tmp = w83795_read(client, W83795_REG_ALARM_CTRL); 685 tmp = w83795_read(client, W83795_REG_ALARM_CTRL);
672 /* Switch to interrupt status for intrusion if needed */ 686 /* Switch to interrupt status for intrusion if needed */
673 if (tmp & ALARM_CTRL_RTSACS) 687 if (tmp & ALARM_CTRL_RTSACS)
@@ -1603,8 +1617,10 @@ store_sf_setup(struct device *dev, struct device_attribute *attr,
1603 1617
1604#define NOT_USED -1 1618#define NOT_USED -1
1605 1619
1606/* Don't change the attribute order, _max, _min and _beep are accessed by index 1620/*
1607 * somewhere else in the code */ 1621 * Don't change the attribute order, _max, _min and _beep are accessed by index
1622 * somewhere else in the code
1623 */
1608#define SENSOR_ATTR_IN(index) { \ 1624#define SENSOR_ATTR_IN(index) { \
1609 SENSOR_ATTR_2(in##index##_input, S_IRUGO, show_in, NULL, \ 1625 SENSOR_ATTR_2(in##index##_input, S_IRUGO, show_in, NULL, \
1610 IN_READ, index), \ 1626 IN_READ, index), \
@@ -1618,8 +1634,10 @@ store_sf_setup(struct device *dev, struct device_attribute *attr,
1618 show_alarm_beep, store_beep, BEEP_ENABLE, \ 1634 show_alarm_beep, store_beep, BEEP_ENABLE, \
1619 index + ((index > 14) ? 1 : 0)) } 1635 index + ((index > 14) ? 1 : 0)) }
1620 1636
1621/* Don't change the attribute order, _beep is accessed by index 1637/*
1622 * somewhere else in the code */ 1638 * Don't change the attribute order, _beep is accessed by index
1639 * somewhere else in the code
1640 */
1623#define SENSOR_ATTR_FAN(index) { \ 1641#define SENSOR_ATTR_FAN(index) { \
1624 SENSOR_ATTR_2(fan##index##_input, S_IRUGO, show_fan, \ 1642 SENSOR_ATTR_2(fan##index##_input, S_IRUGO, show_fan, \
1625 NULL, FAN_INPUT, index - 1), \ 1643 NULL, FAN_INPUT, index - 1), \
@@ -1648,8 +1666,10 @@ store_sf_setup(struct device *dev, struct device_attribute *attr,
1648 SENSOR_ATTR_2(fan##index##_target, S_IWUSR | S_IRUGO, \ 1666 SENSOR_ATTR_2(fan##index##_target, S_IWUSR | S_IRUGO, \
1649 show_fanin, store_fanin, FANIN_TARGET, index - 1) } 1667 show_fanin, store_fanin, FANIN_TARGET, index - 1) }
1650 1668
1651/* Don't change the attribute order, _beep is accessed by index 1669/*
1652 * somewhere else in the code */ 1670 * Don't change the attribute order, _beep is accessed by index
1671 * somewhere else in the code
1672 */
1653#define SENSOR_ATTR_DTS(index) { \ 1673#define SENSOR_ATTR_DTS(index) { \
1654 SENSOR_ATTR_2(temp##index##_type, S_IRUGO , \ 1674 SENSOR_ATTR_2(temp##index##_type, S_IRUGO , \
1655 show_dts_mode, NULL, NOT_USED, index - 7), \ 1675 show_dts_mode, NULL, NOT_USED, index - 7), \
@@ -1668,8 +1688,10 @@ store_sf_setup(struct device *dev, struct device_attribute *attr,
1668 SENSOR_ATTR_2(temp##index##_beep, S_IWUSR | S_IRUGO, \ 1688 SENSOR_ATTR_2(temp##index##_beep, S_IWUSR | S_IRUGO, \
1669 show_alarm_beep, store_beep, BEEP_ENABLE, index + 17) } 1689 show_alarm_beep, store_beep, BEEP_ENABLE, index + 17) }
1670 1690
1671/* Don't change the attribute order, _beep is accessed by index 1691/*
1672 * somewhere else in the code */ 1692 * Don't change the attribute order, _beep is accessed by index
1693 * somewhere else in the code
1694 */
1673#define SENSOR_ATTR_TEMP(index) { \ 1695#define SENSOR_ATTR_TEMP(index) { \
1674 SENSOR_ATTR_2(temp##index##_type, S_IRUGO | (index < 4 ? S_IWUSR : 0), \ 1696 SENSOR_ATTR_2(temp##index##_type, S_IRUGO | (index < 4 ? S_IWUSR : 0), \
1675 show_temp_mode, store_temp_mode, NOT_USED, index - 1), \ 1697 show_temp_mode, store_temp_mode, NOT_USED, index - 1), \
@@ -1875,8 +1897,10 @@ static int w83795_get_device_id(struct i2c_client *client)
1875 1897
1876 device_id = i2c_smbus_read_byte_data(client, W83795_REG_DEVICEID); 1898 device_id = i2c_smbus_read_byte_data(client, W83795_REG_DEVICEID);
1877 1899
1878 /* Special case for rev. A chips; can't be checked first because later 1900 /*
1879 revisions emulate this for compatibility */ 1901 * Special case for rev. A chips; can't be checked first because later
1902 * revisions emulate this for compatibility
1903 */
1880 if (device_id < 0 || (device_id & 0xf0) != 0x50) { 1904 if (device_id < 0 || (device_id & 0xf0) != 0x50) {
1881 int alt_id; 1905 int alt_id;
1882 1906
@@ -1928,8 +1952,10 @@ static int w83795_detect(struct i2c_client *client,
1928 return -ENODEV; 1952 return -ENODEV;
1929 } 1953 }
1930 1954
1931 /* If Nuvoton chip, address of chip and W83795_REG_I2C_ADDR 1955 /*
1932 should match */ 1956 * If Nuvoton chip, address of chip and W83795_REG_I2C_ADDR
1957 * should match
1958 */
1933 if ((bank & 0x07) == 0) { 1959 if ((bank & 0x07) == 0) {
1934 i2c_addr = i2c_smbus_read_byte_data(client, 1960 i2c_addr = i2c_smbus_read_byte_data(client,
1935 W83795_REG_I2C_ADDR); 1961 W83795_REG_I2C_ADDR);
@@ -1941,10 +1967,12 @@ static int w83795_detect(struct i2c_client *client,
1941 } 1967 }
1942 } 1968 }
1943 1969
1944 /* Check 795 chip type: 795G or 795ADG 1970 /*
1945 Usually we don't write to chips during detection, but here we don't 1971 * Check 795 chip type: 795G or 795ADG
1946 quite have the choice; hopefully it's OK, we are about to return 1972 * Usually we don't write to chips during detection, but here we don't
1947 success anyway */ 1973 * quite have the choice; hopefully it's OK, we are about to return
1974 * success anyway
1975 */
1948 if ((bank & 0x07) != 0) 1976 if ((bank & 0x07) != 0)
1949 i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL, 1977 i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL,
1950 bank & ~0x07); 1978 bank & ~0x07);
@@ -2193,8 +2221,10 @@ static int w83795_probe(struct i2c_client *client,
2193 /* The W83795G has a dedicated BEEP pin */ 2221 /* The W83795G has a dedicated BEEP pin */
2194 data->enable_beep = 1; 2222 data->enable_beep = 1;
2195 } else { 2223 } else {
2196 /* The W83795ADG has a shared pin for OVT# and BEEP, so you 2224 /*
2197 * can't have both */ 2225 * The W83795ADG has a shared pin for OVT# and BEEP, so you
2226 * can't have both
2227 */
2198 tmp = w83795_read(client, W83795_REG_OVT_CFG); 2228 tmp = w83795_read(client, W83795_REG_OVT_CFG);
2199 if ((tmp & OVT_CFG_SEL) == 0) 2229 if ((tmp & OVT_CFG_SEL) == 0)
2200 data->enable_beep = 1; 2230 data->enable_beep = 1;