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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/hwmon/coretemp.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/hwmon/coretemp.c')
-rw-r--r--drivers/hwmon/coretemp.c20
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index caef39cda8c8..e9b7fbc5a447 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -33,6 +33,7 @@
33#include <linux/list.h> 33#include <linux/list.h>
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <linux/cpu.h> 35#include <linux/cpu.h>
36#include <linux/pci.h>
36#include <asm/msr.h> 37#include <asm/msr.h>
37#include <asm/processor.h> 38#include <asm/processor.h>
38 39
@@ -161,6 +162,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
161 int usemsr_ee = 1; 162 int usemsr_ee = 1;
162 int err; 163 int err;
163 u32 eax, edx; 164 u32 eax, edx;
165 struct pci_dev *host_bridge;
164 166
165 /* Early chips have no MSR for TjMax */ 167 /* Early chips have no MSR for TjMax */
166 168
@@ -168,11 +170,21 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
168 usemsr_ee = 0; 170 usemsr_ee = 0;
169 } 171 }
170 172
171 /* Atoms seems to have TjMax at 90C */ 173 /* Atom CPUs */
172 174
173 if (c->x86_model == 0x1c) { 175 if (c->x86_model == 0x1c) {
174 usemsr_ee = 0; 176 usemsr_ee = 0;
175 tjmax = 90000; 177
178 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
179
180 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
181 && (host_bridge->device == 0xa000 /* NM10 based nettop */
182 || host_bridge->device == 0xa010)) /* NM10 based netbook */
183 tjmax = 100000;
184 else
185 tjmax = 90000;
186
187 pci_dev_put(host_bridge);
176 } 188 }
177 189
178 if ((c->x86_model > 0xe) && (usemsr_ee)) { 190 if ((c->x86_model > 0xe) && (usemsr_ee)) {
@@ -216,7 +228,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
216 if (err) { 228 if (err) {
217 dev_warn(dev, 229 dev_warn(dev,
218 "Unable to access MSR 0xEE, for Tjmax, left" 230 "Unable to access MSR 0xEE, for Tjmax, left"
219 " at default"); 231 " at default\n");
220 } else if (eax & 0x40000000) { 232 } else if (eax & 0x40000000) {
221 tjmax = tjmax_ee; 233 tjmax = tjmax_ee;
222 } 234 }
@@ -454,7 +466,7 @@ static int __init coretemp_init(void)
454 family 6 CPU */ 466 family 6 CPU */
455 if ((c->x86 == 0x6) && (c->x86_model > 0xf)) 467 if ((c->x86 == 0x6) && (c->x86_model > 0xf))
456 printk(KERN_WARNING DRVNAME ": Unknown CPU " 468 printk(KERN_WARNING DRVNAME ": Unknown CPU "
457 "model %x\n", c->x86_model); 469 "model 0x%x\n", c->x86_model);
458 continue; 470 continue;
459 } 471 }
460 472