diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-26 18:18:32 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-29 18:14:37 -0400 |
commit | f44a0120ef07cc9a1f36ab86751ec2b0598d7a2b (patch) | |
tree | da63bafbf4bbff7d7a2154827d8c7366852c5969 /drivers/gpu | |
parent | 489bc476b4c2b3097fe9e980379bbbab260a6156 (diff) |
drm/radeon/dpm: fix si_calculate_memory_refresh_rate()
Update alogorithm as per internal advice.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/si_dpm.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 6ecbb875d211..80c1f506cc0f 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c | |||
@@ -37,8 +37,6 @@ | |||
37 | 37 | ||
38 | #define SMC_RAM_END 0x20000 | 38 | #define SMC_RAM_END 0x20000 |
39 | 39 | ||
40 | #define DDR3_DRAM_ROWS 0x2000 | ||
41 | |||
42 | #define SCLK_MIN_DEEPSLEEP_FREQ 1350 | 40 | #define SCLK_MIN_DEEPSLEEP_FREQ 1350 |
43 | 41 | ||
44 | static const struct si_cac_config_reg cac_weights_tahiti[] = | 42 | static const struct si_cac_config_reg cac_weights_tahiti[] = |
@@ -4040,16 +4038,15 @@ static int si_force_switch_to_arb_f0(struct radeon_device *rdev) | |||
4040 | static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, | 4038 | static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, |
4041 | u32 engine_clock) | 4039 | u32 engine_clock) |
4042 | { | 4040 | { |
4043 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | ||
4044 | u32 dram_rows; | 4041 | u32 dram_rows; |
4045 | u32 dram_refresh_rate; | 4042 | u32 dram_refresh_rate; |
4046 | u32 mc_arb_rfsh_rate; | 4043 | u32 mc_arb_rfsh_rate; |
4047 | u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; | 4044 | u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
4048 | 4045 | ||
4049 | if (pi->mem_gddr5) | 4046 | if (tmp >= 4) |
4050 | dram_rows = 1 << (tmp + 10); | 4047 | dram_rows = 16384; |
4051 | else | 4048 | else |
4052 | dram_rows = DDR3_DRAM_ROWS; | 4049 | dram_rows = 1 << (tmp + 10); |
4053 | 4050 | ||
4054 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); | 4051 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); |
4055 | mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; | 4052 | mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; |