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authorAlex Deucher <alexander.deucher@amd.com>2012-02-02 10:11:12 -0500
committerDave Airlie <airlied@redhat.com>2012-02-03 04:41:35 -0500
commitf2746f83d50287fdb6768e0f20168c64b6a7c9cb (patch)
tree867c02d19bd230b9842132941a4199f21ebfc49c /drivers/gpu
parentc9068eb296fc682513f8612168f605c169b773e4 (diff)
drm/radeon/kms: add r1xx/r2xx CS support for tiled textures
Not likely this will be implemented anytime soon, but for completeness... Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/r100.c12
-rw-r--r--drivers/gpu/drm/radeon/r200.c12
2 files changed, 22 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 7dd6a1c47345..99bb00649357 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1558,7 +1558,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1558 r100_cs_dump_packet(p, pkt); 1558 r100_cs_dump_packet(p, pkt);
1559 return r; 1559 return r;
1560 } 1560 }
1561 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1561 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1562 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1563 tile_flags |= RADEON_TXO_MACRO_TILE;
1564 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1565 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1566
1567 tmp = idx_value & ~(0x7 << 2);
1568 tmp |= tile_flags;
1569 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1570 } else
1571 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1562 track->textures[i].robj = reloc->robj; 1572 track->textures[i].robj = reloc->robj;
1563 track->tex_dirty = true; 1573 track->tex_dirty = true;
1564 break; 1574 break;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 2f44397f6df7..a59cc474d537 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -215,7 +215,17 @@ int r200_packet0_check(struct radeon_cs_parser *p,
215 r100_cs_dump_packet(p, pkt); 215 r100_cs_dump_packet(p, pkt);
216 return r; 216 return r;
217 } 217 }
218 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 218 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
219 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
220 tile_flags |= R200_TXO_MACRO_TILE;
221 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
222 tile_flags |= R200_TXO_MICRO_TILE;
223
224 tmp = idx_value & ~(0x7 << 2);
225 tmp |= tile_flags;
226 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
227 } else
228 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
219 track->textures[i].robj = reloc->robj; 229 track->textures[i].robj = reloc->robj;
220 track->tex_dirty = true; 230 track->tex_dirty = true;
221 break; 231 break;