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authorKenneth Graunke <kenneth@whitecape.org>2010-09-11 04:24:50 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:19:47 -0400
commiteeccdcac07c1e21d25e7d3cf70030059a3017f0c (patch)
tree23642ef5cc72448dbde93e02d5d9b55c096a7221 /drivers/gpu
parentf49f0586191fe16140410db0a46d43bdc690d6af (diff)
drm/i915: Rename graphics reset registers.
The graphics domains are listed as GRDOM in the documentation, and the GDRST PCI config register (0xc0) is only valid on I965 and GM45. Newer chips (like Sandy Bridge) have a different GDRST. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c6
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h10
3 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7209997f18fe..45027d5ad1e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -330,7 +330,7 @@ int i915_resume(struct drm_device *dev)
330static int i965_reset_complete(struct drm_device *dev) 330static int i965_reset_complete(struct drm_device *dev)
331{ 331{
332 u8 gdrst; 332 u8 gdrst;
333 pci_read_config_byte(dev->pdev, GDRST, &gdrst); 333 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
334 return gdrst & 0x1; 334 return gdrst & 0x1;
335} 335}
336 336
@@ -375,8 +375,8 @@ int i965_reset(struct drm_device *dev, u8 flags)
375 * well as the reset bit (GR/bit 0). Setting the GR bit 375 * well as the reset bit (GR/bit 0). Setting the GR bit
376 * triggers the reset; when done, the hardware will clear it. 376 * triggers the reset; when done, the hardware will clear it.
377 */ 377 */
378 pci_read_config_byte(dev->pdev, GDRST, &gdrst); 378 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
379 pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | 0x1); 379 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
380 380
381 /* Wait for the hardware to reset (but no more than 500 ms) */ 381 /* Wait for the hardware to reset (but no more than 500 ms) */
382 if (wait_for(i965_reset_complete(dev), 500)) { 382 if (wait_for(i965_reset_complete(dev), 500)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b5e54c2900f..b1dc943a02cc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -401,7 +401,7 @@ static void i915_error_work_func(struct work_struct *work)
401 case 4: 401 case 4:
402 DRM_DEBUG_DRIVER("resetting chip\n"); 402 DRM_DEBUG_DRIVER("resetting chip\n");
403 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 403 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
404 if (!i965_reset(dev, GDRST_RENDER)) { 404 if (!i965_reset(dev, GRDOM_RENDER)) {
405 atomic_set(&dev_priv->mm.wedged, 0); 405 atomic_set(&dev_priv->mm.wedged, 0);
406 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 406 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
407 } 407 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18e3749fbd11..565a7a3ccd4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -108,10 +108,12 @@
108#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 108#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
109#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 109#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
110#define LBB 0xf4 110#define LBB 0xf4
111#define GDRST 0xc0 111
112#define GDRST_FULL (0<<2) 112/* Graphics reset regs */
113#define GDRST_RENDER (1<<2) 113#define I965_GDRST 0xc0
114#define GDRST_MEDIA (3<<2) 114#define GRDOM_FULL (0<<2)
115#define GRDOM_RENDER (1<<2)
116#define GRDOM_MEDIA (3<<2)
115 117
116/* VGA stuff */ 118/* VGA stuff */
117 119