diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-04-28 00:07:06 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-05-19 02:21:59 -0400 |
commit | e9ebb68b86dd75fe2d61467f834dcf572e6859df (patch) | |
tree | a5cc7cc64617ba02d328bcf3c782d034acd7ad40 /drivers/gpu | |
parent | 7e99a9b2b5386c0ea4234d2845932ff4ab8e4829 (diff) |
drm/nv50: support fractional feedback divider on newer chips
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_calc.c | 87 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_crtc.c | 48 |
4 files changed, 120 insertions, 24 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 453df3f6053f..acd31ed861ef 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -22,7 +22,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ | |||
22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ | 22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ |
23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ | 23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ |
24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ | 24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ |
25 | nv17_gpio.o nv50_gpio.o | 25 | nv17_gpio.o nv50_gpio.o \ |
26 | nv50_calc.o | ||
26 | 27 | ||
27 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o | 28 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o |
28 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o | 29 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 94d8dd27bde8..5b134438effe 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -1170,6 +1170,12 @@ int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |||
1170 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | 1170 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1171 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | 1171 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); |
1172 | 1172 | ||
1173 | /* nv50_calc. */ | ||
1174 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, | ||
1175 | int *N1, int *M1, int *N2, int *M2, int *P); | ||
1176 | int nv50_calc_pll2(struct drm_device *, struct pll_lims *, | ||
1177 | int clk, int *N, int *fN, int *M, int *P); | ||
1178 | |||
1173 | #ifndef ioread32_native | 1179 | #ifndef ioread32_native |
1174 | #ifdef __BIG_ENDIAN | 1180 | #ifdef __BIG_ENDIAN |
1175 | #define ioread16_native ioread16be | 1181 | #define ioread16_native ioread16be |
diff --git a/drivers/gpu/drm/nouveau/nv50_calc.c b/drivers/gpu/drm/nouveau/nv50_calc.c new file mode 100644 index 000000000000..2cdc2bfe7179 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nv50_calc.c | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include "drmP.h" | ||
26 | #include "drm_fixed.h" | ||
27 | #include "nouveau_drv.h" | ||
28 | #include "nouveau_hw.h" | ||
29 | |||
30 | int | ||
31 | nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk, | ||
32 | int *N1, int *M1, int *N2, int *M2, int *P) | ||
33 | { | ||
34 | struct nouveau_pll_vals pll_vals; | ||
35 | int ret; | ||
36 | |||
37 | ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals); | ||
38 | if (ret <= 0) | ||
39 | return ret; | ||
40 | |||
41 | *N1 = pll_vals.N1; | ||
42 | *M1 = pll_vals.M1; | ||
43 | *N2 = pll_vals.N2; | ||
44 | *M2 = pll_vals.M2; | ||
45 | *P = pll_vals.log2P; | ||
46 | return ret; | ||
47 | } | ||
48 | |||
49 | int | ||
50 | nv50_calc_pll2(struct drm_device *dev, struct pll_lims *pll, int clk, | ||
51 | int *N, int *fN, int *M, int *P) | ||
52 | { | ||
53 | fixed20_12 fb_div, a, b; | ||
54 | |||
55 | *P = pll->vco1.maxfreq / clk; | ||
56 | if (*P > pll->max_p) | ||
57 | *P = pll->max_p; | ||
58 | if (*P < pll->min_p) | ||
59 | *P = pll->min_p; | ||
60 | |||
61 | /* *M = ceil(refclk / pll->vco.max_inputfreq); */ | ||
62 | a.full = dfixed_const(pll->refclk); | ||
63 | b.full = dfixed_const(pll->vco1.max_inputfreq); | ||
64 | a.full = dfixed_div(a, b); | ||
65 | a.full = dfixed_ceil(a); | ||
66 | *M = dfixed_trunc(a); | ||
67 | |||
68 | /* fb_div = (vco * *M) / refclk; */ | ||
69 | fb_div.full = dfixed_const(clk * *P); | ||
70 | fb_div.full = dfixed_mul(fb_div, a); | ||
71 | a.full = dfixed_const(pll->refclk); | ||
72 | fb_div.full = dfixed_div(fb_div, a); | ||
73 | |||
74 | /* *N = floor(fb_div); */ | ||
75 | a.full = dfixed_floor(fb_div); | ||
76 | *N = dfixed_trunc(fb_div); | ||
77 | |||
78 | /* *fN = (fmod(fb_div, 1.0) * 8192) - 4096; */ | ||
79 | b.full = dfixed_const(8192); | ||
80 | a.full = dfixed_mul(a, b); | ||
81 | fb_div.full = dfixed_mul(fb_div, b); | ||
82 | fb_div.full = fb_div.full - a.full; | ||
83 | *fN = dfixed_trunc(fb_div) - 4096; | ||
84 | *fN &= 0xffff; | ||
85 | |||
86 | return clk; | ||
87 | } | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index 41fe8aec0a12..b4e4a3b05eae 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c | |||
@@ -264,38 +264,40 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update) | |||
264 | int | 264 | int |
265 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) | 265 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) |
266 | { | 266 | { |
267 | uint32_t pll_reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head); | 267 | uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head); |
268 | struct nouveau_pll_vals pll; | 268 | struct pll_lims pll; |
269 | struct pll_lims limits; | ||
270 | uint32_t reg1, reg2; | 269 | uint32_t reg1, reg2; |
271 | int ret; | 270 | int ret, N1, M1, N2, M2, P; |
272 | 271 | ||
273 | ret = get_pll_limits(dev, pll_reg, &limits); | 272 | ret = get_pll_limits(dev, reg, &pll); |
274 | if (ret) | 273 | if (ret) |
275 | return ret; | 274 | return ret; |
276 | 275 | ||
277 | ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll); | 276 | if (pll.vco2.maxfreq) { |
278 | if (ret <= 0) | 277 | ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P); |
279 | return ret; | 278 | if (ret <= 0) |
279 | return 0; | ||
280 | 280 | ||
281 | if (limits.vco2.maxfreq) { | ||
282 | NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", | 281 | NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", |
283 | pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P); | 282 | pclk, ret, N1, M1, N2, M2, P); |
284 | 283 | ||
285 | reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00; | 284 | reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00; |
286 | reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00; | 285 | reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00; |
287 | nv_wr32(dev, pll_reg, 0x10000611); | 286 | nv_wr32(dev, reg, 0x10000611); |
288 | nv_wr32(dev, pll_reg + 4, reg1 | (pll.M1 << 16) | pll.N1); | 287 | nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1); |
289 | nv_wr32(dev, pll_reg + 8, | 288 | nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); |
290 | reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2); | ||
291 | } else { | 289 | } else { |
292 | NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n", | 290 | ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P); |
293 | pclk, ret, pll.N1, pll.M1, pll.log2P); | 291 | if (ret <= 0) |
292 | return 0; | ||
293 | |||
294 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | ||
295 | pclk, ret, N1, N2, M1, P); | ||
294 | 296 | ||
295 | reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000; | 297 | reg1 = nv_rd32(dev, reg + 4) & 0xffc00000; |
296 | nv_wr32(dev, pll_reg, 0x50000610); | 298 | nv_wr32(dev, reg, 0x50000610); |
297 | nv_wr32(dev, pll_reg + 4, reg1 | | 299 | nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); |
298 | (pll.log2P << 16) | (pll.M1 << 8) | pll.N1); | 300 | nv_wr32(dev, reg + 8, N2); |
299 | } | 301 | } |
300 | 302 | ||
301 | return 0; | 303 | return 0; |