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authorAlex Deucher <alexander.deucher@amd.com>2014-01-27 11:54:44 -0500
committerAlex Deucher <alexander.deucher@amd.com>2014-01-29 15:23:05 -0500
commite9a321c6b2ac954a7dbf235f419c255a424a1273 (patch)
tree00f898ea95a749b64b284c375566055f7ee7cc65 /drivers/gpu
parent50efa51afddb50a6ab47ee15614fcf180130888c (diff)
drm/radeon: fix DAC interrupt handling on DCE5+
DCE5 and newer hardware only has 1 DAC. Use the correct offset. This may fix display problems on certain board configurations. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
-rw-r--r--drivers/gpu/drm/radeon/si.c2
-rw-r--r--drivers/gpu/drm/radeon/sid.h2
3 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4116d0279596..f2b9e21ce4da 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4348,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4348 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4348 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4349 } 4349 }
4350 4350
4351 /* only one DAC on DCE6 */ 4351 /* only one DAC on DCE5 */
4352 if (!ASIC_IS_DCE6(rdev)) 4352 if (!ASIC_IS_DCE5(rdev))
4353 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4353 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4354 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 4354 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
4355 4355
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index e641725ae543..09ec4f6c53bb 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5682,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
5682 } 5682 }
5683 5683
5684 if (!ASIC_IS_NODCE(rdev)) { 5684 if (!ASIC_IS_NODCE(rdev)) {
5685 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 5685 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5686 5686
5687 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 5687 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5688 WREG32(DC_HPD1_INT_CONTROL, tmp); 5688 WREG32(DC_HPD1_INT_CONTROL, tmp);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index caa3e61a38c2..9239a6d29128 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -822,7 +822,7 @@
822# define GRPH_PFLIP_INT_MASK (1 << 0) 822# define GRPH_PFLIP_INT_MASK (1 << 0)
823# define GRPH_PFLIP_INT_TYPE (1 << 8) 823# define GRPH_PFLIP_INT_TYPE (1 << 8)
824 824
825#define DACA_AUTODETECT_INT_CONTROL 0x66c8 825#define DAC_AUTODETECT_INT_CONTROL 0x67c8
826 826
827#define DC_HPD1_INT_STATUS 0x601c 827#define DC_HPD1_INT_STATUS 0x601c
828#define DC_HPD2_INT_STATUS 0x6028 828#define DC_HPD2_INT_STATUS 0x6028