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authorBen Skeggs <bskeggs@redhat.com>2012-07-26 17:53:02 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-08-03 01:40:24 -0400
commite2b34fa0466500de7814fc4e492689cee5ac120b (patch)
tree9b94432024b56dd7b264437b7e2a2a7a22b4b7ea /drivers/gpu
parent0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (diff)
drm/nve0/fifo: add support for the flip completion swmthd
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/nve0_fifo.c37
1 files changed, 33 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nve0_fifo.c b/drivers/gpu/drm/nouveau/nve0_fifo.c
index 1855ecbd843b..e98d144e6eb9 100644
--- a/drivers/gpu/drm/nouveau/nve0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nve0_fifo.c
@@ -294,6 +294,25 @@ nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
294 printk(" on channel 0x%010llx\n", (u64)inst << 12); 294 printk(" on channel 0x%010llx\n", (u64)inst << 12);
295} 295}
296 296
297static int
298nve0_fifo_page_flip(struct drm_device *dev, u32 chid)
299{
300 struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
301 struct drm_nouveau_private *dev_priv = dev->dev_private;
302 struct nouveau_channel *chan = NULL;
303 unsigned long flags;
304 int ret = -EINVAL;
305
306 spin_lock_irqsave(&dev_priv->channels.lock, flags);
307 if (likely(chid >= 0 && chid < priv->base.channels)) {
308 chan = dev_priv->channels.ptr[chid];
309 if (likely(chan))
310 ret = nouveau_finish_page_flip(chan, NULL);
311 }
312 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
313 return ret;
314}
315
297static void 316static void
298nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit) 317nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
299{ 318{
@@ -303,11 +322,21 @@ nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
303 u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f; 322 u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
304 u32 subc = (addr & 0x00070000); 323 u32 subc = (addr & 0x00070000);
305 u32 mthd = (addr & 0x00003ffc); 324 u32 mthd = (addr & 0x00003ffc);
325 u32 show = stat;
326
327 if (stat & 0x00200000) {
328 if (mthd == 0x0054) {
329 if (!nve0_fifo_page_flip(dev, chid))
330 show &= ~0x00200000;
331 }
332 }
306 333
307 NV_INFO(dev, "PSUBFIFO %d:", unit); 334 if (show) {
308 nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat); 335 NV_INFO(dev, "PFIFO%d:", unit);
309 NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n", 336 nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
310 unit, chid, subc, mthd, data); 337 NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
338 unit, chid, subc, mthd, data);
339 }
311 340
312 nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008); 341 nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
313 nv_wr32(dev, 0x040108 + (unit * 0x2000), stat); 342 nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);