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authorZhenyu Wang <zhenyu.z.wang@intel.com>2010-11-04 05:02:54 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-04 05:39:15 -0400
commite07ac3a0b17ed9dec26b742ea41514063ef12386 (patch)
treed02accfc81e76a60a3bf29e93c24213aa6aea2e4 /drivers/gpu
parent5e84e1a487bf6ae912aac1142bdf399b8bdc9238 (diff)
drm/i915; Don't apply Ironlake FDI clock workaround to Sandybridge
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_display.c7
2 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c2c19b6285e..90414ae86afc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1321,6 +1321,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
1321 1321
1322#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1322#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1323#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1323#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1324#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1324 1325
1325#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1326#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1326 1327
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e839c762456..48d8fd686ea9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2212,9 +2212,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
2212 udelay(100); 2212 udelay(100);
2213 2213
2214 /* Ironlake workaround, disable clock pointer after downing FDI */ 2214 /* Ironlake workaround, disable clock pointer after downing FDI */
2215 I915_WRITE(FDI_RX_CHICKEN(pipe), 2215 if (HAS_PCH_IBX(dev))
2216 I915_READ(FDI_RX_CHICKEN(pipe) & 2216 I915_WRITE(FDI_RX_CHICKEN(pipe),
2217 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); 2217 I915_READ(FDI_RX_CHICKEN(pipe) &
2218 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2218 2219
2219 /* still set train pattern 1 */ 2220 /* still set train pattern 1 */
2220 reg = FDI_TX_CTL(pipe); 2221 reg = FDI_TX_CTL(pipe);