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authorDave Airlie <airlied@gmail.com>2014-07-05 17:49:59 -0400
committerDave Airlie <airlied@gmail.com>2014-07-05 17:49:59 -0400
commitdfd7aecfd6d227831d77719379d4c7137f444fee (patch)
tree9ddf609cb0ac13555dce0930fe93c6e951352e0e /drivers/gpu
parent80e6e6b1764023ac1fba41e22a8503245b0fa573 (diff)
parent5549d25f642a7e6cfb8744d0031a9da404f696d6 (diff)
Merge tag 'drm-intel-fixes-2014-07-03' of git://anongit.freedesktop.org/drm-intel
Fixes for 3.16-rc3; most importantly Jesse brings back VGA he took away on a bunch of machines. Also a vblank fix for BDW and a power workaround fix for VLV. * tag 'drm-intel-fixes-2014-07-03' of git://anongit.freedesktop.org/drm-intel: drm/i915: Drop early VLV WA to fix Voltage not getting dropped to Vmin drm/i915: only apply crt_present check on VLV drm/i915: Wait for vblank after enabling the primary plane on BDW
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c27
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c8
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c8
3 files changed, 42 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5f285fba4e41..556c916dbf9d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2087,6 +2087,7 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2087static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, 2087static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2088 enum plane plane, enum pipe pipe) 2088 enum plane plane, enum pipe pipe)
2089{ 2089{
2090 struct drm_device *dev = dev_priv->dev;
2090 struct intel_crtc *intel_crtc = 2091 struct intel_crtc *intel_crtc =
2091 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 2092 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2092 int reg; 2093 int reg;
@@ -2106,6 +2107,14 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2106 2107
2107 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 2108 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2108 intel_flush_primary_plane(dev_priv, plane); 2109 intel_flush_primary_plane(dev_priv, plane);
2110
2111 /*
2112 * BDW signals flip done immediately if the plane
2113 * is disabled, even if the plane enable is already
2114 * armed to occur at the next vblank :(
2115 */
2116 if (IS_BROADWELL(dev))
2117 intel_wait_for_vblank(dev, intel_crtc->pipe);
2109} 2118}
2110 2119
2111/** 2120/**
@@ -11088,6 +11097,22 @@ const char *intel_output_name(int output)
11088 return names[output]; 11097 return names[output];
11089} 11098}
11090 11099
11100static bool intel_crt_present(struct drm_device *dev)
11101{
11102 struct drm_i915_private *dev_priv = dev->dev_private;
11103
11104 if (IS_ULT(dev))
11105 return false;
11106
11107 if (IS_CHERRYVIEW(dev))
11108 return false;
11109
11110 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11111 return false;
11112
11113 return true;
11114}
11115
11091static void intel_setup_outputs(struct drm_device *dev) 11116static void intel_setup_outputs(struct drm_device *dev)
11092{ 11117{
11093 struct drm_i915_private *dev_priv = dev->dev_private; 11118 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -11096,7 +11121,7 @@ static void intel_setup_outputs(struct drm_device *dev)
11096 11121
11097 intel_lvds_init(dev); 11122 intel_lvds_init(dev);
11098 11123
11099 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support) 11124 if (intel_crt_present(dev))
11100 intel_crt_init(dev); 11125 intel_crt_init(dev);
11101 11126
11102 if (HAS_DDI(dev)) { 11127 if (HAS_DDI(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61cb90e729a6..ee72807069e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3209,6 +3209,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
3209*/ 3209*/
3210static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 3210static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3211{ 3211{
3212 struct drm_device *dev = dev_priv->dev;
3213
3214 /* Latest VLV doesn't need to force the gfx clock */
3215 if (dev->pdev->revision >= 0xd) {
3216 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3217 return;
3218 }
3219
3212 /* 3220 /*
3213 * When we are idle. Drop to min voltage state. 3221 * When we are idle. Drop to min voltage state.
3214 */ 3222 */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b66ddcdfb33..9a17b4e92ef4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -691,6 +691,14 @@ intel_post_enable_primary(struct drm_crtc *crtc)
691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
692 692
693 /* 693 /*
694 * BDW signals flip done immediately if the plane
695 * is disabled, even if the plane enable is already
696 * armed to occur at the next vblank :(
697 */
698 if (IS_BROADWELL(dev))
699 intel_wait_for_vblank(dev, intel_crtc->pipe);
700
701 /*
694 * FIXME IPS should be fine as long as one plane is 702 * FIXME IPS should be fine as long as one plane is
695 * enabled, but in practice it seems to have problems 703 * enabled, but in practice it seems to have problems
696 * when going from primary only to sprite only and vice 704 * when going from primary only to sprite only and vice