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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-07-12 16:43:25 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-07-16 02:14:30 -0400
commitd18ea1b58a5003eb6fca03aff03c4c01321e6cb1 (patch)
tree1a95ffb03a9df3468f547524ede686cf9b35a667 /drivers/gpu
parent63573eb7ba3d1bdc1db25fe79314609a4189a306 (diff)
drm/i915: unify PM interrupt preinstall sequence
Since the addition of VECS we have a slightly different enable sequence for PM interrupts on ivb/hsw vs snb and vlv. Usually that will end up in hard to track down surprises. Hence unifiy things and since we have copies of this code in 3 places now, extract it into its own little helper. Note that this changes the irq preinstall sequence a bit for snb and vlv: We now also clear the PM registers in the preinstall hook, in addition to the PM register clearing/setup already done when actually enabling rps. So this doesn't fix a bug but simply unifies the code across all platforms. After the postinstall hook is similarly unified we can rip out the then redundant PM interrupt setup from the rps code. v3: Rebase on top of the retained double-GTIIR clearing. Also resurrect the masking/disabling of the gen6+ PM interrupts as spotted by Ben Widaswky. v4: Move the DE interrupt reset code out of gen5_gt_irq_preinstall back to ironlake_irq_preinstall where it really belongs. Spotted by Paulo. v3: Improve the commit message to more clearly spell out why we want to unify the code and what exactly changes. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> [danvet: s/GT/PM/ to fix up a comment which Ben spotted while reviewing.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c39
1 files changed, 21 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 64db680fb7a4..0d54a550ec6d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2054,6 +2054,23 @@ static void ibx_irq_preinstall(struct drm_device *dev)
2054 POSTING_READ(SDEIER); 2054 POSTING_READ(SDEIER);
2055} 2055}
2056 2056
2057static void gen5_gt_irq_preinstall(struct drm_device *dev)
2058{
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060
2061 /* and GT */
2062 I915_WRITE(GTIMR, 0xffffffff);
2063 I915_WRITE(GTIER, 0x0);
2064 POSTING_READ(GTIER);
2065
2066 if (INTEL_INFO(dev)->gen >= 6) {
2067 /* and PM */
2068 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2069 I915_WRITE(GEN6_PMIER, 0x0);
2070 POSTING_READ(GEN6_PMIER);
2071 }
2072}
2073
2057/* drm_dma.h hooks 2074/* drm_dma.h hooks
2058*/ 2075*/
2059static void ironlake_irq_preinstall(struct drm_device *dev) 2076static void ironlake_irq_preinstall(struct drm_device *dev)
@@ -2064,16 +2081,11 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
2064 2081
2065 I915_WRITE(HWSTAM, 0xeffe); 2082 I915_WRITE(HWSTAM, 0xeffe);
2066 2083
2067 /* XXX hotplug from PCH */
2068
2069 I915_WRITE(DEIMR, 0xffffffff); 2084 I915_WRITE(DEIMR, 0xffffffff);
2070 I915_WRITE(DEIER, 0x0); 2085 I915_WRITE(DEIER, 0x0);
2071 POSTING_READ(DEIER); 2086 POSTING_READ(DEIER);
2072 2087
2073 /* and GT */ 2088 gen5_gt_irq_preinstall(dev);
2074 I915_WRITE(GTIMR, 0xffffffff);
2075 I915_WRITE(GTIER, 0x0);
2076 POSTING_READ(GTIER);
2077 2089
2078 ibx_irq_preinstall(dev); 2090 ibx_irq_preinstall(dev);
2079} 2091}
@@ -2092,15 +2104,7 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
2092 I915_WRITE(DEIER, 0x0); 2104 I915_WRITE(DEIER, 0x0);
2093 POSTING_READ(DEIER); 2105 POSTING_READ(DEIER);
2094 2106
2095 /* and GT */ 2107 gen5_gt_irq_preinstall(dev);
2096 I915_WRITE(GTIMR, 0xffffffff);
2097 I915_WRITE(GTIER, 0x0);
2098 POSTING_READ(GTIER);
2099
2100 /* Power management */
2101 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2102 I915_WRITE(GEN6_PMIER, 0x0);
2103 POSTING_READ(GEN6_PMIER);
2104 2108
2105 ibx_irq_preinstall(dev); 2109 ibx_irq_preinstall(dev);
2106} 2110}
@@ -2121,9 +2125,8 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
2121 /* and GT */ 2125 /* and GT */
2122 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2126 I915_WRITE(GTIIR, I915_READ(GTIIR));
2123 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2127 I915_WRITE(GTIIR, I915_READ(GTIIR));
2124 I915_WRITE(GTIMR, 0xffffffff); 2128
2125 I915_WRITE(GTIER, 0x0); 2129 gen5_gt_irq_preinstall(dev);
2126 POSTING_READ(GTIER);
2127 2130
2128 I915_WRITE(DPINVGTT, 0xff); 2131 I915_WRITE(DPINVGTT, 0xff);
2129 2132