drm/i915: always set FDI composite sync bit

It's needed for 3 pipe support as well as just regular functionality
(e.g. DisplayPort).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Adam Jackson <ajax@redhat.com>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

2 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f6eed169630..d8bf9cf348ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3189,6 +3189,7 @@
 #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
 
 /* both Tx and Rx */
+#define  FDI_COMPOSITE_SYNC             (1<<11)
 #define  FDI_LINK_TRAIN_AUTO            (1<<10)
 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 186cde29994d..2e28c687010c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2601,6 +2601,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+        temp |= FDI_COMPOSITE_SYNC;
         I915_WRITE(reg, temp | FDI_TX_ENABLE);
 
         reg = FDI_RX_CTL(pipe);
@@ -2608,6 +2609,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
         temp &= ~FDI_LINK_TRAIN_AUTO;
         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+        temp |= FDI_COMPOSITE_SYNC;
         I915_WRITE(reg, temp | FDI_RX_ENABLE);
 
         POSTING_READ(reg);