diff options
author | Jani Nikula <jani.nikula@intel.com> | 2012-12-04 09:36:28 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-12-04 16:30:25 -0500 |
commit | bfd7590d3eed3650e910a22a92dc23ea50e60a41 (patch) | |
tree | 181e4a24af76a22264a9cf017657b190a9cf2cb1 /drivers/gpu | |
parent | 633cf8f5056c3e72158e4dbc387b3d65926d2d55 (diff) |
drm/i915: do not access BLC_PWM_CTL2 on pre-gen4 hardware
The BLC_PWM_CTL2 register does not exist before gen4. While at it, do a
slight drive by cleanup of the code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_panel.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index c758ad277473..bee8cb6108a7 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -130,8 +130,9 @@ static int is_backlight_combination_mode(struct drm_device *dev) | |||
130 | return 0; | 130 | return 0; |
131 | } | 131 | } |
132 | 132 | ||
133 | static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) | 133 | static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) |
134 | { | 134 | { |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
135 | u32 val; | 136 | u32 val; |
136 | 137 | ||
137 | /* Restore the CTL value if it lost, e.g. GPU reset */ | 138 | /* Restore the CTL value if it lost, e.g. GPU reset */ |
@@ -141,21 +142,22 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) | |||
141 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { | 142 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { |
142 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; | 143 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; |
143 | } else if (val == 0) { | 144 | } else if (val == 0) { |
144 | I915_WRITE(BLC_PWM_PCH_CTL2, | ||
145 | dev_priv->regfile.saveBLC_PWM_CTL2); | ||
146 | val = dev_priv->regfile.saveBLC_PWM_CTL2; | 145 | val = dev_priv->regfile.saveBLC_PWM_CTL2; |
146 | I915_WRITE(BLC_PWM_PCH_CTL2, val); | ||
147 | } | 147 | } |
148 | } else { | 148 | } else { |
149 | val = I915_READ(BLC_PWM_CTL); | 149 | val = I915_READ(BLC_PWM_CTL); |
150 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { | 150 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
151 | dev_priv->regfile.saveBLC_PWM_CTL = val; | 151 | dev_priv->regfile.saveBLC_PWM_CTL = val; |
152 | dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); | 152 | if (INTEL_INFO(dev)->gen >= 4) |
153 | dev_priv->regfile.saveBLC_PWM_CTL2 = | ||
154 | I915_READ(BLC_PWM_CTL2); | ||
153 | } else if (val == 0) { | 155 | } else if (val == 0) { |
154 | I915_WRITE(BLC_PWM_CTL, | ||
155 | dev_priv->regfile.saveBLC_PWM_CTL); | ||
156 | I915_WRITE(BLC_PWM_CTL2, | ||
157 | dev_priv->regfile.saveBLC_PWM_CTL2); | ||
158 | val = dev_priv->regfile.saveBLC_PWM_CTL; | 156 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
157 | I915_WRITE(BLC_PWM_CTL, val); | ||
158 | if (INTEL_INFO(dev)->gen >= 4) | ||
159 | I915_WRITE(BLC_PWM_CTL2, | ||
160 | dev_priv->regfile.saveBLC_PWM_CTL2); | ||
159 | } | 161 | } |
160 | } | 162 | } |
161 | 163 | ||
@@ -164,10 +166,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) | |||
164 | 166 | ||
165 | static u32 _intel_panel_get_max_backlight(struct drm_device *dev) | 167 | static u32 _intel_panel_get_max_backlight(struct drm_device *dev) |
166 | { | 168 | { |
167 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
168 | u32 max; | 169 | u32 max; |
169 | 170 | ||
170 | max = i915_read_blc_pwm_ctl(dev_priv); | 171 | max = i915_read_blc_pwm_ctl(dev); |
171 | 172 | ||
172 | if (HAS_PCH_SPLIT(dev)) { | 173 | if (HAS_PCH_SPLIT(dev)) { |
173 | max >>= 16; | 174 | max >>= 16; |