Merge commit 'origin/master' into next

Conflicts:
	include/linux/kvm.h

18 files changed, 140 insertions, 32 deletions

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f831ea159291..96eddd17e050 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -92,6 +92,7 @@ config DRM_I830
 config DRM_I915
         tristate "i915 driver"
         depends on AGP_INTEL
+        select SHMEM
         select DRM_KMS_HELPER
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index cea665d86dd3..b54ba63d506e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -662,6 +662,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
                 return NULL;
         }
 
+        /* Some EDIDs have bogus h/vtotal values */
+        if (mode->hsync_end > mode->htotal)
+                mode->htotal = mode->hsync_end + 1;
+        if (mode->vsync_end > mode->vtotal)
+                mode->vtotal = mode->vsync_end + 1;
+
         drm_mode_set_name(mode);
 
         if (pt->misc & DRM_EDID_PT_INTERLACED)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index dc8e374a0b55..65ef011fa8ba 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -599,7 +599,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
         struct drm_framebuffer *fb = fb_helper->fb;
         int depth;
 
-        if (var->pixclock == -1 || !var->pixclock)
+        if (var->pixclock != 0)
                 return -EINVAL;
 
         /* Need to resize the fb object !!! */
@@ -691,7 +691,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
         int ret;
         int i;
 
-        if (var->pixclock != -1) {
+        if (var->pixclock != 0) {
                 DRM_ERROR("PIXEL CLCOK SET\n");
                 return -EINVAL;
         }
@@ -904,7 +904,7 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev,
         fb_helper->fb = fb;
 
         if (new_fb) {
-                info->var.pixclock = -1;
+                info->var.pixclock = 0;
                 if (register_framebuffer(info) < 0)
                         return -EINVAL;
         } else {
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 80391995bdec..e9dbb481c469 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -552,7 +552,7 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
         vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
         vma->vm_ops = obj->dev->driver->gem_vm_ops;
         vma->vm_private_data = map->handle;
-        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+        vma->vm_page_prot =  pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
 
         /* Take a ref for this mapping of the object, so that the fault
          * handler can dereference the mmap offset's pointer to the object.
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index c861d80fd779..97dc5a4f0de4 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -103,6 +103,11 @@ static struct drm_mm_node *drm_mm_kmalloc(struct drm_mm *mm, int atomic)
         return child;
 }
 
+/* drm_mm_pre_get() - pre allocate drm_mm_node structure
+ * drm_mm:      memory manager struct we are pre-allocating for
+ *
+ * Returns 0 on success or -ENOMEM if allocation fails.
+ */
 int drm_mm_pre_get(struct drm_mm *mm)
 {
         struct drm_mm_node *node;
@@ -253,12 +258,14 @@ void drm_mm_put_block(struct drm_mm_node *cur)
                                 prev_node->size += next_node->size;
                                 list_del(&next_node->ml_entry);
                                 list_del(&next_node->fl_entry);
+                                spin_lock(&mm->unused_lock);
                                 if (mm->num_unused < MM_UNUSED_TARGET) {
                                         list_add(&next_node->fl_entry,
                                                  &mm->unused_nodes);
                                         ++mm->num_unused;
                                 } else
                                         kfree(next_node);
+                                spin_unlock(&mm->unused_lock);
                         } else {
                                 next_node->size += cur->size;
                                 next_node->start = cur->start;
@@ -271,11 +278,13 @@ void drm_mm_put_block(struct drm_mm_node *cur)
                 list_add(&cur->fl_entry, &mm->fl_entry);
         } else {
                 list_del(&cur->ml_entry);
+                spin_lock(&mm->unused_lock);
                 if (mm->num_unused < MM_UNUSED_TARGET) {
                         list_add(&cur->fl_entry, &mm->unused_nodes);
                         ++mm->num_unused;
                 } else
                         kfree(cur);
+                spin_unlock(&mm->unused_lock);
         }
 }
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f8ce9a3a420d..26bf0552b3cb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -267,10 +267,10 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
         uint32_t *mem;
 
         for (page = 0; page < page_count; page++) {
-                mem = kmap(pages[page]);
+                mem = kmap_atomic(pages[page], KM_USER0);
                 for (i = 0; i < PAGE_SIZE; i += 4)
                         seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
-                kunmap(pages[page]);
+                kunmap_atomic(pages[page], KM_USER0);
         }
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57204e298975..a725f6591192 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -296,6 +296,7 @@ typedef struct drm_i915_private {
         u32 saveVBLANK_A;
         u32 saveVSYNC_A;
         u32 saveBCLRPAT_A;
+        u32 saveTRANSACONF;
         u32 saveTRANS_HTOTAL_A;
         u32 saveTRANS_HBLANK_A;
         u32 saveTRANS_HSYNC_A;
@@ -326,6 +327,7 @@ typedef struct drm_i915_private {
         u32 saveVBLANK_B;
         u32 saveVSYNC_B;
         u32 saveBCLRPAT_B;
+        u32 saveTRANSBCONF;
         u32 saveTRANS_HTOTAL_B;
         u32 saveTRANS_HBLANK_B;
         u32 saveTRANS_HSYNC_B;
@@ -414,6 +416,16 @@ typedef struct drm_i915_private {
         u32 savePFB_WIN_SZ;
         u32 savePFA_WIN_POS;
         u32 savePFB_WIN_POS;
+        u32 savePCH_DREF_CONTROL;
+        u32 saveDISP_ARB_CTL;
+        u32 savePIPEA_DATA_M1;
+        u32 savePIPEA_DATA_N1;
+        u32 savePIPEA_LINK_M1;
+        u32 savePIPEA_LINK_N1;
+        u32 savePIPEB_DATA_M1;
+        u32 savePIPEB_DATA_N1;
+        u32 savePIPEB_LINK_M1;
+        u32 savePIPEB_LINK_N1;
 
         struct {
                 struct drm_mm gtt_space;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c3ceffa46ea0..aa7fd82aa6eb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -254,10 +254,15 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         int ret = IRQ_NONE;
-        u32 de_iir, gt_iir;
+        u32 de_iir, gt_iir, de_ier;
         u32 new_de_iir, new_gt_iir;
         struct drm_i915_master_private *master_priv;
 
+        /* disable master interrupt before clearing iir  */
+        de_ier = I915_READ(DEIER);
+        I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+        (void)I915_READ(DEIER);
+
         de_iir = I915_READ(DEIIR);
         gt_iir = I915_READ(GTIIR);
 
@@ -290,6 +295,9 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
                 gt_iir = new_gt_iir;
         }
 
+        I915_WRITE(DEIER, de_ier);
+        (void)I915_READ(DEIER);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 992d5617e798..6eec8171a44e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -239,6 +239,11 @@ static void i915_save_modeset_reg(struct drm_device *dev)
         if (drm_core_check_feature(dev, DRIVER_MODESET))
                 return;
 
+        if (IS_IGDNG(dev)) {
+                dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
+                dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
+        }
+
         /* Pipe & plane A info */
         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -263,6 +268,11 @@ static void i915_save_modeset_reg(struct drm_device *dev)
                 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 
         if (IS_IGDNG(dev)) {
+                dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
+                dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
+                dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
+                dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
+
                 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
                 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
 
@@ -270,6 +280,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
                 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
                 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
 
+                dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
                 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
                 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
@@ -314,6 +325,11 @@ static void i915_save_modeset_reg(struct drm_device *dev)
                 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
 
         if (IS_IGDNG(dev)) {
+                dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
+                dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
+                dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
+                dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
+
                 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
                 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
 
@@ -321,6 +337,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
                 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
                 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
 
+                dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
                 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
                 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
@@ -368,6 +385,11 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
                 fpb1_reg = FPB1;
         }
 
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
+                I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
+        }
+
         /* Pipe & plane A info */
         /* Prime the clock */
         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -395,6 +417,11 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
                 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 
         if (IS_IGDNG(dev)) {
+                I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
+                I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
+                I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
+                I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
+
                 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
                 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 
@@ -402,6 +429,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
                 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
                 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 
+                I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
                 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
                 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
                 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
@@ -439,7 +467,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
         /* Actually enable it */
         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
         DRM_UDELAY(150);
-        if (IS_I965G(dev))
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
         DRM_UDELAY(150);
 
@@ -454,6 +482,11 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
                 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 
         if (IS_IGDNG(dev)) {
+                I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
+                I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
+                I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
+                I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
+
                 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
                 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 
@@ -461,6 +494,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
                 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
                 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 
+                I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
                 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
                 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
                 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 212e22740fc1..e5051446c48e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -262,8 +262,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
                 } while (time_after(timeout, jiffies));
         }
 
-        if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
-            CRT_HOTPLUG_MONITOR_COLOR)
+        if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
+            CRT_HOTPLUG_MONITOR_NONE)
                 return true;
 
         return false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ba6546b7c7f..099f420de57a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -863,10 +863,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         intel_clock_t clock;
-        int max_n;
-        bool found;
         int err_most = 47;
-        found = false;
+        int err_min = 10000;
 
         /* eDP has only 2 clock choice, no n/m/p setting */
         if (HAS_eDP)
@@ -890,10 +888,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         }
 
         memset(best_clock, 0, sizeof(*best_clock));
-        max_n = limit->n.max;
         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
                 /* based on hardware requriment prefer smaller n to precision */
-                for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
+                for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
                         /* based on hardware requirment prefere larger m1,m2 */
                         for (clock.m1 = limit->m1.max;
                              clock.m1 >= limit->m1.min; clock.m1--) {
@@ -907,18 +904,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                                         this_err = abs((10000 - (target*10000/clock.dot)));
                                         if (this_err < err_most) {
                                                 *best_clock = clock;
-                                                err_most = this_err;
-                                                max_n = clock.n;
-                                                found = true;
                                                 /* found on first matching */
                                                 goto out;
+                                        } else if (this_err < err_min) {
+                                                *best_clock = clock;
+                                                err_min = this_err;
                                         }
                                 }
                         }
                 }
         }
 out:
-        return found;
+        return true;
 }
 
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 663ab6de0b58..c33451aec1bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
         struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
         u32 temp;
 
-        if (mode != DRM_MODE_DPMS_ON) {
-                temp = I915_READ(hdmi_priv->sdvox_reg);
+        temp = I915_READ(hdmi_priv->sdvox_reg);
+
+        /* HW workaround, need to toggle enable bit off and on for 12bpc, but
+         * we do this anyway which shows more stable in testing.
+         */
+        if (IS_IGDNG(dev)) {
                 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
+                POSTING_READ(hdmi_priv->sdvox_reg);
+        }
+
+        if (mode != DRM_MODE_DPMS_ON) {
+                temp &= ~SDVO_ENABLE;
         } else {
-                temp = I915_READ(hdmi_priv->sdvox_reg);
-                I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE);
+                temp |= SDVO_ENABLE;
         }
+
+        I915_WRITE(hdmi_priv->sdvox_reg, temp);
         POSTING_READ(hdmi_priv->sdvox_reg);
+
+        /* HW workaround, need to write this twice for issue that may result
+         * in first write getting masked.
+         */
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(hdmi_priv->sdvox_reg, temp);
+                POSTING_READ(hdmi_priv->sdvox_reg);
+        }
 }
 
 static void intel_hdmi_save(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 901befe03da2..d67c42555ab9 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -107,6 +107,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
                         base += 3;
                         break;
                 case ATOM_IIO_WRITE:
+                        (void)ctx->card->reg_read(ctx->card, CU16(base + 1));
                         ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
                         base += 3;
                         break;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 757f5cd37744..224506a2f7b1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -519,6 +519,7 @@ typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  * AGP
  */
 int radeon_agp_init(struct radeon_device *rdev);
+void radeon_agp_resume(struct radeon_device *rdev);
 void radeon_agp_fini(struct radeon_device *rdev);
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 23ea9955ac59..54bf49a6d676 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -237,6 +237,18 @@ int radeon_agp_init(struct radeon_device *rdev)
 #endif
 }
 
+void radeon_agp_resume(struct radeon_device *rdev)
+{
+#if __OS_HAS_AGP
+        int r;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r)
+                        dev_warn(rdev->dev, "radeon AGP reinit failed\n");
+        }
+#endif
+}
+
 void radeon_agp_fini(struct radeon_device *rdev)
 {
 #if __OS_HAS_AGP
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index fce4c4087fda..29763ceae3af 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -566,8 +566,9 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
                 radeon_i2c_do_lock(radeon_connector, 0);
 
                 if (!radeon_connector->edid) {
-                        DRM_ERROR("DDC responded but not EDID found for %s\n",
-                                  drm_get_connector_name(connector));
+                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
+                                        drm_get_connector_name(connector));
+                        ret = connector_status_connected;
                 } else {
                         radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 
@@ -720,8 +721,8 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                 radeon_i2c_do_lock(radeon_connector, 0);
 
                 if (!radeon_connector->edid) {
-                        DRM_ERROR("DDC responded but not EDID found for %s\n",
-                                  drm_get_connector_name(connector));
+                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
+                                        drm_get_connector_name(connector));
                 } else {
                         radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 
@@ -1149,6 +1150,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
                         if (ret)
                                 goto failed;
                         radeon_connector->dac_load_detect = true;
+                        /* RS400,RC410,RS480 chipset seems to report a lot
+                         * of false positive on load detect, we haven't yet
+                         * found a way to make load detect reliable on those
+                         * chipset, thus just disable it for TV.
+                         */
+                        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
+                                radeon_connector->dac_load_detect = false;
                         drm_connector_attach_property(&radeon_connector->base,
                                                       rdev->mode_info.load_detect_property,
                                                       1);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e3f9edfa40fe..41bb76fbe734 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -688,6 +688,8 @@ int radeon_resume_kms(struct drm_device *dev)
                 return -1;
         }
         pci_set_master(dev->pdev);
+        /* resume AGP if in use */
+        radeon_agp_resume(rdev);
         radeon_resume(rdev);
         radeon_restore_bios_scratch_regs(rdev);
         fb_set_suspend(rdev->fbdev_info, 0);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 7935f793bf62..ba68c9fe90a1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -137,8 +137,6 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 
 void rv515_vga_render_disable(struct radeon_device *rdev)
 {
-        WREG32(R_000330_D1VGA_CONTROL, 0);
-        WREG32(R_000338_D2VGA_CONTROL, 0);
         WREG32(R_000300_VGA_RENDER_CONTROL,
                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 }
@@ -382,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 
         /* Stop all video */
-        WREG32(R_000330_D1VGA_CONTROL, 0);
         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -391,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
         WREG32(R_006880_D2CRTC_CONTROL, 0);
         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
+        WREG32(R_000330_D1VGA_CONTROL, 0);
+        WREG32(R_000338_D2VGA_CONTROL, 0);
 }
 
 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -404,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
         mdelay(1);
         /* Restore video state */
+        WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
+        WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
-        WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
-        WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 }