drm/radeon: properly handle cg on asics without UVD

Don't try and enable clockgating if the asic doesn't have
UVD.  Use rdev->has_uvd rather than using local checks.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 2 insertions, 6 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d325280e2f9f..1d656f7b13f2 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5215,14 +5215,12 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
 
 static void si_init_cg(struct radeon_device *rdev)
 {
-        bool has_uvd = true;
-
         si_enable_mgcg(rdev, true);
         si_enable_cgcg(rdev, true);
         /* disable MC LS on Tahiti */
         if (rdev->family == CHIP_TAHITI)
                 si_enable_mc_ls(rdev, false);
-        if (has_uvd) {
+        if (rdev->has_uvd) {
                 si_enable_uvd_mgcg(rdev, true);
                 si_init_uvd_internal_cg(rdev);
         }
@@ -5230,9 +5228,7 @@ static void si_init_cg(struct radeon_device *rdev)
 
 static void si_fini_cg(struct radeon_device *rdev)
 {
-        bool has_uvd = true;
-
-        if (has_uvd)
+        if (rdev->has_uvd)
                 si_enable_uvd_mgcg(rdev, false);
         si_enable_cgcg(rdev, false);
         si_enable_mgcg(rdev, false);